National Instruments TNT5004 Reference Manual

GPIB

TNT5002TM Technical Reference
Manual

PCI to GPIB High-Performance Non-Controller

TNT5002 Technical Reference Manual

May 2004 Edition

Part Number 370595B-01

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Important Information

Warranty

The TNT5002 is warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by
receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the
warranty period. This warranty includes parts and labor.

The media on which you receive National Instruments software are warranted not to fail to execute programming instructions, due to defects
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Trademarks

HS488™, National Instruments™, NI™, ni.com™, NI-488.2™, NI-488DDK™, TNT4882™, TNT488C™, and TNT5002™ are trademarks of
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Contents

About This Manual

Product Features ............................................................................................................xi

How To Use This Manual..............................................................................................xii

Conventions ...................................................................................................................xiii

Mnemonic Conventions...................................................................................xiv

Related Documentation..................................................................................................xv

Chapter 1
Architectural Overview

TNT5002 Block Diagram ..............................................................................................1-1

TNT5002 Mode Selection .............................................................................................1-2

FIFO Overview ..............................................................................................................1-2

DMA Overview .............................................................................................................1-3

Chapter 2
Signal Pins

Signal Definitions and Conventions ..............................................................................2-1

GPIB Signals..................................................................................................................2-2

GPIB Data Signals...........................................................................................2-2

GPIB Interface Management Signals ..............................................................2-2

GPIB Handshake Signals ................................................................................2-3

Device Signals ...............................................................................................................2-4

Miscellaneous Signals (All Modes).................................................................2-4

Miscellaneous Signals (PCI4882 Mode).........................................................2-5

Indicator Signals..............................................................................................2-5

PCI Signals ....................................................................................................................2-6

Generic Interface Signals...............................................................................................2-8

Power/Ground Pins ........................................................................................................2-9

PCI4882 Power/Ground Pins ..........................................................................2-9

GEN4882 Power/Ground Pins ........................................................................2-9

Chapter 3
Register Descriptions

Register Groups .............................................................................................................3-1

Register Groups in PCI4882 Mode .................................................................3-1

Register Groups in GEN4882 Mode ...............................................................3-2

PCI4882 Mode Register Map ........................................................................................3-2

© National Instruments Corporation v TNT5002 Technical Reference Manual

Contents

GEN4882 Mode Register Map...................................................................................... 3-4

TNT5002 Status/Control Register Group...................................................................... 3-5

TNT5002 Status/Control Registers Sorted by Offset ..................................... 3-5

TNT5002 Status/Control Registers Sorted by Mnemonic .............................. 3-6

TNT5002 Status/Control Register Descriptions ............................................. 3-7

PCI Configuration Registers.......................................................................................... 3-10

PCI Configuration Register Map .................................................................... 3-10

PCI Configuration Register Descriptions ....................................................... 3-11

DMA Status/Control Registers......................................................................................3-26

DMA Status/Control Registers Sorted by Offset ............................................ 3-26

DMA Status/Control Registers Sorted by Mnemonic..................................... 3-27

DMA Status/Control Register Descriptions.................................................... 3-28

4882 Register Set........................................................................................................... 3-45

4882-Mode Registers Sorted by Offset........................................................... 3-45

4882-Mode Registers Sorted by Mnemonic ................................................... 3-47

4882-Mode Register Descriptions ..................................................................3-49

Serial Number Register ................................................................................................. 3-113

Chapter 4
Functional Description—PCI4882 and GEN4882 Modes

Overview ....................................................................................................................... 4-1

GPIB Reset Manager..................................................................................................... 4-2

Overview......................................................................................................... 4-2

Hardware Resets ............................................................................................. 4-2

Register Bit Description.................................................................................. 4-3

Operation......................................................................................................... 4-4

Talker/Listener Manager ............................................................................................... 4-6

Overview......................................................................................................... 4-6

Register Bit Definitions .................................................................................. 4-6

Operation......................................................................................................... 4-10

GPIB Transfer Manager ................................................................................................ 4-11

Overview......................................................................................................... 4-11

Initialization Phase—Register Bit Definitions................................................ 4-12

Initialization Phase—Operation...................................................................... 4-21

Data Transfer Phase—Register Bit Definitions .............................................. 4-23

Data Transfer Phase—Operation .................................................................... 4-25

Termination Phase—Register Bit Definitions ................................................4-27

Termination Phase—Operation....................................................................... 4-29

Using 8-bit FIFOs ........................................................................................... 4-29

Device Clear Block........................................................................................................ 4-30

Overview......................................................................................................... 4-30

Register Bit Definitions .................................................................................. 4-30

Operation......................................................................................................... 4-31

TNT5002 Technical Reference Manual vi ni.com

Contents

Device Trigger Block.....................................................................................................4-33

Overview .........................................................................................................4-33

Register Bit Definitions...................................................................................4-33

Operation .........................................................................................................4-35

Serial Poll Response Manager .......................................................................................4-36

Overview .........................................................................................................4-36

Register Bit Definitions...................................................................................4-36

Operation .........................................................................................................4-39

Parallel Poll Response Manager ....................................................................................4-42

Overview .........................................................................................................4-42

Register Bit Definitions...................................................................................4-42

Operation .........................................................................................................4-44

Remote Local Block ......................................................................................................4-46

Overview .........................................................................................................4-46

Register Bit Definitions...................................................................................4-46

Operation .........................................................................................................4-48

HS488 Manager .............................................................................................................4-49

Overview .........................................................................................................4-49

Register Bit Description ..................................................................................4-49

Operation .........................................................................................................4-57

Timer..............................................................................................................................4-59

Overview .........................................................................................................4-59

Register Bit Definitions...................................................................................4-59

Operation .........................................................................................................4-61

Interrupts........................................................................................................................4-63

Overview .........................................................................................................4-63

Register Bit Descriptions.................................................................................4-63

Operation .........................................................................................................4-65

Debugging Bits ..............................................................................................................4-66

Overview .........................................................................................................4-66

Register Bit Descriptions.................................................................................4-66

Miscellaneous Bits.........................................................................................................4-76

Overview .........................................................................................................4-76

Rarely Used GPIB Transfer Bits .....................................................................4-76

Rarely Used Controller Bits ............................................................................4-78

Rarely Used Interrupt Bits...............................................................................4-79

Rarely Used Addressing Mode Bits...............................................................................4-81

Register Bit Definitions...................................................................................4-81

Operation—Extended Dual Addressing Mode................................................4-83

© National Instruments Corporation vii TNT5002 Technical Reference Manual

Contents

Chapter 5
DMA Manager

DMA Overview ............................................................................................................. 5-1

Link Chaining Overview ............................................................................................... 5-2

DMA Transfers..............................................................................................................5-3

Initialization Phase.......................................................................................... 5-3

Transfer Phase.................................................................................................5-4

Termination Phase........................................................................................... 5-4

Alignment of Data in the DFIFO .................................................................... 5-5

Chapter 6
Serial ROM

Overview ....................................................................................................................... 6-1

Serial Autoload..............................................................................................................6-1

Serial ROM Contents .................................................................................................... 6-1

PCI Device ID................................................................................................. 6-2

Serial Number ................................................................................................. 6-2

Remaining Bytes ............................................................................................. 6-2

Accessing the EEPROM ................................................................................. 6-2

Register Bit Descriptions ................................................................................6-3

Chapter 7
Clocks

Clock Domains .............................................................................................................. 7-1

PCI4882 Mode............................................................................................................... 7-1

GEN4882 Mode............................................................................................................. 7-1

Chapter 8
Reset Considerations

Hardware Resets............................................................................................................8-1

PCI Reset (PCI4882 Mode Only) ................................................................... 8-1

Generic Reset (GEN4882 Mode Only)........................................................... 8-1

Software Resets ............................................................................................................. 8-2

GPIB Software Reset (PCI4882 Mode Only) ................................................. 8-2

GPIB Hardware Reset (PCI_4882 Mode).......................................................8-2

GPIB pon (All Modes)....................................................................................8-2

GPIB Reset (All Modes) ................................................................................. 8-2

DMA Reset (PCI4882 Mode) ......................................................................... 8-3

Power-on Considerations ................................................................................ 8-3

TNT5002 Technical Reference Manual viii ni.com

Appendix A
Electrical Specifications and Timing

Appendix B
Mechanical Information

Appendix C
GPIB Remote Messages

Appendix D
Technical Support and Professional Services

Contents

© National Instruments Corporation ix TNT5002 Technical Reference Manual

About This Manual

The TNT5002 is high performance GPIB interface that supports the
following two modes of usage (refer to Chapter 1, Architectural Overview,
for a complete description of different modes):

• PCI4882 mode—In this mode, the TNT5002 is able to run all NI-488.2
based drivers developed for the PCI-GPIB unmodified. This mode is
functionally equivalent to One-chip mode in the NI TNT4882 with a
PCI interface. This is the default mode for the TNT5002.

• GEN4882 mode—In this mode, the TNT5002 is functionally
equivalent to One-chip mode in the NI TNT4882/TNT4882C. Any
application written for the TNT4882/TNT4882C in mode will run
unmodified on the TNT5002.

The TNT5002 implements IEEE 488.1 Interface Functions SH1, AH1, T5,
TE5, L3, LE3, SR1, RL1, PP1, PP2, DC1, and DT1. The TNT5002 also
implements HS488 Interface Functions AHE1, SHE1, and CF1.

The TNT5002 implements Controller function C0, allowing no Controller
capability in any mode.

A DMA Controller with a 64-byte FIFO may be used in PCI4882 mode.
This may be used in addition to the 32-byte GPIB FIFO, effectively making
a 96-byte FIFO.

The TNT5002 also implements IEEE 488.1 Electrical Driver/Receiver
Capability E2 (three-state drivers).

Product Features

• Complies with PCI Local Bus Specification, Revision 2.1 or 2.2

• Complies with IEEE 488.1 Standard Digital Interface for
Programmable Instrumentation and IEEE 488.2

• Complete backwards compatibility with software written using
NI-488.2, NI-488DDK, or NI-Device

• Complies with HS488

1

Assuming PCI4882 or GEN4882 modes

© National Instruments Corporation xi TNT5002 Technical Reference Manual

1

About This Manual

• PCI Bus-master

1

• Auto-negotiating handshake, can use HS488 capable instruments and
non-HS488 instruments simultaneously

1

• Automatic GPIB EOS and/or NL remote message detection

• 144-pin PQFP package or 256 Fine-pitch BGA package

•3.3V core

• 3.3V or 5V PCI/Generic interface signaling environments

• Integrated IEEE 488.1 compliant three-state GPIB transceivers

• Can use PCI clock or external 40 MHz clock for GPIB circuitry
(40 MHz external clock required for maximum transfer rates and all
HS488 transfers)

• 32-bit PCI or 16/8-bit generic interface

• 64-byte PCI DMA FIFO

• 32-byte GPIB FIFO

• Transfer rates up to 8 Mbytes/s using HS488

1

1

1

• Transfer rates up to 1.5 Mbytes/s using IEEE 488.1 handshake

• TNT5002 performs the following IEEE 488.1 Interface Functions:
SH1, AH1, T5, TE5, L3, LE3, SR1, RL1, PP1, PP2, DC1, DT1, C0

• TNT5002 performs HS488 Functions AHE1, SHE1, and CF1

1

• NI TNT4882 One-chip compatible register set

• Indicator pins: REM, talk addressed, listen addressed

• Synchronous design

How To Use This Manual

This manual is designed for use in two ways. Chapter 3, Register

Descriptions, contains a listing of registers sorted first by group and then

alphabetically. Chapter 4, Functional Description—PCI4882 and

GEN4882 Modes, contains different sections addressing different GPIB

concepts, such as parallel polling and GPIB data transfers.

Users who are very familiar with the register set may find Chapter 3,

Register Descriptions, easier to use because specific registers are easy to

find. Users who are less familiar may find Chapter 4, Functional

Description—PCI4882 and GEN4882 Modes, easier because all of the

1

Assuming PCI4882 mode

TNT5002 Technical Reference Manual xii ni.com

About This Manual

register bits needed to perform a certain GPIB function are often located in
different registers.

Conventions

The following conventions appear in this manual:

» The » symbol leads you through nested menu items and dialog box options

to a final action. The sequence File»Page Setup»Options directs you to
pull down the File menu, select the Page Setup item, and select Options
from the last dialog box.

# The pound sign indicates a signal is active low. Active low signals are

logically asserted when in a low state; such as a pin being grounded or a
register bit being 0.

+ The plus symbol is a logical binary OR operator.

& The ampersand symbol is a logical binary AND operator.

~ The tilde is a logical unary negation operator.

* The asterisk is the multiplication operator.

This icon denotes a note, which alerts you to important information.

active-low Active-low means that the signal should be at a logic low state to be

asserted. For example, RST# is an active-low signal that resets various
internal registers. The registers are reset when RST# is at logic 0 (ground).

byte 8 bits

DMA DMA is an acronym for Direct Memory Access. In the TNT5002, DMA is

used to transfer data automatically between system memory and the GPIB
FIFO. During DMA transfers, a DMA controller initiates register accesses.

dword 32 bits

IEEE 488.1 and IEEE 488.1 and IEEE 488.2 refer to the ANSI/IEEE Standard 488.1-1987
IEEE 488.2 and the ANSI/IEEE Standard 488.2-1992, respectively, which define the

GPIB.

italic Italic text denotes variables, emphasis, a cross reference, or an introduction

to a key concept. This font also denotes text that is a placeholder for a word
or value that you must supply.

© National Instruments Corporation xiii TNT5002 Technical Reference Manual

About This Manual

monospace Text in this font denotes text or characters that you should enter from the

keyboard, sections of code, programming examples, and syntax examples.
This font is also used for the proper names of disk drives, paths, directories,
programs, subprograms, subroutines, device names, functions, operations,
variables, filenames, and extensions.

word 16 bits

Mnemonic Conventions

There are many mnemonics that appear in this manual. Some mnemonics
are spelled identically but may differ in case; some are all capitalized and
some are all lower case. The following guidelines describe the naming
convention used:

Convention Examples

Register mnemonics are capitalized. CHOR, CFG, PCIDR

Register bit mnemonics are capitalized. ADSR[LPAS],

DCR[BERHAND]

Register bit mnemonics are prefixed by the register in which they are
accessed, except when they are used in the bit descriptions of the

CHSR[ERROR],
CFG[CCEN]

registers in which the bit is accessed.

A mnemonic for a register bit may refer to a bit in more than one
register. This is clarified by prefixing a bit mnemonic with the register

CHSR[INT],
ISR3[INT]

in which the bit is accessed.

Similar bits in a given register may be grouped together and indexed
with brackets.

One bit of a group of similar bits in a given register may be indexed
without brackets.

PPR[LPPE[3:0]],
CHCR[SWAP[1:0]]

PPR[LPPE2],
CHCR[SWAP0]

Signal pins are capitalized. FRAME#, DAV#, SCL

GPIB local messages as defined in IEEE 488.1 are lower case. rdy, nba

GPIB remote messages as defined in IEEE 488.1 are capitalized. TCT, DCL

All GPIB signal pin names are suffixed with #. DAV#, NRFD#

All AUXCR, AUXMR, and CMDR commands are capitalized. IFC, ~IST

TNT5002 Technical Reference Manual xiv ni.com

Convention Examples

All IEEE 488.1 state machine state names are capitalized. SDYS, CIDS

About This Manual

The indexing brackets may be left off a bus name if the entire bus is
the subject of the context.

Related Documentation

The following documents contain information that you might find helpful
as you read this manual:

• ANSI/IEEE Standard 488.1-1987, IEEE Standard Digital Interface

for Programmable Instrumentation

• ANSI/IEEE Standard 488.2-1992, IEEE Standard Codes, Formats,

Protocols, and Common Commands

DIO#, AD

© National Instruments Corporation xv TNT5002 Technical Reference Manual

Architectural Overview

TNT5002 Block Diagram

TNT5002

PCI

PCI Core

DMA FIFO

Chip

Status Control

Registers

1

1

GPIB Core

GPIB FIFO

Generic

Por t

PCI Config

Registers

DMA

Status/Control

Registers

0

Mode

4882 Registers

GPIB Transceivers

GPIB

© National Instruments Corporation 1-1 TNT5002 Technical Reference Manual

Chapter 1 Architectural Overview

TNT5002 Mode Selection

There are two distinct modes of operation in the TNT5002. PCI4882 and GEN4882 modes
implement the TNT4882 One-chip register set. This register set can be accessed through a
generic IO interface or a PCI interface. PCI4882 mode implements a PCI bus-master
interface. GEN4882 mode implements a generic IO interface. The two different modes of
operation are outlined in the following table. The interface must be selected by the MODE pin
and must not be changed dynamically since the pinout is significantly different between
interfaces.

User Configuration TNT5002 Features

GPIB

MODE

Mode

PCI4882 3.3V CMDR[SOFT_RESET] 4882 PCI 64 + 32

GEN4882 GND CMDR[SOFT_RESET] 4882 Generic 32

Pin

Reset Command

Register

Set

Interface

Tota l FI F O

Depth

(Bytes)

FIFO Overview

If the TNT5002 is in PCI4882 mode, there are two FIFOs: a 32-byte FIFO connected to the
GPIB and a 64-byte FIFO connected to the PCI bus.

The 32-byte GPIB FIFO (GFIFO) is used for both GPIB reads and writes. It can be written to
and read from simultaneously by the DMA Controller and Source/Acceptor GPIB state
machines.

The 64-byte DMA FIFO (DFIFO) connected to the PCI bus is used for DMA transfers. This
FIFO is connected to the PCI bus on one side and the GFIFO on the other side.

During DMA transfers, bytes are automatically transferred between the DFIFO and GFIFO.
The GFIFO should never be directly accessed. The TNT5002 always interprets all DMA
accesses between the GFIFO and DMA FIFO as 16-bit operations. During programmed IO
(PIO) operations, the DMA FIFO is never accessed, just the GFIFO.

If the TNT5002 is in GEN4882 mode, there is one 32-byte FIFO connected to the GPIB. This
FIFO can be accessed through either PIO or DMA.

TNT5002 Technical Reference Manual 1-2 ni.com

DMA Overview

If the TNT5002 is in PCI4882 mode, the DMA Controller must be used to maximize transfer
rates. The GPIB registers in the TNT5002 are configured in the same manner regardless of
whether DMA is used. If DMA is used, the GPIB FIFO should not be directly accessed
because the DMA Controller automatically transfers data between the DMA FIFO and GPIB
FIFO.

If the TNT5002 is in GEN4882 mode, an external DMA controller can be connected to the
TNT5002.

Chapter 1 Architectural Overview

© National Instruments Corporation 1-3 TNT5002 Technical Reference Manual

Signal Pins

Signal Definitions and Conventions

Type Definition

I Standard input only.

O Standard output only.

TS Tristate bi-directional.

STS Sustained tristate. Active low signal must be pulled high for one cycle

when deasserting.

OD Standard open drain.

PU Signal is pulled up internally with a 25 kΩ–100 kΩ resistor. Although

these pins are pulled up internally, they should also be connected to either

3.3V or GND.

2

PD Signal is pulled down internally with a 30 kΩ–90 kΩ resistor. Although

these pins are pulled up internally, they should also be connected to either

3.3V or GND.

GT GPIB Transceiver.

© National Instruments Corporation 2-1 TNT5002 Technical Reference Manual

Chapter 2 Signal Pins

GPIB Signals

The following 16 signals implement the GPIB protocol as described in IEEE 488.1. These
signals exist in all modes.

GPIB Data Signals

Pin Name Type Description

DIO#[8:1] GT Data Lines—The eight DIO lines carry command and data

messages on the GPIB. All commands and most data bytes use
the 7-bit ASCII or ISO code set, leaving the eighth bit, DIO8#,
unused or used for parity. However, applications may use
DIO8# as a normal data signal for 8-bit data.

GPIB Interface Management Signals

These signals are used for signaling among controllers and devices.

Pin Name Type Description

IFC# GT Interface Clear—The System Controller asserts IFC# to

place all devices into a known quiescent state.

AT N # GT Attention—The Controller-in-Charge asserts ATN# when it

sends commands and unasserts ATN# when it sends data
messages.

SRQ# GT Service Request—A device asserts SRQ# to request service

from a Controller.

REN# GT Remote Enable—The System Controller asserts REN# to

enable devices for remote programming.

EOI# GT End or Identify—A Talker asserts EOI# to signal the end of

data. EOI# is also asserted by the Controller-in-Charge to
signal the execution of a parallel poll.

TNT5002 Technical Reference Manual 2-2 ni.com

Chapter 2 Signal Pins

GPIB Handshake Signals

These signals are used to handshake data and command bytes using both 3-wire and HS488
transfer protocols.

Pin Name Type Description

DAV# GT Data Valid—DAV# indicates whether DIO# is stable and

whether devices can safely accept the signals. When a
Controller sends commands, it controls DAV#, and when a
Talker sends data it controls DAV#.

NRFD# GT Not Ready for Data—NRFD# indicates whether a Listener is

ready to receive a data byte. NRFD# is driven by all active
Listeners when a Talker is sending data or by all devices when
the Controller is sending commands. NRFD# is also used by
the Talker to control HS488 transfers.

NDAC# GT Not Data Accepted—NDAC# indicates whether all devices

have accepted the byte for which DAV# was most recently
asserted. NDAC# is driven by all active Listeners when a
Talker is sending data or by all devices when a Controller is
sending commands.

© National Instruments Corporation 2-3 TNT5002 Technical Reference Manual

Chapter 2 Signal Pins

Device Signals

Miscellaneous Signals (All Modes)

Pin Name Type Description

EXT_CLK I GPIB Circuitry Clock—This clock may be used for the

GPIB circuitry. It should be driven by an external oscillator at
40MHz. In PCI4882 or PCI9914 modes this pin must remain
undriven if USE_PCI_CLK is asserted because the GPIB
circuitry will be clocked by PCI_CLK.

TRIGGER O Trigger—The trigger pin is asserted when the DT state

machine is in DTAS. DTAS is entered after receiving the
Group Execute Trigger (GET) command as an Addressed
Listener, or after writing AUXMR[TRIG]. TRIGGER
unasserts after either leaving DTAS or three clock cycles after
writing AUXMR[TRIG].

SRQ_OE# I, PU SRQ# Output Enable—This debugging pin asynchronously

enables the SRQ# transceiver when asserted. The logic state is
then determined by SRQ_DATA. This pin must be unasserted
for normal operation.

SRQ_DATA I, PU SRQ# Data Input—When SRQ_OE# is asserted this

debugging pin determines the drive state of the SRQ#
transceiver. Asserting this pin causes the SRQ# transceiver to
drive SRQ# actively false. Unasserting this pin causes the
SRQ# transceiver to drive SRQ# actively true.

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Chapter 2 Signal Pins

Miscellaneous Signals (PCI4882 Mode)

Pin Name Type Description

USE_ROM I, PU Use Serial Rom—This pin determines if the TNT5002 loads

a PCI Device ID and serial number from the serial ROM.
If this pin is asserted, serial autoload occurs. If this pin is
unasserted, serial autoload does not occur.

SCL O Serial ROM Clock Pin—This clock is generated by the

TNT5002 and connected to the clock input of a serial ROM.
The frequency of this clock is approximately 65 kHz when
PCI_CLK is 33 MHz.

SDA TS, PU Serial ROM Data Pin—This bidirectional data pin is the

serial data line between the TNT5002 and serial ROM. This
pin is an output when writing to the serial ROM and an input
when reading from the serial ROM.

DIS_SUBSYS I, PU Disable PCI SUBSYSTEM ID—If this pin is asserted,

reading the PCI SUBSYSTEM ID returns 0x00000000. If this
pin is actively driven low, reading the PCI SUBSYSTEM ID
register returns the same value as the PIDR.

USE_PCI_CLK I Use PCI Clock—When this pin is asserted, the GPIB

circuitry is clocked by the PCI_CLK. If this pin is unasserted,
the GPIB circuitry is clocked by EXT_CLK.

Indicator Signals

These pins indicate various states of the GPIB state machines. These are general purpose
outputs and can be used to drive an LED, for example. These signals exist in all modes.

Pin Name Type Description

LADCS O Active Listener—This pin asserts when the Listener state

machine is in LADS or LACS. This pin reflects the state of
ADSR[LA].

TADCS O Active Talker—This pin asserts when the Talker state

machine is in TADS, TACS, or SPAS. This pin reflects the
state of ADSR[LA].

REMT O Remote Enabled—This pin asserts when the Remote/Local

state machine is in REMS or RWLS. This pin reflects the state
of ISR2[REM].

© National Instruments Corporation 2-5 TNT5002 Technical Reference Manual

Chapter 2 Signal Pins

PCI Signals

These signals implement a PCI interface. These signals only exist in PCI4882 mode.
In GEN4882 mode, these pins have different functionality.

Pin Name Type Description

PCI_CLK I PCI Clock—This is the clock input from the PCI bus.

AD[31:0] TS PCI Address/Data—These signals are the multiplexed PCI

address and data bus.

C/BE#[3:0] TS Command/Byte Enable—These signals are the multiplexed

command and byte enables. During the PCI address phase
C/BE# conveys the type of transfer taking place. Following the
address phase, C/BE# indicates whether valid data is present
on the four byte lanes of the AD bus.

PAR TS Parity—PAR carries the even parity over the AD and C/BE#

buses during address and data phases. The device that drives
AD and CBE# also drives PAR. PAR is valid one clock cycle
after AD and C/BE# are valid.

FRAME# STS Frame—A PCI master asserts FRAME# to indicate the

beginning and duration of a transaction. FRAME# assertion
indicates the beginning of a PCI transaction. Data transactions
can continue while FRAME# is asserted. FRAME#
unassertion indicates the final data phase requested by the
initiator.

IRDY# STS Initiator Ready—IRDY# is driven by the initiator of a

transaction to indicate the initiator’s ability to complete the
current data phase. During a write transaction, IRDY# is
asserted when valid data is driven onto the AD bus. During a
read, IRDY# is asserted when the initiator is able to accept
data for the current data phase.

TRDY# STS Target Ready—TRDY# is driven be the target of a

transaction to indicate the target’s ability to complete the
current data phase. During a write transaction, TRDY# is
asserted when the target is able to accept data for the current
data phase. During a read, TRDY# is asserted when the target
is driving valid data onto the AD bus.

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Chapter 2 Signal Pins

Pin Name Type Description

DEVSEL# STS Device Select—DEVSEL# is asserted by the target to indicate

that the device is accepting the transaction.

STOP# STS Stop—This signal is driven by the target to request that the

initiator stop the current transaction.

IDSEL STS Initialization Device Select—This signal is used as the chip

select for Type 0 PCI configuration accesses to PCI
configuration space.

PERR# STS Parity Error—PERR# is asserted when a parity error is

detected. PERR# can be asserted by the target during a write
transaction and by the initiator during a read transaction.

SERR# TS System Error—SERR# is asserted to indicate a serious

system problem or a parity error during the address phase of a
data transfer.

REQ# TS Bus Request—REQ# is asserted to request access to the bus.

GNT# I Bus Grant—GNT# is asserted to grant access to the bus.

INTA# TS Interrupt—This signal is asynchronously asserted to

interrupt the CPU.

PCI_RST# I PCI Reset—This signal is used to initialize the device to a

known state. While PCI_RST# is asserted all PCI and GPIB
signals are tri-stated. PCI_RST# must be asserted during
power-up to ensure that the GPIB signals do not glitch when
connected to another device.

© National Instruments Corporation 2-7 TNT5002 Technical Reference Manual

Chapter 2 Signal Pins

Generic Interface Signals

These signals implement a generic bus interface. These signals only exist in GEN4882 mode.
In PCI4882 mode, these pins have different functionality.

Pin Name Type Description

DACK# I DMA Acknowledge—DACK#, along with IORD# or

IOWT#, asserts during DMA accesses.

CS# I Chip Select—CS#, along with IORD# or IOWT#, asserts

during IO accesses.

DRQ O DMA Request—DRQ is asserted to request a DMA transfer.

HWORD# I 16-Bit Access—HWORD# is asserted during 16-bit register

accesses and unasserted for 8-bit register accesses. HWORD#
is ignored during DMA accesses.

INT TS Interrupt—INT asserts when an enabled interrupt condition

is true.

IOA[6:0] I Address—IOA selects a register during IO accesses.

IOD[15:0] IO Data—IOD is the 16-bit bi-directional data bus used for DMA

and IO accesses. During 8-bit writes data must be on the lower
8 bits. During 8-bit reads the data will be smeared across both
byte lanes. Unused signals in 8-bit mode should not be left
floating.

IORD# I Read—IORD# is asserted to indicate an IO or DMA read.

IOWT# I Write—IOWT# is asserted to indicate an IO or DMA write.

RESET# I Reset—RESET# resets the chip to its initial power-on state.

RESET# also asynchronously tri-states the GPIB transceivers.

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Chapter 2 Signal Pins

Power/Ground Pins

The location of power and ground pins are the same among all modes, although the meaning
of the pins changes slightly.

PCI4882 Power/Ground Pins

The following pins supply power to the TNT5002 in PCI4882 mode.

Pin Name Description

3.3V Core/GPIB Transceiver Power—These pins provide power for the digital
core and all output signal pins except PCI signals. These pins must be connected
to a 3.3V source. If not connected directly to the PCI 3.3V power rail, the 3.3V
supply they are connected to cannot vary by more than 170mV. If these pins are
connected to the PCI 3.3V rail, that rail may vary according to the PCI
Specification.

VIO PCI Transceiver Power—These pins provide power for the PCI Transceivers.

These must be connected to 3.3V or 5V as allowed by the PCI Specification.

GND Ground—These pins are ground pins for both power inputs.

VIO_SEL VIO Comparator—This input is used to determine whether VIO is 3.3V or 5V.

This signal is compared against 3.3V and must be directly connected to VIO.

GEN4882 Power/Ground Pins

The following pins supply power to the TNT5002 in GEN4882 mode.

Pin Name Description

3.3V Core/GPIB Transceiver Power—These pins provide power for the digital
core and all output signal pins except the Generic Interface signals. These pins
must be connected to a 3.3V source.

VIO Generic Interface Transceiver Power—These pins provide power for the

Generic Interface Transceivers. The generic interface pins can be powered from
either 3.3V or 5V. The voltage connected to VIO is used to drive the generic
interface pins.

GND Ground—These pins are ground pins for both power inputs.

© National Instruments Corporation 2-9 TNT5002 Technical Reference Manual

Chapter 2 Signal Pins

Pin Name Description

VIO_SEL VIO Comparator—This input is used to determine whether VIO is 3.3V or 5V.

This signal is compared against 3.3V and must be directly connected to VIO.

PWR_GOOD Power Good—This input must be unasserted while 3.3V is out of the specified

operating range. For example, this pin must be unasserted while 3.3V is
ramping up as well as ramping down.

TNT5002 Technical Reference Manual 2-10 ni.com

Register Descriptions

Register Groups

The following tables group the registers into functional blocks such that all registers in a given
block serve a similar function.

Register Groups in PCI4882 Mode

Offset from PBAR0 Register Group

0x000–0x2FF Chip Status/Control

0x300–0x3FF PCI Configuration

0x400–0x4FF Miscellaneous Status/Control

0x500–0x5FF DMA Status/Control

0x600–0x7FF Reserved

3

Offset from PBAR1 Register Group

0x0000–0x00FF Reserved

0x0100–0x011F 4882 Register Set

0x0120–0x012F Reserved

0x0130–0x013F Reserved

0x0140–0x014F Reserved

0x0150–0x1FFF Reserved

0x2000–0x3FFF Serial Number

© National Instruments Corporation 3-1 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

Register Groups in GEN4882 Mode

Offset Register Group

0x00–0x1F 4882 Register Set

0x20–0x2F Reserved

0x30–0x3F Reserved

0x40–0x4F GPIB Test/Status

0x50–0x7F Reserved

PCI4882 Mode Register Map

TNT5002 Technical Reference Manual 3-2 ni.com

0×00

0×FF

PCI Memory Space

0×00

PBAR0

PCI Config Space

Chapter 3 Register Descriptions

Status/Control Registers

CHIP

Status/Control

PCI Configuration

Miscellaneous
Status/Control

DMA

Status/Control

Reserved

0×000

0×300

0×400

0×500

0×600

PBAR0 + 0×7FF

IODWBSR

†

PBAR1

IOWBSR1

††

PBAR1 + 0×2000

PBAR1 + 0×3FFF

†

IODWBSR is a register that defines the

location of GPIB Registers in PBAR1.

††

IOWBSR1 is a register that defines the

location of the serial number in PBAR1.

GPIB Registers

Reserved

4882 Register Set

Reserved

Reserved

Reserved

Reserved

Serial Number

Serial Number

(All Offsets)

0×7FF

0×0000

0×0100

0×0120

0×0130

0×0140

0×0150

0×1FFF

0×0000

0×1FFF

© National Instruments Corporation 3-3 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

GEN4882 Mode Register Map

The following register map is valid when interfacing through generic interface. These
registers are accessed by asserting CS# or DACK# and IORD# or IOWR#.

GPIB Registers

4882 Register Set

Reserved

Reserved

Reserved

0×00

0×20

0×30

0×40

0×50

Reserved

0×FF

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Chapter 3 Register Descriptions

TNT5002 Status/Control Register Group

These registers are only available in PCI4882 mode. This register group is used to control and
configure the PCI interface.

TNT5002 Status/Control Registers Sorted by Offset

Registers at offsets not listed are reserved.

Offset

from PBAR0

0x14 LCISR2 Reserved Local CPU Interrupt Status 2

0xC0 IODWBSR IO Device Window Base/Size IO Device Window Base/Size

0xC4 IOWBSR1 IO Window 1 Base/Size IO Window 1 Base/Size

Mnemonic Write Register Read Register

© National Instruments Corporation 3-5 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

TNT5002 Status/Control Registers Sorted by Mnemonic

Registers at offsets not listed are reserved.

Offset

Mnemonic

IODWBSR 0xC0 IO Device Window Base/Size IO Device Window Base/Size

IOWBSR1 0xC4 IO Window 1 Base/Size IO Window 1 Base/Size

LCISR2 0x14 Reserved Local CPU Interrupt Status 2

from PBAR0

Write Register Read Register

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Chapter 3 Register Descriptions

TNT5002 Status/Control Register Descriptions

IO Device Window Base Size Register (IODWBSR)

Offset 0xC0 from PBAR0 Reset Value: 0x00000000 Read/Write

BA[31:24]

31 30 29 28 27 26 25 24

BA[23:16]

23 22 21 20 19 18 17 16

B[15:12] R R R R

15 14 13 12 11 10 9 8

WENAB R R R R R R R

7 6 5 4 3 2 1 0

The IODWBSR determines the address of the GPIB registers. This register must be written
with PBAR1 + 0x00000080 to access the GPIB registers.

Mnemonic Type Description

BA[31:12] R/W Base Address—The base address of the GPIB registers in

PCI address space. These bits are only valid when WENAB
is set.

WENAB R/W Window Enable—If this bit is set, the Window is enabled.

If this bit is clear the window is disabled.

R R/W Reserved—Always write 0 to these bits. These bits are read

as either 0 or 1.

© National Instruments Corporation 3-7 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

IO Window Base/Size Register 1 (IOWBSR1)

Offset 0xC4 from PBAR0 Reset Value: 0x00000000 Read/Write

BA[31:24]

31 30 29 28 27 26 25 24

BA[23:16]

23 22 21 20 19 18 17 16

BA[15:8]

15 14 13 12 11 10 9 8

WENAB R R WSIZE[4:0]

7 6 5 4 3 2 1 0

The IODWBSR determines the address of the serial number. This register must be written
with PBAR1 + 0x0000208C to access the serial number.

Mnemonic Type Description

BA[31:8] R/W Base Address—The base address in PCI address space. The

number of bits compared is determined by the WSIZE[4:0].

WENAB R/W Window Enable—If this bit is set, the Window is enabled.

If this bit is clear the window is disabled.

WSIZE[4:0] R/W Window Size—These bits determine the size of the serial

number window in PBAR1. The size in bytes is 2

(WSIZE + 1)

.
WSIZE should be set to 01100, indicating the size of the
window is 8 kB.

R R/W Reserved—Always write 0 to these bits. These bits are read

as either 0 or 1.

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Chapter 3 Register Descriptions

Local CPU Interrupt Status 2 (LCISR2)

Offset 0x14 from PBAR0 Reset Value: 0x00000000 Read Only

PCIINT R R R R R R R

31 30 29 28 27 26 25 24

R R R R R R R R

23 22 21 20 19 18 17 16

R R R R R R R R

15 14 13 12 11 10 9 8

R R R R R R R R

7 6 5 4 3 2 1 0

This register reflects various interrupts. This register should not be accessed for most
applications.

Mnemonic Type Description

PCIINT R PCI Interrupt—PCIINT is ISR3[INT].

R R Reserved—Always write 0 to these bits. These bits are read

as either 0 or 1.

© National Instruments Corporation 3-9 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

PCI Configuration Registers

These registers are only available in PCI4882 mode.

PCI Configuration Register Map

All PCI devices must support a set of configuration registers that control the behavior of the
PCI device and provide a consistent location for a PCI device to indicate its status. The PCI
specification does support some functionality that is superfluous to the requirements of the
TNT5002’s PCI interface. The register space, as implemented in the PCI interface, is shown
in the following table.

Offset in

PCI Config

Mnemonic

PIDR

PSCR

PCCRIDR

PLIVR 0x0C PBAR0 + 0x30C 0 Latency Timer Cache Line Size

PBAR0 0x10 PBAR0 + 0x310 Base Address Register 0

PBAR1 0x14 PBAR0 + 0x314 Base Address Register 1

Reserved 0x18 PBAR0 + 0x318 Reserved

Reserved 0x1C PBAR0 + 0x31C Reserved

Reserved 0x20 PBAR0 + 0x320 Reserved

Reserved 0x24 PBAR0 + 0x324 Reserved

PCISR 0x28 PBAR0 + 0x328 Reserved/CIS Pointer Register

PSUBR 0x2C PBAR0 + 0x32C Subsystem ID Subsystem Vendor ID

Reserved 0x30 PBAR0 + 0x330 Reserved

Reserved 0x34 PBAR0 + 0x334 Reserved

Reserved 0x38 PBAR0 + 0x338 Reserved

PLRIDR 0x3C PBAR0 + 0x33C Max_Lat Min_Gnt Interrupt Pin Interrupt Line

Space

0x00

0x04

0x08

Offset in

Memory Space

PBAR0 + 0x300

PBAR0 + 0x304

PBAR0 + 0x308

Byte 3 Byte 2 Byte 1 Byte 0

31 24 23 16 15 8 70

Device ID Vendor ID

PCI Status PCI Control

Class Code Revision ID

PBACOR 0x40 PBAR0 + 0x340 Base Address Configuration Register

Reserved 0x44 PBAR0 + 0x344 Reserved

PERCR 0x48 PBAR0 + 0x348 Expansion ROM Configuration Register

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Chapter 3 Register Descriptions

PCI Configuration Register Descriptions

Device ID/Vendor ID Register (PIDR)

Offset 0x00 from PCI Config Space, 0x300 from PBAR0 Reset Value: See Description Read Only

DEVICE_ID[15:8]

31 30 29 28 27 26 25 24

DEVICE_ID[7:0]

23 22 21 20 19 18 17 16

VENDOR_ID[15:8]

15 14 13 12 11 10 9 8

VENDOR_ID[7:0]

7 6 5 4 3 2 1 0

Mnemonic Type Description

DEVICE_ID[15:0] R Device Identification Number—The default DEVICE_ID

of the TNT5002 is 0xC850. The default DEVICE_ID is
overwritten from a serial ROM if USE_ROM is asserted or
not connected.

VENDOR_ID[15:0] R Vendor Identification Number—This sixteen bit value is

assigned by the PCI Special Interest Group. National
Instruments’ PCI Vendor ID number is 0x1093.

© National Instruments Corporation 3-11 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

PCI Status and Control Register (PSCR)

Offset 0x04 from PCI Config Space, 0x304 from PBAR0 Reset Value: 0x02000000 Read/Write

PERRDT SERRDT SMABT RTAB T STABT SPEEDA SPEEDB PA RD T

31 30 29 28 27 26 25 24

FBBC 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

0 0 0 0 0 0 0 SERREN

15 14 13 12 11 10 9 8

ADSTEP PERREN 0 MWIEN 0 MSTREN MEMEN IOEN

7 6 5 4 3 2 1 0

Bits 31–16 are status bits. The PCI interface sets the bits in these registers. In order to clear a
bit in the status register, a PCI device must write a one to the bit. This convention is required
by the PCI specification. Bits 15–0 are control bits, and these bits are read/write.

Mnemonic Type Description

PERRDT R/W Parity Error Detect—This bit is set when the PCI interface

detects a parity error even when parity error handling is
disabled by clearing PERREN.

SERRDT R/W System Error Detected—The PCI interface sets this bit

when it asserts SERR#.

SMABT R/W Signal Master Abort—The PCI interface sets this bit if it

terminates a PCI master cycle with a master abort.

RTABT R/W Receive Target Abort—The PCI interface sets this bit to

indicate that it received a target abort while performing a PCI
master cycle.

STABT R/W Signal Target Abort—The PCI interface sets this bit if it

terminates a slave cycle with a target abort.

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Chapter 3 Register Descriptions

Mnemonic Type Description

SPEEDA
SPEEDB

R/W Address Decoding Speed—SPEEDA and SPEEDB are

hardwired to 0 and 1, respectively, to indicate that the PCI
interface is a medium speed decoder. These bits are set in
accordance with the PCI specification requirements. Writes to
these bits are ignored.

PA RD T R/W Parity Detect—The PCI interface sets this bit if three

conditions are met:

• The PCI interface asserted PERR# or detected that PERR#
was asserted by another device.

• The PCI interface was performing a master cycle when
PERR# was asserted.

• PERREN is set.

FBBC R/W Fast Back-to-Back Capable—This bit is hardwired to 1

indicating that the PCI interface supports fast back-to-back
transfers as a PCI slave. Writes to this bit are ignored.

SERREN R/W SERR# Enable—Setting this bit permits the PCI interface to

assert SERR# during system error conditions. Clearing this
bit prevents the PCI interface from asserting SERR#.

ADSTEP R/W Address Stepping—This bit is hardwired to 0 to indicate that

address or data stepping is not performed. Writes to this bit
are ignored.

PERREN R/W Parity Error Response Enable—Setting this bit enables the

PCI interface to assert PERR# and set PERRDT. If this bit is
cleared, the PCI interface must ignore parity errors and
continue normal operations.

MWIEN R/W Memory Write/Invalidate Enable—Setting this bit allows

the PCI interface to initiate memory write and invalidate and
memory read line cycles as a PCI master. Clearing this bit
makes the PCI interface initiate standard memory write and
read cycles.

© National Instruments Corporation 3-13 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

Mnemonic Type Description

MSTREN R/W Master Mode Enable—Setting this bit permits the PCI

interface to operate as a PCI master. Clearing this bit disables
master mode.

MEMEN R/W Memory Space Response Enable—Setting this bit permits

the PCI interface to respond to PCI memory cycles that map
to the PCI interface. Clearing this bit makes the PCI interface
ignore all PCI memory space transfers.

IOEN R/W IO Space Response Enable—Setting this bit permits the PCI

interface to respond to PCI IO space cycles that map to the
PCI interface. Clearing this bit makes the PCI interface ignore
all PCI IO space transfers.

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Chapter 3 Register Descriptions

Class Code and Revision ID Register (PCCRIDR)

Offset 0x08 from PCI Config Space, 0x308 from PBAR0 Reset Value: 0x07800002 Read Only

CLASS_CODE[23:16]

31 30 29 28 27 26 25 24

CLASS_CODE[15:8]

23 22 21 20 19 18 17 16

CLASS_CODE[7:0]

15 14 13 12 11 10 9 8

REVISION_ID[7:0]

7 6 5 4 3 2 1 0

This register describes the type of PCI device according to the PCI specification.

Mnemonic Ty pe Description

CLASS_CODE[23:0] R Determine the PCI Interface’s Device Class—This value

is set to 0x078000, indicating the TNT5002 base class is
“Simple Communications Controller,” the subclass is
“Other Communications Device,” and the register level
programming interface is 0x00.

REVISION_ID[7:0] R Revision Code—This byte determines the revision level of

the PCI interface. The TNT5002 is revision 0x02. This
value may be changed in future versions of the TNT5002.

© National Instruments Corporation 3-15 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

Latency Timer Value (PLIVR)

Offset 0x0C from PCI Config Space, 0x30C from PBAR0 Reset Value: 0x00000000 Read Only

BIST[7:0]

31 30 29 28 27 26 25 24

HEADER_TYPE[7:0]

23 22 21 20 19 18 17 16

LATENCY_TIMER[7:0]

15 14 13 12 11 10 9 8

CACHELINE_SZ[7:0]

7 6 5 4 3 2 1 0

Mnemonic Ty pe Description

BIST[7:0] R Built-in Self Test—These bits return 0.

HEADER_TYPE[7:0] R Header Type—These bits return 0.

LATENCY[7:0] R Maximum Bus Tenure—The value in this register

specifies the maximum time, in PCI clocks, that the PCI
interface can occupy the PCI bus when it performs master
cycles. This value is written by a PCI host device, most
commonly a host CPU.

CACHE LINE[7:0] R Specify the Cache Line Size—This indicates the size of a

host PCI’s cache line in 4 byte increments. The PCI
interface uses the cache line value to determine whether to
use memory write and invalidate or memory read line cycles
when the MWIEN bit is set in the PSCR.

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Chapter 3 Register Descriptions

Base Address Register 0 (PBAR0)

Offset 0x10 from PCI Config Space, 0x310 from PBAR0 Reset Value: 0xFFFFF800 Read/Write

ADRBASE[23:16]

31 30 29 28 27 26 25 24

ADRBASE[15:8]

23 22 21 20 19 18 17 16

ADRBASE[7:0]

15 14 13 12 11 10 9 8

0 0 0 0 0 0 1MEG/0 IO

7 6 5 4 3 2 1 0

PBAR0 defines the base address from which the Chip Status/Control, PCI Configuration,
Miscellaneous Status/Control, and DMA Status/Control register groups are accessed.

Mnemonic Type Description

ADRBASE[23:0] R/W Base Address—This field specifies the starting address of the

window that the PCI interface recognizes. The size of the
window defined by this register is 2 kB.

1MEG/0 R Type—When a base address register maps to PCI memory

space, a one in this read-only bit directs a PCI host to place the
window defined by this base address register within the first
1 megabyte of system memory. A zero indicates that the PCI
host can locate this window anywhere in memory space.
When a base register maps to IO space, this bit always returns

0. Writes to this bit are ignored.

IO R IO Space Indicator—A 0 in this ready-only bit directs a PCI

host to locate the address window defined by this base address
register into PCI memory space. A 1 directs the PCI host to
locate this window in PCI IO space. Writes to this bit are
ignored.

© National Instruments Corporation 3-17 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

Base Address Register 1 (PBAR1)

Offset 0x14 from PCI Config Space, 0x314 from PBAR0 Reset Value: 0xFFFFFC00 Read/Write

ADRBASE[23:16]

31 30 29 28 27 26 25 24

ADRBASE[15:8]

23 22 21 20 19 18 17 16

ADRBASE[7:0]

15 14 13 12 11 10 9 8

0 0 0 0 0 0 1MEG/0 IO

7 6 5 4 3 2 1 0

PBAR1 defines the base address from which the 4882 Register Set, 9914 Register Set, GPIB
Test/Status, and Serial Number register groups are accessed.

Mnemonic Type Description

ADRBASE[23:0] R/W Base Address—This field specifies the starting address of the

window that the PCI interface recognizes. The size of the
window defined by this register is 16 kB.

1MEG/0 R/W Type—When a base address register maps to PCI memory

space, a one in this read-only bit directs a PCI host to place the
window defined by this base address register within the first
1 megabyte of system memory. A zero indicates that the PCI
host can locate this window anywhere in memory space.
When a base register maps to IO space, this bit always returns

0. Writes to this bit are ignored.

IO R/W IO Space Indicator—A 0 in this ready-only bit directs a PCI

host to locate the address window defined by this base address
register into PCI memory space. A 1 directs the PCI host to
locate this window in PCI IO space. Writes to this bit are
ignored.

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Chapter 3 Register Descriptions

CIS Pointer Register Register (PCISR)

Offset 0x28 from PCI Config Space, 0x328 from PBAR0 Reset Value: 0x00000000 Read/Write

CIS[31:24]

31 30 29 28 27 26 25 24

CIS[23:16]

23 22 21 20 19 18 17 16

CIS[15:8]

15 14 13 12 11 10 9 8

CIS[7:0]

7 6 5 4 3 2 1 0

This register is the Cardbus Information Structure and is only used for Cardbus applications.

Mnemonic Type Description

CIS R/W Card Information Structure—Stores the 32 bit memory

address of the Card information structure for Cardbus
applications. This register is fully readable/writeable when
PERCR[CBUSEN] is set. Otherwise, this register always
returns 0.

© National Instruments Corporation 3-19 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

Subsystem ID Register (PSUBR)

Offset 0x2C from PCI Config Space, 0x32C from PBAR0 Reset Value: See Description Read Only

SUBSYSTEM_ID[15:8]

31 30 29 28 27 26 25 24

SUBSYSTEM_ID[7:0]

23 22 21 20 19 18 17 16

SUBVENDOR_ID[15:8]

15 14 13 12 11 10 9 8

SUBVENDOR_ID[7:0]

7 6 5 4 3 2 1 0

This register implements the PCI Subsystem ID and Subsystem Vendor ID fields as required
by PCI Specification 2.2. The reset value of this register depends on DIS_SUBSYS.

Mnemonic Type Description

SUBSYSTEM_ID[15:0] R Subsystem ID—If DIS_SUBSYS is asserted or not

connected, these bits return 0x0000. If DIS_SUBSYS
is actively unasserted, SUBSYSTEM_ID returns
PIDR[DEVICE_ID[15:0]].

SUBVENDOR_ID[15:0] R Subsystem Vendor ID—If DIS_SUBSYS is

asserted or not connected, these bits return 0x0000.
If DIS_SUBSYS is actively unasserted,
SUBVENDOR_ID returns PIDR[VENDOR_ID[15:0]].

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Chapter 3 Register Descriptions

Latency Request Interrupt Definition Register (PLRIDR)

Offset 0x3C from PCI Config Space, 0x33C from PBAR0 Reset Value: 0x00000100 Read/Write

MAX_LAT[7:0]

31 30 29 28 27 26 25 24

MIN_GNT[7:0]

23 22 21 20 19 18 17 16

INT_PIN[7:0]

15 14 13 12 11 10 9 8

INT_LINE[7:0]

7 6 5 4 3 2 1 0

This register implements the various fields required by PCI Specification 2.2.

Mnemonic Type Description

MAX_LAT[7:0] R Maximum Requested Latency—These bits are hard-wired

to 0. Writes to these bits are ignored.

MIN_GNT[7:0] R Minimum Bus Grant Time—These bits are hard-wired to 0.

Writes to these bits are ignored.

INT_PIN[7:0] R Interrupt Pin—This read-only byte specifies which interrupt

pin the PCI interface uses for interrupts. This byte is
hardwired to 0x01 since the PCI interface can use only the
INTA# signal. Writes to these bits are ignored.

INT_LINE[7:0] R/W Interrupt Line—This read-write byte specifies interrupt line

routing information. It has no effect on the PCI interface. The
PCI host device writes a value in this byte which an interrupt
service routine can use to determine interrupt vector and
priority information.

© National Instruments Corporation 3-21 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

Base Address Configuration Register (PBAC0R)

Offset 0x40 from PCI Config Space, 0x340 from PBAR0 Reset Value: 0x0000B4A8 Read/Write

R R R R R R R R

31 30 29 28 27 26 25 24

R R R R R R R R

23 22 21 20 19 18 17 16

B1_EN B1_S[4:0] B1_1MEG 0

15 14 10 9 8

B0_EN B0_S[4:0] B0_1MEG 0

7 6 2 1 0

This fields in this register are used to configure PBAR0 and PBAR1. Most applications should
not access this register.

Mnemonic Type Description

B0_EN
B1_EN

R/W PBAR0/PBAR1 Enable—Setting these bits enable PBAR0

or PBAR1. When PBAR0 or PBAR1 are enabled a PCI host
can read and write data from and to it, and the PCI interface
uses the contents of this register to decode incoming PCI
addresses. If PBAR0 or PBAR1 is disabled, it returns all zeros
when it is read as required by the PCI specification.

B0_S[4:0]
B1_S[4:0]

R/W PBAR0/PBAR1 Window Size—These bits specify the

amount of PCI memory space that the PBAR0 or PBAR1
requires. The amount of address space is 2

[Bx_S+1]

bytes long.
The PCI specification recommends that if the address space
being requested lies in PCI memory space, Bx_S should be
greater than 12. If the address space being requested lies in
PCI IO space, Bx_S should be greater than 8.

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Chapter 3 Register Descriptions

Mnemonic Type Description

B0_1MEG
B1_1MEG

R/W Memory Type—When PBAR0 or PBAR1 maps to PCI

memory space, setting this bit directs a PCI host to place the
window defined by this base address register within the first
megabyte of system memory. A zero indicates that the PCI
host can locate this window anywhere in memory space.
When a Base Address Register maps to IO space, this bit is
ignored. B0_1MEG/ B1_1MEG reflects the state of
PBAR0[1MEG/0]/PBAR1[1MEG/0].

R R/W Reserved—Always write 0 to these bits. These bits are read

as either 0 or 1.

© National Instruments Corporation 3-23 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

Expansion ROM Configuration Register (PERCR)

Offset 0x48 from PCI Config Space, 0x348 from PBAR0 Reset Value: 0xC7000000 Read/Write

R BEERREN CBUSEN FAST EN # WRITEEN HWRL2 HWRL1 HWRL0

31 30 29 28 27 26 25 24

R R R R R R R R

23 22 21 20 19 18 17 16

R R R R R R R R

15 14 13 12 11 10 9 8

R R R R R R R R

7 6 5 4 3 2 1 0

Mnemonic Type Description

BEERREN R/W Bus Error on Unsupported BE Codes—Setting this bit

enables the PCI interface to terminate a PCI slave transfer
with a target abort if the initiating PCI master uses a
non-aligned BE# encoding. If this bit is cleared, the PCI
interface terminates the transfer with a disconnect allowing
the PCI master to assume the transfer completed successfully,
but the interface does not actually initiate a cycle.

CBUSEN R/W Card Bus Support Enable—Setting this bit enable the CIS

pointer register (PCISR). Clearing this bit makes the PCISR
return 0.

FASTEN# R/W Fast Back-to-Back Enable—Clearing this bit sets the

PSCR[FBBC] by indicating support for fast back-to-back
cycles. Setting this bit clears PSCR[FBBC]. This feature
helps deal with finicky BIOS that might not handle fast
back-to-back properly.

WRITEEN R/W Write Enable—Setting this bit makes the PLRIDR

(MAR_LAT and MIN_GNT) writable. Clearing this bit
makes these registers read-only.

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Chapter 3 Register Descriptions

Mnemonic Type Description

HWRL[2:0] R/W Hardware Retry Limit—These bits specify the number of

times the PCI interface retries a PCI cycle before returning a
bus error to the port that initiated the transfer. The number of
retries is 2

HWRL

.

R R/W Reserved—Always write 0 to these bits. These bits are read

as 1 or 0.

© National Instruments Corporation 3-25 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

DMA Status/Control Registers

These registers are only available in PCI4882 mode. This register group is used to control and
monitor status of the DMA controller.

DMA Status/Control Registers Sorted by Offset

Registers at offsets not listed are reserved.

Offset from

PBAR0

0x500 CHOR Channel Operation Channel Operation

0x504 CHCR Channel Control Channel Control

0x508 TCR Transfer Count Transfer Count

0x50C MCR Memory Configuration Memory Configuration

0x510 MAR Memory Address Memory Address

0x514 DCR Device Configuration Device Configuration

Mnemonic Write Register Read Register

0x51C LKCR Link Configuration Link Configuration

0x520 LKAR Link Address Link Address

0x528 BAR Base Address Base Address

0x52C BCR Base Count Base Count

0x53C CHSR Reserved Channel Status

0x540 FCR Reserved FIFO Count

TNT5002 Technical Reference Manual 3-26 ni.com

DMA Status/Control Registers Sorted by Mnemonic

Registers at offsets not listed are reserved.

Offset from

Mnemonic

BAR 0x528 Base Address Base Address

BCR 0x52C Base Count Base Count

CHCR 0x504 Channel Control Channel Control

CHOR 0x500 Channel Operation Channel Operation

CHSR 0x53C Reserved Channel Status

DCR 0x514 Device Configuration Device Configuration

FCR 0x540 Reserved FIFO Count

LKAR 0x520 Link Address Link Address

LKCR 0x51C Link Configuration Link Configuration

MAR 0x510 Memory Address Memory Address

PBAR0

Write Register Read Register

Chapter 3 Register Descriptions

MCR 0x50C Memory Configuration Memory Configuration

TCR 0x508 Transfer Count Transfer Count

© National Instruments Corporation 3-27 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

DMA Status/Control Register Descriptions

Base Address Register (BAR)

Offset 0x528 from PBAR0 Reset Value: 0x00000000 Read/Write

BAR[31:24]

31 30 29 28 27 26 25 24

BAR[23:16]

23 22 21 20 19 18 17 16

BAR[15:8]

15 14 13 12 11 10 9 8

BAR[7:0]

7 6 5 4 3 2 1 0

Mnemonic Type Description

BAR[31:0] R/W Base Address Register—The BAR is loaded automatically

by the DMA Controller with the address from the current link
node.

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Chapter 3 Register Descriptions

Base Count Register (BCR)

Offset 0x52C from PBAR0 Reset Value: 0x00000000 Read/Writee

BCR[31:24]

31 30 29 28 27 26 25 24

BCR[23:16]

23 22 21 20 19 18 17 16

BCR[15:8]

15 14 13 12 11 10 9 8

BCR[7:0]

7 6 5 4 3 2 1 0

Mnemonic Type Description

BCR[31:0] R/W Base Count Register—The BCR is loaded automatically by

the DMA Controller with the count from the current link
node.

© National Instruments Corporation 3-29 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

Channel Control Register (CHCR)

Offset 0x504 from PBAR0 Reset Value: 0x55550000 Read/Write

0 1 0 1 0 1 0 1

31 30 29 28 27 26 25 24

0 1 0 1 0 1 0 1

23 22 21 20 19 18 17 16

0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

0 0 0 0 DIR RMODE[2:0]

7 6 5 4 3 2 1 0

This register is used to configure the DMA controller and should be configured prior to any
DMA transfer.

Mnemonic Type Description

DIR R/W Transfer Direction—DIR indicates the direction of data

flow of a DMA transfer.

DIR Direction

0 .....................Memory to GPIB

1 .....................GPIB to Memory

RMODE[2:0] R/W Transfer Mode Select—Determines the mode of operation

for the DMA Controller Channel.

RMODE[2:0] DMA Type

100 .................... Link Short

other ..................Reserved

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Chapter 3 Register Descriptions

Channel Operation Register (CHOR)

Offset 0x500 from PBAR0 Reset Value: 0x00000512 Read/Write

DMARESET R R R R R R R

31 30 29 28 27 26 25 24

R R R R R R R R

23 22 21 20 19 18 17 16

R R R R 0 1 0 1

15 14 13 12 11 10 9 8

CLR DONE R R FRESET ABORT STOP 1 START

7 6 5 4 3 2 1 0

This register is used to control DMA transfers, including starting and stopping transfers.

Mnemonic Type Description

DMARESET R/W DMA Reset—Setting this bit causes the DMA Controller to

be reset. Refer to Chapter 8, Reset Considerations, for more
information.

CLR DONE R/W Clear Done Status Bit—Setting this bit clears the DONE

status bit. The DONE status bit is also automatically cleared
when a new operation is started.

FRESET R/W FIFO Reset—Setting this bit clears the FIFO. The bit is

automatically cleared.

ABORT R/W Abort DMA Operation—When this bit is written with a one,

the current DMA stops after the completion of any transfer
started before the bit was set. All bytes in the FIFO are lost.
This bit clears when START is set.

STOP R/W Stop DMA—When this bit is written with a one, the current

DMA is stopped after the FIFO has been allowed to empty.
This bit clears when START is set.

© National Instruments Corporation 3-31 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

Mnemonic Type Description

START R/W Start DMA Operation—A DMA transfer is started by

writing this bit with a one after programming the appropriate
address, count, configuration, and control registers.

R R/W Reserved—Always write 0 to these bits. These bits are read

as either 0 or 1.

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Chapter 3 Register Descriptions

Channel Status Register (CHSR)

Offset 0x53C from PBAR0 Reset Value: 0x00000000 Read Only

R R R R R R DONE R

31 30 29 28 27 26 25 24

R R R R R R R R

23 22 21 20 19 18 17 16

ERROR SABORT R STOPS OPERR[1:0] RFERR R

15 14 13 12 11 10 9 8

R DRQA R MERR[1:0] DERR[1:0]

7 6 5 4 3 2 1 0

This register contains status information about the DMA Controller.

Mnemonic Type Description

DONE R DMA Done—This bit clears when the DMA is started and

sets when the transfer is completed normally or by an error.

ERROR R Error Occurred—Indicates the transfer completed due to an

error. The other bits indicate the type of error.

SABORT R Software Abort—This bit asserts when CHOR[ABORT]

is set.

STOPS R Stopped Status—This bit sets when CHOR[STOP] is set.

Note: STOPS is not status that the DMA Controller has
stopped but that the STOP bit was written. To get status that
the DMA Controller has STOPPED, enable the DONE IE,
then write STOP in the CHOR to get an interrupt that the
DMA Controller has actually stopped.

© National Instruments Corporation 3-33 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

Mnemonic Type Description

OPERR[1:0] R Operation Error Code—An illegal FIFO operation such as

reading an empty FIFO or writing a full FIFO occurred.
OPERR is just a status bit, it does not stop the DMA
Controller from finishing a transfer.

OPERR[1:0] Error

00 ......................... FIFO Error

01 ......................... Bus Error

others.................... Reserved

XFERR R Transfer Error—One or more of the transfer processes

terminated with an error. Refer to the LERR, MERR, and
DERR bit to determine the type.

DRQA R DRQA Status—The state of the DRQ signal from the GPIB

circuitry.

MERR[1:0] R Memory Transfer Error—These bits indicate the type of

error which stopped the memory transfer process.

MERR[1:0] Error

00 ...................... No Error

01 ......................Bus Error

10 ...................... Retry Limit Exceeded

11 ......................Other Error

DERR[1:0] R Device Transfer Error—These bits indicate the type of error

which stopped the device transfer process.

DERR[1:0] Error

00 ...................... No Error

01 ......................Bus Error

10 ...................... Retry Limit Exceeded

11 ......................Other Error

R R Reserved—Always write 0 to these bits. These bits are read

as either 0 or 1.

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Chapter 3 Register Descriptions

Device Configuration Register (DCR)

Offset 0x514 from PBAR0 Reset Value: 0x00040241 Read/Write

0 0 0 R R R R R

31 30 29 28 27 26 25 24

RL[2:0] RD[1:0] REQS[2:0]

23 22 21 20 19 18 17 16

R R ASEQ[3:0] PSIZE[1:0]

15 14 13 12 11 10 9 8

R 1 R R R 0 R 1

7 6 5 4 3 2 1 0

This register is used to configure how the DMA Controller accesses the GPIB circuitry. This
register should not be accessed for most applications.

Mnemonic Type Description

RL[2:0] R/W Retry Limit—These bits determine the maximum number of

times a single transfer may be retried. If the limit is exceeded,
a retry error is reported and the operation is stopped. When
programmed to zero, the first retry results in an error. The
limit selects a power of two number of retries that cause an
error 0, 1, 2, 4, 8, …, 64.

RD[1:0] R/W Request Delay Limiter—These bits determine the delay that

must elapse between transfers. This limit is always enforced
for retry cycles. The limit may be enforced for all cycle when
the request mode is internal and limited. This has the
following values:

RD[1:0] Clock Cycles

00..................... 0

01..................... 32

10..................... 512

11..................... 8192

© National Instruments Corporation 3-35 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

Mnemonic Type Description

REQS[2:0] R/W Request Source—This selects the type of DMA request for

the process.

REQS[2:0] Request Source

000 .............Internal Maximum Rate

001 .............Internal Limited Rate,

uses RD[1:0] values

010 .............Disable Process. Programmed

I/O to the FIFO

100 .............Hardware Request, DRQ line

from the internal IO bus

others ...........Reserved

ASEQ[3:0] R/W Address Sequence Selection—Determines how the Device

address is modified for the next transfer. ASEQ[3] is the sign
bit while the others select a power of two to multiply by the
Port Transfer Size.

ASEQ[2:0] ASEQ[3] = 0 ASEQ[3] = 1

(increment address) (decrement address)

000 ...........+ 0..............................– 0

001 ...........+ 1 * SIZE .................– 1 * SIZE

010 ...........+ 2 * SIZE .................– 2 * SIZE

011 ...........+ 4 * SIZE .................– 4 * SIZE

100 ...........+ 8 * SIZE .................– 8 * SIZE

101 ...........+ 16 * SIZE ...............– 16 * SIZE

110 ...........+ 32 * SIZE ...............– 32 * SIZE

111 ...........+ 64 * SIZE ...............– 64 * SIZE

where size is defined as follows:

PSIZE[1:0] SIZE (bytes)

00 ...................invalid

01 ...................1

10 ...................2

11 ...................4

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Chapter 3 Register Descriptions

Mnemonic Type Description

PSIZE[1:0] R/W Port Transfer Size—The size of the port for the transfer. The

actual transfer size may be smaller when aligning addresses
and draining the FIFO.

PSIZE[1:0] Port Transfer Size

00................... Reserved

01................... 8-bit

10................... 16-bit

11................... 32-bit

R R/W Reserved—Always write 0 to these bits. These bits are read

as either 0 or 1.

© National Instruments Corporation 3-37 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

FIFO Count Register (FCR)

Offset 0x540 from PBAR0 Reset Value: 0x00000000 Read Only

R R R R R R R R

31 30 29 28 27 26 25 24

ECR[7:0]

23 22 21 20 19 18 17 16

R R R R R R R R

15 14 13 12 11 10 9 8

FCR[7:0]

7 6 5 4 3 2 1 0

This register contains the current number of empty bytes positions in the DFIFO. This register
should not be accessed for most applications.

Mnemonic Type Description

ECR[7:0] R Empty FIFO Locations—ECR indicates the number of

empty locations (bytes) in the DFIFO.

FCR[7:0] R FIFO Count—FCR indicates the number of bytes remaining

in the DFIFO. A transfer is complete when both the TCR and
FCR reach zero.

R R Reserved—These bits are read as either 0 or 1.

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Chapter 3 Register Descriptions

Link Address Register (LKAR)

Offset 0x520 from PBAR0 Reset Value: 0x00000000 Read/Write

LKAR[31:24]

31 30 29 28 27 26 25 24

LKAR[23:16]

23 22 21 20 19 18 17 16

LKAR[15:8]

15 14 13 12 11 10 9 8

LKAR[7:0]

7 6 5 4 3 2 1 0

Mnemonic Type Description

LKAR[31:0] R/W Link Address Register—The LKAR points to the next entry

when chaining is used. The address of the first link is
manually programmed to the LKAR, and the register is
modified as subsequent links are loaded from memory. The
LKAR must be aligned to the boundary of the programmed
transfer size.

© National Instruments Corporation 3-39 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

Link Configuration Register (LKCR)

Offset 0x51C from PBAR0 Reset Value: 0x00000000 Read/Write

R R R R R R R R

31 30 29 28 27 26 25 24

RL[2:0] R R R R

23 22 21 20 19 18 17 16

R R R R ASEQ[1:0] PSIZE[1:0]

15 14 13 12 11 10 9 8

R R R R R R R R

7 6 5 4 3 2 1 0

This register is used to configure how the DMA Controller fetches links from memory.

Mnemonic Type Description

RL[2:0] R/W Retry Limit—These bits determine the maximum number of

times a single transfer may be retried. If the limit is exceeded,
a retry error is reported and the operation is stopped. When
programmed to zero, the first retry results in an error. The
limit selects a power of two number of retries that cause an
error 0, 1, 2, 4, 8, …, 64.

ASEQ[1:0] R/W Address Sequence Selection—Determines how the address

is modified for the next transfer.

ASEQ[1:0] Next Address Selection

00 ...................Don’t Count

01 ...................Increment

10 ...................Decrement

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Chapter 3 Register Descriptions

Mnemonic Type Description

PSIZE[1:0] R/W Port Transfer Size—The size of the port for the transfer.

PSIZE[1:0] Port Size

01................... 8-bit

10................... 16-bit

11................... 32-bit

The link process packs smaller data into the 32 bit dwords
required by the link process. Unlike data transfers, the
transfers must be aligned on the proper boundary.

R R/W Reserved—Always write 0 to these bits. These bits are read

as either 0 or 1.

© National Instruments Corporation 3-41 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

Memory Address Register (MAR)

Offset 0x510 from PBAR0 Reset Value: 0x00000000 Read/Write

MAR[31:24]

31 30 29 28 27 26 25 24

MAR[23:16]

23 22 21 20 19 18 17 16

MAR[15:8]

15 14 13 12 11 10 9 8

MAR[7:0]

7 6 5 4 3 2 1 0

Mnemonic Type Description

MAR[31:0] R/W Memory Address Register—The MAR is loaded

automatically by the DMA Controller with the mem_address
from the current link node and incremented according to
MCR[ASEQ] as data is read from memory. If the address is
not aligned to the programmed size boundary as specified by
MCR[PSIZE], the DMA Controller does smaller transfer
until alignment occurs.

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Chapter 3 Register Descriptions

Memory Configuration Register (MCR)

Offset 0x50C from PBAR0 Reset Value: 0x00040700 Read/Write

R R R R R R R R

31 30 29 28 27 26 25 24

R R R R R 1 0 0

23 22 21 20 19 18 17 16

R R 0 0 0 1 PSIZE[1:0]

15 14 13 12 11 10 9 8

R R R R R R R R

7 6 5 4 3 2 1 0

This register is used to configure how the DMA Controller writes and reads data from to and
from memory.

Mnemonic Type Description

PSIZE[1:0] R/W Port Transfer Size—The size of the port for the transfer. The

actual transfer size may be smaller when aligning addresses
and draining the FIFO.

PSIZE[1:0] Port Transfer Size

00..................... Reserved

01..................... 8-bit

10..................... 16-bit

11..................... 32-bit

R R/W Reserved—Always write 0 to these bits. These bits are read

as either 0 or 1.

© National Instruments Corporation 3-43 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

Transfer Count Register (TCR)

Offset 0x508 from PBAR0 Reset Value: 0x00000000 Read/Write

TCR[31:24]

31 30 29 28 27 26 25 24

TCR[23:16]

23 22 21 20 19 18 17 16

TCR[15:8]

15 14 13 12 11 10 9 8

TCR[7:0]

7 6 5 4 3 2 1 0

Mnemonic Type Description

TCR[31:0] R/W Transfer Count Register—The TCR is loaded automatically

by the DMA Controller with the count from the current link
node. The TCR is automatically decremented as data enters
the DFIFO.

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Chapter 3 Register Descriptions

These registers are only available in PCI4882 and GEN4882 modes. These registers control the GPIB circuitry.

Register Offset Ty pe Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DIR 0x00 R DIR7 DIR6 DI R5 DIR4 DIR3 DIR2 DIR1 DIR0

ISR1 0x02 R CPT APT DET END DEC ERR DO DI

IMR1 0x02 W CPT IE APT IE DET IE END IE DEC IE ERR IE DO IE DI IE

ISR2 0x04 R INT SRQI LOK REM R LOKC REMC ADSC

IMR2 0x04 W 0 SRQI IE 0 0 0 LOKC IE REMC IE ADSC IE

SPSR 0x06 R S8 PEND S6 S5 S4 S3 S2 S1

SPMR 0x06 W S8 rsv/RQS S6 S5 S4 S3 S2 S1

ADSR 0x08 R R AT N N SPMS LPAS TPAS LA TA MINOR

ADMR 0x08 W TON LON 1 1 0 0 ADM1 ADM0

CNT2 0x09 R/W CNT23 CNT22 CNT21 CNT20 CNT19 CNT18 CNT17 CNT16

CPTR 0x0A R CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0

AUXMR 0x0A W AUX7 AUX6 AUX5 AUX4 AUX3 AUX2 AUX1 AUX0

AUXRA 0x0A W 1 0 0 BIN XEOS REOS HLDE HLDA

AUXRB 0x0A W 1 0 1 ISS 0 TRI SPEOI CPT_ENABLE

AUXRE 0x0A W 1 1 0 0 DHADT DHADC DHDT DHDC

AUXRF 0x0A W 1 1 0 1 DHATA DHALA DHUNTL DHALL

AUXRG 0x0A W 0 1 0 0 NTNL RPP2 DISTCT CHES

AUXRI 0x0A W 1 1 1 0 USTD PP2 0 SISB

AUXRJ 0x0A W 1 1 1 1 TM3 TM2 TM1 TM0

PPR 0x0A W 0 1 1 U S P3 P2 P1

CNT3 0x0B R/W CNT31 CNT30 CNT29 CNT28 CNT27 CNT26 CNT25 CNT24

ADR0 0x0C R/W 0 DT0 DL0 PRIMADDR5 PRIMADDR4 PRIMADDR3 PRIMADDR2 PRIMADDR1

ADR1 0x0C W 1 DT1 DL1 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1

HSSEL 0x0D W 0 0 GOTOSIDS NODMA 0 0 0 ONEC

4882 Register Set

4882-Mode Registers Sorted by Offset

© National Instruments Corporation 3-45 TNT5002 Technical Reference Manual

ADR1 0x0E R EOI DT1 DL1 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1

Chapter 3 Register Descriptions

Register Offset Ty pe Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

EOSR 0x0E W EOS7 EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOS0

AUXRK 0x0F W 0 0 0 0 0 0 TM5 TM4

AUXRL 0x0F W 0 0 0 1 0 0 0 EN_IBSTA

STS1 0x10 R DONE SC IN DRQ STOP DAV HALT GSYNC

CFG 0x10 W 0 TL CHLTE IN A/BN CCEN 0 0 16/8N

DSR 0x11 R DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1

PT1 0x11 W 0 0 PT1_EN PT1_4 PT1_3 PT1_2 PT1_1 PT1_0

NIC_DELAY 0x11 W 0 1 0 NIC_DELAY4 NIC_DELAY3 NIC_DELAY2 NIC_DELAY1 NIC_DELAY0

DAV_HOLD 0x11 W 1 0 0 DAV_HOLD4 DAV_HOLD3 DAV_HOLD2 DAV_HOLD1 DAV_HOLD0

DIO_SETUP 0x11 W 1 1 0 DIO_SETUP4 DIO_SETUP 3 DIO_SETUP2 DIO_SETUP1 DIO_SETUP0

IMR3 0x12 R/W 0 GFIFO_RDY IE 0 STOP IE NFF IE NEF IE TLCINT IE DONE IE

HIER 0x13 W DGA DGB 0 NO_TSETUP 0 0 0 PMT_W_EOS

CNT0 0x14 R/W CNT7 CNT6 CNT5 CNT 4 CNT3 CNT2 CNT1 CNT0

MISC 0x15 W 0 0 0 HSE SLOW WRAP NOAS NOTS

CNT1 0x16 R/W CNT15 CNT14 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8

CSR 0x17 R V3 V2 V1 V0 1 R 0 0

KEYREG 0x17 W 0 0 MSTD NO_T1 0 0 0 0

GFIFO 0x18 R/W GFIFO7 GFIFO6 GFIFO5 GFIFO4 GFIFO3 GFIFO2 GFIFO1 GFIFO0

GFIFO 0x19 R/W GFIFO15 GFIFO14 GFIFO13 GFIFO12 GFIFO11 GFIFO10 GFIFO9 GFIFO8

ISR3 0x1A R INT GFIFO_RDY R STOP NFF NEF TLCINT DONE

SASR 0x1B R NBA AEHS ANHS1 ANHS2 ADHS AC RDY SH1A SH1B

DCR 0x1B W DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1

STS2 0x1C R 1 16/8N 0 1 AFFN AEFN BFFN BEFN

CMDR 0x1C W CMD7 CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0

ISR0 0x1D R NBA STBO NL EOS IFCI ATN I TO SYNC

IMR0 0x1D W 1 STBO IE NLEN BTO IFCI IE ATN I I E TO IE SYNC IE

BSR 0x1F R AT N DAV NDAC NRFD EOI SRQ IFC REN

BCR 0x1F W 0 DAV NDAC NRFD EOI SRQ 0 0

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Chapter 3 Register Descriptions

Register Offset Ty pe Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADMR 0x08 W TON LON 1 1 0 0 ADM1 ADM0

ADR0 0x0C R/W 0 DT0 DL0 PRIMADDR5 PRIMADDR4 PRIMADDR3 PRIMADDR2 PRIMADDR1

ADR1 0x0C W 1 DT1 DL1 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1

ADR1 0x0E R EOI DT1 DL1 ADDR5 ADDR4 ADDR3 ADDR2 ADDR 1

ADSR 0x08 R R AT N N SPMS LPAS TPAS LA TA MINOR

AUXMR 0x0A W AUX7 AUX6 AUX5 AUX4 AUX3 AUX2 AUX1 AUX0

AUXRA 0x0A W 1 0 0 BIN XEOS REOS HLDE HLDA

AUXRB 0x0A W 1 0 1 ISS 0 TRI SPEOI CPT_ENABLE

AUXRE 0x0A W 1 1 0 0 DHADT DHADC DHDT DHDC

AUXRF 0x0A W 1 1 0 1 DHATA DHALA DHUNTL DHALL

AUXRG 0x0A W 0 1 0 0 NTNL RPP2 DISTCT CHES

AUXRI 0x0A W 1 1 1 0 USTD PP2 0 SISB

AUXRJ 0x0A W 1 1 1 1 TM3 TM2 TM1 TM0

AUXRK 0x0F W 0 0 0 0 0 0 TM5 TM4

AUXRL 0x0F W 0 0 0 1 0 0 0 EN_IBSTA

BCR 0x1F W AT N DAV NDAC NRFD EOI SRQ IFC REN

BSR 0x1F R 0 DAV NDAC NRFD EOI SRQ 0 0

CFG 0x10 W 0 TL CHLTE IN A/BN CCEN0 0 0 16/8N

CMDR 0x1C W CMD7 CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0

CNT0 0x14 R/W CNT7 CNT6 CNT5 CNT 4 CNT3 CNT2 CNT1 CNT0

CNT1 0x16 R/W CNT15 CNT14 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8

CNT2 0x09 R/W CNT23 CNT22 CNT21 CNT20 CNT19 CNT18 CNT17 CNT16

CNT3 0x0B R/W CNT31 CNT30 CNT29 CNT28 CNT27 CNT26 CNT25 CNT24

CPTR 0x0A R CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0

CSR 0x17 R V3 V2 V1 V0 1 R 0 0

DAV_HOLD 0x11 W 1 0 0 DAV_HOLD4 DAV_HOLD3 DAV_HOLD2 DAV_HOLD1 DAV_HOLD0

4882-Mode Registers Sorted by Mnemonic

DCR 0x1B W DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1

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Chapter 3 Register Descriptions

Register Offset Ty pe Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DIO_SETUP 0x11 W 1 1 0 DIO_SETUP4 DIO_SETUP 3 DIO_SETUP2 DIO_SETUP1 DIO_SETUP0

DIR 0x00 R DIR7 DIR6 DI R5 DIR4 DIR3 DIR2 DIR1 DIR0

DSR 0x11 R DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1

EOSR 0x0E W EOS7 EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOS0

GFIFO 0x18 R/W GFIFO7 GFIFO6 GFIFO5 GFIFO4 GFIFO3 GFIFO2 GFIFO1 GFIFO0

GFIFO 0x19 R/W GFIFO15 GFIFO14 GFIFO13 GFIFO12 GFIFO11 GFIFO10 GFIFO9 GFIFO8

HIER 0x13 W DGA DGB 0 NO_TSETUP 0 0 0 PMT_W_EOS

HSSEL 0x0D W 0 0 GOTOSIDS NODMA 0 0 0 ONEC

IMR0 0x1D W 1 STBO IE NLEN BTO IFCI IE ATN I I E TO IE SYNC IE

ISR0 0x1D R NBA STBO NL EOS IFCI ATN I TO SYNC

IMR1 0x02 W CPT IE APT IE DET IE END IE DEC IE ERR IE DO IE DI IE

ISR1 0x02 R CPT APT DET END DEC ERR DO DI

IMR2 0x04 W 0 SRQI IE 0 0 0 LOKC IE REMC IE ADSC IE

ISR2 0x04 R INT SRQI LOK REM R LOKC REMC ADSC

IMR3 0x12 R/W 0 GFIFO_RDY IE 0 STOP IE NFF IE NEF IE TLCINT IE DONE IE

ISR3 0x1A R INT GFIFO_RDY R STOP NFF NEF TLCINT DONE

KEYREG 0x17 W 0 0 MSTD NO_T1 0 0 0 0

MISC 0x15 W 0 0 0 HSE SLOW WRAP NOAS NOTS

NIC_DELAY 0x11 W 0 1 0 NIC_DELAY4 NIC_DELAY3 NIC_DELAY2 NIC_DELAY1 NIC_DELAY0

PPR 0x0A W 0 1 1 U S P3 P2 P1

PT1 0x11 W 0 0 PT1_EN PT1_4 PT1_3 PT1_2 PT1_1 PT1_0

SASR 0x1B R NBA AEHS ANHS1 ANHS2 ADHS AC RDY SH1A SH1B

SPMR 0x06 W S8 rsv/RQS S6 S5 S4 S3 S2 S1

SPSR 0x06 R S8 PEND S6 S5 S4 S3 S2 S1

STS1 0x10 R DONE SC IN DRQ STOP DAV HALT GSYNC

STS2 0x1C R 1 16/8N 0 1 AFFN AEFN BFFN BEFN

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Chapter 3 Register Descriptions

4882-Mode Register Descriptions

Address Mode Register (ADMR)

Offset 0x08 in 4882 Register Set Reset Value: 0x30 Write Only

ADDR_MODE

7 0

The ADMR is used to select the addressing mode and should be configured before clearing
pon.

Mnemonic Type Description

ADDR_MODE W Address Mode—The ADMR selects the addressing mode of

the device. The following lists all address modes. Refer to the
following table for more information on each mode.

Addressing Mode ADMR

No Addressing.............................. 0x30

Normal Addressing ...................... 0x31

Extended Addressing.................... 0x32

Normal Dual Addressing.............. 0x31

Extended Dual Addressing........... 0x33

Normal Multiple Addressing........ 0x30

Extended Multiple Addressing..... 0x30

Talk Only ...................................... 0xB0

Listen Only................................... 0x70

Talk and Listen ............................. 0xF0

Number of

Addressing Mode ADMR

No Addressing 0x30 0 N/A N/A

Normal Addressing 0x31 1 Primary Address Disabled

Extended Addressing 0x32 1 Primary Address Secondary Address

Normal Dual Addressing 0x31 2 Device 1 Primary Address Device 2 Primary Address

Extended Dual Addressing 0x33 2 Device 1 Primary Address Device 2 Primary Address

Normal Multiple Addressing 0x30 3+ Disabled Disabled

© National Instruments Corporation 3-49 TNT5002 Technical Reference Manual

GPIB Devices

ADR0 ADR1

Chapter 3 Register Descriptions

Number of

Addressing Mode ADMR

Extended Multiple Addressing 0x30 3+ Disabled Disabled

Talk Only 0xB0 1 Disabled Disabled

Listen Only 0x70 1 Disabled Disabled

Talk and Listen 0xF0 1 Disabled Disabled

GPIB Devices

ADR0 ADR1

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Chapter 3 Register Descriptions

Address Write Register 0 (ADR0)

Offset 0x0C in 4882 Register Set Reset Value: 0x00 Write Only

0 DT0 DL0 PRIM_ADDR[4:0]

7 6 5 4 0

ADR0 configures how the device is addressed on the GPIB.

Mnemonic Type Description

DT0 W Disable Primary Talker—If DT0 is set, the primary Talker

is not enabled and PRIM_ADDR is not compared to GPIB
Talk commands. If DT0 is cleared, the primary Talker
responds to GPIB Talk commands matching PRIM_ADDR.

DL0 W Disable Primary Listener—If DL0 is set, the primary

Listener is not enabled and PRIM_ADDR is not compared to
GPIB Listen commands. If DL0 is cleared, the primary
Listener responds to GPIB Listen commands matching
PRIM_ADDR.

PRIM_ADDR[4:0] W Primary Address—The meaning of PRIM_ADDR depends

on the Addressing Mode as selected by ADMR.

Addressing Mode PRIM_ADDR

No Addressing............................ Disabled

Normal Addressing .................... Primary Address

Extended Addressing.................. Primary Address

Normal Dual Addressing............ Device 1 Primary Address

Extended Dual Addressing......... Device 1 Primary Address

Normal Multiple Addressing...... Disabled

Extended Multiple Addressing... Disabled

Talk Only .................................... Disabled

Listen Only................................. Disabled

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Chapter 3 Register Descriptions

Address Read Register 0 (ADR0)

Offset 0x0C in 4882 Register Set Reset Value: 0x00 Read Only

0 DT0 DL0 PRIM_ADDR[4:0]

7 6 5 4 0

ADR0 reflects the GPIB addressing configuration of the device.

Mnemonic Type Description

DT0 R Disable Primary Talker—If DT0 is set, the primary Talker

is not enabled and PRIM_ADDR is not compared to GPIB
Talk commands. If DT0 is cleared, the primary Talker
responds to GPIB Talk commands matching PRIM_ADDR.

DL0 R Disable Primary Listener—If DL0 is set, the primary

Listener is not enabled and PRIM_ADDR is not compared to
GPIB Listen commands. If DL0 is cleared, the primary
Listener responds to GPIB Listen commands matching
PRIM_ADDR.

PRIM_ADDR[4:0] R Primary Address—The meaning of PRIM_ADDR depends

on the Addressing Mode as selected by ADMR.

Addressing Mode PRIM_ADDR

No Addressing ............................N/A

Normal Addressing .....................Primary Address

Extended Addressing ..................Primary Address

Normal Dual Addressing ............Device 1 Primary Address

Extended Dual Addressing .........Device 1 Primary Address

Normal Multiple Addressing ......Disabled

Extended Multiple Addressing ...Disabled

Talk Only ....................................Disabled

Listen Only .................................Disabled

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Chapter 3 Register Descriptions

Address Write Register 1 (ADR1)

Offset 0x0C in 4882 Register Set Reset Value: 0x80 Write Only

1 DT1 DL1 ADDR[4:0]

7 6 5 4 0

ADR1 configures how the device is addressed on the GPIB. ADR1 should be configured
before clearing pon.

Mnemonic Type Description

DT1 W Disable Talker—If DT1 is set, the secondary Talker is not

enabled and ADDR is not compared to GPIB Talk commands.
If DT1 is cleared, the secondary Talker responds to GPIB Talk
commands matching ADDR.

DL1 W Disable Listener—If DL1 is set, the secondary Listener is

not enabled and ADDR is not compared to GPIB Listen
commands. If DL1 is cleared, the secondary Listener
responds to GPIB Listen commands matching ADDR.

ADDR[4:0] W Other Address—Some of the Addressing Modes selected in

the ADMR require an additional address. The following table
shows the meaning of ADDR for each Addressing Mode.

Addressing Mode ADR1

No Addressing............................ Disabled

Normal Addressing .................... Disabled

Extended Addressing.................. Secondary Address

Normal Dual Addressing............ Device 2 Primary Address

Extended Dual Addressing......... Device 2 Primary Address

Normal Multiple Addressing...... Disabled

Extended Multiple Addressing... Disabled

Talk Only .................................... Disabled

Listen Only................................. Disabled

Talk and Listen ........................... Disabled

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Chapter 3 Register Descriptions

Address Read Register 1 (ADR1)

Offset 0x0E in 4882 Register Set Reset Value: 0x00 Read Only

EOI DT1 DL1 ADDR[4:0]

7 6 5 4 0

ADR1 reflects the GPIB addressing configuration of the device.

Mnemonic Type Description

EOI R EOI Received—This bit indicates the state of the EOI# line

when the most recent data byte was accepted. If EOI is set, the
EOI# line was asserted.

DT1 R Disable Talker—If DT1 is set, the secondary Talker is not

enabled and ADDR is not compared to GPIB Talk commands.
If DT1 is cleared, the secondary Talker responds to GPIB Talk
commands matching ADDR.

DL1 R Disable Listener—If DL1 is set, the secondary Listener is

not enabled and ADDR is not compared to GPIB Listen
commands. If DL1 is cleared, the secondary Listener
responds to GPIB Listen commands matching ADDR.

ADDR[4:0] R Other Address—Some of the Addressing Modes selected in

the ADMR require an additional address. The following table
shows the meaning of ADDR for each Addressing Mode.

Addressing Mode ADR1

No Addressing ............................Disabled

Normal Addressing .....................Disabled

Extended Addressing ..................Secondary Address

Normal Dual Addressing ............Device 2 Primary Address

Extended Dual Addressing .........Device 2 Primary Address

Normal Multiple Addressing ......Disabled

Extended Multiple Addressing ...Disabled

Talk Only ....................................Disabled

Listen Only .................................Disabled

Talk and Listen............................Disabled

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Chapter 3 Register Descriptions

Address Status Register (ADSR)

Offset 0x08 in 4882 Register Set Reset Value: 0x00 Read Only

R AT N N SPMS LPAS TPAS LA TA MINOR

7 6 5 4 3 2 1 0

The ADSR reflects various states and signals used to determine the address status.

Mnemonic Type Description

AT N N R Attention—ATNN reflects the level of the ATN# pin.

If ATNN is cleared, the ATN# signal is asserted.

SPMS R Serial Poll Mode State—SPMS indicates whether the Talker

state machine is in SPMS. When SPMS and TA are both set,
the Talker can send a serial poll response byte.

SPMS is set by:
SPE & ACDS

SPMS is cleared by:
(SPD & ACDS) + pon + IFC

LPAS R Listener Primary Address State—LPAS indicates that the

Listener has received its primary listen address (MLA). LPAS
is cleared after receiving any primary command byte that is
not MLA.

LPAS is set by:
MLA & ACDS

LPAS is cleared by:
(PCG & ~MLA & ACDS) + pon

TPAS R Talker Primary Address State—TPAS indicates that the

Talker has received its primary talk address (MTA). TPAS is
cleared after receiving any primary command byte that is not
MTA.

TPAS is set by:
MTA & ACDS

TPAS is cleared by:
(PCG & ~MTA & ACDS) + pon

LA R Listen Addressed—When LA is set, the Listener state

machine is in LACS or LADS.

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Chapter 3 Register Descriptions

Mnemonic Type Description

TA R Talk Addressed—When TA is set, the Talker state machine

is in TADS, TACS, or SPAS.

MINOR R Major/Minor—In normal dual addressing mode or extended

dual addressing mode, MINOR indicates whether the
information in the ADSR bits apply to the major or minor
Talker and Listener state machines. The major address is the
address written to ADR0. The minor address is the address
written to ADR1. MINOR sets when the last addressing
command received was for the minor address. MINOR clears
when the last addressing command received was for the major
address. Minor never sets in other modes.

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Chapter 3 Register Descriptions

Auxilliary Mode Register (AUXMR)

Offset 0x0A in 4882 Register Set Reset Value: 0x00 Write Only

AUXMR_CMD

7 0

The AUXMR is used to issue auxiliary commands to the device. Once a command is written
to the AUXMR, it affects some part of the circuit and another command may be written
immediately afterwards. All commands not appearing in the following table are reserved.

AUXMR

Command

CH_RST 0x02 Chip Reset—CH_RST asserts the local pon message.

Va lu e Description

The pon message logically disconnects the TNT5002
from the GPIB. In addition, CH_RST:

• Clears all bits in SPMR, AUXRA, AUXRB, AUXRE,
AUXRF, AUXRG, AUXRI, AUXRJ, AUXRK, BCR,
MISC, HIER, EOSR and PT1.

• Clears the ist parallel poll flag

• Sets the PPMODE1 bit in PPR

Refer to Chapter 8, Reset Considerations, for more
information about reseting the TNT5002.

CLR_ADSC 0x5B Clear ISR2[ADSC]—When AUXRI[SISB] is set,

CLR_ADSC is used to clear ISR2[ADSC].

CLR_ATNI 0x5D Clear ISR0[ATNI]—When AUXRI[SISB] is set,

CLR_ATNI is used to clear ISR0[ATNI].

CLR_DEC 0x56 Clear ISR1[DEC]—When AUXRI[SISB] is set,

CLR_DEC is used to clear ISR1[DEC].

CLR_DET 0x54 Clear ISR1[DET]—When AUXRI[SISB] is set,

CLR_DET is used to clear ISR1[DET].

CLR_END 0x55 Clear ISR1[END]—When AUXRI[SISB] is set,

CLR_END is used to clear ISR1[END].

CLR_ERR 0x57 Clear ISR1[ERR]—When AUXRI[SISB] is set,

CLR_ERR is used to clear ISR1[ERR].

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Chapter 3 Register Descriptions

AUXMR

Command

Va lu e Description

CLR_IFCI 0x5C Clear ISR0[IFCI]—When AUXRI[SISB] is set,

CLR_IFCI is used to clear ISR0[IFCI].

CLR_SRQI 0x58 Clear ISR2[SRQI]—When AUXRI[SISB] is set,

CLR_SRQI is used to clear ISR2[SRQI].

CLR_LOKC 0x59 Clear ISR2[LOKC]—When AUXRI[SISB] is set,

CLR_LOKC is used to clear ISR2[LOKC].

CLR_REMC 0x5A Clear ISR2[REMC]—When AUXRI[SISB] is set,

CLR_REMC is used to clear ISR2[REMC].

CLR_SYNC/
SET_SYNC

0x5E/0x5F Clear/Set ISR0[SYNC]—CLR_SYNC and SET_SYNC

are used to set and clear ISR0[SYNC].

HLDI 0x51 Holdoff Immediately—HLDI prevents the Acceptor

state machine from transitioning from ANRS to ACRS.
NRFD# remains asserted in ANRS causing an RFD
holdoff.

INVALID 0x07 Release DAC Holdoff (Invalid)—INVALID releases a

DAC holdoff. If ISR1[APT] is set, the command that
caused the DAC holdoff is interpreted as an Other
Secondary Address (OSA).

IST/~IST 0x09/0x01 Set/Clear Parallel Poll Flag (ist)—IST and ~IST set and

clear the Parallel Poll Flag (ist). Refer to the Parallel Poll

Response Manager section of Chapter 4, Functional
Description—PCI4882 and GEN4882 Modes, for more

information.

LTN_CONT 0x1B Listen in Continuous Mode—LTN_CONT asserts the

local ltn message and also sets Continuous Holdoff
mode, regardless of AUXRA[HOLDOFFMODE].
If Continuous Holdoff mode was set by LTN_CONT,
that holdoff mode will remain selected until the device
becomes unaddressed to listen or LTN is issued.

LUL 0x0C Unlisten—LUL forces the Listener state machine into

LIDS.

LUN 0x1C Local Unlisten—LUN causes the Listener state machine

to enter LIDS if the Controller state machine is in CACS.

LUT 0x0B Untalk—LUT forces the Talker state machine into TIDS.

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Chapter 3 Register Descriptions

AUXMR

Command

Va lu e Description

PAG EI N 0x50 Page-in Registers—This command is implemented only

for backwards compatibility reasons.

PON 0x00 Pulse Pon—The PON command sets the local pon

message for 1 clock cycle, then clears pon.

PULSE_RTL 0x05 Pulse Return to Local—PULSE_RTL sets the rtl local

message for one clock cycle (if rtl is not already set), then
clears rtl.

REQT/REQF 0x18/0x19 Request True/Request False—REQT indirectly causes

the SRQ# to assert. REQF causes the SRQ# to unassert.
These commands are inputs to the IEEE 488.2 Service
Request Synchronization circuitry.

RHDF 0x03 Release Holdoff—RHDF clears the RFD holdoff state.

The Acceptor state machine enters the RFD holdoff state
following the HLDI command or as configured to do so
by AUXRA[HOLDOFFMODE].

TRIG 0x04 Trigger—This command forces the TRIG pin to assert

for 3 clock cycles. This command has no effect on
ISR1[DET] or the DT interface function.

VA L I D 0x0F Release DAC Holdoff (Valid)—This command clears

the DAC holdoff condition. If ISR1[APT] is set, this
command causes the GPIB command to be interpreted as
MSA.

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Chapter 3 Register Descriptions

Auxiliary Register A (AUXRA)

Offset 0x0A in 4882 Register Set Reset Value: 0x80 Write Only

1 0 0 BIN XEOS REOS HOLDOFFMODE[1:0]

7 6 5 4 3 2 1 0

AUXRA controls the EOS and END GPIB Remote Messages and specifies the RFD Holdoff
mode.

Mnemonic Type Description

BIN W Binary EOS—BIN selects whether the EOSR represents

an 8-bit binary number or a 7-bit ASCII character. When
BIN is set, the EOSR is treated as an 8-bit value. All 8 bits
of a data byte must match EOSR to generate the END
condition. When BIN is cleared, the EOSR is treated as a
7-bit value. Only the lower 7 bits of a data byte must match
the EOSR to generate the END condition.

XEOS W Transmit END with EOS—XEOS permits or prohibits

automatic transmission of the GPIB END message at the
same time as the EOS message when in TACS. If XEOS
is set and the byte being sourced onto the GPIB matches
the contents of the EOSR, EOI# is sent true along with the
data. Setting CFG[CCEN] is the preferred way of sending
EOI# during transfers.

REOS W Enable EOS when Receiving—When REOS is set, each

byte received is compared to the EOSR to detect the END
condition. When REOS is cleared, data bytes received are
not compared to the EOSR to detect the END condition.

HOLDOFFMODE[1:0] W Acceptor Holdoff Mode—When receiving data bytes,

HOLDOFFMODE affects how the local rdy message is
generated.

HOLDOFFMODE[1:0] Holdoff Mode

00........................ Normal

01........................ RFD Holdoff on All Data

10........................ RFD Holdoff on END

11........................ Continuous

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Chapter 3 Register Descriptions

Auxiliary Register B (AUXRB)

Offset 0x0A in 4882 Register Set Reset Value: 0xA0 Write Only

1 0 1

7 6 5 4 3 2 1 0

ISS

0

TRI SPEOI CPT_ENABLE

AUXRB affects several different circuits. Refer to individual register bit descriptions.

Mnemonic Type Description

ISS W Individual Status Select—The value of the Parallel Poll Flag

is used as the local ist message when AUXRB[ISS] is cleared.
The value of SRQS is used as the local ist message when
AUXRB[ISS] is set.

TRI W Enable 500ns T1 Delay—TRI affects the duration of the T1

delay.

SPEOI W Send END During Serial Polls—When SPEOI is set, EOI#

is asserted with all serial poll responses.

CPT_ENABLE W Command Pass Through Enable—CPT_ENABLE is set to

allow the detection of undefined commands and to set
ISR1[CPT]. Clearing CPT_ENABLE clears ISR1[CPT] and
prevents detecting undefined commands.

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Chapter 3 Register Descriptions

Auxiliary Register E (AUXRE)

Offset 0x0A in 4882 Register Set Reset Value: 0xC0 Write Only

1 1 0 0 DHADT DHADC DHDT DHDC

7 6 5 4 3 2 1 0

Setting each bit in the AUXRE causes a DAC holdoff whenever a particular command is
received.

Mnemonic Type Description

DHADT W DAC Holdoff on GET Commands—DHADT causes a DAC

holdoff whenever the GET command is received.

DHADC W DAC Holdoff on DCL or SDC Command—DHADC

causes a DAC holdoff whenever the DCL or SDC command
is received.

DHDT W DAC Holdoff on Device Trigger—DHDT causes a DAC

holdoff whenever the Device Trigger command is received
(GET when the device is listen addressed).

DHDC W DAC Holdoff on Device Clear—DHDC causes a DAC

holdoff whenever the Device Clear command is received
(either SDC when the device is listen addressed or DCL).

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Chapter 3 Register Descriptions

Auxiliary Register F (AUXRF)

Offset 0x0A in 4882 Register Set Reset Value: 0xD0 Write Only

1 1 0 1 DHATA DHALA DHUNTL DHALL

7 6 5 4 3 2 1 0

Setting each bit in the AUXRF causes a DAC holdoff whenever a particular command is
received.

Mnemonic Type Description

DHATA W DAC Holdoff on All Talk Addresses—DHATA causes a

DAC holdoff on all commands in the range 0x40 to 0x5E
inclusive. DIO8 is ignored for all command bytes. When
performing a DAC holdoff due to DHATA, ISR1[CPT] sets.

DHALA W DAC Holdoff on All Listen Addresses—DHALA causes a

DAC holdoff on all commands in the range 0x20 to 0x3E
inclusive. DIO8 is ignored for all command bytes. When
performing a DAC holdoff due to DHALA, ISR1[CPT] sets.

DHUNTL W DAC Holdoff on UNT and UNL—DHUNTL causes a DAC

holdoff on the UNT and UNL commands. DIO8 is ignored on
all command bytes. When performing a DAC holdoff due to
DHUNTL, ISR1[CPT] sets.

DHALL W DAC Holdoff on All UCG, ACG, and SCG

Commands—DHALL causes a DAC holdoff on all
commands in the ranges 0x00 to 0x1F inclusive and 0x60 to
0x7F inclusive. DIO8 is ignored on all command bytes. When
performing a DAC holdoff due to DHALL, ISR1[CPT] sets.

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Chapter 3 Register Descriptions

Auxiliary Register G (AUXRG)

Offset 0x0A in 4882 Register Set Reset Value: 0x40 Write Only

0 1 0 0 0 0 0 CHES

7 6 5 4 3 2 1 0

AUXRG affects several different circuits. Refer to individual register bit descriptions.

Mnemonic Type Description

CHES W Change Holdoff on END Behavior—CHES prevents an

RFD holdoff after receiving END when in normal holdoff
mode. Normally when an END byte is received, Acceptor End
Holdoff State (AEHS) is entered. AEHS is cleared when
AUXMR[RHDF] is issued. When CHES is set, AEHS is
immediately cleared when in normal holdoff mode.

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Chapter 3 Register Descriptions

Auxiliary Register I (AUXRI)

Offset 0x0A in 4882 Register Set Reset Value: 0xE0 Write Only

1 1 1 0 USTD PPMODE2 0 SISB

7 6 5 4 3 2 1 0

AUXRI affects several different circuits. Refer to individual register bit descriptions.

Mnemonic Type Description

USTD W Enable 1100ns T1 Delay—USTD effects the duration of the

T1 delay.

PPMODE2 W Parallel Poll Mode 2—This bit, together with

PPR[PPMODE1], determine how the device is configured for
parallel polls. Refer to Parallel Poll Response Manager
section of Chapter 4, Functional Description—PCI4882 and

GEN4882 Modes, for a description of this bit.

SISB W Static Interrupt Bits—SISB controls the conditions that

clear the bits in ISR0, ISR1, and ISR2. If SISB is cleared,
reading one of these registers clears the bits in that register.
If SISB is set, the bits are cleared as described in this manual.
SISB should normally be set.

© National Instruments Corporation 3-65 TNT5002 Technical Reference Manual

Chapter 3 Register Descriptions

Auxiliary Register J (AUXRJ)

Offset 0x0A in 4882 Register Set Reset Value: 0xF0 Write Only

1 1 1 1 TM[3:0]

7 6 5 4 3 0

AUXRJ and AUXRK implement a general-purpose timer that can cause an interrupt. The
timer can also be used in byte timeout mode. In this mode the timer restarts each time a byte
is read from or written to the GFIFO.

Mnemonic Type Description

TM[3:0] W Timer—TM[3:0], together with AUXRK[TM[5:4]]

determines the timeout duration of the timer. The timeout
duration depends on the input clock frequency. The table in
the following section, Auxiliary Register K (AUXRK), shows
the timeout duration assuming a 40 MHz clock. For other
clock frequencies, the timeout duration can be scaled by the
ratio of the frequencies.

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Chapter 3 Register Descriptions

Auxiliary Register K (AUXRK)

Offset 0x0F in 4882 Register Set Reset Value: 0x00 Write Only

0 0 0 0 0 0 TM[5:4]

7 6 5 4 3 0

AUXRJ and AUXRK implement a general-purpose timer that can cause an interrupt. The
timer can also be used in byte timeout mode. In this mode the timer restarts each time a byte
is read from or written to the GFIFO.

Mnemonic Type Description

TM[5:4] W Timer—TM[5:4], together with AUXRJ[TM[3:0]]

determines the timeout duration of the timer as specified in
the following table. The timeout duration depends on the
input clock frequency. The table shows the timeout duration
assuming a 40 MHz clock. For other clock frequencies, the
timeout duration can be scaled by the ratio of the frequencies.

Approximate Timeout Duration

TM[5:0]

(40MHz Clock)

000000 Disabled

000001 16.0 µs

000010 32.0 µs

000011 128 µs

000100 256 µs

000101 1.02 ms

000110 4.10 ms

000111 16.4 ms

001000 32.8 ms

001001 131 ms

001010 262 ms

001011 1.05 s

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Chapter 3 Register Descriptions

Approximate Timeout Duration

TM[5:0]

(40MHz Clock)

001100 4.19 s

001101 16.8 s

001110 33.6 s

001111 134 s

010001 300 s

100001 1,000 s

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Chapter 3 Register Descriptions

Bus Control Register (BCR)

Offset 0x1F in 4882 Register Set Reset Value: 0x00 Write Only

0 DAV NDAC NRFD EOI SRQ 0 0

7 6 5 4 3 2 1 0

The BCR allows the GPIB Interface Management and Handshake signals to be arbitrarily
asserted.

Mnemonic Type Description

DAV
NDAC
NRFD
EOI
SRQ

W
W
W
W
W

GPIB Control Bits—Writing a bit in the BCR causes the
corresponding GPIB signal to assert (unless MISC[WRAP]
is set). The TNT5002 can’t assert ATN#, IFC#, or REN#.

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Chapter 3 Register Descriptions

Bus Status Register (BSR)

Offset 0x1F in 4882 Register Set Reset Value: 0x00 Read Only

AT N DAV NDAC NRFD EOI SRQ IFC REN

7 6 5 4 3 2 1 0

The BSR is used to read the state of the GPIB Interface Management and Handshake signals.

Mnemonic Type Description

AT N
DAV
NDAC
NRFD
EOI
SRQ
IFC
REN

R
R

GPIB Monitor Bits—The BSR indicates the status of the

GPIB signals.
R
R
R
R
R
R

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Chapter 3 Register Descriptions

GPIB Transfer Configuration (CFG)

Offset 0x10 in 4882 Register Set Reset Value: 0x00 Write Only

0 TLCHLTE IN A/BN CCEN 0 0 16/8N

7 6 5 4 3 2 1 0

The CFG register is used to configure GPIB transfers.

Mnemonic Type Description

TLCHLTE W Halt on TLC Interrupts—TLCHLTE determines which

conditions halt the GPIB Transfer Manager (once it has been
started with the CMDR[GO]). When TLCHLTE is set, the
GPIB Transfer manager also halts when any enabled interrupt
in IMR0, IMR1, or IMR2 asserts.

When TLCHLTE is cleared, the GPIB Transfer manager halts
when the CMDR[STOP] is issued or all of the bytes specified
in the CNT3–0 registers have been transferred.

In most applications, the GPIB Transfer manager should only
be stopped in response to some of the IMR0, IMR1, or IMR2
interrupts. Typically, TLCHLTE is cleared. When an interrupt
asserts, software determines whether the interrupt should stop
the GPIB Transfer manager. CMDR[STOP] can then be
issued to stop the GPIB Transfer manager.

IN W Direction—IN indicates the direction of the GPIB transfer.

For sending commands or data, IN should be cleared. IN
should be set for receiving data. Command bytes are received
regardless of the state of IN.

A/BN W First FIFO—When packing and unpacking data into the

FIFO in 16-bit mode, the GPIB Transfer Manager alternates
writing (or reading) between the upper and lower bytes. If
A/BN is cleared, the GPIB Transfer manager writes (or reads)
the first byte to GFIFO[7:0]. If A/BN is set, the GPIB Transfer
manager writes (or reads) the first byte to GFIFO[15:8].

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Mnemonic Type Description

CCEN W Send EOI# With Last Byte—When CCEN is set and the

GPIB transfer manager is sending GPIB data, EOI# is

asserted with the last byte of the transfer.

16/8N W 16-bit Wide FIFO—When 16/8N is set, the GFIFO is 16-bits

wide and may be accessed using byte or word accesses. When

16/8N is cleared, only the low-order byte of each position in

the GFIFO is used. 16/8N should always be set unless the host

is not capable of supporting 16 bit transfers to the TNT5002.

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Chapter 3 Register Descriptions

Command Register (CMDR)

Offset 0x1C in 4882 Register Set Reset Value: 0x00 Write Only

CMDR_CMD

7 0

The CMDR is used to issue commands to the device. Once a command is written to the
CMDR, it affects some part of the circuit and another command may be written immediately
afterwards. All commands not appearing in the following table are reserved.

CMDR Command Va lu e Description

GO 0x04 Go—The GO command starts the GPIB Transfer

manager. GO clears the internal HALT signal. When
HALT is set, the local nba and rdy messages become
false. HALT must be cleared to transfer data bytes.

HARD_RESET 0x40 Hardware Reset—Issuing HARD_RESET has the same

affect as asserting a hardware reset (PCI_RST# or
RESET#). Refer to Chapter 8, Reset Considerations,
for more information on resets.

RESET_FIFO 0x10 Reset FIFO—The RESET_FIFO command resets the

FIFOs to the empty state.

SC/~SC 0x02/0x03 Set/Clear System Control Enable—These commands

set and clear the System Controller functions.

SOFT_RESET 0x22 Software Reset—The SOFT_RESET command resets

the GPIB Transfer manager. Specifically, SOFT_RESET:

• Clears all bits in CFG, HSSEL, and IMR3

• Sets DONE, STOP, HALT, and GSYNC

• Resets the GFIFO

• Configures the CNT registers for 16-bit operation

Refer to Chapter 8, Reset Considerations, for more
information on resets.

STOP 0x08 Stop—The STOP command stops the GPIB Transfer

manager. STOP sets the internal HALT signal. When
HALT is set, the local nba and rdy messages become
false. HALT must be cleared to transfer data bytes.

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Chapter 3 Register Descriptions

Count Registers (CNT0, CNT1, CNT2, CNT3)

CNT0

Offset 0x14 in 4882 Register Set Reset Value: 0xFF Read/Write

CNT[7:0]

7 0

CNT1

Offset 0x16 in 4882 Register Set Reset Value: 0xFF Read/Write

CNT[15:8]

7 0

CNT2

Offset 0x09 in 4882 Register Set Reset Value: 0xFF Read/Write

CNT[23:16]

7 0

CNT3

Offset 0x0B in 4882 Register Set Reset Value: 0xFF Read/Write

CNT[31:24]

7 0

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