National Instruments TNT4882 TNT4882 reference manual (370872A-01)

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TNT4882

Programmer Reference Manual

July 1995 Edition

Part Number 370872A-01

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Limited Warranty

The TNT4882™ integrated circuit (“equipment”) is warranted against defects in material and workmanship under normal use and service for a period of one (1) year from the date of shipment from the National Instruments factory. During this period of one year, National Instruments shall at its sole option either repair, replace, or credit the Buyer for defective equipment if: (i) Buyer returns the equipment to National Instruments, FOB the National Instruments factory in Austin, Texas; (ii) Buyer notifies National Instruments promptly upon discovery of any defect in writing, including a detailed description of the defect; and (iii) upon examination of the returned equipment, National Instruments is satisfied that the circuit is defective and that the cause of such defect is not alteration or repair by someone other than National Instruments, neglect, accident, misuse, improper installation, or use contrary to any instructions issued by National Instruments.

A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work. Prior to issuance of an RMA by National Instruments, Buyer shall allow National Instruments the opportunity to inspect the equipment on-site at Buyer’s facility.

This warranty expires one year from date of original shipment regardless of any warranty performance during that warranty period. The warranty provided herein is Buyer’s sole and exclusive remedy for nonconformity of the equipment or for breach of any warranty. THE ABOVE IS IN LIEU OF ALL OTHER WARRANTIES EXPRESSED OR IMPLIED. NATIONAL INSTRUMENTS SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. BUYER’S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE BUYER. NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS, OR INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY THEREOF. This limitation of the liability of National Instruments will apply regardless of the form of action, whether in contract or tort, including negligence. National Instruments recommends against the use of its products as critical components in any life support devices or systems whose failure to perform can reasonably be expected to cause significant injury to a human. Buyer assumes all risk for such application and agrees to indemnify National Instruments for all damages which may be incurred due to use of the National Instruments standard devices in medical or life support applications. Any action against National Instruments must be brought within one year after the cause of action accrues.

National Instruments believes that the information in this manual is accurate. The document has been carefully reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition. The reader should consult National Instruments if errors are suspected. In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it.

Copyright

nder the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written consent of National Instruments Corporation.

Trademarks

NAT4882®, Turbo488®, and TNT4882™, are trademarks of National Instruments Corporation.

Product and company names listed are trademarks or trade names of their respective companies.

WARNING REGARDING MEDICAL AND CLINICAL

USE OF NATIONAL INSTRUMENTS PRODUCTS

National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the part of the user or application designer. Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel, and all traditional medical safeguards, equipment, and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used. National Instruments products are NOT intended to be a substitute for any form of established process, procedure, or equipment used to monitor or safeguard human health and safety in medical or clinical treatment.

About This Manual ............................................................................................. xvii

Organization of This Manual......................................................................... xvii

Conventions Used in This Manual................................................................. xviii

Related Documentation ................................................................................. xviii

Customer Communication ............................................................................. xix

Chapter 1 Introduction and General Description

TNT4882 Features ......................................................................................... 1-1

IEEE 488 Capabilities ..................................................................... 1-1

CPU Interface Features ................................................................... 1-4

Bus Interface Capabilities ............................................................... 1-4

Chapter 2 TNT4882 Architectures

Turbo+7210 Mode ......................................................................................... 2-1

Turbo+9914 Mode ......................................................................................... 2-2

One-Chip Mode ............................................................................................. 2-2

Choosing a TNT4882 Architecture Mode ..................................................... 2-2

One-Chip Mode............................................................................... 2-2

Turbo+9914 Mode........................................................................... 2-3

Turbo+7210 Mode........................................................................... 2-3

Changing the TNT4882 Architecture Modes ................................................ 2-3

Architecture After a Hardware Reset .............................................. 2-4

Changing between Turbo+9914 Mode and

Turbo+7210 Mode........................................................................... 2-4

Changing between One-Chip Mode and Turbo+7210 Mode.......... 2-4

..................................................................................... 2-1

........................................................ 1-1

Chapter 3 TNT4882 Interface Registers

One-Chip Mode/Turbo+7210 Mode Registers.............................................. 3-1

Hidden Registers: One-Chip Mode/Turbo+7210 Mode................. 3-4

Address Register Map....................................................... 3-4

Auxiliary Mode Register Map .......................................... 3-4

SH_CNT Map ................................................................... 3-5

The Page-In State (One-Chip Mode/Turbo+7210 Mode) ............... 3-5

When to Use the Page-In State ......................................... 3-5

How to Page-In ................................................................. 3-6

Turbo+9914 Mode Registers ......................................................................... 3-7

Hidden Registers: Turbo+9914 Mode............................................ 3-9

Accessory Read Register Map.......................................... 3-9

The SWAP Bit................................................................................. 3-9

Setting the SWAP Bit ....................................................... 3-9

.......................................................................... 3-1

Contents

Recommendation .............................................................. 3-10

The Page-In Condition (Turbo+9914 Mode) .................................. 3-10

8-Bit Versus 16-Bit Accesses.......................................................... 3-10

9914 and 7210 Registers with Identical Names.............................. 3-11

Accessory Register A (ACCRA)..................................................... 3-12

Accessory Register B (ACCRB) ..................................................... 3-13

Accessory Register E (ACCRE) ..................................................... 3-14

Accessory Register F (ACCRF)...................................................... 3-15

Accessory Register I (ACCRI)........................................................ 3-16

Accessory Register J (ACCRJ) ....................................................... 3-17

Accessory Write Register (ACCWR) ............................................. 3-19

Address Mode Register (ADMR) ................................................... 3-20

Address Register (ADR)—One-Chip Mode,

Turbo+7210 Mode........................................................................... 3-22

Address Register (ADR)—Turbo+9914 Mode ............................... 3-23

Address Register 0 (ADR0)............................................................. 3-24

Address Register 1 (ADR1)............................................................. 3-25

Address Status Register (ADSR)—Turbo+7210 Mode.................. 3-26

Address Status Register (ADSR)—Turbo+9914 Mode.................. 3-29

Auxiliary Command Register (AUXCR)........................................ 3-32

Auxiliary Mode Register (AUXMR)............................................... 3-41

Auxiliary Register A (AUXRA) ..................................................... 3-51

Auxiliary Register B (AUXRB)...................................................... 3-53

Auxiliary Register E (AUXRE)....................................................... 3-55

Auxiliary Register F (AUXRF)....................................................... 3-56

Auxiliary Register G (AUXRG) ..................................................... 3-57

Auxiliary Register I (AUXRI)......................................................... 3-59

Auxiliary Register J (AUXRJ) ........................................................ 3-61

Bus Control Register (BCR)/Bus Status Register (BSR)................ 3-63

Carry Cycle Register (CCR) ........................................................... 3-64

Command/Data Out Register (CDOR) ........................................... 3-65

Configuration Register (CFG)......................................................... 3-66

Command Register (CMDR)........................................................... 3-69

Count 0 Register (CNT0) ................................................................ 3-71

Count 1 Register (CNT1) ................................................................ 3-71

Count 2 Register (CNT2) ................................................................ 3-71

Count 3 Register (CNT3) ................................................................ 3-71

Count Registers ............................................................................... 3-72

32-Bit Mode...................................................................... 3-72

16-Bit Mode...................................................................... 3-72

Command Pass Through Register (CPTR) ..................................... 3-73

Chip Signature Register (CSR) ....................................................... 3-74

DIO Control Register (DCR)........................................................... 3-75

Data In Register (DIR) .................................................................... 3-76

DIO Status Register (DSR) ............................................................. 3-77

End-of-String Register (EOSR)....................................................... 3-78

First-In First-Out Buffer (FIFO(A/B)) ............................................ 3-79

TNT4882 Programmer Reference vi © National Instruments Corp.

Contents

FIFO A.............................................................................. 3-79

FIFO B .............................................................................. 3-79

High-Speed Enable Register (HIER)............................................... 3-81

Handshake Select Register (HSSEL) .............................................. 3-83

Interrupt Mask Register 0 (IMR0)—One-Chip Mode,

Turbo+7210 Mode........................................................................... 3-84

Interrupt Status Register 0 (ISR0)—One-Chip Mode,

Turbo+7210 Mode........................................................................... 3-84

Interrupt Mask Register 0 (IMR0)—Turbo+9914 Mode ................ 3-88

Interrupt Status Register 0 (ISR0)—Turbo+9914 Mode................. 3-88

Interrupt Mask Register 1 (IMR1)—One-Chip Mode,

Turbo+7210 Mode........................................................................... 3-92

Interrupt Status Register 1 (ISR1)—One-Chip Mode,

Turbo+7210 Mode........................................................................... 3-92

Interrupt Mask Register 1 (IMR1)—Turbo+9914 Mode ................ 3-98

Interrupt Status Register 1 (ISR1)—Turbo+9914 Mode................. 3-98

Interrupt Mask Register 2 (IMR2)—One-Chip Mode,

Turbo+7210 Mode........................................................................... 3-103

Interrupt Status Register 2 (ISR2)—One-Chip Mode,

Turbo+7210 Mode........................................................................... 3-103

Interrupt Mask Register 2 (IMR2)—Turbo+9914 Mode ................ 3-107

Interrupt Status Register 2 (ISR2)—Turbo+9914 Mode................. 3-107

Interrupt Mask Register 3 (IMR3)................................................... 3-111

Interrupt Status Register 3 (ISR3) ................................................... 3-111

Board Interrupt Register (INTR)..................................................... 3-114

Key Control Register (KEYREG)................................................... 3-115

Miscellaneous Register (MISC)...................................................... 3-117

Parallel Poll Register (PPR)—Turbo+7210 Mode.......................... 3-119

Parallel Poll Register (PPR)—Turbo+9914 Mode.......................... 3-122

Programmable T1 Register (PT1) .................................................. 3-123

Source/Acceptor Status Register (SASR) ....................................... 3-124

SH_CNT Register (SH_CNT)........................................................ 3-126

Serial Poll Mode Register (SPMR) ................................................. 3-127

Serial Poll Status Register (SPSR).................................................. 3-127

Status 1 Register (STS1) ................................................................. 3-129

Status 2 Register (STS2) ................................................................. 3-132

T12 Register (T12) ......................................................................... 3-133

T13 Register (T13).......................................................................... 3-134

T17 Register (T17).......................................................................... 3-135

Timer Register (TIMER)................................................................. 3-136

Chapter 4 TNT4882 Programming Considerations

Chip Initialization .......................................................................................... 4-1

1. Reset the Turbo488 Circuitry of the TNT4882.......................... 4-1

2. Place the TNT4882 in Turbo+7210 Mode ................................. 4-1

3. Configure the TNT4882 for One-Chip Mode ............................ 4-2

4. Make Sure that the Local Power-On Message is Asserted ........ 4-2

.................................................... 4-1

Contents

5. Configure the TNT4882 for GPIB Operation ............................ 4-2

A. Set the GPIB Address(es) .......................................... 4-2

B. Write the Initial Serial Poll Response........................ 4-2

C. Configure the Initial Parallel Response ..................... 4-2

D. Enable Interrupts........................................................ 4-3

E. Set the GPIB Handshake Parameters ......................... 4-3

6. Clear the Local Power-On Message to Begin

GPIB Operation.......................................................................... 4-3

GPIB Talker or Listener Considerations ....................................................... 4-3

GPIB Addressing............................................................................. 4-3

Logical and Physical Devices ........................................... 4-3

Normal and Extended Addressing .................................... 4-3

Implementing One Logical Device:

Normal Addressing ........................................................... 4-4

Implementing One Logical Device:

Extended Addressing ........................................................ 4-4

Implementing Two Logical Devices:

Normal Addressing ........................................................... 4-4

Implementing Two Logical Devices:

Extended Addressing ........................................................ 4-5

Implementing Three or More Logical Devices:

Normal Addressing ........................................................... 4-6

Implementing Three or More Logical Devices:

Extended Addressing ........................................................ 4-7

Programmed Implementation of a Talker and Listener................... 4-7

GPIB Data Transfers...................................................................................... 4-7

Initialization..................................................................................... 4-7

Conducting the Transfer.................................................................. 4-8

Programmed I/O................................................................ 4-9

Interrupt-Driven Status Reporting .................................... 4-11

DMA ................................................................................. 4-11

Termination ..................................................................................... 4-12

Terminal Count ................................................................. 4-12

TLCINT Signal ................................................................. 4-12

Software Abort.................................................................. 4-12

Post Termination ............................................................................. 4-12

Device Status Reporting ................................................................................ 4-13

Requesting Service.......................................................................... 4-13

Asserting the SRQ signal.................................................. 4-13

IEEE 488.2 Service Requesting........................................ 4-13

7210-Style Service Requesting ......................................... 4-13

Responding to Serial Polls............................................................... 4-14

Responding to Parallel Polls ........................................................... 4-14

The ist Message................................................................. 4-14

Remote Configuration....................................................... 4-14

Local Configuration.......................................................... 4-15

Disabling the Parallel Poll Response ................................ 4-15

Acceptor Handshake Holdoffs in One-Chip Mode ....................................... 4-15

TNT4882 Programmer Reference viii © National Instruments Corp.

Contents

The GPIB rdy Message and RFD Holdoffs..................................... 4-15

Generating the rdy Message.............................................. 4-15

Immediate RFD Holdoff ................................................... 4-15

Data Byte RFD Holdoffs................................................... 4-16

DAC Holdoffs ................................................................................. 4-16

Determining When DAC Holdoffs Occur......................... 4-17

Hardware Interrupts ....................................................................................... 4-18

The INTR Pin.................................................................................. 4-18

The TNT4882_INT Signal.............................................................. 4-18

The TLCINT Signal ........................................................................ 4-18

Using the Timer ............................................................................................. 4-19

The Timer........................................................................................ 4-19

Global Timeouts.............................................................................. 4-19

Byte Timeouts ................................................................................. 4-19

Remote/Local State Considerations............................................................... 4-19

Device Triggering.......................................................................................... 4-20

Device Clearing ............................................................................................. 4-20

Using the KEY Pins....................................................................................... 4-21

Writing a DS1204 Key.................................................................... 4-21

Reading a DS1204 Key ................................................................... 4-21

Using the Key Pins as General Purpose I/O Pins............................ 4-21

T1 Delay Generation...................................................................................... 4-21

The T1 Delay................................................................................... 4-21

HSTS Definition.............................................................................. 4-22

T1 Delay.......................................................................................... 4-22

Chapter 5 Hardware Considerations: Generic Pin Configuration

CPU Interface Pins......................................................................................... 5-1

Data Buses....................................................................................... 5-1

8-Bit I/O Accesses ............................................................ 5-1

16-Bit I/O Accesses .......................................................... 5-2

8-Bit DMA Accesses ........................................................ 5-2

16-Bit DMA Accesses ...................................................... 5-2

Data Bus Control Signals ................................................................ 5-3

ABUSN and BBUSN........................................................ 5-3

ABUS_OEN and BBUS_OEN ......................................... 5-3

ADDR4–0 and CSN.......................................................... 5-3

RDN and WRN ................................................................. 5-3

CPUACC and RDY1 ........................................................ 5-3

DRQ .................................................................................. 5-5

DACKN ............................................................................ 5-5

BURST_RDN ................................................................... 5-5

Other CPU Interface Pins................................................................ 5-6

FIFO_RDY ....................................................................... 5-6

INTR ................................................................................. 5-6

PAGED ............................................................................. 5-6

...................... 5-1

Contents

Mode Pins........................................................................................ 5-6

MODE............................................................................... 5-6

SWAPN............................................................................. 5-6

MODE and SWAPN Pin Recommendations.................... 5-7

RESETN ........................................................................... 5-7

GPIB Device Status Pins ............................................................................... 5-7

TADCS—Talker Addressed Signal ................................................ 5-7

LADCS—Listener Addressed Signal.............................................. 5-7

TRIG—Trigger Signal..................................................................... 5-8

DCAS—Device Clear ..................................................................... 5-8

REM—Remote Signal..................................................................... 5-8

GPIB Signal Pins ........................................................................................... 5-8

Key Pins........................................................................................... 5-8

Oscillator Pins ................................................................................. 5-9

Crystal Oscillator .............................................................. 5-9

Discrete Oscillator Circuit ................................................ 5-9

Chapter 6 Hardware Considerations: ISA Pin Configuration

CPU Interface Pins......................................................................................... 6-1

Data Buses....................................................................................... 6-1

DATA15–8 ....................................................................... 6-1

DATA7–0 ......................................................................... 6-2

Data Bus Control Signals ................................................................ 6-2

D15_8_OEN and D7_0_OEN........................................... 6-2

BHEN_N........................................................................... 6-3

ADDR9–5, SW9–5, AEN_N ............................................ 6-3

ADDR4–0 ......................................................................... 6-3

IORN, IOWN.................................................................... 6-3

Other CPU Interface Pins................................................................ 6-3

DRQ .................................................................................. 6-3

DACKN ............................................................................ 6-4

INTR ................................................................................. 6-4

IOCHRDY ........................................................................ 6-4

IOCS16N........................................................................... 6-5

MODE............................................................................... 6-5

SENSE_8_16N ................................................................. 6-5

RESET .............................................................................. 6-5

Other Pins....................................................................................................... 6-5

.............................. 6-1

Appendix A Common Questions

TNT4882 Programmer Reference x © National Instruments Corp.

............................................................................................. A-1

Appendix B Clocking the TNT4882 at Frequencies Less than 40 MHz

..................................................................................................................... B-1

HS 488 Capability.......................................................................................... B-1

WR* Signal Recovery Time.......................................................................... B-1

T1 Delay—Byte Sourcing Speed................................................................... B-2

Internal Timer ................................................................................................ B-3

RDY Signal.................................................................................................... B-4

DRQ Timer .................................................................................................... B-4

Interrupts........................................................................................................ B-4

Acceptor Functions........................................................................................ B-4

Trigger Pulse Width....................................................................................... B-4

Appendix C Introduction to the GPIB

History of the GPIB ....................................................................................... C-1

The IEEE 488.1 Specification ....................................................................... C-2

IEEE 488.2 and SCPI Specifications............................................................. C-2

Problems with IEEE 488.1 Compatible Devices............................. C-2

The IEEE 488.2 Solution................................................................. C-2

SCPI Specification........................................................................... C-3

GPIB Hardware Configuration...................................................................... C-4

GPIB Signals and Lines................................................................... C-7

Data Lines ....................................................................................... C-7

Interface Management Lines ........................................................... C-8

Handshake Lines ............................................................................. C-11

Physical and Electrical Specifications............................................. C-13

Controllers, Talkers, and Listeners................................................................ C-14

Controllers ....................................................................................... C-14

Talkers and Listeners....................................................................... C-15

Data and Command Messages....................................................................... C-17

GPIB Addressing Protocol............................................................................. C-17

Reading the Multiline Interface Command Messages Table .......... C-19

Secondary Addressing..................................................................... C-19

Unaddressing Command Messages................................................. C-19

Termination Methods..................................................................................... C-19

.................................................................................. C-1

Interface Clear (IFC)......................................................... C-8

Attention (ATN)................................................................ C-9

Remote Enable (REN) ...................................................... C-10

End-or-Identify (EOI) ....................................................... C-10

Service Request (SRQ) ..................................................... C-11

Not Ready For Data (NRFD)............................................ C-11

Not Data Accepted (NDAC) ............................................. C-12

Data Valid (DAV)............................................................. C-12

Three-Wire Handshake Process........................................ C-13

Contents

EOS Method.................................................................................... C-20

EOI Method..................................................................................... C-20

Count Method.................................................................................. C-20

Combinations of Termination Methods........................................... C-21

Serial Polling ................................................................................................. C-21

Servicing SRQs ............................................................................... C-21

Serial Polling Devices ..................................................................... C-21

Status Byte Model for IEEE 488.1.................................................. C-23

ESR and SRE Registers................................................................... C-23

Status Byte Model for IEEE 488.2.................................................. C-23

Parallel Polling............................................................................................... C-25

Overview of Parallel Polls............................................................... C-25

Clearing and Triggering Devices................................................................... C-28

Appendix D Introduction to HS488

Objectives of HS488...................................................................................... D-1

Fast Transfer Rates.......................................................................... D-1

Compatibility with Existing IEEE 488.1 Devices........................... D-1

No Additional Software Overhead—

Automatic HS488 Detection ........................................................... D-1

No Changes to the IEEE 488.2 Standard......................................... D-1

No Added Cabling Restrictions beyond IEEE 488.1 ...................... D-2

IEEE 488.1 Requirements If T1 Delay Is 350 ns........................................... D-2

Additional HS488 System Requirements ...................................................... D-2

Sequence of Events in Data Transfers ........................................................... D-2

Case 1: Talker and Listener Are HS488 Capable........................... D-4

Case 2: Talker Is HS488 Capable, But Listener Is Not

HS488 Capable................................................................................ D-5

Case 3: Talker Is Not HS488 Capable ........................................... D-6

Transfer Holdoffs—3 Cases .......................................................................... D-6

Case 1: Listener's Buffer Nearly Full ............................................. D-7

Case 2: Listener Wants to Resume Three-Wire

Handshake ....................................................................................... D-8

Case 3: Talker Sends EOI or EOS ................................................. D-9

System Configuration .................................................................................... D-9

Determining the Value of the PPR Message..................... C-26

Configuring a Device for Parallel Polls............................ C-26

Determining the PPE Message.......................................... C-27

Physical Representation of the PPR Message................... C-27

........................................................................................ D-1

Appendix E Standard Commands for Programmable Instruments (SCPI)

IEEE 488.2 Common Commands Required by SCPI ................................... E-2

SCPI Required Commands............................................................................ E-3

SCPI Optional Commands............................................................................. E-3

Programming with SCPI................................................................................ E-4

TNT4882 Programmer Reference xii © National Instruments Corp.

......... E-1

Contents

Constructing SCPI Commands by Using the Hierarchical

Command Structure......................................................................... E-5

Parsing SCPI Commands ................................................................ E-7

Appendix F Multiline Interface Command Messages

.................................................... F-1

Appendix G Mnemonics Key

..................................................................................................... G-1

Appendix H Customer Communication

............................................................................... H-1

Glossary......................................................................................................... Glossary-1

Index.......................................................................................................................... I-1

Figures

Figure 2-1. Turbo+7210 or Turbo+9914 Mode Block Diagram ........................... 2-1

Figure 2-2. One-Chip Mode Block Diagram ......................................................... 2-2

Figure 2-3. Changing the Three TNT4882 Architecture Modes ........................... 2-3

Figure 3-1. FIFO Register Data Flow.................................................................... 3-80

Figure 4-1. Flow Chart of Polled GPIB Transfers................................................. 4-9

Figure 4-2. The TNT4882 INTR Pin ..................................................................... 4-18

Figure 5-1. TNT4882 Generic Pin Configuration ................................................. 5-1

Figure 5-2. Recommended Circuit for a Third Overtone Mode Crystal ............... 5-9

Figure 6-1. TNT4882 ISA Pin Configuration........................................................ 6-1

Figure B-1. Illustration of Tw1.............................................................................. B-2

Figure C-1. Structure of the GPIB Standards......................................................... C-3

Figure C-2. Linear Configuration........................................................................... C-5

Figure C-3. Star Configuration............................................................................... C-6

Figure C-4. GPIB Connector and Pin Assignments ............................................... C-7

Figure C-5. Three-Wire Handshake Process.......................................................... C-12

Figure C-6. System Setup Example ....................................................................... C-16

Figure C-7. Events During a Serial Poll................................................................. C-22

Figure C-8. IEEE 488.2 Standard Status Structures............................................... C-24

Figure C-9. Example Exchange of Messages During a Parallel Poll ..................... C-25

Contents

Figure D-1. IEEE 488.1 and HS488 Transfers....................................................... D-3

Figure D-2. Talker and Listener Are HS488 Capable............................................ D-4

Figure D-3. Talker Is HS488 Capable, But Listener Is Not HS488 Capable......... D-5

Figure D-4. Talker Is Not HS488 Capable, But Listener Is HS488 Capable......... D-6

Figure D-5. Acceptor Buffer Full........................................................................... D-7

Figure D-6. Acceptor Wants to Resume Three-Wire Handshake.......................... D-8

Figure D-7. Program Message Terminator............................................................. D-9

Figure E-1. Partial Command Categories .............................................................. E-4

Figure E-2. Simple Command Tree for the SENSe Command Subsystem ........... E-4

Figure E-3. Partial Command Tree for the SENSe Command Subsystem ............ E-5

Figure E-4. Partial Command Tree for the SOURce Command Subsystem ......... E-6

Figure E-5. Partial Command Tree for the TRIGger Command Subsystem ......... E-6

Tables

Table 1-1. TNT4882 IEEE 488 Interface Capabilities ......................................... 1-1

Table 3-1. TNT4882 Register Bit Map: One-Chip Mode and

Turbo+7210 Mode .............................................................................. 3-2

Table 3-2. Hidden Registers at Offset C (ADR) .................................................. 3-4

Table 3-3. Hidden Registers at Offset A (AUXMR)............................................ 3-4

Table 3-4. Register Map of the SH_CNT Register .............................................. 3-5

Table 3-5. One-Chip Mode and Turbo+7210 Mode Page-In State Register

Offsets ................................................................................................. 3-6

Table 3-6. TNT4882 Register Bit Map: Turbo+9914 Mode ............................... 3-7

Table 3-7. Hidden Registers at the ACCR Offset ................................................ 3-9

Table 3-8. Timeout Values in Turbo+9914 Mode ............................................... 3-17

Table 3-9. Valid ADMR Patterns ......................................................................... 3-20

Table 3-10. Auxiliary Command Summary ........................................................... 3-32

Table 3-11. Auxiliary Command Description........................................................ 3-34

Table 3-12. Auxiliary Command Summary ........................................................... 3-42

Table 3-13. Auxiliary Command Description........................................................ 3-44

Table 3-14. Clear Conditions for SISB Bit ............................................................ 3-60

Table 3-15. Timeout Values in 7210 Mode ........................................................... 3-61

Table 3-16. Command Summary: Detailed Description ....................................... 3-69

Table 3-17. Parallel Poll Register Example ........................................................... 3-121

Table 3-18. CNT Value and the Accessed Register ............................................... 3-126

Table 4-1. T1 Delay Settings................................................................................ 4-22

Table 5-1. Generic Pin Configuration Byte Lane Table (I/O Accesses).............. 5-2

Table 5-2. Quartz Crystal Specifications ............................................................. 5-10

Table 6-1. ISA Pin Configuration Byte Lane Table ............................................. 6-2

TNT4882 Programmer Reference xiv © National Instruments Corp.

Contents

Table B-1. T1 Delay Lengths—Turbo+7210 and One-Chip Modes .................... B-2

Table B-2. T1 Delay Lengths—Turbo+9914 Mode ............................................. B-3

Table C-1. PPR Message Value ............................................................................ C-26

Table C-2. Determining the PPE Message............................................................ C-27

Table D-1. HS488 Limitations.............................................................................. D-2

Table D-2. Start of Transfer—Three Cases........................................................... D-3

Table E-1. IEEE 488.2 Common Commands Required by SCPI......................... E-2

Table E-2. SCPI Required Commands ................................................................. E-3

About This Manual

This manual describes the programmable features of the TNT4882 and contains information that is suitable for programmers and engineers who wish to write software for the TNT4882.

This manual assumes that you are already familiar with general IEEE 488 concepts.

Organization of This Manual

This manual is organized as follows:

• Chapter 1, Introduction and General Description, explains the features and

capabilities of the TNT4882.

• Chapter 2, TNT4882 Architectures, discusses the internal hardware architectures of

the TNT4882.

• Chapter 3, TNT4882 Interface Registers, contains TNT4882 address maps and a

detailed description of the TNT4882 interface registers.

• Chapter 4, TNT4882 Programming Considerations, explains important TNT4882

programming considerations.

• Chapter 5, Hardware Considerations: Generic Pin Configuration, supplements the

information contained in the TNT4882 Single-Chip IEEE 488.2 Talker/Listener ASIC data sheet.

• Chapter 6, Hardware Considerations: ISA Pin Configuration, supplements the

information contained in the TNT4882 Single-Chip IEEE 488.2 Talker/Listener ASIC data sheet.

• Appendix A, Common Questions, list common questions and answers.

• Appendix B, Clocking the TNT4882 at Frequencies Less than 40 MHz, discusses

some factors to consider when clocking the TNT4882 at frequencies less than 40 MHz.

• Appendix C, Introduction to the GPIB, discusses the history of the GPIB, GPIB

hardware configurations, and serial polling.

• Appendix D, Introduction to HS488, describes HS488 and the sequence of events in

data transfers.

About This Manual

• Appendix E, Standard Commands for Programmable Instruments (SCPI), discusses

the SCPI document, the required SCPI commands, and SCPI programming.

• Appendix F, Multiline Interface Command Messages, lists the multiline interface

messages and describes the mnemonics and messages that correspond to the interface functions.

• Appendix G, Mnemonics Key, defines the mnemonics (abbreviations) that this

manual uses for functions, remote messages, local messages, states, bits, registers, integrated circuits, and system functions.

• Appendix H, Customer Communication, contains forms you can use to request help

from National Instruments or to comment on our products and manuals.

• The Glossary contains an alphabetical list and a description of the terms that this

manual uses, including abbreviations, acronyms, metric prefixes, mnemonics, and symbols.

• The Index contains an alphabetical list of the key terms and topics that this

manual uses, and it includes the page number where you can locate each term and topic.

Conventions Used in This Manual

This manual uses the following conventions. italic Italic text denotes emphasis, a cross reference, or an

introduction to a key concept.

bold italic Bold italic text denotes a note, caution, or warning. IEEE 488 and IEEE 488 and IEEE 488.2 refer to the ANSI/IEEE

IEEE 488.2 Standard 488.1-1987 and ANSI/IEEE Standard 488.2-1992,

respectively, which define the GPIB.

The Glossary lists abbreviations, acronyms, metric prefixes, mnemonics, symbols, and terms.

Customer Communication

National Instruments wants to receive your comments on our products and manuals. We are interested in the applications you develop with our products, and we want to help if you have problems with them. To make it easy for you to contact us, this manual contains comment and configuration forms for you to complete. These forms are in Appendix H, Customer Communication, at the end of this manual.

Chapter 1 Introduction and General Description

This chapter explains the features and capabilities of the TNT4882. The National Instruments TNT4882 provides a single-chip Talker/Listener (TL) interface

to the General Purpose Interface Bus (GPIB). It combines the circuitry of the Turbo488 performance-enhancing ASIC, the NAT4882 IEEE 488.2 ASIC, and many new features to provide a complete GPIB solution.

The TNT4882 performs the interface functions defined in the ANSI IEEE Standard

488.1-1987 and the additional requirements and recommendations of the ANSI IEEE Standard 488.2-1987. For faster data transfers, the TNT4882 includes an on-chip, first-in first-out (FIFO) buffer and circuitry to implement HS488, a new high-speed mode for GPIB transfers. The TNT4882 contains 16 enhanced IEEE 488.1 compliant transceivers and can be directly connected to the GPIB. The flexible CPU interface can be easily interfaced to any 16- or 8-bit microprocessor.

Because the TNT4882 contains the NAT4882 register set, which in turn contains the NEC µPD7210 and TI TMS9914A register sets, you can easily port existing code directly to the TNT4882. The TNT4882 also contains Turbo488 circuitry and many new features to reduce software overhead.

The TNT4882 can be characterized as a bus translator: it converts messages and signals from the CPU into appropriate GPIB messages and signals. In GPIB terminology, the TNT4882 implements GPIB board and device functions to communicate with the central processor and memory. From the host CPU, the TNT4882 is an interface to the outside world.

TNT4882 Features

IEEE 488 Capabilities

The National Instruments TNT4882 has the features necessary to provide a high-performance IEEE 488 interface. Table 1-1 lists the capabilities of the TNT4882 in terms of the IEEE 488 standard codes.

Table 1-1. TNT4882 IEEE 488 Interface Capabilities

Capability Code Description

SH1 Complete Source Handshake Capability AH1 Complete Acceptor Handshake Capability; DAC and RFD

Holdoff on Certain Events

(continues)

Introduction and General Description Chapter 1

Table 1-1. TNT4882 IEEE 488 Interface Capabilities (Continued)

Capability Code Description

T5 Complete Talker Capability

• Basic Talker

• Serial Poll

• Talk-Only Mode

• Unaddressed on MLA

• Send END or EOS

TE5 Complete Extended Talker Capability

• Basic Extended Talker

• Serial Poll

• Talk-Only Mode

• Unaddressed on MSA & LPAS

• Send END or EOS

L3 Complete Listener Capability

• Basic Listener

• Listen-Only Mode

• Unaddressed on MTA

• Detect END or EOS

LE3 Complete Extended Listener Capability

• Basic Extended Listener

• Listen-Only Mode

• Unaddressed on MSA & TPAS

• Detect END or EOS

SR1 Complete Service Request Capability

RL1 Complete Remote/Local Capability

PP1 Remote Parallel Poll Configuration

PP2 Local Parallel Poll Configuration DC1 Complete Device Clear Capability DT1 Complete Device Trigger Capability

C0 No Controller Capability

E2 Three-State Drivers (Open-Collector Drivers During Parallel

Polls)

The TNT4882 has complete Source and Acceptor Handshake capability. It can operate as a basic Talker or an extended Talker and can respond to a Serial Poll. If you place

TNT4882 Programmer Reference 1-2 © National Instruments Corp.

Chapter 1 Introduction and General Description

the TNT4882 in talk-only mode, it is unaddressed to talk when it receives its listen address. The TNT4882 GPIB interface can also operate as a basic Listener or an extended Listener. If you place it in listen-only mode, it is unaddressed to listen when it receives its talk address. The TNT4882 can request service from a Controller.

Device Clear and Trigger capability is included in the interface, but the interpretation is software dependent.

Other GPIB features include the following:

• Messages are not sent when there are no Listeners

• HS488 capable

• 16 IEEE 488.1 transceivers integrated on-chip

• Automatic detection of EOS and/or New Line (NL) messages

• Programmable data transfer rates

• Automatic processing of IEEE 488 commands and read undefined commands

• Ability to use six addressing modes – Automatic single or dual primary addressing detection – Automatic single primary with single secondary address detection – Single or dual primary with multiple secondary addressing – Multiple primary addressing

• Automatic detection of EOS and/or NL messages

Introduction and General Description Chapter 1

CPU Interface Features

• FIFO buffers for high-speed transfers

• Byte-to-word packing and unpacking

• DMA interface to the host system – Cycle steal – Burst – Time limited

• 32-bit internal transfer byte counter

• Special last byte circuitry to reduce software overhead

• Interrupts – Interrupts can be individually enabled and cleared – Many interrupting conditions are available

• Programmable timer interrupts for general-purpose timing use

• Device-status indicator pins

Bus Interface Capabilities

• On-chip ISA interface glue circuitry

• Generic interfacing to other buses

TNT4882 Programmer Reference 1-4 © National Instruments Corp.

Chapter 2 TNT4882 Architectures

This chapter discusses the internal hardware architectures of the TNT4882. The TNT4882 has three different internal hardware architectures: one-chip mode,

Turbo+7210 mode, and Turbo+9914 mode. The architecture determines which set of registers is available to the host interface, the behavior of the bits in the registers, and how the FIFOs interface to the GPIB.

Turbo+7210 Mode

In Turbo+7210 mode, the TNT4882 behaves like a Turbo488 ASIC that is connected to a NAT4882BPL ASIC. The NAT4882BPL behaves like a µPD7210 that has many enhancements.

To write data to the GPIB, the host interface writes the data to the FIFOs of the TNT4882. A transfer state machine transfers the data from the FIFOs to the NAT4882 circuitry, then the NAT4882 circuitry sends the data across the GPIB.

To read data from the GPIB, the NAT4882 circuitry reads data bytes from the GPIB. The transfer state machine transfers the data from the NAT4882 circuitry to the FIFOs, then the host interface reads the data from the FIFOs.

ISA

Interface

Logic

Read/

Write

Control

Turbo488 Circuitry

FIFOs

Byte

Counter

Status Registers

NAT4882

Interface Circuitry

Transfer Machine

Configuration

and

Interrupt Control

State

NAT4882 Circuitry

Read/

Write

Control

Configuration

and

Status Registers

Interrupt Control

Timer

GPIB

Data

Registers

IEEE 488

Interface

Functions

IEEE 488 Monitor

IEEE 488

Transceivers

Local GPIB Signals

GPIB

Figure 2-1. Turbo+7210 or Turbo+9914 Mode Block Diagram

TNT4882 Architectures Chapter 2

Turbo+9914 Mode

In Turbo+9914 mode, the TNT4882 behaves like a Turbo488 ASIC that is connected to a NAT4882BPL ASIC. The NAT4882BPL behaves like a TMS9914A that has many enhancements.

Like Turbo+7210 mode, a transfer state machine in Turbo+9914 mode must transfer data between the FIFOs of the TNT4882 and the NAT4882 circuitry.

One-Chip Mode

In one-chip mode, the FIFOs of the TNT4882 are directly connected to the GPIB and the TNT4882 has a register set that is similar to Turbo+7210 mode. However, one-chip mode does not need a transfer state machine to transfer data either to or from the FIFOs.

FIFOs

ISA

Interface

Logic

Read/

Write

Control

Byte

Counter

Configuration

and

Status Registers

Timer

Interrupt Control

IEEE 488 Monitor

IEEE 488

Interface

Functions

HS488

Interface

Functions

IEEE 488

Transceivers

Figure 2-2. One-Chip Mode Block Diagram

Choosing a TNT4882 Architecture Mode

One-Chip Mode

One-chip mode is the simplest and fastest TNT4882 architecture. National Instruments recommends that you use one-chip mode to develop new software. The National Instruments ESP-488TL package uses one-chip mode.

IEEE 488 Bus

TNT4882 Programmer Reference 2-2 © National Instruments Corp.

Chapter 2 TNT4882 Architectures

You can use the TNT4882 in one-chip mode without using the HS488 high-speed GPIB protocol, but HS488 is available only when the TNT4882 is in one-chip mode. Therefore, you cannot use HS488 in Turbo+9914 and Turbo+7210 mode.

Turbo+9914 Mode

If you are porting code that was written for the TMS9914A to the TNT4882, you may want to use Turbo+9914 mode. The 7210-style registers used in one-chip mode are similar to the 9914-style registers, so it is not difficult to port code to use one-chip mode. However, you may feel more comfortable if you use the 9914-style registers.

Turbo+7210 Mode

In Turbo+7210 mode, the TNT4882 is compatible with the Turbo488+NAT4882BPL chip set: only applications written for this chip set should use Turbo+7210 mode. Turbo+7210 mode is similar to one-chip mode, so National Instruments recommends that you use one-chip mode to develop new software.

Changing the TNT4882 Architecture Modes

Figure 2-3 shows how you change the TNT4882 architecture modes.

Hardware Reset while

Mode Pin Grounded

sw7210 auxiliary

command

Turbo + 9914

sw9914 auxiliary

ONEC=1

Illegal.

Don't do this

Note: ONEC is bit 0 of the HSSEL Register

Figure 2-3. Changing the Three TNT4882 Architecture Modes

command

Hardware Reset while

Mode Pin Unconnected

Turbo + 7210

ONEC=0

One Chip

ONEC=1

TNT4882 Architectures Chapter 2

Architecture After a Hardware Reset

During a hardware reset, the TNT4882 examines the level of the MODE pin. Generally, the MODE pin is either connected to logic ground or unconnected. If the MODE pin is unconnected, an internal pull-up resistor pulls the MODE pin to a logic high level. If the MODE pin is at a logic low level during a hardware reset, the TNT4882 enters Turbo+9914 mode. If the MODE pin is at a logic high level during a hardware reset, the TNT4882 enters Turbo+7210 mode.

Changing between Turbo+9914 Mode and Turbo+7210 Mode

After the hardware reset, the host interface can change the TNT4882 from Turbo+9914 mode to Turbo+7210 mode by writing the sw7210 auxiliary command to the Accessory Read Register (ACCR). The host interface can change the TNT4882 from Turbo+7210 mode to Turbo+9914 mode by writing the sw9914 auxiliary command to the Auxiliary Mode Register (AUXMR).

Changing between One-Chip Mode and Turbo+7210 Mode

The host interface can change the TNT4882 from Turbo+7210 mode to one-chip mode by writing a 1 to the One Chip (ONEC) bit of the Handshake Select Register (HSSEL[0]). The host interface can change the TNT4882 from one-chip mode to Turbo+7210 mode by writing a 0 to ONEC.

TNT4882 Programmer Reference 2-4 © National Instruments Corp.

Chapter 3 TNT4882 Interface Registers

This chapter contains TNT4882 address maps and a detailed description of the TNT4882 interface registers.

One-Chip Mode/Turbo+7210 Mode Registers

Table 3-1 is the register bit map for the TNT4882 in one-chip mode and Turbo+7210 mode.

TNT4882 Interface Registers Chapter 3

Table 3-1. TNT4882 Register Bit Map: One-Chip Mode and Turbo+7210 Mode

Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(hex)

DIR 0 R DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1

CDOR 0 W DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1

ISR1 2 R CPT APT DET END RX DEC ERR DO DI

IMR1 2 W CPT IE APT IE DET IE END IE DEC IE ERR IE DO IE DI IE

ISR2 4 R INT X LOK REM X LOKC REMC ADSC

IMR2 4 W 0 0 DMAO DMAI 0 LOKCIEREMCIEADSC

ACCWR*

SPSR 6 R S8 PEND S6 S5 S4 S3 S2 S1

SPMR 6 W S8 rsv /

INTR*

ADSR 8 R X ATN* SPMS LPAS TPAS LA TA MJMN

ADMR 8 W ton lon 1 1 0 0 ADM1 ADM0

CNT2 9 R/W CNT23 CNT22 CNT21 CNT20 CNT19 CNT18 CNT17 CNT16

CPTR A R CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0

5 W 0 0 0 0 0 0 0 DMAEN

S6 S5 S4 S3 S2 S1

RQS

7 W 0 0 0 0 0 0 0 INTEN

AUXMR A W AUX7 AUX6 AUX5 AUX4 AUX3 AUX2 AUX1 AUX0

CNT3 B R/W CNT31 CNT30 CNT29 CNT28 CNT27 CNT26 CNT25 CNT24

ADR0 C R X DT0 DL0 AD5-0 AD4-0 AD3-0 AD2-0 AD1-0

ADR C W ARS DT DL AD5 AD4 AD3 AD2 AD1

HSSEL D W 0 0 GO2

SIDS

ADR1 E R EOI DT1 DL1 AD5-1 AD4-1 AD3-1 AD2-1 AD1-1

EOSR E W EOS7 EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOS0

STS1 10 R DONE 0 IN DRQ STOP DAV HALT GSYNC

CFG 10 W 0 TLC

HLTE

DSR 11 R DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1

NO DMA 0 0 0 ONEC

IN A/BN CCEN TMOE TIM/

BYTN

16/8N

(continues)

TNT4882 Programmer Reference 3-2 © National Instruments Corp.

Chapter 3 TNT4882 Interface Registers

Table 3-1. TNT4882 Register Bit Map: One-Chip Mode and Turbo+7210 Mode

(Continued)

Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(hex)

SH_CNT 11 W CNT2 CNT1 CNT0 TD4 TD3 TD2 TD1 TD0

IMR3 12 R/W 0 INTSRC2IE0 STOP IE NFF IE NEF IE TLC

HIER 13 W DGA DGB 0 NO_

TSETUP

CNT0 14 R/W CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0

MISC 15 W 0 0 0 HSE SLOW WRAP NOAS NOTS

CNT1 16 R/W CNT15 CNT14 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8

CSR 17 R V3 V2 V1 V0 KEYDQMODE 0 0

KEYREG 17 W 0 SWAP 0 0 KEY

FIFOB 18 R/W FB7 FB6 FB5 FB4 FB3 FB2 FB1 FB0

FIFOA 19 R/W FA15 FA14 FA13 FA12 FA11 FA10 FA9 FA8

ISR3 1A R INT INTSRC2X STOP NFF NEF TLC

CCR1AWD7D6D5 D4 D3D2D1D0

0 0 0 PMT_

CLK

KEY DAT

INT IE

KEY

DATA

INT

DONE

W_ EOS

KEY

RST*

DONE

SASR 1B R nba AEHS ANHS1 ANHS2 ADHS ACRDY SH1A SH1B

DCR 1B W DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1

STS2 1C R 1 16/8N 0 1 AFFN AEFN BFFN BEFN

CMDR 1C W CMD7 CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0

ISR0 1D R nba STBO NL EOS IFCI ATNI TO SYNC

IMR0 1D W 1 STBOIENLEN BTO IFCI IE ATNIIETO IE SYNC

TIMER 1E R/W TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0

BSR 1F R ATN DAV NDAC NRFD EOI SRQ IFC REN

BCR 1F W ATN DAV NDAC NRFD EOI SRQ IFC REN

* These registers are accessible only in the ISA pin configuration.

TNT4882 Interface Registers Chapter 3

Hidden Registers: One-Chip Mode/Turbo+7210 Mode

In addition to the registers shown in Table 3-1, the TNT4882 contains hidden registers. All hidden registers are write-only registers. Two or more hidden registers can appear at the same offset. When you write an 8-bit pattern to these offsets, some of the bits determine the hidden register that will be written; the other bits represent the value written to the register.

Address Register Map

The TNT4882 has two address registers: ADR1 and ADR0. Table 3-1 shows the offsets for the readable portion of ADR1 and ADR0. The writable portion of ADR0 and ADR1 appears at the offset of the Address Register (ADR) shown in Table 3-1. Table 3-2 shows the bit map for the two writable address registers.

Table 3-2. Hidden Registers at Offset C (ADR)

ADR0 0 DT0 DL0 AD5-0 AD4-0 AD3-0 AD2-0 AD1-0 ADR1 1 DT1 DL1 AD5-1 AD4-1 AD3-1 AD2-1 AD1-1

Auxiliary Mode Register Map

Several hidden registers appear at the Auxiliary Mode Register (AUXMR) offset. Table 3-3 shows these hidden registers.

Table 3-3. Hidden Registers at Offset A (AUXMR)

PPR 0 1 1 U S P3 P2 P1 AUXRA 1 0 0 BIN XEOS REOS HLDE HLDA AUXRB 1 0 1 ISS 0 TRI SPEOI CPT

AUXRE 1100DHADT DHADC DHDT DHDC

ENABLE

(continues)

TNT4882 Programmer Reference 3-4 © National Instruments Corp.

Chapter 3 TNT4882 Interface Registers

Table 3-3. Hidden Registers at Offset A (AUXMR) (Continued)

AUXRF 1101DHATA DHALA DHUNTL DHALL

AUXRG 0100NTNL 0 0 CHES

AUXRI 1110USTD PP2 0 SISB

AUXRJ 1111TM3 TM2 TM1 TM0

SH_CNT Map

Several hidden registers appear at the SH_CNT offset. Table 3-4 shows these hidden registers.

Table 3-4. Register Map of the SH_CNT Register

PT1 W 0 0 PT1_

ENA T17 W 0 1 0 T17_4 T17_3 T17_2 T17_1 T17_0 T12 W 1 0 0 T12_4 T12_3 T12_2 T12_1 T12_0 T13 W 1 1 0 T13_ 4 T13_3 T13_2 T13_ 1 T13_0

PT1_4 PT1_3 PT1_2 PT1_1 PT1_0

The Page-In State (One-Chip Mode/Turbo+7210 Mode)

The TNT4882 implements a Page-In state to be compatible with designs that assume the TNT4882 ASIC is used in 7210 mode. When the Page-In state is true, several registers are mapped to different locations and other registers are not accessible at any offset.

When to Use the Page-In State

New software should not use the Page-In state. Only applications that require complete software compatibility with the Turbo488 and NAT4882 ASICs should use the Page-In state.

TNT4882 Interface Registers Chapter 3

How to Page-In

The TNT4882 enters the Page-In state when the host interface writes the Page-In auxiliary command to the AUXMR. The TNT4882 registers appear at their Page-In state offset for the first register access after the Page-In command. The TNT4882 leaves the Page-In state at the end of the first register access after the Page-In command. The TNT4882 also enters the Page-In state when the PAGE pin of the TNT4882 is asserted. The TNT4882 exits the Page-In state when the PAGE pin is unasserted. See Table 3-5.

Table 3-5. One-Chip Mode and Turbo+7210 Mode Page-In State Register Offsets

(Hex)

SPSR R 6 Not Accessible

SPMR W 6 Not Accessible

CPTR R A Not Accessible ADR0 R C Not Accessible

ADR W C Not Accessible ADR1 R E Not Accessible EOSR W E Not Accessible

CSR R 17 6

KEYREG W 17 6

SASR R 1B A

ISR0 R 1D C

IMR0 W 1D C

BSR R 1F E

Page-In State

Offset (Hex)

BCR W 1F E

TNT4882 Programmer Reference 3-6 © National Instruments Corp.

Chapter 3 TNT4882 Interface Registers

Turbo+9914 Mode Registers

Table 3-6 is the register bit map for the TNT4882 in Turbo+9914 mode. The offsets in Table 3-6 assume that the SWAP bit is set. See The SWAP Bit section, which is located later in this chapter.

Table 3-6. TNT4882 Register Bit Map: Turbo+9914 Mode

Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(hex)

DIR 0 R DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1

CDOR 0 W DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1

CPTR 2 R CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0

PPR 2 W PP8 PP7 PP6 PP5 PP4 PP3 PP2 PP1

SPSR†

SPMR 4 W S8 rsv/

ACCWR*

ISR2†

ADR 6 W edpa dal dat A5 A4 A3 A2 A1

INTR*

ADSR 8 R REM LLO ATN LPAS TPAS LA TA ulpa

IMR2†

EOSR†

BCR†

4 R S8 PEND S6 S5 S4 S3 S2 S1

S6 S5 S4 S3 S2 S1

RQS

5 W 0 0 0 0 0 0 0 DMAEN

6 R nba STBO NL EOS LLOC ATNI TO 0

7 W 0 0 0 0 0 0 0 INTEN

8 W 1 STBOIENLEN BTO LLOCIEATNIIETO IE 0

8 W EOS7 EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOS0

8 W ATN DAV NDAC NRFD EOI SRQ IFC REN

ACCR†

CNT2 9 R/W CNT23 CNT22 CNT21 CNT20 CNT19 CNT18 CNT17 CNT16

BSR A R ATN DAV NDAC NRFD EOI SRQ IFC REN

AUXCR A W C/S 0 0 F4 F3 F2 F1 F0

CNT3 B R/W CNT31 CNT30 CNT29 CNT28 CNT27 CNT26 CNT25 CNT24

8 W ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0

(continues)

TNT4882 Interface Registers Chapter 3

Table 3-6. TNT4882 Register Bit Map: Turbo+9914 Mode (Continued)

Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(hex)

ISR0 C R INT0 INT1 BI BO END SPAS RLC MAC

IMR0 C W DMAO DMAI BI IE BO IE END IE SPASIERLC IE MAC IE

HSSEL D W 0 0 GO2

SIDS

ISR1 E R GET ERR UNC APT DCAS MA X IFC

IMR1 E W GET IE ERR IE UNC IE APT IE DCASIEMA IE 0 IFC IE

STS1 10 R DONE 0 IN DRQ STOP DAV HALT GSYNC

CFG 10 W 0 TLC

HLTE

IMR3 12 R/W 0 INT

SRC2

HIER 13 W DGA DGB 0 NO_

CNT0 14 R/W CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0

CNT1 16 R/W CNT15 CNT14 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8

FIFOB 18 R/W FB7 FB6 FB5 FB4 FB3 FB2 FB1 FB0

NODMA 0 0 0 ONEC

IN A/BN CCEN TMOE TIM/

BYTN

0 STOP IE NFF IE NEF IE TLC

INT IE

0 0 0 PMT_

TSETUP

16/8N

DONE

W_ EOS

FIFOA 19 R/W FA15 FA14 FA13 FA12 FA11 FA10 FA9 FA8

ISR3 1A R INT INT

SRC2

CCR1AWD7D6D5 D4 D3D2D1D0

STS2 1C R 1 16/8N 0 1 AFFN AEFN BFFN BEFN

CMDR 1C W CMD7 CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0

TIMER 1E R/W TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0

* These registers are accessible only in the ISA pin configuration. † Page-In registers. See Turbo+9914 Page-In State.

0 STOP NFF NEF TLC

INT

DONE

TNT4882 Programmer Reference 3-8 © National Instruments Corp.

Chapter 3 TNT4882 Interface Registers

Hidden Registers: Turbo+9914 Mode

In addition to the registers shown above, the TNT4882 contains hidden registers. All hidden registers are write-only registers. Two or more hidden registers can appear at the same offset. When you write an 8-bit pattern to these offsets, some of the bits determine the hidden register that will be written; the other bits represent the value written to the register.

Accessory Read Register Map

Several hidden registers appear at the ACCR offset. Table 3-7 shows these hidden registers.

Table 3-7. Hidden Registers at the ACCR Offset

ACCRA 1 0 0 BIN XEOS REOS 0 0 ACCRB 1 0 1 ISS 0 0 SPEOI 0

ACCRE 1100DHADT DHADC 0 0 ACCRF 1101DHATA DHALA DHUNTL DHALL

ACCRI 1110USTD PP1 0 DMAE ACCRJ 1111TM3 TM2 TM1 TM0

The SWAP Bit

The offsets of some Turbo+9914 mode registers depend on the value of the SWAP bit. SWAP does not affect the offsets of Turbo+7210 mode or one-chip mode registers.

In Turbo+9914 mode, the TNT4882 transfer state machine moves data between the FIFOs and the TNT4882 circuitry. The transfer state machine assumes that the Data In Register (DIR) and the Command/Data Out Register (CDOR) are located at offset 0. In Turbo+9914 mode, however, the DIR and CDOR are located at offset 0 only if SWAP = 1. If the FIFOs will be used in Turbo+9914 mode, the SWAP bit should be 1.

Setting the SWAP Bit

During a hardware reset, the TNT4882 samples the logic value on the SWAPN pin. If SWAPN is low during a hardware reset, the SWAP bit is set. If SWAPN is high during a hardware reset, the SWAP bit is cleared. You can also set or clear the SWAP bit by

TNT4882 Interface Registers Chapter 3

writing to the Key Control Register (KCR). KCR is accessible only when the TNT4882 is in Turbo+7210 mode or one-chip mode.

Note: If you use the TNT4882 in the ISA pin configuration, the SWAPN pad is not

accessible external to the chip but is internally shorted to the MODE pin. Thus, in ISA pin configuration, if the MODE pin is asserted during a hardware reset, the TNT4882 powers up in Turbo+9914 mode with the SWAP bit set.

Recommendation

For applications that use Turbo+9914 mode, National Instruments recommends that the SWAP bit is set in Turbo+9914 mode. The easiest way to implement a Turbo+9914 mode application is to connect the MODE pin and SWAPN pin to ground.

The Page-In Condition (Turbo+9914 Mode)

Four writable registers can appear at the same offset as the Address Status Register (offset 4 if SWAP = 0; offset 8 if SWAP = 1). After a hardware or software reset, no writable register appears at the Address Status Register (ADSR) offset; the TNT4882 ignores writes to that offset.

One Page-In auxiliary command exists for each of the four registers. The host interface can make one of the four registers accessible by issuing the appropriate Page-In command to the Auxiliary Command Register (AUXCR). The paged-in register remains accessible at the ADSR offset until the host interface either pages-in another register or issues the Clear Page-In Register auxiliary command.

When any one of the four writable registers is accessible at the ADSR offset, Interrupt Status Register 2 (ISR2) is accessible at the same offset as the ADR, and the Serial Poll Status Register (SPSR) is accessible at the same offset as the Serial Poll Mode Register (SPMR).

Register Bit Descriptions

8-Bit Versus 16-Bit Accesses

All TNT4882 registers are 8-bit registers. However, by making a 16-bit access to the same offset as FIFO B, the host interface can access FIFO A and FIFO B simultaneously to form a 16-bit register.

TNT4882 Programmer Reference 3-10 © National Instruments Corp.

Chapter 3 TNT4882 Interface Registers

9914 and 7210 Registers with Identical Names

Some registers are accessible only in Turbo+9914 mode and some registers are accessible only in Turbo+7210 mode or one-chip mode. Some registers are accessible in several modes, but their bits have completely different meanings. Make sure you read the bit descriptions that are appropriate for the mode your application uses.

All registers are listed in alphabetical order. The registers are alphabetized according to their mnemonics.

TNT4882 Interface Registers Chapter 3

Accessory Register A (ACCRA)

Mode: Turbo+9914 mode Attributes: Write only

Accessed at the same offset as ACCR

76543210 1 0 0 BIN XEOS REOS 0 0

Accessory Register A (ACCRA) controls the EOS and END messages. A ch_rst auxiliary command or a hardware reset clears ACCRA.

Bit Mnemonic Description

4w BIN Binary bit

The BIN bit selects the length of the EOS message. If BIN = 1, the EOSR is treated as an 8-bit byte. When BIN = 0, the EOSR is treated as a 7-bit register (for ASCII characters), and only a 7-bit comparison is done with the data on the GPIB.

3w XEOS Transmit END With EOS bit

The XEOS bit permits or prohibits automatic transmission of the GPIB END message at the same time as the EOS message when the TNT4882 is in Talker Active State (TACS). If XEOS = 1 and the byte in the CDOR matches the contents of the EOSR, the EOI line is sent true along with the data.

2w REOS END On EOS Received bit

The REOS bit permits or prohibits setting the END bit (ISR0[3]r) when the TNT4882 receives the EOS message as a Listener. If REOS = 1 and the byte in the DIR matches the byte in the EOSR, the END bit is set and the acceptor function treats the EOS character just as if it were received with EOI asserted.

TNT4882 Programmer Reference 3-12 © National Instruments Corp.

Chapter 3 TNT4882 Interface Registers

Accessory Register B (ACCRB)

Mode: Turbo+9914 mode Attributes: Write only

Accessed at the same offset as ACCR

76543210 1 0 1 ISS 0 0 SPEOI 0

Bit Mnemonic Description

4w ISS Individual Status Select bit

ISS determines the value of the TNT4882 ist message. When ISS = 1, ist takes on the value of the TNT4882 SRQS. (The TNT4882 is asserting the GPIB SRQ message when it is in SRQS.) If ISS = 0, ist takes on the value of the TNT4882 Parallel Poll Flag. You set and clear the Parallel Poll Flag by using the Set Parallel Poll Flag and Clear Parallel Poll Flag auxiliary commands.

1w SPEOI Send Serial Poll EOI bit

SPEOI permits or prohibits the transmission of the END message in SPAS. If SPEOI = 1, EOI is sent true when the TNT4882 is in SPAS and is sourcing an STB. Otherwise, EOI is sent false in SPAS.

TNT4882 Interface Registers Chapter 3

Accessory Register E (ACCRE)

Mode: Turbo+9914 mode Attributes: Write only

Accessed at the same offset as ACCR

7654 3 2 10 1 1 0 0 DHADT DHADC 0 0

Accessory Register E (ACCRE) determines how the TNT4882 uses a Data Accepted (DAC) holdoff. A ch_rst auxiliary command or a hardware reset clears ACCRE.

Each bit of ACCRE enables DAC holdoffs on a GPIB command or group of commands. When a GPIB Controller sends the specified command to the TNT4882, the CPT bit sets and the TNT4882 performs a DAC holdoff. See the DAC Holdoffs section in Chapter 4,

TNT4882 Programming Considerations.

Bit Mnemonic Description

3w DHADT DAC Holdoff On GET bit

2w DHADC DAC Holdoff On DCL Or SDC bit

TNT4882 Programmer Reference 3-14 © National Instruments Corp.

Chapter 3 TNT4882 Interface Registers

Accessory Register F (ACCRF)

Mode: Turbo+9914 mode Attributes: Write only

Accessed at the same offset as ACCR

7654 3 2 1 0 1101DHATA DHALA DHUNTL DHALL

Accessory Register F (ACCRF) determines how the TNT4882 uses a DAC holdoff. A ch_rst auxiliary command or a hardware reset clears ACCRF.

Each bit of ACCRF enables DAC holdoffs on a GPIB command or group of commands. When a GPIB Controller sends the specified command to the TNT4882, the CPT bit sets and the TNT4882 performs a DAC holdoff. See the DAC Holdoffs section in Chapter 4,

TNT4882 Programming Considerations.

Bit Mnemonic Description

3w DHATA DAC Holdoff On All Talker Addresses bit

2w DHALA DAC Holdoff On All Listener Addresses bit

1w DHUNTL DAC Holdoff On The UNT Or UNL Command bit

0w DHALL DAC Holdoff On All UCG, ACG, And SCG Commands

bit

TNT4882 Interface Registers Chapter 3

Accessory Register I (ACCRI)

Mode: Turbo+9914 mode Attributes: Write only

Accessed at the same offset as ACCR

76543210 1110USTD PP1 0 DMAE

Bit Mnemonic Description

3w USTD Ultra Short T1 Delay bit

If USTD = 1, the T1 delay can be as short as 350 ns. See the T1 Delay Generation section in Chapter 4, TNT4882 Programming Considerations.

2w PP1 Parallel Poll bit 1

The PP1 bit permits or prohibits the TNT4882's ability to automatically respond to remote parallel poll configuration. If PP1 = 1, the interface can be configured remotely for parallel polls.

The Acceptor Handshake does not perform a DAC holdoff or set the UNC bit when it receives a Parallel Poll Command (PPC or PPU).

If PP1 = 0, parallel polls must be configured through the PPR, and Parallel Poll commands must be monitored by UNC.

0w DMAE DMA Enable bit

If you use the FIFOs for data transfers, set DMAE. For GPIB reads, also set DMAI in IMR0. For GPIB writes, also set DMAO in IMR0.

TNT4882 Programmer Reference 3-16 © National Instruments Corp.

Chapter 3 TNT4882 Interface Registers

Accessory Register J (ACCRJ)

Mode: Turbo+9914 mode Attributes: Write only

Accessed at the same offset as ACCR

76543210 1111TM3TM2TM1TM0

Accessory Register J (ACCRJ) sets the timeout value of the Timer interrupt. The timeout value can be set between 15 µs to 125 s when the TNT4882 clock is 40 MHz. The Timer starts when TM[3–0] are written with a nonzero value. The TO bit in ISR2 sets when the timeout value expires. The Timer is cleared when a 0 is written to TM[3–0]. For more information on the Timer interrupt capability, see the Interrupt Status Register 2 (ISR2)—Turbo+9914 Mode section in this chapter. The ACCRJ is reset by a hardware reset or a ch_rst auxiliary command.

Note: This timer is independent of the DRQ assertion timer described by the TIMER. Bit Mnemonic Description

3–0w TM[3–0] Timer bits 3 through 0

Table 3-8 lists the approximate timeout values that ACCRJ supports at 40 MHz. If the TNT4882 uses another clock frequency, the timeout value can be computed with the following formula:

time = (2

Table 3-8. Timeout Values in Turbo+9914 Mode

factor

* 5)/frequency.

TM3–0 Timeout Value (> or =) Factor

0000 Disabled – 0001 16 µs7 0010 32 µs8 0011 128 µs10 0100 256 µs11

(continues)

TNT4882 Interface Registers Chapter 3

ACCRJ (continued)

Table 3-8. Timeout Values in Turbo+9914 Mode

(Continued)

TM3–0 Timeout Value (> or =) Factor

0101 1 ms 13 0110 4 ms 15 0111 16 ms 17 1000 33 ms 18 1001 131 ms 20 1010 262 ms 21 1011 1 s 23 1100 4 s 26 1101 17 s 27 1110 34 s 28 1111 134 s 30

Depending on the value of the BTO bit, IMR2[4]w, the Timer works with two different types of timeouts. If BTO = 0, the Timer starts when the host interface writes a nonzero value to the Timer Register. When the Timer reaches the timeout value, it sets the TO bit.

If BTO = 1, the Timer operates in byte timeout mode. In this mode, the Timer starts when the host interface writes a nonzero value to the Timer Register. The Timer counts until it reaches the timeout value. However, reads of the DIR or writes of the CDOR clear the Timer and force it to begin counting again. If TO is set in byte timeout mode, it remains set until the Timer Register is written. Further reads of DIR or writes of CDOR have no effect on TO until the Timer Register is written.

TNT4882 Programmer Reference 3-18 © National Instruments Corp.

Chapter 3 TNT4882 Interface Registers

Accessory Write Register (ACCWR)

Type: All modes

ISA pin configuration only

Attributes: Write only

7654321 0 0 0 0 0 0 0 0 DMAEN

Bit Mnemonic Description

7–1w 0 Write 0 to these bits.

0w DMAEN DMA Enable bit

When DMAEN = 0, the TNT4882 tristates the DRQ pin and ignores the DACKN pin. When DMAEN = 1, the TNT4882 responds to DMA accesses and drives DRQ high or low. The host interface should set DMAEN at the beginning of a DMA transfer, before the host interface enables the DMA controller. The host interface should clear DMAEN at the completion of a DMA transfer.

A hardware reset clears DMAEN.

TNT4882 Interface Registers Chapter 3

Address Mode Register (ADMR)

Type: One-chip mode

Turbo+7210 mode

Attributes: Write only

76543210

ton lon 1 1 0 0 ADM1 ADM0

The host interface can put the TNT4882 into one of six GPIB addressing modes by writing to the Address Mode Register (ADMR). The value of the ADMR is undefined after a hardware reset. Before the host interface can clear pon, it must write a valid pattern to the ADMR. All values not defined in the following table are reserved.

Table 3-9. Valid ADMR Patterns

Hex Value

of ADMR

30 No Addressing

The Controller cannot address the TNT4882 to become a Talker or Listener in no-addressing mode.

31 Normal Dual Addressing

The TNT4882 can implement one or two logical devices by using normal dual addressing.

See the GPIB Addressing section in Chapter 4, TNT4882 Programming Considerations.

32 Extended Single Addressing

Extended single addressing mode implements the Extended Listener and Extended Talker functions, as defined in the IEEE 488 standard, without intervention from the host interface.

See the GPIB Addressing section in Chapter 4, TNT4882 Programming Considerations.

GPIB Addressing Mode

(continues)

TNT4882 Programmer Reference 3-20 © National Instruments Corp.

Chapter 3 TNT4882 Interface Registers

ADMR (continued)

Table 3-9. Valid ADMR Patterns (Continued)

Hex Value

of ADMR

33 Extended Dual Addressing

Extended dual addressing mode implements the Extended Listener and Extended Talker functions, as defined in the IEEE 488 standard. This mode requires intervention from the host interface.

See the GPIB Addressing section in Chapter 4, TNT4882 Programming Considerations.

70 Listen Only (lon)

The TNT4882 becomes a GPIB Listener and enters the Listener Active State (LACS). Do not use lon if a GPIB Controller is present in the GPIB system.

The host interface should write a hex 30 (No Addressing) to the ADMR immediately after it writes lon to the ADMR. To force the TNT4882 to exit LACS, issue the unlisten (lul) auxiliary command.

B0 Talk Only (ton)

The TNT4882 becomes a GPIB Talker. Do not use ton if a GPIB Controller is present in the GPIB system.

The host interface should write a hex 30 (No Addressing) to the ADMR immediately after it writes ton to the ADMR. To force the TNT4882 to exit TACS, issue the local untalk (lut) auxiliary command.

GPIB Addressing Mode

TNT4882 Interface Registers Chapter 3

Address Register (ADR)—One-Chip Mode, Turbo+7210 Mode

Type: One-chip mode

Turbo+7210 mode

Attributes: Write only

76543210

ARS DT DL AD5 AD4 AD3 AD2 AD1

Writing to the Address Register (ADR) loads the internal registers ADR0 and ADR1. You must load both ADR0 and ADR1 for all addressing modes.

Bit Mnemonic Description

7w ARS Address Register Select bit

If ARS = 1, writing to the ADR loads the seven low-order bits of ADR into internal register ADR1. If ARS = 0, writing to the ADR loads the seven low-order bits of ADR into ADR0.

6w DT Disable Talker bit

DT = 1 disables recognition of the GPIB talk address formed from AD5 through AD1(ADR[4–0]w). ADR0 and ADR1 have independent DT bits.

5w DL Disable Listener bit

DL = 1 disables recognition of the GPIB listen address formed from AD5 through AD1(ADR[4–0]w). ADR0 and ADR1 have independent DL bits.

4–0w AD[5–1] TNT4882 GPIB Address bits 5 through 1

These bits specify the GPIB address of the TNT4882. The corresponding GPIB talk address is formed by adding hex 40 to AD[5–1], while the corresponding GPIB listen address is formed by adding hex 20 to AD[5–1]. The value written to AD[5–1] should not be 11111 (binary), because the corresponding talk and listen addresses would conflict with the GPIB Untalk (UNT) and GPIB Unlisten (UNL) commands.

TNT4882 Programmer Reference 3-22 © National Instruments Corp.

Chapter 3 TNT4882 Interface Registers

Address Register (ADR)—Turbo+9914 Mode

Mode: Turbo+9914 mode Attributes: Write only

76543210

edpa dal dat A5 A4 A3 A2 A1

ADR is used to load the primary GPIB address of the interface.

Bit Mnemonic Description

7w edpa Enable Dual Primary Addressing Mode bit

Setting edpa enables the dual primary addressing mode of the TNT4882. If edpa = 1, the TNT4882 ignores the least significant bit (A1) of its GPIB address. The TNT4882 then has two consecutive primary addresses. The ulpa bit indicates which address is active.

6w dal Disable Listener bit

Setting dal returns the TNT4882 Listener function to LIDS and forces the TNT4882 Listener function to remain in LIDS even if the chip receives its GPIB listen address or a lon auxiliary command.

5w dat Disable Talker bit

Setting dat returns the TNT4882 Talker function to TIDS and forces the Talker function to remain in TIDS even if the chip receives its GPIB talk address or a ton auxiliary command.

4–0w A[5–1] TNT4882 GPIB Address bits 5 through 1

AD[5–1] specify the primary GPIB address of the TNT4882. The corresponding GPIB talk address is formed by adding hex 40 to AD[5–1], while the corresponding GPIB listen address is formed by adding hex 20. AD[5–1] should not be 11111 (binary), because the corresponding talk and listen addresses then conflict with the GPIB UNT and GPIB UNL commands.

TNT4882 Interface Registers Chapter 3

Address Register 0 (ADR0)

Type: One-chip mode

Turbo+7210 mode

Attributes: Read only

76543210

X DT0 DL0 AD5–0 AD4–0 AD3–0 AD2–0 AD1–0

Address Register 0 (ADR0) reflects the internal GPIB address status of the TNT4882. In extended single addressing mode, ADR0 indicates the address and enable bits for the primary GPIB address of the TNT4882. In the dual primary addressing modes, ADR0 indicates the TNT4882 major primary GPIB address. See the GPIB Addressing section in Chapter 4, TNT4882 Programming Considerations.

Bit Mnemonic Description

7r X Reads back a 1 or 0.

6r DT0 Disable Talker 0 bit

If DT0 = 1, the primary (or major) Talker is not enabled, and this register is not compared with GPIB Talker addresses.

If DT0 = 0, the TNT4882 responds to a GPIB talk address matching bits AD[5–0 through 1–0].

5r DL0 Disable Listener 0 bit

If DL0 = 1, the primary (or major) Listener is not enabled, and this register is not compared with GPIB Listener addresses.

If DL0 = 0, the TNT4882 responds to a GPIB listen address matching bits AD[5–0 through 1–0].

4–0r AD[5–0 – 1–0] TNT4882 GPIB Address bits 5–0 through 1–0

These are the lower 5 bits of the TNT4882 GPIB primary (or major) address. The primary talk address is formed by adding hex 40 to AD[5–0 through 1–0], while the listen address is formed by adding hex 20.

TNT4882 Programmer Reference 3-24 © National Instruments Corp.

Chapter 3 TNT4882 Interface Registers

Address Register 1 (ADR1)

Type: One-chip mode

Turbo+7210 mode

Attributes: Read only

76543210

EOI DT1 DL1 AD5–1 AD4–1 AD3–1 AD2–1 AD1–1

Address Register 1 (ADR1) indicates the status of the GPIB address and enable bits for the secondary address of the TNT4882 if extended single addressing is used. ADR1 indicates the minor primary address of the TNT4882 if dual primary addressing is used. See the GPIB Addressing section in Chapter 4, TNT4882 Programming Considerations.

Bit Mnemonic Description

7r EOI End-or-Identify bit

EOI indicates the value of the GPIB EOI line that is latched when a data byte is received by the TNT4882 GPIB Acceptor Handshake (AH) function. If EOI = 1, the EOI line was asserted with the received byte. EOI is cleared by issuing the chip reset auxiliary command. EOI is updated after each byte is received.

6r DT1 Disable Talker 1 bit

If DT1 = 1, the secondary (or minor) Talker function is not enabled—that is, the GPIB secondary address (or minor primary talk address) is not compared with this register.

5r DL1 Disable Listener 1 bit

If DL1 = 1, the secondary (or minor) Listener function is not enabled—that is, the GPIB secondary address (or minor primary listen address) is not compared with this register.

4–0r AD[5–1 – 1–1] TNT4882 GPIB Address bits 5–1 through 1–1

These bits indicate the TNT4882 secondary or minor address. Form the secondary address byadding hex 60 to bits AD[5–1 through 1–1]. Form the minor talk address by adding hex 40 to AD[5–1 through 1–1]. Form the listen address by adding a hex 20.

TNT4882 Interface Registers Chapter 3

Address Status Register (ADSR)—Turbo+7210 Mode

Type: One-chip mode

Turbo+7210 mode

Attributes: Read only

76543210

X ATN* SPMS LPAS TPAS LA TA MJMN

The Address Status Register (ADSR) contains information that you can use to monitor the TNT4882 GPIB address status.

Bit Mnemonic Description

7r X Don't care bit

This bit reads as 1 or 0.

6r ATN* Attention* bit

ATN* is a status bit that indicates the current level of the GPIB ATN* signal. If ATN* = 0, the GPIB ATN* signal is asserted.

5r SPMS Serial Poll Mode State bit

If SPMS = 1, the TNT4882 GPIB Talker (T) or Talker Extended (TE) function is enabled to participate in a serial poll.

SPMS is set by

SPE & ACDS

SPMS is cleared by

(SPD & ACDS) + pon + IFC

TNT4882 Programmer Reference 3-26 © National Instruments Corp.

Chapter 3 TNT4882 Interface Registers

ADSR—Turbo+7210 Mode (continued)

Bit Mnemonic Description

4r LPAS Listener Primary Addressed State bit

LPAS indicates that the TNT4882 has received its primary listen address. See the Address Mode Register (ADMR) section in this chapter.

LPAS is cleared by

(PCG & ~MLA & ACDS) + pon

3r TPAS Talker Primary Addressed State bit

TPAS indicates that the TNT4882 has received its primary GPIB talk address. See the Address Mode Register (ADMR) section in this chapter.

TPAS is cleared by

(PCG & ~MTA & ACDS) + pon

2r LA Listener Active bit

LA = 1 when the TNT4882 has been addressed or programmed as a GPIB Listener—that is, the TNT4882 is in the Listener Active State (LACS) or the Listener Addressed State (LADS). The TNT4882 is addressed to listen when it receives its listen address from the CIC. The TNT4882 can also be programmed to listen by using the Listen-Only (lon) bit in the ADMR.

If the TNT4882 is addressed to listen, it is automatically unaddressed to talk.

LA is also cleared by

(UNL & ACDS) + IFC + pon + lul

1r TA Talker Active bit

TA = 1 when the TNT4882 has been addressed or programmed as the GPIB Talker—that is, the TNT4882 is in the Talker Active State (TACS), the Talker Addressed

TNT4882 Interface Registers Chapter 3

ADSR—Turbo+7210 Mode (continued)

Bit Mnemonic Description

State (TADS), or the Serial Poll Active State (SPAS). The TNT4882 can be addressed to talk when it receives its talk address from the CIC. It can also be programmed to talk by using the Talk-Only (ton) bit in the ADMR.

If the TNT4882 is addressed to talk, it is automatically unaddressed to listen.

TA is also cleared by

(OTA & ACDS) + IFC + pon + lut

0r MJMN Major-Minor bit

MJMN indicates whether the information in the other ADSR bits applies to the TNT4882 major or minor Talker and Listener functions. MJMN = 1 when the TNT4882 receives its GPIB minor talk address or minor listen address. MJMN clears when the TNT4882 receives its major talk or major listen address. The pon message also clears MJMN.

Note: Only one Talker or Listener can be active at a

time. The MJMN bit indicates which, if either, of the TNT4882 Talker and Listener functions is addressed or active.

MJMN is always 0 unless the normal or extended dual primary addressing mode is enabled. (See the Address

Mode Register section in this chapter.)

TNT4882 Programmer Reference 3-28 © National Instruments Corp.

Chapter 3 TNT4882 Interface Registers

Address Status Register (ADSR)—Turbo+9914 Mode

Mode: Turbo+9914 mode Attributes: Read only

76543210

REM LLO ATN LPAS TPAS LA TA ulpa

The Address Status Register (ADSR) contains information that you can use to monitor the TNT4882 GPIB address status.

Bit Mnemonic Description

7r REM Remote bit 6r LLO Local Lockout bit

LLO and REM indicate the status of the TNT4882 GPIB Remote/Local (RL1) function. REM = 1 when the TNT4882 GPIB RL1 function is in either Remote State (REMS) or Remote With Lockout State (RWLS). LLO = 1 when the TNT4882 is in Local With Lockout State (LWLS) or RWLS.

REM LLO RL1 State

0 0 LOCS 0 1 LWLS 1 0 REMS 1 1 RWLS

5r ATN Attention bit

ATN indicates the current level of the GPIB ATN signal. If ATN = 1, the GPIB ATN signal is asserted.

4r LPAS Listener Primary Addressed State bit

LPAS indicates that the TNT4882 has accepted its primary listen address.

LPAS is cleared by

(PCG & ~MLA & ACDS) + pon

TNT4882 Interface Registers Chapter 3

ADSR—Turbo+9914 Mode (continued)

Bit Mnemonic Description

3r TPAS Talker Primary Addressed State bit

TPAS indicates that the TNT4882 has accepted its primary talk address.

TPAS is cleared by

(PCG & ~MTA & ACDS) + pon

2r LA Listener Active bit

LA = 1 when the TNT4882 has been addressed or programmed as a GPIB Listener—that is, the TNT4882 is in LACS or LADS. The TNT4882 is addressed to listen by receiving its listen address from the CIC. You can also program the TNT4882 to listen by using the Listen-Only auxiliary command.

If the TNT4882 is addressed to listen, it is automatically unaddressed to talk.

LA is cleared by

pon + IFC + (UNL & ACDS)

1r TA Talker Active bit

TA = 1 when the TNT4882 has been addressed or programmed as the GPIB Talker—that is, the TNT4882 is in TACS, TADS, or SPAS. The TNT4882 can be addressed to talk by receiving its talk address from the CIC. You can also program the TNT4882 to talk by using the Talk-Only auxiliary command.

If the TNT4882 is addressed to talk, it is automatically unaddressed to listen.

TA is cleared by

pon + IFC + (OTA & ACDS)

TNT4882 Programmer Reference 3-30 © National Instruments Corp.

Chapter 3 TNT4882 Interface Registers

ADSR—Turbo+9914 Mode (continued)

Bit Mnemonic Description

0r ulpa Upper/Lower Primary Address bit

ulpa indicates the least significant bit of the last primary address that the TNT4882 received.

Note: Only one Talker or Listener is active at a time.

ulpa indicates which, if either, TNT4882 Talker or Listener function is addressed or active.

The ch_rst auxiliary command clears ulpa.

TNT4882 Interface Registers Chapter 3

Auxiliary Command Register (AUXCR)

Mode: Turbo+9914 mode Attributes: Write only

76543210

C/S 0 0 F4 F3 F2 F1 F0

Use the AUXCR to issue auxiliary commands. Two basic types of commands are implemented in the AUXCR: pulsed and static. Use static commands to enable (set) or disable (clear) various features of the TNT4882. The pulsed commands stay active for one clock pulse after the AUXCR has been written.

Note: Writes to the AUXCR must be separated by at least four clock cycles.

Table 3-10 summarizes the auxiliary commands and Table 3-11 describes the auxiliary commands.

Table 3-10. Auxiliary Command Summary

Hex

Code

00 80

01 81

02 pulsed rhdf Release RFD Holdoff 03

83 04

84 05 pulsed nbaf New Byte Available False 06

86 07

87 08 pulsed

Type Mnemonic Auxiliary Command

static static

~swrst

swrst

nonvalid valid

~hdfa

hdfa

~hdfe

hdfe

~fget

fget

~rtl

rtl

feoi

Clear Software Reset Set Software Reset

Nonvalid Release DAC Holdoff Valid Release DAC Holdoff

Clear Holdoff On All Data Set Holdoff On All Data

Clear Holdoff On END Only Set Holdoff On END Only

Clear Force Group Execute Trigger Set Force Group Execute Trigger

Clear Return To Local Set Return To Local

Send EOI With The Next Byte

(continues)

TNT4882 Programmer Reference 3-32 © National Instruments Corp.

Chapter 3 TNT4882 Interface Registers

AUXCR (continued)

Table 3-10. Auxiliary Command Summary (Continued)

Hex

Code

09 89

0A 8A

13 93

14 pulsed pts Pass Through Next Secondary 15

95 17

97 18

98 99 pulsed sw7210 Switch To 7210 Mode

1A 9A

Type Mnemonic Auxiliary Command

static static

pulsed pulsed

~lon

lon

~ton

ton

~dai

dai

~stdl

stdl

~vstdl

vstdl

~rsv2

rsv2

reqf reqt

Clear Listen Only Set Listen Only

Clear Talk Only Set Talk Only

Clear Disable IMR2, IMR1, and IMR0 Interrupts Set Disable IMR2, IMR1, and IMR0 Interrupts

Clear Short T1 Settling Time Set Short T1 Settling Time

Clear Very Short T1 Delay Set Very Short T1 Delay

Clear Request Service bit 2 Set Request Service bit 2

Request rsv False (reqf)

Request rsv True (reqt) 1C pulsed ch_rst Issue a Chip Reset 1D

9D 1E pulsed piimr2 Page-In Interrupt Mask Register 2 1F pulsed pibcr Page-In Bus Control Register 9C pulsed clrpi Clear Page-In Registers 9E pulsed pieosr Page-In End-of-String Register 9F pulsed piaccr Page-In Accessory Register

Values not specified are reserved.

static static

~ist

ist

Clear Parallel Poll Flag

Set Parallel Poll Flag

TNT4882 Interface Registers Chapter 3

AUXCR (continued)

Table 3-11. Auxiliary Command Description

Data

Pattern

(Hex)

00 80

01 81

Description

Clear Software Reset (~swrst) Set Software Reset (swrst)

The local swrst message places all GPIB interface functions into their idle states. swrst is equivalent to the GPIB local pon message.

swrst is set by a hardware reset, the ch_rst auxiliary command, or the swrst auxiliary command. You should configure the TNT4882 while swrst is set. Configuration includes writing the address of the device into the Address Register, writing mask values into the Interrupt Mask Registers, and selecting the desired features in the Auxiliary Command, Accessory, and Address Registers.

When swrst is cleared, the device becomes logically existent on the GPIB.

Clear DAC Holdoff (nonvalid) Clear DAC Holdoff (valid)

These commands clear a DAC holdoff condition. When APT = 1, nonvalid indicates that the last GPIB command byte received from the Controller was an invalid secondary address. Valid indicates a valid secondary address.

A DAC holdoff caused by any other GPIB command byte should be released with the invalid command.

02 Release RFD Holdoff (rhdf)

This command releases any RFD holdoffs that hdfa or hlde have caused.

03 83

TNT4882 Programmer Reference 3-34 © National Instruments Corp.

Clear Holdoff On All Data (~hdfa) Set Holdoff On All Data (hdfa)

If hdfa is true, the TNT4882 performs an RFD holdoff after it receives a data byte. To complete the handshake, you must issue the rhdf command after the TNT4882 receives each byte.

(continues)

Chapter 3 TNT4882 Interface Registers

AUXCR (continued)

Table 3-11. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

04 84

05 New Byte Available False (nbaf)

06 86

Clear Holdoff On END Only (~hdfe) Set Holdoff On END Only (hdfe)

If hdfe is true, the TNT4882 performs an RFD holdoff after it receives a data byte that satisfies the END condition.

nbaf forces the local message, nba, to become false. This action prohibits the TNT4882 from sending the last byte written to the CDOR.

Clear Force Group Execute Trigger (~fget) Set Force Group Execute Trigger (fget)

These commands generate a trigger condition. If the host interface issues ~fget, the TR pin pulses asserted for at least

five clock cycles. If the host interface issues fget, the TR pin asserts and remains asserted

until the host interface issues ~fget. These commands do not set or clear the GET bit.

Description

07 87

Clear Return To Local (~rtl) Set Return To Local (rtl)

These commands set and clear the IEEE 488 standard rtl local message. If the host interface issues the ~rtl command, the IEEE 488 standard rtl

message pulses true. If the host interface issues the rtl command, the rtl message becomes true

and remains true until the host interface issues ~rtl.

(continues)

TNT4882 Interface Registers Chapter 3

AUXCR (continued)

Table 3-11. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

08 Send EOI With The Next Byte (feoi)

The Send EOI command causes the GPIB EOI line to go true with the next data byte transmitted.

09 89

0A 8A

13 93

Clear Listen Only (~lon) Set Listen Only (lon)

lon forces the Listener function into the Listener Active State. ~lon forces the Listener function to leave the Listener Active State.

Clear Talk Only (~ton) Set Talk Only (ton)

ton forces the Talker function into the Talker Active State. ~ton forces the Talker function to leave the Talker Active State.

Clear Disable IMR2, IMR1, And IMR0 Interrupts (~dai) Set Disable IMR2, IMR1, And IMR0 Interrupts (dai)

Issuing dai disables the interrupt pin. The Interrupt Status Registers and any holdoffs selected in the Interrupt Mask Register are not affected by the dai command.

Description

(continues)

TNT4882 Programmer Reference 3-36 © National Instruments Corp.

Chapter 3 TNT4882 Interface Registers

AUXCR (continued)

Table 3-11. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

14 Pass Through Next Secondary (pts)

After you issue the pts command, UNC (ISR1[5]) sets when the TNT4882 receives a secondary command from the Controller.

If PP1 = 0, you can use the pts command to implement remote parallel poll configuration.

Note: It is simpler to set the PP1 bit to implement remote parallel poll

configuration. When PP1 = 1, the TNT4882 interprets remote parallel poll configuration commands without software intervention.

If the TNT4882 receives the PPC command, UNC sets. When the control program detects UNC, the control program issues pts. UNC sets again when the Controller sends the PPE command. The control program reads the CPTR to obtain the PPE command, then the control program writes the appropriate value to the PPR.

15 95

Clear Short T1 Delay (~stdl) Set Short T1 Delay (stdl)

Issuing stdl makes the T1 delay time 1.1 µs.

Description

17 97

18 98

Clear Very Short T1 Delay (~vstdl) Set Very Short T1 Delay (vstdl)

Issuing vstdl reduces the T1 delay time to 500 ns.

Clear Request Service bit 2 (~rsv2) Set Request Service bit 2 (rsv2)

The rsv2 bit performs the same function as the rsv bit in the SPMR, but it provides a means of requesting service that is independent of the SPMR. With rsv2, you can make minor updates to the SPMR without affecting the state of service request. rsv2 is cleared when the serial poll status byte is sent to the Controller during a serial poll (SPAS & APRS & STRS).

(continues)

TNT4882 Interface Registers Chapter 3

AUXCR (continued)

Table 3-11. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

99 Switch To 7210 Mode (sw7210)

Issuing sw7210 places the TNT4882 into 7210 compatibility mode.

1A 9A

1C Chip Reset (ch_rst)

Request rsv False (reqf) Request rsv True (reqt)

The reqt and reqf commands are inputs to the IEEE 488.2 Service Request Synchronization Circuit. Use these commands to set and clear the local rsv message.

If STBO IE = 0, reqt and reqf are not issued immediately; they are issued on the write of the SPMR that follows the issuing of the reqt or reqf auxiliary command.

If STBO IE = 1, reqt and reqf are issued immediately. See the IEEE

488.2 Service Requesting section in Chapter 4, TNT4882 Programming Considerations.

The ch_rst auxiliary command resets the TNT4882 to the following conditions:

Description

• The local swrst message is set and the interface functions are placed in their idle states.

• The SPMR bits are cleared.

• The EOS and NL bits are cleared.

• The ACCRA, ACCRB, ACCRE, ACCRF, ACCRI, and ACCRJ registers are cleared.

• The Parallel Poll Flag local message is cleared.

• The ulpa bit is cleared.

(continues)

Chapter 3 TNT4882 Interface Registers

AUXCR (continued)

Table 3-11. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

1D 9D

1E Page-In Interrupt Mask Register 2 (piimr2)

Clear Parallel Poll Flag (~ist) Set Parallel Poll Flag (ist)

The ~ist and ist commands set and clear the Parallel Poll Flag. The value of the Parallel Poll Flag is used as the local ist message when bit four of Accessory Register B (ISS) = 0. The value of SRQS is used as the local ist message when ISS = 1. A ch_rst auxiliary command or a hardware reset clears the local ist message.

Issuing piimr2 maps IMR2 to the ADSR offset. After this command is issued, you can access IMR2 at the ADSR offset until one of the following events occurs:

• A hardware reset occurs.

• The ch_rst auxiliary command is issued.

• Another register is paged into the ADSR offset.

• The Clear Page-In auxiliary command is issued.

Description

1F Page-In Bus Control Register (pibcr)

Issuing pibcr maps the BCR to the ADSR offset. After this command is issued, you can access BCR at the ADSR offset until one of the following events occurs:

• A hardware reset occurs.

• The ch_rst auxiliary command is issued.

• Another register is paged into the ADSR offset.

• The Clear Page-In auxiliary command is issued.

(continues)

TNT4882 Interface Registers Chapter 3

AUXCR (continued)

Table 3-11. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

9C Clear Page-In Registers (clrpi)

Issuing clrpi removes the previously paged-in Accessory Register from the ADSR offset. After this command is issued, writes to offset 2 have no effect until a Page-In auxiliary command is issued.

9E Page-In End-of-String Register (pieosr)

Issuing pieosr maps the EOSR to the ADSR offset. After this command is issued, you can access EOSR at the ADSR offset until one of the following events occurs:

• A hardware reset occurs.

• The ch_rst auxiliary command is issued.

• Another register is paged into the ADSR offset.

• The Clear Page-In auxiliary command is issued.

9F Page-In Accessory Register (piaccr)

Issuing piaccr maps the Accessory Register to the ADSR offset. After this command is issued, you can access ACCR at the ADSR offset until one of the following events occurs:

Description

• A hardware reset occurs.

• The ch_rst auxiliary command is issued.

• Another register is paged into the ADSR offset.

• The Clear Page-In auxiliary command is issued.

Chapter 3 TNT4882 Interface Registers

Auxiliary Mode Register (AUXMR)

Type: One-chip mode

Turbo+7210 mode

Attributes: Write only

Permits access to hidden registers

76543210

AUX7 AUX6 AUX5 AUX4 AUX3 AUX2 AUX1 AUX0

Use the AUXMR to issue auxiliary commands and to write the following eight hidden registers:

• Parallel Poll Register (PPR)

• Auxiliary Register A (AUXRA)

• Auxiliary Register B (AUXRB)

• Auxiliary Register E (AUXRE)

• Auxiliary Register F (AUXRF)

• Auxiliary Register G (AUXRG)

• Auxiliary Register I (AUXRI)

• Auxiliary Register J (AUXRJ)

Note: You should issue commands at intervals of at least 200 ns.

For more information, see the Hidden Registers: One-Chip Mode/Turbo+7210 Mode section, which is located earlier in this chapter.

TNT4882 Interface Registers Chapter 3

AUXMR (continued)

Table 3-12 summarizes the auxiliary commands and Table 3-13 describes the auxiliary commands.

Table 3-12. Auxiliary Command Summary

Hex

Code*

00 Immediate Execute Power-On (pon) 01 Clear Parallel Poll Flag (~ist) 02 Chip Reset (ch_rst) 03 Finish Handshake (rhdf) 04 Trigger (trig) 05 Clear Or Pulse Return To Local (rtl) 06 Send EOI (seoi) 07 Nonvalid Secondary Command Or

Address (nonvalid) 09 Set Parallel Poll Flag (ist) 0B† Untalk Command (lut) 0C† Unlisten Command (lul) 0D Set Return To Local 0E† New Byte Available False (nbaf)

Auxiliary Command

0F Valid Secondary Command or Address

(valid) 15† Switch To Turbo+9914 Mode Command 18†

19†

Request rsv True (reqt)

Request rsv False (reqf)

(continues)

Chapter 3 TNT4882 Interface Registers

AUXMR (continued)

Table 3-12. Auxiliary Command Summary (Continued)

Hex

Code*

50† Page-In Additional Registers 51† Holdoff Handshake Immediately (hldi) 54† Clear DET (ISR1[5]r) Command 55† Clear END (ISR1[4]r) Command 56† Clear DEC (ISR1[3]r) Command 57† Clear ERR (ISR1[2]r) Command 59† Clear LOKC (ISR2[2]r) Command 5A† Clear REMC (ISR2[1]r) Command 5B† Clear ADSC (ISR2[0]r) Command 5C† Clear IFCI (ISR0[3]r) Command 5D† Clear ATNI (ISR0[2]r) Command 5E†

5F†

* Represents all eight bits of the AUXMR. † Denotes an auxiliary command not available in

Clear SYNC (ISR0[0]r) Command

Set SYNC (ISR0[0]r) Command

the NEC µPD7210.

Auxiliary Command

TNT4882 Interface Registers Chapter 3

AUXMR (continued)

Table 3-13. Auxiliary Command Description

Data

Pattern

(Hex)

00 Immediate Execute Power-On (pon)

The Immediate Execute Power-On auxiliary command sets the local pon message true, then clears it. If the local pon message is already asserted, the pon auxiliary command simply clears the local pon message. The following figure illustrates the behavior of the local pon message:

local pon message

true

HW reset +

chip_reset aux. command

When the local pon message is true, the TNT4882 holds all GPIB interface functions in their idle states.

Description

start of pon aux. command pulse

end of pon aux. command pulse

01 09

Clear Parallel Poll Flag (~ist) Set Parallel Poll Flag (ist)

These commands set and clear the Parallel Poll Flag. The value of the Parallel Poll Flag is used as the local ist message when AUXRB[4]w = 0. The value of SRQS is used as ist when ISS = 1. A chip reset auxiliary command or hardware reset clears ist.

(continues)

Chapter 3 TNT4882 Interface Registers

AUXMR (continued)

Table 3-13. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

02 Chip Reset

The chip reset auxiliary command resets the TNT4882 to the following conditions:

• The local pon message is set and the interface functions are

• The SPMR bits are cleared.

• The TRM[1–0] bits are cleared.

• The EOI bit is cleared.

• The AUXRA, AUXRB, AUXRE, AUXRF, AUXRG, AUXRI,

• The Parallel Poll Flag is cleared.

Description

placed in their idle states.

and AUXRJ registers are cleared.

– The BCR is cleared. – The MISC register is cleared. – The HIER is cleared. – The PT1 bit is cleared.

The interface functions remain in their idle states until they are released by an Immediate Execute pon command. While the interface functions are in their idle states, the host interface can program the TNT4882 writable bits to their desired states.

03 Finish Handshake (rhdf)

The Finish Handshake command finishes a GPIB handshake that was stopped because of a Holdoff On RFD condition.

See The GPIB rdy Message and RFD Holdoffs section in Chapter 4, TNT4882 Programming Considerations.

(continues)

TNT4882 Interface Registers Chapter 3

AUXMR (continued)

Table 3-13. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

04 Trigger (trig)

The Trigger command generates a high pulse on the TRIG pin. The Trigger command performs the same function as if the DET (Device Trigger) bit (ISR1[5]r) were set. The DET bit is not set by issuing the Trigger command.

06 Send EOI (seoi)

Return To Local (rtl) Return To Local (rtl)

The two Return To Local commands implement the rtl message as defined by the IEEE 488 standard. If the host interface writes 05 hex, the rtl message is generated in the form of a pulse. If rtl is already set, this command clears it. If the host interface writes 0D hex, the rtl command is set and remains set until either the 05 hex rtl command is issued or a chip reset auxiliary command is issued.

One-Chip Mode

The seoi command is ignored. In one-chip mode, you can use CCEN to make the TNT4882 automatically generate EOI. See the CCEN bit in the Configuration Register (CFG) section of this chapter.

Turbo+7210 Mode

The seoi command causes the GPIB End-or-Identify (EOI) line to go true with the next data byte transmitted. The EOI line is cleared upon completion of the Handshake for that byte. The TNT4882 recognizes the seoi command only if TACS = 1 (that is, the TNT4882 is in the Talker Active State) when NTNL = 0.

Description

07 Nonvalid Secondary Command Or Address (nonvalid)

The Nonvalid command releases a DAC holdoff. If APT = 1, the TNT4882 operates as if an Other Secondary Address (OSA) message had been received.

0B* Untalk (lut)

This command issues the local unt message, forcing the Talker function to enter TIDS.

(continues)

Chapter 3 TNT4882 Interface Registers

AUXMR (continued)

Table 3-13. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

0C* Unlisten (lul)

This command issues the local unl message, forcing the Listener function to enter LIDS.

0E* New Byte Available False (nbaf)

One-Chip Mode

The nbaf is ignored in one-chip mode. See description of the nba bit, ISR0[7]r.

Turbo+7210 Mode

The nbaf command causes the local message, nba, to become false. Consider the following situation. The TNT4882 is a Talker. A byte is written to the CDOR. The GPIB Controller asserts ATN before the TNT4882 transfers this byte. The Controller unasserts ATN and the TNT4882 is still a Talker.

If NTNL is set, the Talker transmits the byte stored in the CDOR. The nbaf command suppresses the transmission of this byte.

0F Valid Secondary Command Or Address (valid)

The Valid command releases a DAC holdoff. If APT = 1, the TNT4882 operates as if a My Secondary Address (MSA) message had been received.

Description

15* Switch to 9914A Mode

One-Chip Mode

The TNT4882 should not be switched to the 9914A compatibility mode.

Turbo+7210 Mode

This command puts the interface chip in Turbo+9914 compatibility mode.

(continues)

TNT4882 Interface Registers Chapter 3

AUXMR (continued)

Table 3-13. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

18* 19*

50* Page-In Additional Registers (page-in)

Request rsv True (reqt) Request rsv False (reqf)

The reqt and reqf commands are inputs to the IEEE 488.2 Service Request Synchronization Circuitry. These commands set and clear the local rsv message.

If STBO = 1, the reqt and reqf commands are issued immediately. If STBO IE = 0, the reqt and reqf commands are not issued immediately: they are issued on the write of the SPMR that follows the issuing of the reqt or reqf auxiliary command.

The Page-In command is implemented only for compatibility. You should not use it in new designs, because you can directly access all registers.

The Page-In command causes the TNT4882 to enter the Page-In state. The Page-In state changes the offset of several registers. See The Page-In State (One-Chip Mode/Turbo+7210 Mode) section, which is located earlier in this chapter.

The TNT4882 exits the Paged-In state when either the host interface accesses any 7210 register or when the Turbo488 transfer function performs a carry cycle.

Description

51* Immediate Holdoff

This command forces the Acceptor Handshake function to immediately perform an RFD holdoff when Listener. Issuing this command forces a transition into ANRS, where the handshake is held off until a finish handshake is issued.

54* Clear DET

This command clears the DET bit (ISR1[5]r). Use this command to clear the DET bit when SISB = 1.

(continues)

Chapter 3 TNT4882 Interface Registers

AUXMR (continued)

Table 3-13. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

55* Clear END

This command clears the END bit (ISR1[4]r). Use this command to clear the END bit when SISB = 1.

56* Clear DEC

This command clears the DEC bit (ISR1[3]r). Use this command to clear the DEC bit when SISB = 1.

57* Clear ERR

This command clears the ERR bit (ISR1[2]r). Use this command to clear the ERR bit when SISB = 1.

59* Clear LOKC

This command clears the LOKC bit (ISR2[2]r). Use this command to clear the LOKC bit when SISB = 1.

5A* Clear REMC

This command clears the REMC bit (ISR2[1]r). Use this command to clear the REMC bit when SISB = 1.

Description

5B* Clear ADSC

This command clears the ADSC bit (ISR2[0]r). Use this command to clear the ADCS bit when SISB = 1.

5C* Clear IFCI

This command clears the IFCI bit (ISR0[3]r). Use this command to clear the IFCI bit when SISB = 1.

5D* Clear ATNI

This command clears the ATNI bit (ISR0[2]r). Use this command to clear the ATNI bit when SISB = 1.

(continues)

TNT4882 Interface Registers Chapter 3

AUXMR (continued)

Table 3-13. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

5E* 5F*

* Denotes an auxiliary command not available in the µPD7210.

Clear SYNC Set SYNC

These commands control the SYNC function by resetting or starting it.

Description

Chapter 3 TNT4882 Interface Registers

Auxiliary Register A (AUXRA)

Type: One-chip mode

Turbo+7210 mode

Attributes: Write only

Accessed at the same offset as AUXMR

76543210 1 0 0 BIN XEOS REOS HLDE HLDA

AUXRA controls the EOS and END messages and specifies the RFD holdoff mode. A chip reset auxiliary command or a hardware reset clears AUXRA. You write to AUXRA at the same offset as the AUXMR.

Bit Mnemonic Description

4w BIN Binary bit

BIN selects the length of the EOS message. If BIN = 1, the End-of-String Register (EOSR) is treated as an 8-bit byte. When BIN = 0, the EOSR is treated as a 7-bit register (for ASCII characters), and only a 7-bit comparison is done with the data on the GPIB.

3w XEOS Transmit END With EOS bit

One-Chip Mode

XEOS is used to transmit the GPIB END message. However, the preferred method of sending END in one-chip mode uses the CCEN bit, CFG[3]w.

Turbo+7210 Mode

XEOS permits or prohibits automatic, simultaneous transmission of the GPIB END message and the EOS message when the TNT4882 is in TACS. If XEOS = 1 and the byte in the CDOR matches the contents of the EOSR, the EOI line is sent true along with the data.

TNT4882 Interface Registers Chapter 3

AUXRA (continued)

Bit Mnemonic Description

2w REOS END On EOS Received bit

The REOS bit permits or prohibits setting the END bit (ISR1[4]r) when the TNT4882 receives the EOS message as a Listener. If REOS = 1 and the byte in the DIR matches the byte in the EOSR, the END RX bit is set and the acceptor function treats the EOS character just as if it were received with EOI asserted.

1–0w HLDE Holdoff On End bit

HLDA Holdoff On All Data bit

HLDE and HLDA together determine the GPIB data-receiving mode. The following table shows the four possible data-receiving modes.

HLDE HLDA Data-Receiving Mode

0 0 Normal Handshake Mode 0 1 RFD Holdoff on All Data Mode 1 0 RFD Holdoff on END Mode 1 1 Continuous Mode

See The GPIB rdy Message and RFD Holdoffs section in Chapter 4, TNT4882 Programming Considerations.

Chapter 3 TNT4882 Interface Registers

Auxiliary Register B (AUXRB)

Type: One-chip mode

Turbo+7210 mode

Attributes: Write only

Accessed at the same offset as AUXMR

76543210 1 0 1 ISS 0 TRI SPEOI CPT

ENABLE

AUXRB affects several interface functions. A chip reset auxiliary command or a hardware reset clears AUXRB. You write to AUXRB at the same offset as the AUXMR.

Bit Mnemonic Description

4w ISS Individual Status Select bit

ISS determines the value of the TNT4882 ist message. When ISS = 1, ist takes on the value of the TNT4882 Service Request State (SRQS). (The TNT4882 is asserting the GPIB SRQ message when it is in SRQS.) If ISS = 0, ist takes on the value of the TNT4882 Parallel Poll Flag. You set and clear the Parallel Poll Flag by using the Set Parallel Poll Flag and Clear Parallel Poll Flag auxiliary commands.

2w TRI Three-State Timing bit

TRI determines the TNT4882 GPIB Source Handshake Timing (T1). Clearing TRI sets the low-speed timing (T1 ≥ 2 µs). Setting TRI enables the TNT4882 to use a shorter T1 delay. See the T1 Delay Generation section in Chapter 4, TNT4882 Programming Considerations.

1w SPEOI Send Serial Poll EOI bit

SPEOI determines whether the TNT4882 sends EOI when a Controller serial polls the TNT4882.

SPEOI EOI During Serial Polls

0 Sent False 1 Sent True

TNT4882 Interface Registers Chapter 3

AUXRB (continued)

Bit Mnemonic Description

0w CPT ENABLE Command Pass Through Enable bit

The CPT ENABLE bit permits or prohibits detecting undefined GPIB commands and permits or prohibits setting the CPT bit (ISR1[7]r).

Chapter 3 TNT4882 Interface Registers

Auxiliary Register E (AUXRE)

Type: One-chip mode

Turbo+7210 mode

Attributes: Write only

Accessed at the same offset as AUXMR

7654 3 2 1 0 1100DHADT DHADC DHDT DHDC

AUXRE determines when the TNT4882 performs a DAC holdoff. A chip reset auxiliary command or a hardware reset clears AUXRE.

Each bit of AUXRE enables DAC holdoffs on a GPIB command or group of commands. When a GPIB Controller sends the specified command to the TNT4882, the CPT bit sets and the TNT4882 performs a DAC holdoff. See the DAC Holdoffs section in Chapter 4,

TNT4882 Programming Considerations.

Bit Mnemonic Description

3w DHADT DAC Holdoff On GET Command bit

2w DHADC DAC Holdoff On DCL Or SDC Command bit

1w DHDT DAC Holdoff On DTAS Command bit

0w DHDC DAC Holdoff On DCAS Command bit

TNT4882 Interface Registers Chapter 3

Auxiliary Register F (AUXRF)

Type: One-chip mode

Turbo+7210 mode

Attributes: Write only

Accessed at the same offset as AUXMR

765432 1 0 1101DHATA DHALA DHUNTL DHALL

AUXRF determines when the TNT4882 uses a DAC holdoff. A chip reset auxiliary command or a hardware reset clears AUXRF.

Each bit of AUXRF enables DAC holdoffs on a GPIB command or group of commands. When a GPIB Controller sends the specified command to the TNT4882, the CPT bit sets and the TNT4882 performs a DAC holdoff. See the DAC Holdoffs section in Chapter 4,

TNT4882 Programming Considerations.

Bit Mnemonic Description

3w DHATA DAC Holdoff On All Talker Addresses Command bit

2w DHALA DAC Holdoff On All Listener Addresses Command bit

1w DHUNTL DAC Holdoff On The UNT Or UNL Command bit

0w DHALL DAC Holdoff On All UCG, ACG, And SCG Commands

bit

Chapter 3 TNT4882 Interface Registers

Auxiliary Register G (AUXRG)

Type: One-chip mode

Turbo+7210 mode

Attributes: Write only

Accessed at the same offset as AUXMR

76543210 0100NTNL 0 0 CHES

A chip reset auxiliary command or a hardware reset clears AUXRG.

Bit Mnemonic Description

3w NTNL No Talking When No Listener bit

One-Chip Mode

NTNL is not used. Write 0 to this bit.

Turbo+7210 Mode

Set NTNL to prevent the TNT4882 from sourcing data (talking) when there is no external Listener, to modify the setting of the ERR bit, to modify the way the nba local message is cleared, and to change the EOI generation function. If the TNT4882 is used in an IEEE 488.2 device, you should set NTNL.

If NTNL = 0, the following actions occur:

• The TNT4882 handshake function enters STRS after the T1 delay has elapsed and NRFD is unasserted.

• The ERR bit is set on TACS & SDYS & DAC & RFD or SIDS & (write CDOR) or the transition from SDYS to SIDS.

• The local nba message is cleared upon entering SIDS or STRS.

• The Send EOI auxiliary command is ignored or forgotten upon exiting TACS.

TNT4882 Interface Registers Chapter 3

AUXRG (continued)

Bit Mnemonic Description

If NTNL = 1, the following actions occur:

• The TNT4882 handshake function does not make the transition from SDYS to STRS unless an external Listener exists—that is, a device on the GPIB is asserting NDAC.

• The ERR bit is set when the T1 delay has elapsed and TACS & SDYS & EXTDAC & RFD (where EXTDAC refers to some device on the GPIB asserting NDAC).

0w CHES Clear Holdoff On End Select bit

CHES determines how long the TNT4882 remembers that it detected an END condition.

If CHES = 0, the TNT4882 remembers the detection of the END condition until the host interface issues the Release Handshake Holdoff auxiliary command.

If CHES = 1, the TNT4882 remembers the detection of the END condition until the Release Handshake Holdoff auxiliary command is issued or the DIR is read when in the normal Handshake Holdoff mode—that is, HLDE and HLDA = 0.

Chapter 3 TNT4882 Interface Registers

Auxiliary Register I (AUXRI)

Type: One-chip mode

Turbo+7210 mode

Attributes: Write only

Accessed at the same offset as AUXMR

76543210 1110USTD PP2 0 SISB

A chip reset auxiliary command or a hardware reset clears AUXRI.

Bit Mnemonic Description

3w USTD Ultra Short T1 Delay bit

USTD sets the value of the T1 delay (used by the Source Handshake function for data setup) to 350 ns for the second and subsequent data bytes sent after ATN unasserts. If USTD = 0, the TRI bit (AUXRB[2]w) determines the value of T1. See the T1 Delay Generation section in Chapter 4, TNT4882 Programming Considerations.

2w PP2 Parallel Poll bit 2

If PP2 = 0, the TNT4882 responds to parallel polls in the same manner as the µPD7210—that is, it supports Parallel Poll functions PP1 and PP2 simultaneously. However, a contradiction arises because PP1 requires the interface to be configured by remote GPIB commands, and PP2 requires the interface to be configured locally and ignore remote GPIB commands.

When PP2 = 1, the chip ignores remote GPIB commands—that is, PPC and PPU are treated as undefined commands, allowing a true implementation of PP2. In addition, setting PP2 and U (PPR[4]w) lets the TNT4882 support PP0 (no Parallel Poll response).

1w 0 Write 0 to this bit.

TNT4882 Interface Registers Chapter 3

AUXRI (continued)

Bit Mnemonic Description

0w SISB Static Interrupt Status Bits bit

If SISB = 0, reading ISR0, ISR1, or ISR2 clears the bits of that register.

If SISB = 1, the bits remain set until a certain condition is met. Table 3-14 lists the condition that clears each interrupt status bit when SISB = 1.

Table 3-14. Clear Conditions for SISB Bit

Bit Clear Condition when SISB = 1

ADSC pon + clearADSC + ton + lon APT pon + valid + nonvalid ATNI pon + clearATNI CPT pon + read CPTR DEC pon + clearDEC DET pon + clearDET DI pon + (finish handshake) * (Holdoff mode) + read DIR DO pon + ~TACS + ~SGNS + nba END pon + clearEND ERR pon + clearERR IFCI pon + clearIFCI LOKC pon + clearLOKC REMC pon + clearREMC

Note: Interrupt Status bits STBO, SYNC, and

TO are not affected by the SISB bit.

Chapter 3 TNT4882 Interface Registers

Auxiliary Register J (AUXRJ)

Type: One-chip mode

Turbo+7210 mode

Attributes: Write only

Accessed at the same offset as AUXMR

76543210 1111TM3TM2TM1TM0

AUXRJ sets the timeout value of the Timer interrupt. The timeout value can be set between 15 µs to 125 s when the TNT4882 clock is 40 MHz. The Timer is started when TM[3–0] are written with a nonzero value; the Timer sets the TO bit in ISR0 when the timeout value expires. The Timer is cleared when a 0 is written to TM[3–0]. For more information on the Timer interrupt capability, see the Interrupt Status Register 0 (ISR0)—One-Chip Mode, Turbo+7210 Mode section in this chapter. AUXRJ is reset by a hardware or chip reset auxiliary command.

Note: This timer is independent of the DRQ assertion timer described by the TIMER. Bit Mnemonic Description

3–0w TM[3–0] Timer bits 3 through 0

Table 3-15 lists the approximate timeout values that AUXRJ supports at 40 MHz. If the TNT4882 uses another clock frequency, the timeout value can be computed with the following formula:

time = (2

factor

* 5)/frequency.

Table 3-15. Timeout Values in 7210 Mode

TM3–0 Timeout Value (> or =) Factor

0000 Disable 0001 16 µs7 0010 32 µs8 0011 128 µs10 0100 256 µs11

(continues)

TNT4882 Interface Registers Chapter 3

AUXRJ (continued)

Table 3-15. Timeout Values in 7210 Mode

(Continued)

TM3–0 Timeout Value (> or =) Factor

0101 1 ms 13 0110 4 ms 15 0111 16 ms 17 1000 33 ms 18 1001 131 ms 20 1010 262 ms 21 1011 1 s 23 1100 4 s 25 1101 17 s 27 1110 34 s 28 1111 134 s 30

Depending on the value of the BTO bit, IMR0[4]w, the Timer works with two different types of timeouts. If BTO = 0, the Timer starts when the host interface writes a nonzero value to the Timer Register. When the Timer reaches the timeout value, it sets the TO bit. If BTO = 1, the Timer operates in byte timeout mode. In this mode, the Timer starts when the host interface writes a nonzero value to the Timer Register and counts until it reaches the timeout value. However, reads of the DIR or writes of the CDOR clear the Timer and force it to start counting over. If TO is set in byte timeout mode, it remains set until the Timer Register is written. Further reads of DIR or writes of CDOR have no effect on TO until the Timer Register is written.

When BTO = 1 in one-chip mode, the Timer is cleared whenever a byte is transferred between the FIFOs and the GPIB.

Chapter 3 TNT4882 Interface Registers

Bus Control Register (BCR)/Bus Status Register (BSR)

Type: All modes Attributes: Write only (BCR)

Read only (BSR)

Reads of the Bus Status Register (BSR) return the status of the GPIB control lines at the time of the read. Write ones to bits in the Bus Control Register (BCR) to assert the corresponding GPIB control lines.

76543210

ATN DAV NDAC NRFD EOI SRQ IFC REN

Bit Mnemonic Description

7r ATN GPIB Attention Status bit 7w ATN GPIB Attention Control bit

6r DAV GPIB Data Valid Status bit 6w DAV GPIB Data Valid Control bit

5r NDAC GPIB Not Data Accepted Status bit 5w NDAC GPIB Not Data Accepted Control bit

4r NRFD GPIB Not Ready For Data Status bit 4w NRFD GPIB Not Ready For Data Control bit

3r EOI GPIB End-or-Identify Status bit 3w EOI GPIB End-or-Identify Control bit

2r SRQ GPIB Service Request Status bit 2w SRQ GPIB Service Request Control bit

1r IFC GPIB Interface Clear Status bit 1w IFC GPIB Interface Clear Control bit

0r REN GPIB Remote Enable Status bit 0w REN GPIB Remote Enable Control bit

TNT4882 Interface Registers Chapter 3

Carry Cycle Register (CCR)

Type: Turbo+7210 mode

Turbo+9914 mode

Attributes: Write only

76543210

D7 D6 D5 D4 D3 D2 D1 D0

One-Chip Mode

The Carry Cycle Register (CCR) is ignored in one-chip mode. See the description of the CCEN bit, CFG[3]w, in the Configuration Register (CFG) section in this chapter.

Turbo+7210 Mode Turbo+9914 Mode

If CCEN = 1, the TNT4882 performs a carry cycle before the last byte of a GPIB transfer operation is transferred between the FIFOs and the CDOR or DIR. During a carry cycle, the TNT4882 writes the contents of the CCR to the register at offset 0A (hex) of the TNT4882.

The CCR holds the 8-bit auxiliary command that is written during carry cycles. Any auxiliary command is valid. For GPIB writes, you generally write the seoi auxiliary command pattern to the CCR. For GPIB reads, you generally write the Holdoff On All auxiliary command pattern to the CCR. If the last byte of the current transfer requires no special action, the CCEN bit in the Configuration Register must be cleared so a carry cycle will not take place. The CCR is not affected by a reset.

In Turbo+7210 mode, the AUXMR is at offset 0A. Notice that auxiliary registers also appear at offset A.

In Turbo+9914 mode, carry cycles are usually performed when the SWAP condition is true. If SWAP is true, the ACCR appears at offset 0A.

Chapter 3 TNT4882 Interface Registers

Command/Data Out Register (CDOR)

Type: Turbo+7210 mode

Turbo+9914 mode

Attributes: Write only

76543210

DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1

Bit Mnemonic Description

7–0w DIO[8–1] GPIB data lines DIO[8–1]

One-Chip Mode

Do not use the CDOR in one-chip mode.

Turbo+7210 Mode Turbo+9914 Mode

The CDOR moves data from the CPU to the GPIB when the interface is the GPIB Talker. Writing to the CDOR sets the local message, nba. When nba is true, the Source Handshake (SH) function can transfer the data in the CDOR to other GPIB devices. Writing to the CDOR can also reset the internal timer. (See the Auxiliary Register J section in this chapter.)

The CDOR and the DIR use separate latches. A read of the DIR does not change data in the CDOR. The CDOR is a transparent latch; thus, the GPIB data bus (DIO(8–1)) reflects changes on the CPU data bus during write cycles to the CDOR.

TNT4882 Interface Registers Chapter 3

Configuration Register (CFG)

Type: All modes Attributes: Write only

765432 1 0 0 TLCHLTE IN A/BN CCEN TMOE TIM/BYTN 16/8N

The Configuration Register (CFG) contains bits that are used to configure the TNT4882 for a GPIB transfer. All the bits in the CFG are cleared on reset.

Bit Mnemonic Description

7w 0 Write 0 to this bit.

6w TLCHLTE TLC Halt Enable bit

If TLCHLTE = 1, IMR2, IMR1, and IMR0 interrupts cause the HALT signal to assert. HALT causes the GPIB transfer to stop.

If the NOAS bit, MISC[1], or the NOTS bit, MISC[0], is set, certain TNT4882 interrupts do not cause a HALT even if TLCHLTE is asserted.

5w IN Data Direction Transfer bit

IN determines the direction of the GPIB transfer operation. IN = 1 indicates a GPIB read operation. The TNT4882 reads data from the GPIB and stores it in its FIFOs.

IN = 0 indicates a GPIB write operation. The TNT4882 transfers data from the FIFOs to the GPIB.

4w A/BN FIFO First bit

This bit indicates which FIFO—A or B—the first GPIB data byte should be transferred to or from. If A/BN = 1, FIFO A is first.

Chapter 3 TNT4882 Interface Registers

CFG (continued)

Bit Mnemonic Description

3w CCEN Carry Cycle Enable bit

If CCEN = 1, the TNT4882 inserts a carry cycle before the last byte of a GPIB transfer operation is transferred between the FIFOs and the TNT4882.

One-Chip Mode

In this mode, the CCR is ignored. On the last byte of a GPIB write, EOI is asserted if CCEN = 1.

Turbo+7210 Mode Turbo+9914 Mode

During a carry cycle, the TNT4882 writes the contents of the CCR to the register at offset 0A (hex) of the TNT4882. In Turbo+7210 mode, the AUXMR appears at offset A. In Turbo+9914 mode, the ACCR appears at offset A if the SWAP bit is set. CCEN forces a GPIB read operation to holdoff the handshake on the last byte or forces a GPIB write operation to send EOI with the last byte.

2w TMOE Timer Timeout Enable bit

TMOE limits the duration of DMA burst transfers. If TMOE = 1, the TNT4882 unasserts the DMA Request (DRQ) signal after the amount of time or the number of transfers specified by the TIM/BYTN bit and the Timer Register (TIMER) passes. This bit helps limit the amount of time that the DMA Controller serving the TNT4882 holds the bus while transferring data between the TNT4882 and memory.

1w TIM/BYTN Time Or Byte Limit bit

If TIM/BYTN = 1, the DRQ assertion timer begins counting when the host interface performs a DMA access of the TNT4882 FIFOs. If DRQ unasserts, the DRQ assertion timer resets and reloads the timeout value from the TIMER. If the DRQ assertion timer reaches its time limit, the TNT4882 unasserts DRQ during the next DMA access of the TNT4882 FIFOs.

TNT4882 Interface Registers Chapter 3

CFG (continued)

Bit Mnemonic Description

If TIM/BYTN = 0, the TIMER contains the number of transfers for which the DMA Request signal remains asserted. TIM/BYTN is not used if TMOE = 0.

0w 16/8N 16- or 8-Bit Mode bit

16/8N determines whether the TNT4882 packs and unpacks data from both FIFO A and B or from only FIFO B.

If 16/8N = 1, the TNT4882 packs and unpacks data from both FIFO A and B. The host interface should transfer data to and from the FIFOs as 16-bit words.

If 16/8N = 0, the TNT4882 uses only FIFO B. Data should transfer to and from FIFO B as 8-bit bytes.

Chapter 3 TNT4882 Interface Registers

Command Register (CMDR)

Type: All modes Attributes: Write only

76543210

CMD7 CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0

By writing command codes to the Command Register (CMDR), you cause special actions to occur. A command code is assigned to each special action. Patterns that are not specified in Table 3-16 are reserved; do not write them to the CMDR.

Note: Accesses to the CMDR must be separated by at least four clock cycles.

Table 3-16. Command Summary: Detailed Description

Hex

Code

04 GO

Description

One-Chip Mode

The GO command clears the HALT signal. The transfer state machine is not used in one-chip mode.

Turbo+7210 Mode Turbo+9914 Mode

The GO command starts the Turbo+7210 and Turbo+9914 transfer state machine, which is a functional module within the TNT4882. This command is sent after all the programming registers in the TNT4882 are programmed for a GPIB transfer. Sending this command clears the DONE and STOP bit in ISR3 so that command or data transfers between the FIFOs and the CDOR or DIR begin.

(continues)

TNT4882 Interface Registers Chapter 3

CMDR (continued)

Table 3-16. Command Summary: Detailed Description (Continued)

Hex

Code

08 STOP

One-Chip Mode

The Turbo488 transfer state machine is not used in one-chip mode. The STOP command sets the HALT signal. The GO command clears the HALT signal. When HALT = 1, the nba and rdy messages become false. Thus, the TNT4882 does not accept or send any GPIB data bytes.

Turbo+7210 Mode Turbo+9914 Mode

The STOP command stops the TNT4882 transfer state machine. Send this command to stop a GPIB transfer in progress. If a byte is being transferred between the CDOR or DIR and the FIFOs when the STOP command is sent, the byte finishes transferring before the transfer state machine is stopped. After the STOP command is sent, DONE is set when the GPIB is synchronized—that is, the last byte is accepted by all GPIB Listeners and (for GPIB reads only) the FIFOs are empty.

10 RESET FIFO

The RESET FIFO command resets both FIFOs to the empty state.

22 SOFT RESET

Sending the SOFT RESET command

• Clears the CFG, HSSEL, and IMR3 registers.

Description

• Sets the DONE, HALT, STOP, and GSYNC bits.

• Resets the internal FIFOs to empty.

• Resets the GPIB transfer state machine.

• Clears the DRQ signal.

• Configures the byte counters for 16-bit operation.

Chapter 3 TNT4882 Interface Registers

Count 0 Register (CNT0)

Type: All modes Attributes: Read/Write

76543210

CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0

Count 1 Register (CNT1)

Type: All modes Attributes: Read/Write

76543210

CNT15 CNT14 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8

Count 2 Register (CNT2)

Type: All modes Attributes: Read/Write

76543210

CNT23 CNT22 CNT21 CNT20 CNT19 CNT18 CNT17 CNT16

Count 3 Register (CNT3)

Type: All modes Attributes: Read/Write

76543210

CNT31 CNT30 CNT29 CNT28 CNT27 CNT26 CNT25 CNT24

TNT4882 Interface Registers Chapter 3

Count Registers

These four count registers—CNT0, CNT1, CNT2, and CNT3—store the transfer count of the GPIB transfer operation. The transfer counter operates in one of two modes: 16-bit mode and 32-bit mode. The HWE signal determines which mode is used. When HWE is true, the byte counters operate in 32-bit mode. When HWE is false, the byte counters operate in 16-bit mode. A hardware reset or the SOFT_RESET command clears HWE. A write to the CNT3 or CNT2 sets HWE.

A hardware reset sets the CNT0, CNT1, CNT2, and CNT3 to 0xFF. The SOFT_RESET command sets the CNT3 and CNT2 to 0xFF. Before a transfer begins, the transfer count registers must be loaded with the two's complement of the transfer count.

32-Bit Mode

Write the least significant byte of the two's complement of the GPIB transfer count to the CNT0, then write the next most significant bytes of the two's complement of the GPIB transfer count to the CNT1 and CNT2. Finally, write the most significant byte of the two's complement of the GPIB transfer count to the CNT3. Until it reaches the terminal value of zero, the 32-bit counter is incremented once for every byte transferred. You can read the counters at any time to learn the two's complement of the current GPIB transfer count.

Note: To guarantee proper operation, always write to the CNT0 first, then write to

the CNT1. Next, write to the CNT2, then the CNT3. The operation may not complete properly if you write to the counters in any other order.

16-Bit Mode

Write the low byte of the two's complement of the GPIB transfer count to the CNT0, then write the high byte of the two's complement of the GPIB transfer count to the CNT1. Until it reaches the terminal value of zero, the 16-bit counter is incremented once for every byte that is transferred. You can read the counters at any time to learn the two's complement of the current GPIB transfer count.

Chapter 3 TNT4882 Interface Registers

Command Pass Through Register (CPTR)

Type: All modes Attributes: Read only

76543210

CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0

The host interface can examine the GPIB DIO lines by reading the Command Pass Through Register (CPTR). The CPTR has no storage; the host interface should read the CPTR only during a DAC holdoff. See the DAC Holdoffs section in Chapter 4, TNT4882

Programming Considerations.

Bit Mnemonic Description

7–0r CPT[7–0] Command Pass Through bits 7 through 0

TNT4882 Interface Registers Chapter 3

Chip Signature Register (CSR)

Type: One-chip mode

Turbo+7210 mode

Attributes: Read only

76543210

V3 V2 V1 V0 KEYDQ MODE 0 0

The Chip Signature Register (CSR) contains a value unique to each version of the TNT4882. This value can distinguish the CSR from other IEEE 488 chips.

Bit Mnemonic Description

7–4r V[3–0] Reads back 0011, a value unique to the TNT4882. Future

versions of the TNT4882 may read back 01XX.

3r KEYDQ Key Data bit

KEYDQ returns the logic value of the KEYDQ pin. If you are using an electronic key, the KEYDATEN bit in the KEY register must be clear to read data from the key. Key data bits are read from the key memory on the rising edge of KEYCLK.

2r MODE MODE bit

MODE returns the logic value of the MODE pin. The MODE pin determines which mode the TNT4882 is in following a hardware reset. If MODE = 0, the TNT4882 functions in Turbo+9914 mode following a hardware reset. If MODE = 1, the TNT4882 functions in Turbo+7210 mode following a hardware reset.

1–0r 0 These bits read 0.

National Instruments TNT4882 TNT4882 reference manual (370872A-01)

Specifications and Main Features

Frequently Asked Questions

User Manual

Limited Warranty

Copyright

Trademarks

Contents

Figures

Tables

About This Manual

Organization of This Manual

Conventions Used in This Manual

Related Documentation

Customer Communication

Chapter 1 Introduction and General Description

TNT4882 Features

IEEE 488 Capabilities

Table 1-1. TNT4882 IEEE 488 Interface Capabilities

CPU Interface Features

Bus Interface Capabilities

Chapter 2 TNT4882 Architectures

Turbo+7210 Mode

Figure 2-1. Turbo+7210 or Turbo+9914 Mode Block Diagram

Turbo+9914 Mode

One-Chip Mode

Figure 2-2. One-Chip Mode Block Diagram

Choosing a TNT4882 Architecture Mode

One-Chip Mode

Turbo+9914 Mode

Turbo+7210 Mode

Changing the TNT4882 Architecture Modes

Figure 2-3. Changing the Three TNT4882 Architecture Modes

Architecture After a Hardware Reset

Changing between Turbo+9914 Mode and Turbo+7210 Mode

Changing between One-Chip Mode and Turbo+7210 Mode

Chapter 3 TNT4882 Interface Registers

One-Chip Mode/Turbo+7210 Mode Registers

Table 3-1. TNT4882 Register Bit Map: One-Chip Mode and Turbo+7210 Mode

Hidden Registers: One-Chip Mode/Turbo+7210 Mode

Address Register Map

Table 3-2. Hidden Registers at Offset C (ADR)

Auxiliary Mode Register Map

Table 3-3. Hidden Registers at Offset A (AUXMR)

SH_CNT Map

Table 3-4. Register Map of the SH_CNT Register

The Page-In State (One-Chip Mode/Turbo+7210 Mode)

When to Use the Page-In State

How to Page-In

Table 3-5. One-Chip Mode and Turbo+7210 Mode Page-In State Register Offsets

Turbo+9914 Mode Registers

Table 3-6. TNT4882 Register Bit Map: Turbo+9914 Mode

Hidden Registers: Turbo+9914 Mode

Accessory Read Register Map

Table 3-7. Hidden Registers at the ACCR Offset

The SWAP Bit

Setting the SWAP Bit

Recommendation

The Page-In Condition (Turbo+9914 Mode)

Register Bit Descriptions

8-Bit Versus 16-Bit Accesses

9914 and 7210 Registers with Identical Names

Accessory Register A (ACCRA)

Accessory Register B (ACCRB)

Accessory Register E (ACCRE)

Accessory Register F (ACCRF)

Accessory Register I (ACCRI)

Accessory Register J (ACCRJ)

Table 3-8. Timeout Values in Turbo+9914 Mode

Accessory Write Register (ACCWR)

Address Mode Register (ADMR)

Table 3-9. Valid ADMR Patterns

Address Register (ADR)—One-Chip Mode, Turbo+7210 Mode

Address Register (ADR)—Turbo+9914 Mode

Address Register 0 (ADR0)

Address Register 1 (ADR1)

Address Status Register (ADSR)—Turbo+7210 Mode

Address Status Register (ADSR)—Turbo+9914 Mode

Auxiliary Command Register (AUXCR)

Table 3-10. Auxiliary Command Summary