National Instruments SLSC-12101 User Manual

USER GUIDE

SLSC-12101

Prototyping Module

RADIAL SELECTOR

CONNECTOR J1

CONNECTOR J2

SLSC -12101

POWER

READY

PROTOTYPING MODULE

Overview

The SLSC-12101 is a prototyping module intended to help SLSC module developers quickly prototype designs. The module is Level-2 compatible, but can be Level-1 compatible if you configure the rear I/O signals properly.

The SLSC-12101 features a MAX V CPLD as a module controller, which is pre-programmed to provide basic access to the board peripherals. The MAX V CPLD is divided into four banks, and the I/O for each is routed to its own region in the prototyping area. Each bank may have

independent voltage settings to allow the use of different digital standards supported by the CPLD. Custom circuitry in the prototyping area has access to 24 V and 3.3 V rails from the backplane, 5 V from the auxiliary power supply and corresponding bank power supply. Two of the regions of the prototyping area, Bank 1 and Bank 2, include connections to two 44-pin DSUB connectors in the front panel. A fifth region in the prototyping area, labeled RTI, provides additional space to access the upper rear I/O connectors.

The peripherals designed into the SLSC-12101 board include two front panel LEDs (which follow the recommendations of the SLSC Design Guidelines), a 16-position rotary switch, four temperature sensors, and 17 ports 8-bit wide routed to their corresponding banks in the prototyping area.

Additionally, to ease debugging and prototyping, a JTAG header compatible with Altera's USB Blaster pinout is populated on the board which allows you to program the CPLD with a custom design. A MICTOR connector exists between the CPLD and the SLSC connector to allow monitoring of the SLSC interface signals using a logic analyzer such as the one on NI VirtualBench.

Note All modifications to this module must comply with the Switch Load and

Signal Conditioning Module Design Specifications. It is the user's responsibility to

make sure that the product is modified and used in a way that complies with local rules, regulations, and best practices.

Note All specifications and certifications in the manual apply only to the unaltered

product as provided by National Instruments. Any changes to the product invalidate these specifications and certifications.

Related Documentation

This user guide assumes you have access to the documentation of the SLSC Module Development Kit (MDK) and that you are familiar with the following documents:

• Switch Load and Signal Conditioning Module Design Specifications—Specifications SLSC modules must abide in order to be compatible with SLSC systems.

• SLSC Design Guidelines—Describes best practices recommended for SLSC modules.

• SLSC-12101 Schematic—Schematic of the SLSC-12101 prototyping module.

• SLSC-12101 Specifications—Specifications of the unaltered SLSC MDK.

Other Files Available for the SLSC-12101 Module

These files are included in the SLSC Example Modules Files .zip file of the SLSC MDK.

• Module Controller VHDL code—Slsc12101Top.vhd, PkgEdBlock.vhd,

PkgRevision.vhd, PkgSlsc12101Registers.vhd, PkgSlscProtocol.vhd, EdBlock.vhd, Interrupt.vhd, IoPort.vhd, Leds.vhd, SpiChannelSelect.vhd, Control.vhd, CrcGen.vhd, ShiftRegister.vhd, Spi.vhd

• Module Controller Quartus project files—SlscCpldTop.qpf, SlscCpldTop.qsf,

SlscCpldTop.sdc, SlscCpldTop.pof

• SLSC-12101 Capabilities files—SLSC-12101.bin, SLSC-12101.json

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• 2D Mechanical Drawings and 3D Models

• SLSC-12101 PCB Drawing

Required Software

• NI LabVIEW 2015 or newer

• NI-SLSC driver

• To customize the CPLD: Quartus Design software, found on Quartus Software's website

• To customize the Flash: createNvmemImage.py, included in the SLSC MDK files

Other Files

• SLSC-12101.vi—Example VI to access the SLSC-12101 properties.

Getting Started with the SLSC-12101

The SLSC-12101 can be inserted into an SLSC chassis and used the way it is shipped.

Note The SLSC chassis and SLSC modules do not support hot plug-in. The entire

chassis must be powered down when a module is installed or removed.

1. Ensure the CPLD power supplies are properly set.

After taking the module out of its packaging, check that three jumpers are inserted between pins 5 and 10 of headers W2, W3, and W4. This ensures that the voltage is set to

3.3 V for the CPLD I/O banks 2, 3, and 4.

Quartus Design Software is offered in a variety of editions with different features and price ranges. Refer to the Quartus Software website for more information.

SLSC-12101 User Guide | © National Instruments | 3

Figure 1. Jumper Configuration

2. Install the module in the SLSC chassis.

Power off the SLSC chassis and then insert the module into an available slot. If you are using the JTAG connector to program the CPLD or MICTOR cable to a logic analyzer, leave one empty slot to the right of the module for cable routing. Connect the cable(s) before inserting the module in the chassis.

3. Power up the chassis.

As soon as the chassis is powered up, the power LED of the front panel of the SLSC-12101 should be lit green. The chassis will boot-up and start querying the slots for module presence. Once the module is detected, the Ready LED should be lit green.

4. Access the module's properties and physical channels.

Use a host computer with LabVIEW and the NI-SLSC driver installed, and connected to the same network as the SLSC chassis. Open SLSC-12101.vi. This VI gives you access to the properties and physical channels that control the peripherals of the module. You can control the LEDs, read the value dialed in the rotary switch, and access all the DIO going to the prototyping area.

Description of the SLSC-12101

Mechanical Features

Unless otherwise noted, mechanical attributes and restrictions such as maximum component height are defined in the Switch Load and Signal Conditioning Module Design Specifications.

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Top View and Main Components

The following figure shows the top view of the SLSC-12101 module and highlights its most relevant components.

Figure 2. SLSC-12101 Top View

1 1 1 2

BANK 1

BANK 2

BANK 3

RTI

BANK 4

1. Temperature Sensor (4x)

2. Voltage Configuration Header - Bank 2

3. Voltage Configuration Header - Bank 4

4. Voltage Configuration Header - Bank 3

5. MICTOR Connector (for NI VirtualBench)

6. JTAG Header (CPLD Programming)

• Prototyping area—The biggest area of the board is used for prototyping and is divided into five areas filled with thru-hole grids. These grids can be used with standard 0.10" headers, or may have wires or thru-hole components soldered to them. The prototyping area provides access to the majority of the CPLD I/O, the front and rear connectors, power supplies, and ground.

• Module controller—Implemented in a MAX V CPLD, handles the communication with the SLSC chassis and controls the peripherals.

• Variable power supplies for CPLD Banks 2, 3, and 4—These power supplies can be set by the developer by placing the jumper of the corresponding header in the correct position.

Note The jumpers must be set before powering the module and should not be

changed once the system is powered.

• Front and rear connectors—The connectors on the front panel and those facing the RTI area are the same as those recommended in the Switch Load and Signal Conditioning Module Design Specifications and in the SLSC Design Guidelines.

• Rotary switch—The position of the rotary switch can be accessed by standard SLSC properties.

• Front panel LEDs—The LEDs can be controlled through standard SLSC properties.

• Temperature sensors—4x ADT7310 are connected to the CPLD.

SLSC-12101 User Guide | © National Instruments | 5

Front Panel

The following figure shows the front view of the module and highlights its features.

Figure 3. Front Panel

CONNECTOR J1 CONNECTOR J2

SLSC -12 101

PROTOTYPING MODULE

POWER

READY

RADIAL SELECTOR

1. SLSC Interface Compatibility Glyph—This indicates chassis compatibility type.

2. SLSC Rear I/O Compatibility Glyph—This indicates RTI compatibility type, which is left blank for customization. See the Switch Load and Signal Conditioning Module Design Specifications for more information.

3. Top Module Mounting Screw

4. LEDs—See Front Panel LEDs section for more details.

5. Rotary Switch

6. Connector J1 (high-density 44-position DSUB)

7. Connector J2 (high-density 44-position DSUB)

8. Injector/Ejector Handle

9. Bottom Module Mounting Screw

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Connectors

The SLSC-12101 is designed with the front and rear connectors recommended in the Switch Load and Signal Conditioning Module Design Specifications and SLSC Design Guidelines.

The module has the proper connectors for meeting Level-1 compatibility, but you must properly configure signals to and from these connectors in the RTI prototyping area. Refer to the Switch Load and Signal Conditioning Module Design Specifications for compatibility requirements.

Prototyping Area Hole Arrays

The following figure provides information about the arrays of holes found in the prototyping areas. These holes may be used for direct soldering of components and wires, or for attaching standard headers to connect to jumpers or secondary PCBs.

Figure 4. Prototyping Area Hole Array Details

2.54 mm (0.100 in.)

Ø 1.02 mm

(0.040 in.)

plated

Prototyping Area

Hole Array Detail

129.54 mm (5.100 in.)

71.12 mm (2.800 in.)

68.58 mm (2.700 in.)

66.68 mm (2.625 in.)

15.24 mm (0.600 in.)

2.54 mm (0.100 in.)

0.0 mm (0.0 in.)

16.51 mm (0.650 in.)

19.05 mm (0.750 in.)

27.31 mm (1.075 in.)

117.48 mm (4.625 in.)

208.92 mm (8.225 in.)

110.49 mm (4.350 in.)

Mounting Holes

The following figure provides information about the location and size of mounting holes. The three holes across the top of the PCB are reserved for future extension hardware. See the Switch Load and Signal Conditioning Module Design Specifications for information about placement restrictions around these holes.

SLSC-12101 User Guide | © National Instruments | 7

Twelve other mounting holes are provided: three larger holes in the corners of the board, and nine smaller holes forming a grid in the center of the board in the prototyping area. These may be used at the discretion of the module developer to provide mechanical fixturing as needed, including shields, brackets, or mounting standoffs for custom secondary PCBs.

Figure 5. Mounting Hole Sizes and Locations

127.00 mm (5.000 in.)

3X 66.68 mm

(2.625 in.)

3X 9.53 mm

(0.375 in.)

6.35 mm (0.250 in.)

0.0 mm (0.0 in.)

1.27 mm (0.50 in.)

253.54 mm (9.982 in.)

3X Ø 3.18 mm (0.125 in.) Non-plated Thru Holes

3X Holes Reserved for Extension HW

9X Ø 2.69 mm (0.106 in.) Non-plated Thru Holes

3X 110.49 mm (4.350 in.)

3x 198.12 mm (7.800 in.)

0.0 mm (0.0 in.)

2X 11.94 mm (0.470 in.)

3X 19.05 mm (0.750 in.)

3X 123.83 mm

(4.875 in.)

Electrical Features

The Input Rails and Fuse

The module takes its power from the 24 V and 3.3 V provided by the chassis. 3.3 V is only used for the VCCO of Bank 1 and other support circuitry such as the 40 MHz oscillator, flash memory, and thermal sensors. The rest of the banks and the core power used by the CPLD come from cascaded switcher regulators powered from an auxiliary 5 V supply connected to the 24 V rail. Banks 2-4 can be set to different values to allow you to use different digital standards available in the CPLD.

All the 24 V, 5 V, and Banks 1-4 VCCOs are available in the prototyping area to be used by the support circuitry required by your design. You should make sure your design does not exceed the power limitations of these rails.

As required by the Switch Load and Signal Conditioning Module Design Specifications, the 24 V power supply is protected by a 3.5 mA fuse. See the SLSC-12101 Bill of Materials for more information.

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Auxiliary 5 V Power Supply

The programmable power supplies and the CPLD core power supply of 1.8 V are all powered by an auxiliary 5 V power supply which is powered from the 24 V provided by the SLSC chassis. This 5 V power supply is also available in the prototyping area. The power supply can support a maximum of 6 A.

Variable Voltage Power Supplies

The MAX V supports VCCIO of 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V in order to use several I/O standards. The SLSC-12101 has user-configurable power supplies for three of the four CPLD banks. The voltages are set by placing a jumper in the corresponding header connecting the pair labeled with the desired voltage. The jumper should be placed on the board before the module is inserted in the SLSC chassis.

Once a voltage is set for a bank, all the signals on that bank need to use an I/O standard supported by that voltage. For more information about the supported I/O standards and rules to interconnect I/O standards with the MAX V CPLD, refer to Altera's MAX V Device Handbook.

The voltages of all the banks are also routed to the prototyping area to allow the circuits built there to use it. The maximum current that can be withdrawn from each bank depends on the maximum current the source can provide, as well as the estimated current used by the CPLD. Bank 1 is powered directly from the SLSC chassis and, by SLSC Specification 1.0, the module shall not withdraw more than 400 mA. Banks 2-4 take their power from 24 V on-board power supplies and can provide up to 2 A. In addition to the limitations imposed by the current limits on the different rails on the module, you should also consider the power dissipation limitations as defined in the Switch Load and Signal Conditioning Module Design Specifications.

Table 1. Bank Rail Available Voltages and Current Limits

Bank Available Voltages Maximum Current

1 3.3 V fixed, provided by the SLSC backplane 400 mA

2 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V 2 A

3 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V 2 A

4 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V 2 A

Module Controller

The SLSC-12101 Module Controller is implemented using Altera's MAX V 5M1270ZF256I5N. The CPLD is shipped pre-programmed with the compiled version of the

Slsc12101Top.vhd design also included in the SLSC Module Development Kit. The

controller's default image already implements the EdBlock.vhd design to handle SLSC Frames and the required compliance registers as described in Chapter 8 of the Switch Load and Signal Conditioning Design Specifications. Through the ED Mode, the controller can access the peripherals present on the board, such as the front panel LEDs, the front panel rotary switch, and 17 8-bit I/O ports routed from the CPLD to the prototyping area.

SLSC-12101 User Guide | © National Instruments | 9

CPLD Programming

The SLSC-12101 has a header that directly connects to Altera's USB Blaster to quickly program the CPLD with a custom design. You can use the SLSC12101Top.vhd file provided in the SLSC Module Development Kit as a starting point for development.

Front Panel LEDs

The SLSC-12101 has Power and Ready LEDs as recommended in section 3.6 of the Switch Load and Signal Conditioning Design Specifications. The LEDs can be lit red, yellow, and

green—continuously or blinking—so you can implement the information in Table 3-1 of that specification. The default module controller behavior implements the Power Solid Green and the Ready Solid Green as recommended in Table 3-1.

The Leds.vhd component provided with the SLSC Module Development Kit implements an easy interface to control the LEDs through the NI.ReadyLedColor, NI.ReadyLedMode, NI.PowerLedColor, and NI.PowerLedMode properties described in the capabilities file included as part of the kit.

Rotary Switch

The 16-position, 4-bit rotary switch on the front panel is accessible from the CPLD. The value can be accessed through the SLSC API using the NI.RotarySwitch property.

SI5356A Clock Generator

The module has pads for you to add an SI5356A clock generator should you need more clocks in your design. This clock generator can provide up tp four different frequencies on eight pins. Each output clock has two pins. In the SLSC-12101, one pin is routed to a global clock pin of the CPLD, and another pin is routed to the prototyping area. For more information on the routing of these clocks to the prototyping area, refer to the pinout sections and the SLSC-12101 Schematic.

Design Development, Characterization, and Debugging

The SLSC-12101 was designed to provide an easy way to prototype SLSC modules in development. Use the resources provided by the SLSC chassis, the module controller, and the connectors to help you implement your design, to characterize some aspects such as power consumption and dissipation, as well as for increased visibility for diagnostics.

Prototyping Area

Most of the board consists of the prototyping areas, which are filled with hole arrays of

2.54 mm (0.100 in.) pitch. These are all plated holes to ease soldering. There are five main grid areas for prototyping: Bank 1, Bank 2, Bank 3, Bank 4, and RTI. Each bank gives access to signals of the corresponding bank on the CPLD as well as to the corresponding bank VCCO. Banks 1 and 2 also provide access to the front panel connectors.

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The RTI grid contains holes connected to the rear I/O connectors, XJ02 and XJ03, along with several grounds, access to the 24 V supply from the backplane, and two pairs of holes connected to each of the bank rails.

Each of the five grids has its own coordinate system. Rows are numbered from top to bottom, and columns are marked with letters from left to right. Hole A1 is always at the top-left corner. These coordinates are referenced in this document.

For a detailed assignment of the hole arrays, refer to the SLSC-12101 pinout sections of this manual.

Power Consumption Validation

To ease the validation of power consumption in the module, you can monitor the power rails. The 24 V and 3.3 V rails provided by the backplane go through bridge resistors that can be removed so that current measurements can be performed. Resistor R 16 connects the backplane 24 V rail to the module, and W1 provides two holes to connect a bypass cable for current measurement or an external power supply. The 3.3 V rail uses resistor R168 as the bridge and W6 as the bypass holes.

Figure 6. 24 V Bridge Resistor and Bypass Holes

The power supplies for banks 2-4 do not have a bridge resistor. Instead they are routed in such a way that they have a thick trace on the primary side of the board so it can be cut. Holes exist for bypass cables. A dotted line with a label of the bank it supplies power to indicates where the trace should be cut. See the following figures.

Figure 7. Bank 2 Voltage Setting Header and Dotted Lines for Power Trace Cutting

SLSC-12101 User Guide | © National Instruments | 11

Figure 8. Bank 3 and Bank 4 Voltage Setting Header

Logic Analyzer Connector

A 43-pin MICTOR Connector is placed between the CPLD and SLSC Interface connector for direct monitoring of the signals using a logic analyzer. In addition to the SLSC signals, 17 debug lines are connected directly from the CPLD to the connector. In the shipping CPLD image, two of these lines are controlled by DIO ports, one line is a copy of the internal 40 MHz clock, and 14 lines are only driven to GND. You can use all 17 lines to monitor internal signals of your design. See pinout sections for more information on the signal routing to this connector.

Description of the Module Controller HDL

General Architecture

The SLSC-12101 Module Controller instantiated in the MAX V CPLD is implemented in VHDL. The top-level file is Slsc12101Top.vhd. The design uses an instance of EdBlock (EdBlock.vhd) to handle the communication between the SLSC chassis and the Module Controller. The design features an SPI Channel selector which can be used for future SPI channel expansion in the SLSC architecture. This channel expansion can be used in this module to access temperature sensors in the prototyping area.

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Figure 9. SLSC-12101 Block Diagram

Prototyping Area Banks

Front Panel LEDs

Temperature Sensors Alarms

Other Internal

Registers

4x Temp Sensor

Channels

Rdy/Rst#

SLSC-12101 Controller (5M1270ZF25615N)

SpiClk

SpiMOSI

ED_SS#

ID_SS#

Int#

TTM

TFM

Id SPI Channel

MISO

ID_SS

SpiClk

SpiMosi

SpiMISO

RegInterface Bus

IoPort.vhd

Interrupt.vhd

Interrupt

LEDs

17x I/O

Ports

EdBlock

SPI

Channel

Select

SpiChannelSelect.vhd

EdBlock RegInterface

(cRegPortOut, cRegPortIn)

EdBlock.vhd Spi.vhd Control.vhd CrcGen.vhd SlscCpldTop.vhd

Table 2. Main Files Included in the Module Development Kit (Without Dependencies)

File Name Notes

Slsc12101Top.vhd Top-level file which can be compiled to generate a programming

bitfile for the CPLD

SlscCpldTop.qpf Quartus II project file

SlscCpldTop.qsf Quartus II settings file

SlscCpldTop.sdc Constraints file

SlscCpldTop.pof Programming bitfile

EdBlock Implementation

The EdBlock abstracts out the frames received through the SPI lines of the SLSC interface into a register port. You can use it to easily implement registers in your design by calling the RegisterRead and RegisterWrite functions declared in the PkgEdBlock.vhd file. You will only need to focus on implementing a digital circuit that converts these register accesses into useful control and monitor signals in your design.

The Error Detection block is implemented in VHDL and consists of the following files:

File Name Notes

EdBlock.vhd Top-level file of the component which can be instantiated

in a CPLD top-level design. It handles incoming SLSC frames, handles errors when detected, and executes the corresponding register access when valid frames are received.

Spi.vhd, Control.vhd, CrcGen.vhd, ShiftRegister.vhd

Sub-components of the EdBlock.

PkgEdBlock.vhd Contains the RegisterRead and RegisterWrite functions

and records to easily implement registers in a top-level design.

PkgSlscProtocol.vhd Contains constants relevant to the SLSC Specifications

1.0.

Error Detection Block Instantiation

You can instantiate the Error Detection block in your design as follows:

Variable Voltage Power Supplies

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supplies and can provide up to 2 A. In addition to the limitations imposed by the current limits on the different rails on the module, you should also consider the power dissipation limitations as defined in the Switch Load and Signal Conditioning Module Design Specifications.

Table 3. Bank Rail Available Voltages and Current Limits

Bank Available Voltages Maximum Current

1 3.3 V fixed, provided by the SLSC backplane 400 mA

2 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V 2 A

3 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V 2 A

4 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V 2 A

Peripheral Implementations

Along with EdBlock, the Module Development Kit provides a few examples of useful instances that can be used directly with EdBlock to implement common functionality to interact with a wide range of devices that can be placed in the prototyping area or with peripherals already present on the board.

File Name Notes

Interrupt.vhd Customizable entity that implements interrupts which follow

the Switch Load and Signal Conditioning Design Specifications and are compatible with the EdBlock register map.

IoPort.vhd Customizable entity that implements digital I/O compatible

with the EdBlock register map.

Leds.vhd LED controller compatible with the EdBlock register map that

allows the control of bi-color LEDs for the SLSC-12101.

SpiChannelSelect.vhd Customizable entity that allows switching SPI channels for all

the slaves in the SLSC-12101.

Digital Input and Output

The IoPort.vhd file allows the implementation of bi-directional signals on the CPLD. The entity is configurable via generics to set its address base and its port size. Each instantiated block will add three registers of the same size that are defined by the generic kPortSize. Because of this, if the entity is instantiated, you should avoid adding other registers in the range kAddress to kAddress + 2 where kAddress is the address generic of the entity.

The maximum length of kPortSize is 64.

Table 4. Register Descriptions

Output kAddress R/W The value of this register defines the output state

when the corresponding direction bit is set as output (1).

Direction kAddress + 1 R/W For each pin of the port, 1 configures the pin as an

output and 0 configures the pin an input.

Input kAddress + 2 R Mirrors the state of the external pin for read.

Table 5. Signal Descriptions

Signal Name Direction Explanation

Generics

kAddress N/A Defines the base address of the block. This address will also

correspond to the Output register. The next two consecutive addresses are assigned to Direction and Input.

kPortSize N/A Determines the number of I/O implemented. Acceptable values go

from 1 to 64.

Signals

aReset In Board Reset Signal

Clk In Stable clock provided by the CPLD.

caIoPort In/Out Digital input/output.

cRegPortOut Out Signals to the EdBlock Register Port.

cRegPortIn In Signals from the EdBlock Register Port.

I/O Port Instantiation

You can instantiate the I/O Port block in your design as follows:

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SLSC Interrupt

This entity implements an interrupt block that complies with Section 8.1 of the Switch Load and Signal Conditioning Design Specifications. It is configurable through generic constants. It

can handle edge-sensitive and level-sensitive signals. The configuration on the sensitivity is controlled through kSensitivity. The incoming interrupts should be synchronous to Clk.

Table 6. Register Descriptions for the Interrupt Block

Name

Address Type Explanation

Status kRegisterBase R A 1 indicates that an interrupt has occurred. The

interrupt is propagated to IntIn# only if the corresponding bit has been enabled.

Mask kRegisterBase + 1 R A 1 indicates that the corresponding interrupt is

enabled.

Enable kRegisterBase + 2 Strobe Writing a 1 enables the corresponding interrupt

and turns the corresponding bit in the Mask Register into 1. Writing a 0 has no effect.

Disable kRegisterBase + 3 Strobe Writing a 1 disables the corresponding interrupt

and turns the corresponding bit in the Mask Register into a 0. Writing a 0 has no effect.

Ack kRegisterBase + 4 Strobe Writing a 1 to the corresponding bit removes the

interrupt condition. This bit is self-clearing. Writing a 0 has no effect.

Table 7. Signal Descriptions of the Interrupt Component

Signal Name Direction Explanation

Generics

kRegisterBase N/A Defines the base address of the block. This address will

also correspond to the Status register. The next four consecutive addresses are assigned to Mask, InterruptEnable, InterruptDisable, and Ack.

kNumberOfInterrupts N/A Determines the number of interrupts implemented.

Acceptable values range from 1 to 64.

kSensitivity N/A Determines the sensitivity of the corresponding line of

cInterruptsIn. A 0 defines a level sensitive interrupts, while a 1 defines an edge sensitive.

Signals

aReset In Board reset signal.

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