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PXIe-1086DC
User Manual
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National Instruments PXIe-1086DC User Manual

USER MANUAL
PXIe-1086DC
PXIe, 18-Slot (16 Hybrid Slots, 1 PXI Express Slot), Up to 12 GB/s PXI Chassis
The manual includes instructions for installing and configuring your PXIe-1086DC chassis and PXI Express system.

Contents

Getting Started.......................................................................................................................... 2
Installation and Configuration................................................................................................ 12
Maintenance............................................................................................................................ 28
Specifications.......................................................................................................................... 35
Pinouts.....................................................................................................................................46
Where to Go for Support.........................................................................................................51

Getting Started

Unpacking

Carefully inspect the shipping container and the chassis for damage. Check for visible damage to the metal work. Check to make sure all handles, hardware, and switches are undamaged. Inspect the inner chassis for any possible damage, debris, or detached components. If damage appears to have been caused during shipment, file a claim with the carrier. Retain the packing material for possible inspection and/or reshipment.

What You Need to Get Started

The PXIe-1086DC chassis kit contains the following items:
• PXIe-1086DC chassis
• Filler panels
• Power cable
• PXIe-1086DC Safety, Environmental, and Regulatory Information
• Software media with PXI Platform Services 14.0 or newer
• Chassis number labels
• Inhibit fault cable connector
• Ferrite bead for use with redundant power supplies

Key Features

The PXIe-1086DC chassis combines a high-performance 18-slot PXI Express backplane with a high-output power supply and a structural design that has been optimized for maximum
2 | ni.com | PXIe-1086DC User Manual and Specifications
usability in a wide range of applications. The chassis’ modular design ensures a high level of maintainability, resulting in a very low mean time to repair (MTTR). The chassis also features redundant power supplies and fans designed to maximize system availability. The PXIe-1086DC chassis fully complies with the PXI-5 PXI Express Hardware Specification, offering advanced timing and synchronization features.
The key features of the PXIe-1086DC chassis include the following:

High Performance for Instrumentation Requirements

• Up to 4 GB/s (single direction) per PXI Express slot dedicated bandwidth (Gen-2 x8 PCI Express).
• 38.25 W per slot cooling meets increased PXI Express cooling requirements
• Low-jitter internal 10 MHz reference clock for PXI slots with ± 25 ppm stability
• Low-jitter internal 100 MHz reference clock for PXI Express slots with ± 25 ppm stability
• Variable speed fan controller optimizes cooling and acoustic emissions
• Remote power-inhibit control
• Complies with PXI and CompactPCI Specifications

High Reliability

• 0 to 50 °C operating temperature range
• Power supply, temperature, and fan monitoring
• Ethernet interface for remote monitoring

High Availability

• Dual redundant, hot-swappable power supplies
• Redundant, hot-swappable chassis fans

Multi-Chassis Support

• PXI Express System Timing Slot for tight synchronization across chassis
• Front CLK10 I/O connectors
• Switchless CLK10 routing

Optional Features

• Front and rear rack-mount kits
• Replacement power supply
• EMC filler panels
• Slot blockers for improved cooling performance
• Factory installation services
• Replacement fan modules

Chassis Description

The following figures show key features of the PXIe-1086DC chassis front and back panels.
PXIe-1086DC User Manual and Specifications | © National Instruments | 3
Figure 1. Front View of the PXIe-1086DC
PXIe-1086DC
5
8
4
7
6
3
2
1
9
9
9
10
9
16
17
15
14
814813
11 11
12
810
1. Power Inhibit Switch
2. Status LEDs
3. Inhibit/Fault Connector
4. Ground Terminal
5. Backplane Connectors
6. Clk10 Output
7. Clk10 Input
8. PXI Filler Panels (Optional)
10. Fan Door Latch
11. PXI Express Hybrid Peripheral Slots (16x)
12. PXI Express PXI Express System Timing Slot
13. PXI Express System Controller Slot
14. Chassis Power Connector
15. Ethernet Port
16. Chassis Carry Handle
17. System Controller Expansion Slots
9. Removable Feet
4 | ni.com | PXIe-1086DC User Manual and Specifications
Figure 2. Rear View of the PXIe-1086DC
2
2
1
1
3
1
1
5
4
1. Power Supply Cooling Fan
2. Power Supply Handle
3. Earth Ground Terminal (PE)
4. Inhibit Mode Selector Switch
5. Fan Speed Selector Switch

Optional Equipment

Contact National Instruments to order the following options for the PXIe-1086DC chassis.

EMC Filler Panels

EMC filler panel kits are available from National Instruments.

Power Supply Filler Panels

Optional power supply filler panels are available from National Instruments. Use a power supply filler panel if you operate the PXIe-1086DC chassis with a single power supply.

Rack Mount Kits

There are two optional kits for mounting the PXIe-1086DC chassis into a rack. The first option is a pair of mounting brackets for use on the front of the chassis. The second option is a rear rack mount kit. The rear rack mount kit differs from the front kit to allow for easier installation into the rack. Refer to NI Chassis Rack Mount Kit Components for more information.

Slot Blockers

PXI Slot Blocker kits are available from National Instruments. Slot Blockers improve cooling in a chassis by re-routing airflow from empty slots to slots containing PXI modules.

Replacement Power Supply

Replacement power supply kits are available from National Instruments.
PXIe-1086DC User Manual and Specifications | © National Instruments | 5

Replacement Fan Modules

Replacement fan modules are available from National Instruments.

PXIe-1086DC Chassis Backplane Overview

Interoperability with CompactPCI

The design of the PXIe-1086DC provides you the flexibility to use the following devices in a single PXI Express chassis:
• PXI Express compatible products
• CompactPCI Express compatible 2-Link system controller products
• CompactPCI Express compatible Type-2 peripheral products
• PXI peripheral products modified to fit in a hybrid slot
• Standard CompactPCI peripheral products modified to fit in a hybrid slot

System Controller Slot

The system controller slot is Slot 1 of the chassis and is a 2-Link configuration system slot as defined by the CompactPCI Express and PXI Express specifications. It has three expansion slots for system controller modules that are wider than one slot. These slots allow the system controller to expand to the left to prevent it from using peripheral slots.
The backplane connects the system slot to two PCI Express switches using a Gen-2 x8 and a Gen-2 x16 PCI Express link. These switches distribute PCI Express connections to the peripheral slots and to two PCI Express-to-PCI bridges to provide PCI buses to the hybrid peripheral slots. Refer to PXIe-1086DC PCI Express Backplane Diagram.
System slot link 1 is a Gen-2 x8 PCI Express link to PCI Express switch 1, providing a nominal bandwidth of 4 GB/s (single direction) between the system controller and PCI Express switch 1. PXI Express peripheral slots 2-10 are connected to PCI Express switch 1 with Gen-2 x8 PCI Express links and are downstream of system slot link 1. PCI Express-to­PCI bridge 1 is connected to PCI Express switch 1 and provides a 32-bit, 33 MHz PCI bus for hybrid peripheral slots 2-9. PCI Express switch 1 also is connected to PCI Express switch 2 with a Gen-2 x8 PCI Express link for advanced backplane configurations.
System slot link 2 is a Gen-2 x16 PCI Express link to PCI Express switch 2, providing a nominal bandwidth of 8 GB/s (single direction) between the system controller slot and PCI Express switch 2. PXI Express peripheral slots 11-18 are connected to PCI Express switch 2 with Gen-2 x8 PCI Express links and are downstream of system slot link 2. PCI Express-to­PCI bridge 2 is connected to PCI Express switch 2 and provides a 32-bit, 33 MHz PCI bus for hybrid peripheral slots 11-18. PCI Express switch 2 also is connected to PCI Express switch 1 with a Gen-2 x8 PCI Express link for advanced backplane configurations.
The system controller slot also has connectivity to some PXI features such as: PXI_CLK10, PXI Star, PXI Trigger Bus and PXI Local Bus 6.
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By default, the system controller will control the power supply with the PS_ON# signal. A
x8
x1
x8
x1
x16
3H2
H
4
H5H6H7H8H9H
11H12H13H14H15H16H17H18
H
PCIe Switch #1
Port 16 Port 17 Port 8 Port 9
PCIe Switch #2
10
1
PCI Bus (32-bit, 33 MHz) to slots 2-9 PCI Bus (32-bit, 33 MHz) to slots 11-18
PCIe-to-
PCI
Bridge #1
Port 0 Port 4 Port 5
Port 17 Port 8 Port 9
Port 12Port 13 Port 20Port 21
Port 16
Port 20
Port 5Port 4Port 1Port 0
Port 21Port 13 Port 12
x8
x8
x8
x8
x8
x8
x8
x8
x8
x8
x8
x8
x8
x8
x8
x8
x8
PCIe-to-
PCI
Bridge #2
logic low on this line will turn the power supply on.
Note The Inhibit Mode switch on the rear of the chassis must be in the Default
position for the system controller to have control of the power supply. Refer to the Inhibit Mode Switch section for details about the Inhibit Mode switch.

Hybrid Peripheral Slots

The chassis provides 16 hybrid peripheral slots as defined by the PXI-5 PXI Express Hardware Specification: slots 2 to 9 and slots 11 to 18. A hybrid peripheral slot can accept the following
peripheral modules:
• A PXI Express peripheral with x8, x4, or x1 PCI Express link through a switch to the system slot. Each PXI Express peripheral slot can link up to a Gen-2 x8 PCI Express, providing a maximum nominal single-direction bandwidth of 4 GB/s.
• A CompactPCI Express Type-2 Peripheral with x8, x4, or x1 PCI Express link through a PCI Express switch to the system slot.
• A hybrid-compatible PXI Peripheral module modified by replacing the J2 connector with an XJ4 connector installed in the upper eight rows of J2. Refer to the PXI Express Specification for details. The PXI peripheral communicates through the backplane’s 32­bit PCI bus.
• A CompactPCI 32-bit peripheral on the backplane’s 32-bit PCI bus.
The hybrid peripheral slots provide full PXI Express functionality and 32-bit PXI functionality except for PXI Local Bus. The hybrid peripheral slot only connects to PXI Local Bus 6 left and right.
Figure 3. PXIe-1086DC PCI Express Backplane Diagram
PXIe-1086DC User Manual and Specifications | © National Instruments | 7

System Timing Slot

1 2H3H4H5H6H7H8H9H10 11H12H13H14H15H16H17H18
H
DSTAR 6
DSTAR 5
DSTAR 7
DSTAR 4
DSTAR 3
DSTAR 2
DSTAR 1
DSTAR 15
DSTAR 14
DSTAR 13
DSTAR 16
DSTAR 12
DSTAR 11
DSTAR 10
STAR 7
STAR 8
STAR 6
STAR 5
STAR 4
STAR 3
STAR 2
STAR 1 STAR 10
STAR 11
STAR 12
STAR 13
STAR 14
STAR 15
STAR 16
DSTAR 8
DSTAR 9
DSTAR 0
STAR 9
STAR 0
The system timing slot is slot 10. The system timing slot accepts the following peripheral modules:
• A PXI Express System Timing Module with x8, x4, or x1 PCI Express link to the system slot through a PCI Express switch. Each PXI Express peripheral slot can link up to a Gen-2 x8 PCI Express, providing a maximum nominal single-direction bandwidth of 4 GB/s.
• A PXI Express Peripheral with x8, x4, or x1 PCI Express link to the system slot through a PCI Express switch.
• A CompactPCI Express Type-2 Peripheral with x8, x4, or x1 PCI Express link to the system slot through a PCI Express switch.
The system timing slot has three (3) dedicated differential pairs (PXIe_DSTAR) connected from the TP1 and TP2 connectors to the XP3 connector for each PXI Express hybrid peripheral slot, as well as routed back to the XP3 connector of the system timing slot, as shown in the following figure. You can use the PXIe_DSTAR pairs for high-speed triggering, synchronization, and clocking. Refer to the PXI Express Specification for details.
The system timing slot also has a single-ended (PXI Star) trigger connected to every slot. Refer to the following figure for more details.
The system timing slot has a pin (PXI_CLK10_IN) through which a system timing module may source a 10 MHz clock to which the backplane phase-locks. Refer to the System Reference Clock section for details.
The system timing slot has a pin (PXIe_SYNC_CTRL) through which a system timing module can control the PXIe_SYNC100 timing. Refer to the PXI Express Specification and the PXIe SYNC CTRL section of this chapter for details.
Figure 4. PXIe_DSTAR and PXI Star Connectivity Diagram
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PXI Local Bus

7H8H9
H
10
11H12
H
PXI Trigger Bus #2
PXI
Trigger
Bridge #2
PXI
Trigger
Bridge #1
1
2H3H4H5H6
H
PXI Trigger Bus #1
13H14H15H16H17H18
H
PXI Trigger Bus #3
The PXI backplane local bus is a daisy-chained bus that connects each peripheral slot with adjacent peripheral slots to the left and right.
The backplane routes PXI Local Bus 6 between all slots. The left local bus 6 from slot 1 is not routed anywhere, and the right local bus 6 from slot 18 is not routed anywhere.
Local bus signals may range from high-speed TTL signals to analog signals as high as 42 V.
Initialization software uses the configuration information specific to each adjacent peripheral module to evaluate local bus compatibility.

PXI Trigger Bus

All slots on the same PXI bus segment share eight PXI trigger lines. You can use these trigger lines in a variety of ways. For example, you can use triggers to synchronize the operation of several different PXI peripheral modules. In other applications, one module located in the system timing slot can control carefully timed sequences of operations performed on other modules in the system. Modules can pass triggers to one another on the lines, allowing precisely timed responses to asynchronous external events the system is monitoring or controlling.
The PXI trigger lines from adjacent PXI trigger bus segments can be routed in either direction across the PXI trigger bridges through buffers. This allows you to send trigger signals to, and receive trigger signals from, every slot in the chassis. Static trigger routing (user-specified line and directional assignments) can be configured through Measurement & Automation Explorer (MAX). Dynamic routing of triggers (automatic line assignments) is supported through certain National Instruments drivers like NI-DAQmx.

System Reference Clock

The PXIe-1086DC chassis supplies PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 to every peripheral slot with an independent driver for each signal.
An independent buffer (having a source impedance matched to the backplane and a skew of less than 1 ns between slots) drives PXI_CLK10 to each peripheral slot. You can use this common reference clock signal to synchronize multiple modules in a measurement or control system.
Note Although any trigger line may be routed in either direction, it cannot be
routed in more than one direction at a time.
Figure 5. PXI Trigger Bus Connectivity Diagram
PXIe-1086DC User Manual and Specifications | © National Instruments | 9
An independent buffer drives PXIe_CLK100 to each peripheral slot. These clocks are matched
PXIe_CLK100
PXI_CLK10
PXIe_SYNC100
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
in skew to less than 100 ps. The differential pair must be terminated on the peripheral with LVPECL termination for the buffer to drive PXIe_CLK100 so that when there is no peripheral or a peripheral that does not connect to PXIe_CLK100, there is no clock being driven on the pair to that slot.
An independent buffer drives PXIe_SYNC100 to each peripheral slot. The differential pair must be terminated on the peripheral with LVPECL termination for the buffer to drive PXIe_SYNC100 so that when there is no peripheral or a peripheral that does not connect to PXIe_SYNC100, there is no SYNC100 signal being driven on the pair to that slot.
PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 have the default timing relationship described in the following figure.
Figure 6. System Reference Clock Default Behavior
To synchronize the system to an external clock, you can drive PXI_CLK10 from an external source through the PXI_CLK10_IN pin on the System Timing Slot. Refer to the System Timing Slot XP4 Connector Pinout section for the pinout. When a 10MHz clock is detected on this pin, the backplane automatically phase-locks the PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 signals to this external clock and distributes these signals to the slots. Refer to the Specifications for the specification information for an external clock provided on the PXI_CLK10_IN pin of the system timing slot.
You also can drive a 10 MHz clock on the 10 MHz REF IN connector on the front of the chassis. When a 10 MHz clock is detected on this connector, the backplane automatically phase-locks the PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 signals to this external clock and distributes these signals to the slots. Refer to the Specifications section for the specification information for an external clock provided on the 10 MHz REF IN connector on the front panel of the chassis.
If the 10 MHz clock is present on both the PXI_CLK10_IN pin of the System Timing Slot and the 10 MHz REF IN connector on the front of the chassis, the signal on the System Timing Slot is selected. Refer to the following table which explains how the 10 MHz clocks are selected by the backplane.
10 | ni.com | PXIe-1086DC User Manual and Specifications
Table 1. Backplane External Clock Input Configuration
System Timing Slot
PXI_CLK10_IN
Front Chassis
Panel 10 MHz REF
IN
Backplane PXI_CLK10, PXIe_CLK100
and PXIe_SYNC100
No clock present No clock present Backplane generates its own clocks
No clock present 10 MHz clock
present
PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 all phase-locked to front Chassis Panel—10 MHz REF IN
10 MHz clock present No clock present PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to System Timing Slot— PXI_CLK10_IN
10 MHz clock present 10 MHz clock
present
PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 all phase-locked to System Timing Slot— PXI_CLK10__IN
A copy of the backplane’s PXI_CLK10 is exported to the 10 MHz REF OUT connector on the front of the chassis. This clock is driven by an independent buffer.

PXIe_SYNC_CTRL

PXIe_SYNC100 is by default a 10 ns pulse synchronous to PXI_CLK10. The frequency of PXIe_SYNC100 is 10/n MHz, where n is a positive integer. The default for n is 1, giving PXIe_SYNC100 a 100 ns period. However, the backplane allows n to be programmed to other integers. For example, setting n = 3 gives a PXIe_SYNC100 with a 300 ns period while still maintaining its phase relationship to PXI_CLK10. The value for n can be any positive integer from 1 to 255.
The system timing slot has a control pin for PXIe_SYNC100 called PXIe_SYNC_CTRL for use when n > 1. Refer to System Timing Slot XP3 Connector Pinout for the pinout. Refer to the
Specifications for the PXIe_SYNC_CTRL input specifications.
By default, a high-level detected by the backplane on the PXIe_SYNC_CTRL pin causes a synchronous restart for the PXIe_SYNC100 signal. On the next PXI_CLK10 edge the PXIe_SYNC100 signal restarts. This allows several chassis to have their PXIe_SYNC100 in phase with each other. Refer to the following figure for timing details with this method.
PXIe-1086DC User Manual and Specifications | © National Instruments | 11
Figure 7. PXIe_SYNC100 at 3.33 MHz Using PXIe_SYNC_CTRL as Restart
PXI_CLK10
PXIe_SYNC_CTRL
PXIe_SYNC100
SYNC100 Divider
Restarted Here

Installation and Configuration

Safety Information

Caution Before undertaking any troubleshooting, maintenance, or exploratory
procedure, carefully read the following caution notices.
Caution Protection may be impaired if equipment is not used in the manner
specified.
This equipment contains voltage hazardous to human life and safety, and is capable of inflicting personal injury.
• Chassis Grounding—The chassis requires a connection from the premise wire safety ground to the chassis ground. The earth safety ground must be connected during use of this equipment to minimize shock hazards. Refer to the Connecting Safety Ground section for instructions on connecting safety ground.
• Live Circuits—Operating personnel and service personnel must not remove protective covers when operating or servicing the chassis. Adjustments and service to internal components must be undertaken by qualified service technicians. During service of this product, the mains connector to the premise wiring must be disconnected. Dangerous voltages may be present under certain conditions; use extreme caution.
• Explosive Atmosphere—Do not operate the chassis in conditions where flammable gases are present. Under such conditions, this equipment is unsafe and may ignite the gases or gas fumes.
• Part Replacement—Only service this equipment with parts that are exact replacements, both electrically and mechanically. Contact National Instruments for replacement part information. Installation of parts with those that are not direct replacements may cause harm to personnel operating the chassis. Furthermore, damage or fire may occur if replacement parts are unsuitable.
12 | ni.com | PXIe-1086DC User Manual and Specifications
• Modification—Do not modify any part of the chassis from its original condition. Unsuitable modifications may result in safety hazards.
• Location—The chassis is for use in stationary (non-moveable), restricted access locations such as a desk or bench, or for installation in a rack only. Installation and maintenance are to be performed by skilled/trained service persons.

Chassis Cooling Considerations

The PXIe-1086DC chassis is designed to operate on a bench or in an instrument rack. The chassis must be oriented horizontally with the primary exhaust vent at top. Vertical orientation with the chassis handle up is not a supported configuration. Regardless of the configuration, you must provide the cooling clearances as outlined in the following sections.

Providing Adequate Clearance

The primary cooling exhaust vent for the PXIe-1086DC is on the top of the chassis. The primary intake vent is on the bottom of the chassis. The secondary intake vents are located along on the rear of the chassis. Adequate clearance between the chassis and surrounding equipment or blockages must be maintained to ensure proper cooling of the chassis power supply as well as the modules plugged into the chassis. These clearances are outlined in the following figures. Failure to provide these clearances may result in thermal-related failures in the chassis or modules.
PXIe-1086DC User Manual and Specifications | © National Instruments | 13
1.75
(44.5)
3.00
(76.2)
Dimensions are in inches (millimeters)
1.75
(44.5)
PXIe-1086DC
H
Figure 8. PXIe-1086DC Cooling Clearances
The vent locations are shown in the following figure.
14 | ni.com | PXIe-1086DC User Manual and Specifications
Figure 9. PXIe-1086DC Vents
PXIe-1086DC
4
2
1
3
1. Ambient Temperature Sensor
2. PXI Module Air Intake (3x)
3. PXI Module Air Exhaust Vent
4. Airflow

Chassis Ambient Temperature Definition

The chassis fan control system uses ambient intake air temperatures for controlling fan speeds when in Auto Fan Speed mode. Because of this, the chassis ambient temperature is defined as the temperature of the air just outside of the fan intake vents on the bottom of the chassis. Note that this temperature may be higher than ambient room temperature depending on the surrounding equipment and/or blockages present. Ensure ambient intake temperatures do not exceed the ratings in the Operating Environment section of the PXIe-1086DC Specifications. If the temperature exceeds the stated spec, the front-panel temperature LED blinks red.

Setting Fan Speed

The fan-speed selector switch is on the chassis rear panel. Refer to Rear View of the
PXIe-1086DC to locate the fan-speed selector switch. Select High for maximum cooling
performance or Auto for improved acoustic performance. When set to Auto, the chassis intake air temperature determines the fan speed.
PXIe-1086DC User Manual and Specifications | © National Instruments | 15

Installing Filler Panels

Dimensions are in inches (millimeters)
0.35 (8.9)
To maintain proper module cooling performance, install filler panels (provided with the chassis) in unused or empty slots. Secure with the captive mounting screws provided.

Installing Slot Blockers

The cooling performance of the chassis can be improved by installing optional slot blockers. Refer to the National Instruments website at ni.com/info and enter the Info Code
slotblocker for more information about slot blockers.

Fan Access Door Clearance

When installing the PXIe-1086DC chassis, you also must provide the proper clearance for the fan access door to open fully, as shown in the following figure.
Figure 10. Fan Access Door Clearance

Rack Mounting

Rack mount applications require optional rack mount kits available from National Instruments. Refer to the instructions supplied with the rack mount kits to install your PXIe-1086DC chassis in an instrument rack. Refer to NI Chassis Rack Mount Kit Components for more information.
Note You may want to remove the feet from the PXIe-1086DC chassis when rack
mounting. To do so, remove the screw holding the feet and handle in place.

Connecting to Safety Ground and Power Source

The PXIe-1086DC chassis has a single power connector that supplies input power to both chassis power supplies. The power connector is on the front panel.
16 | ni.com | PXIe-1086DC User Manual and Specifications
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