National Instruments PCI-6023E, PCI-MIO-16XE-50, PCI-MIO-16E-4, PCI-MIO-16E-1, PCI-6024E Programmer's Manual
...
DAQ
PCI E Series Register-Level Programmer Manual
Multifunction I/O Boards for PCI Bus Computers
PCI E Series RLPM
November 1998 Edition
Part Number 341079B-01
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© Copyright 1998 National Instruments Corporation. All rights reserved.
Important Information
Warranty
The PCI E Series boards are warranted against defects in materials and workmanship for a period of one year from the
date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or
replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
The media on which you receive National Instruments software are warranted not to fail to execute programming
instructions, due to defects in materials and work man ship, for a peri od of 90 d ays from da te o f sh ipm ent, as evi denced
by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do not
execute programming instructions if National Instruments receives noti ce of su ch defect s d uring th e warranty perio d.
National Instruments does not warrant that the op eration of t he soft ware shall b e uni nterrup ted or erro r free.
A Return Material Authorization (RMA) number must b e ob tain ed fro m th e facto ry an d clearl y mark ed on t he outsi de
of the package before any equipment wil l be accepted for warranty work. National Instruments will pay the shippi ng costs
of returning to the owner parts which are covered by warran ty.
National Instruments believes that the information in this manual is accurate. The document has been c arefully reviewed
for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to
make changes to subsequent editions of th is do cume nt with ou t p rio r no ti ce to hold ers o f thi s ed itio n. The read er sh ou ld
consult National Instruments if errors are suspected. In no event shall National Instruments be liable for any damages
arising out of or related to this docume nt o r th e in form ati on con tai ned in i t.
XCEPT AS SPECIFIED HEREIN
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ATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS
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ATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR IMPLIED, AND SPECIFICALLY DISCLAIMS
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Trademarks
CVI™, DAQ-PnP™, DAQ-STC™, LabVIEW™, MITE™, NI-DAQ™, NI-PGIA™, RTSI™, and SCXI™ are trademarks of
National Instruments Corporation.
Product and company names listed are trademarks or trade names of their respective companies.
WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS
National Instruments products are not designed with com ponent s and tes ting inten ded to ensure a l evel of reliab ilit y
suitable for use in treatment and diagnosis of humans. Applications of National Instruments products invol ving m edical
or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the part of the
user or application designer. Any use or application of National Instruments products for or involving medical or clinical
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Contents
About This Manual
Organization of This Manual.........................................................................................xii
Conventions Used in This Manual.................................................................................xii
Related Documentation........................................... .......................................................xiii
Customer Communication.............................................................................................xiii
Chapter 1
General Description
General Characteristics.................................................................................................. 1-1
Chapter 2
Theory of Operation
Functional Overview......................................................................................................2-1
PCI Interface Circuitry....................................................................................2-6
Analog Input and Timing Circuitry .................................................................2-7
Analog Triggering...........................................................................................2-19
Analog Output and Timing Circuitry..............................................................2-20
Digital I/O Circuitry........................................................................................2-24
Timing I/O Circuitry........................................................................................2-24
RTSI Bus Interface Circuitry...........................................................................2-25
Analog Input Circuitry......................................................................2-8
Data Acquisition Timing Circuitry...................................................2-11
Single-Read Timing............................................................2-11
Data Acquisition Sequence Timing....................................2-12
Posttrigger and Pretrigger Acquisition. .............................................2-18
Analog Output Circuitry ...................................................................2-21
Analog Output Timing Circuitry.......................................................2-22
Single-Point Output............................................................2-22
Waveform Generation ........................................................2-23
Chapter 3
Register Map and Descriptions
Register Map..................................................................................................................3-1
Register Sizes ..................................................................................................3-3
Register Descriptions.....................................................................................................3-3
Misc Register Group........................................................................................3-3
Serial Command Register .................................................................3-4
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National Instruments Corporation v PCI E Series RLPM
Contents
Chapter 4
Programming
PCl Local Bus....................................................... ..................................... ....................4-1
Windowing Registers ....................................................................................................4-5
Programming Examples ................................................................................................4-5
Digital I/O............................................... .......................................................................4-7
Analog Input..................................................................................................................4-8
Misc Command Register ..................................................................3-5
Status Register..................................................................................3-6
Analog Input Register Group..........................................................................3-7
ADC FIFO Data Register.................................................................3-8
Configuration Memory Low Register ..............................................3-9
Configuration Memory High Register..............................................3-11
Analog Output Register Group.......................................................................3-15
AO Configuration Register...............................................................3-16
DAC FIFO Data Register.................................................................3-18
DAC0 Direct Data Register..............................................................3-19
DAC1 Direct Data Register..............................................................3-20
DMA Control Register Group.........................................................................3-21
AI AO Select Register....................................... ...............................3-22
G0 G1 Select Register ......................................................................3-23
DAQ-STC Register Group ..............................................................................3-24
FIFO Strobe Register Group...........................................................................3-24
Configuration Memory Clear Register.............................................3-24
ADC FIFO Clear Register................................................................3-24
DAC FIFO Clear Register................................................................3-24
PCI Initialization for the IBM Compatible System ........................................4-2
Re-mapping the PCI E Series Board...............................................................4-3
PCI Initialization for the Macintosh................................................................4-4
Example 1 .......................................................................................................4-7
Example 2 .......................................................................................................4-7
Example 1 .......................................................................................................4-9
Example 2 .......................................................................................................4-12
Example 3 .......................................................................................................4-14
Example Program .............................................................................4-15
Example 4 .......................................................................................................4-17
Programming the MITE for Different DMA Transfers....................4-20
Example 5 .......................................................................................................4-21
Example 6 .......................................................................................................4-23
Example 7 .......................................................................................................4-25
Example 8 .......................................................................................................4-27
PCI E Series RLPM vi
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National Instruments Corporation
Analog Output................................................................................................................4-31
General-Purpose Counter/Timer....................................................................................4-45
RTSI Trigger Lines Programming Considerations........................................................ 4-52
Analog Triggering..........................................................................................................4-52
Interrupt Programming ..................................................................................................4-56
Interrupt Sharing............................................................................................................4-56
DMA Programming.......................................................................................................4-57
Chapter 5
Calibration
About the EEPROM ...................................................................................................... 5-1
NI-DAQ Calibration Function.......................................................................................5-17
Contents
Example 9........................................................................................................4-29
Example 1........................................................................................................4-32
Example 2........................................................................................................4-34
Example 3........................................................................................................4-39
Example 4........................................................................................................4-41
Example 5........................................................................................................4-43
Example Program..............................................................................4-43
Example 1........................................................................................................4-45
Example 2........................................................................................................4-47
Example 3........................................................................................................4-49
The Link Chaining Mode for DMA Transfer..................................................4-58
Calibration DACs............................................................................................5-14
Appendix A
Customer Communication
Glossary
Index
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National Instruments Corporation vii PCI E Series RLPM
Contents
Figures
Figure 2-1. PCI-MIO-16E-1, PCI-MIO-16E-4, and PCI-6071E Block Diagram ..... 2-1
Figure 2-2. PCI-MIO-16XE-10, PCI-6052E, and PCI-6031E Block Diagram......... 2-2
Figure 2-3. PCI-6023E, PCI-6024E, and PCI-6025E Block Diagram ...................... 2-3
Figure 2-4. PCI-6032E and PCI-6033E Block Diagram ........................................... 2-4
Figure 2-5. PCI-MIO-16XE-50 Block Diagram........................................................2-5
Figure 2-6. PCI Bus Interface Circuitry Block Diagram...........................................2-7
Figure 2-7. Analog Input and Data Acquisition Circuitry Block Diagram ............... 2-8
Figure 2-8. ADC Timing ............................. ..............................................................2-12
Figure 2-9. Timing of Scan in Example 1 .................................................................2-14
Figure 2-10. Multirate Scanning of Two Channels.....................................................2-15
Figure 2-11. Multirate Scanning of Two Channels with 1:x Sampling Rate...............2-15
Figure 2-12. Multirate Scanning of Two Channels with 3:1:1 Sampling Rate ........... 2-16
Figure 2-13. Multirate Scanning of Three Channels with 4:2:1 Sampling Rate .........2-16
Figure 2-14. Multirate Scanning without Ghost..........................................................2-17
Figure 2-15. Occurrences of Conversion on Channel 1 in Example 3........................ 2-17
Figure 2-16. Successive Scans Using Ghost................................................................ 2-17
Figure 2-17. Analog Output Circuitry Block Diagram................................................2-20
Figure 2-18. DAQ-STC Counter Diagram ..................................................................2-24
Figure 2-19. RTSI Bus Interface Circuitry Block Diagram ........................................ 2-26
Tables
Figure 4-1. Analog Trigger Structure........................................................................4-54
Figure 4-2. DMA Structure........................................................................................4-57
Figure 4-3. DMA Link Chaining Mode Structure.....................................................4-59
Figure 5-1. EEPROM Read Timing .......................................................................... 5-2
Figure 5-2. Calibration AC Write Timing.................................................................5-16
Table 2-1. PGIA Gain Set Verses Board ...............................................................2-9
Table 2-2. Analog Input Configuration Memory ..................................................2-18
Table 3-1. PCI E Series Register Map ..................................................................3-2
Table 3-2. PCI E Series Windowed Register Map.................................................3-3
Table 3-3. PGIA Gain Selection.............................................................................3-10
Table 3-4. Calibration Channel Assignments.........................................................3-12
Table 3-5. Differential Channel Assignments........................................................3-13
Table 3-6. Nonreferenced Single-Ended Channel Assignments ...........................3-13
Table 3-7. Referenced Single-Ended Channel Assignments..................................3-14
Table 3-8. Auxiliary Channel Assignments ...........................................................3-15
Table 3-9. Channel Assignments............................................................................3-15
PCI E Series RLPM viii
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National Instruments Corporation
Contents
Table 5-1. PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6071E EEPROM Map ..........5-3
Table 5-2. PCI-MIO-16XE-50 EEPROM Map .....................................................5-5
Table 5-3. PCI-MIO-16XE-10, PCI-6031E, PCI-6032E,
and PCI-6033E EEPROM Map ............................................................5-7
Table 5-4. PCI-6023E EEPROM Map ...................................................................5-9
Table 5-5. PCI-6024E and PCI-6025E EEPROM Map .........................................5-10
Table 5-6. PCI-6052E EEPROM Map ..................................................................5-12
Table 5-7. Type of CALDAC Used on Board .......................................................5-14
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National Instruments Corporation ix PCI E Series RLPM
About This Manual
This manual describes the registers and register map of the PCI E Series
boards and contains information concerning their register-level
programming.
The DAQ-STC, a National Instruments system timing controller ASIC, is
the timing engine that drives the PCI E Series boards. Consequently, the
timing and programming sections in this manual repeat certain information
from, or draw your attention to, sections in the DAQ-STC Technical
Reference Manual. You must use your register-level programmer manual
along with the DAQ-STC Technical Reference Manual for a complete
understanding of PCI E Series board programming.
Unless otherwise noted, text applies to all boards in the PCI E Series. The
PCI E Series boards are:
• PCI-MIO-16E-1
• PCI-MIO-16E-4
• PCI-MIO-16XE-10
• PCI-MIO-16XE-50
• PCI-6023E
• PCI-6024E
• PCI-6025E
• PCI-6031E (MIO-64XE-10)
• PCI-6032E (AI-16XE-10)
• PCI-6033E (AI-64XE-10)
• PCI-6052E
• PCI-6071E (MIO-64E-1)
The PCI E Series boards are high-performance multifunction analog,
digital, and timing I/O boards for the PCI bus computers. Supported
functions include analog input, analog output, digital I/O, and timing I/O.
©
National Instruments Corporation xiii PCI E Series RLPM
About This Manual
Organization of This Manual
The PCI E Series Register-Level Programmer Manual is organized as
follows:
• Chapter 1, General Description, describes the general characteristics
of the PCI E Series boards.
• Chapter 2, Theory of Operation, contains a functional overview of the
PCI E Series boards and explains the operation of each functional unit
making up the PCI E Series boards.
• Chapter 3, Register Map and Descriptions, describes in detail the
address and function of each of the PCI E Series control and status
registers.
• Chapter 4, Programming, contains programming instructions for
operating the circuitry on the PCI E Series boards.
• Chapter 5, Calibration, explains how to calibrate the analog input and
output sections of the PCI E Series boards by reading calibration
constants from the EEPROM and writing them to the calibration
DACs.
• Appendix A, Customer Communication, contains forms you can use to
request help from National Instruments or to comment on our products
and manuals.
• The Glossary contains an alphabetical list and description of terms
used in this manual, including abbreviations, acronyms, metric
prefixes, mnemonics, and symbols.
• The Index contains an alphabetical list of key terms and topics in this
manual, including the page where you can find each one.
Conventions Used in This Manual
The following conventions are used in this manual:
<> Angle brackets containing numbers separated by an ellipsis represent a
range of values associated with a bit or signal name—for example,
DBIO<3..0>.
This icon to the left of bold italicized text denotes a note, which alerts you
to important information.
PCI E Series RLPM xiv
©
National Instruments Corporation
About This Manual
bold Bold text denotes the names of menus, menu items, parameters, dialog
boxes, dialog box buttons or options, icons, windows, Windows 95 tabs,
or LEDs.
bold italic Bold italic text denotes a note, caution, or warning.
italic Italic text denotes variables, emphasis, a cross reference, or an introduction
to a key concept. This font also denotes text from which you supply the
appropriate word or value, as in Windows 3.x.
Macintosh Macintosh refers to all Macintosh computers with the PCI bus, unless
otherwise noted.
monospace Text in this font denotes text or characters that you should literally enter
from the keyboard, sections of code, programming examples, and syntax
examples. This font is also used for the proper names of disk drives, paths,
directories, programs, subprograms, subroutines, device names, functions,
operations, variables, filenames and extensions, and for statements and
comments taken from programs.
PC PC refers to the IBM PC AT and compatible computers with the PCI bus.
Related Documentation
The following National Instruments manuals contain general information
and operating instructions for the PCI E Series boards:
• PCI E Series User Manual
• DAQ-STC Technical Reference Manual
• PCI-6023E/6024E/6025E User Manual
Customer Communication
National Instruments wants to receive your comments on our products
and manuals. We are interested in the applications you develop with our
products, and we want to help if you have problems with them. To make it
easy for you to contact us, this manual contains comment and configuration
forms for you to complete. These forms are in Appendix A, Customer
Communication, at the end of this manual.
©
National Instruments Corporation xv PCI E Series RLPM
General Description
This chapter describes the general characteristics of the PCI E Series
boards.
General Characteristics
The PCI E Series boards are Plug and Play-compatible multifunction
analog, digital, and timing I/O boards for the PCI bus computers. This
family of boards features 12-bit and 16-bit ADCs with 16 and 64 analog
inputs, 12-bit and 16-bit DACs with voltage outputs, eight TTL-compatible
digital I/O, and two 24-bit counter/timers for timing I/O. Because the
PCI E Series boards have no DIP switches, jumpers, or potentiometers,
they are easily configured and calibrated using software. This feature is
made possible by the National Instruments MITE bus interface chip to
connect the boards to the PCI I/O bus. The MITE implements the PCI Local
Bus Specification so that the DMA, interrupts, and base address are all
software configurable.
1
Note
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National Instruments Corporation 1-1 PCI E Series RLPM
Revision C and earlier versions of the PCI-MIO-16XE-50 use the MITE as the
interface chip and do not support the DMA feature.
The PCI E Series boards use the National Instruments DAQ-STC system
timing controller for time-related functions. The DAQ-STC consists of
three timing groups that control analog input, analog output, and
general-purpose counter/timer functions. These groups include a total of
seven 24-bit and three 16-bit counters and a maximum timing resolution
of 50 ns.
A common characteristic with DAQ boards is that you cannot easily
synchronize several measurement functions to a common trigger or timing
event. The PCI E Series boards have the Real-Time System Integration
(RTSI) bus to solve this problem. The RTSI bus consists of our RTSI bus
interface and a ribbon cable to route timing and trigger signals between
several functions on up to five DAQ boards in your PCI bus computer.
The PCI E Series boards can interface to an SCXI system so that you can
acquire over 3,000 analog signals from thermocouples, RTDs, strain
gauges, voltage sources, and current sources. You can also acquire or
Chapter 1 General Description
generate digital signals for communication and control. SCXI is the
instrumentation front end for plug-in DAQ boards.
Y our PCI E Series board is completely software configurable. Refer to your
PCI E Series User Manual if you have not already installed and configured
your board.
PCI E Series RLPM 1-2
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National Instruments Corporation
Theory of Operation
This chapter contains a functional overview of the PCI E Series boards and
explains the operation of each functional unit making up the PCI E Series
boards.
Functional Overview
The block diagram in Figures 2-1 through 2-5 give a functional overview
of each PCI E Series board.
Analog
Trigger
Calibration
DACs
+
Programmable
Gain
Amplifier
–
3
Trigger
Counter/
Timing I/O
Digital I/O
2
Configuration
Memory
Timing/Control
DAQ - STC
Analog Output
Timing/Control
Voltage
REF
(8)*
Analog
Muxes
(8)*
Calibration
Mux
Trigger Level
DACs
I/O Connector
2
Trigger
PFI / Trigger
Timing
Digital I/O (8)
Mux Mode
Selection
Switches
Circuitry
REF
Buffer
12-Bit
Sampling
A/D
Converter
Analog Input
AI Control
DMA/
Interrupt
Request
Bus
Interface
RTSI Bus
Interface
ADC
FIFO
Data (16)
Data (16)
IRQ
DMA
Analog
Input
Control
DAQ-STC
Bus
Interface
Analog
Output
Control
Generic
Bus
Interface
EEPROM
EEPROM
Control
MIO
Interface
MINI
MITE
Interface
Interface
DMA
I/O
Bus
PCI
Bus
Interface
2
Control
Address/Data
Address (5)
PCI Bus
AO Control
DAC0
DAC1
4
Calibration
DACs
DAC
FIFO
Data (16)
RTSI Bus
*(32) for the PCI-6071E
Figure 2-1.
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National Instruments Corporation 2-1 PCI E Series RLPM
PCI-MIO-16E-1, PCI-MIO-16E-4, and PCI-6071E Block Diagram
Chapter 2 Theory of Operation
Voltage
REF
(8)*
Analog
Muxes
(8)*
Trigger Level
DACs
Trigger
PFI / Trigger
Digital I/O (8)
I/O Connector
Timing
Calibration
Mux
2
Mux Mode
Selection
Switches
Analog
Trigger
Circuitry
Calibration
DACs
+
Programmable
Gain
Amplifier
–
3**
Trigger
Counter/
Timing I/O
Digital I/O
2
Configuration
Memory
Analog Input
Timing/Control
DAQ - STC
Analog Output
Timing/Control
AO Control
REF
Buffer
16-Bit
Sampling
A/D
Converter
AI Control
DMA/
Interrupt
Request
Bus
Interface
RTSI Bus
Interface
ADC
FIFO
Data (16)
Data (16)
IRQ
DMA
Analog
Input
Control
DAQ-STC
Bus
Interface
Analog
Output
Control
Generic
Bus
Interface
EEPROM
EEPROM
Control
MIO
Interface
MITE
Interface
Interface
DMA
Bus
I/O
PCI
Bus
Interface
Control
Address/Data
Address (5)
PCI Bus
DAC0
DAC1
4***
* (32) for the PCI-6031E
** (6) for the PCI-6052E
*** (8) for the PCI-6052E
Calibration
DACs
DAC
FIFO
Data (16)
RTSI Bus
Figure 2-2. PCI-MIO-16XE-10, PCI-6052E, and PCI-6031E Block Diagram
PCI E Series RLPM 2-2
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National Instruments Corporation
Chapter 2 Theory of Operation
Voltage
REF
(8)
Analog
Input
Muxes
(8)
Calibration
Mux
PFI / Trigger
Timing
I/O Connector
Digital I/O
DIO (24)
DAC0
DAC1
NOT ON 6023E
Analog Output
Analog Mode
Multiplexer
AO Control
Generator
82C55A
Calibration
Dither
Calibration DACs
6
6025E Only
DACs
PGIA
3
DIO Control
Trigger
Interface
Counter/
Timing I/O
Digital I/O
1
Converter
Configuration
Memory
Analog Input
Timing/Control
DAQ - STC
Analog Output
Timing/Control
A/D
ADC
FIFO
AI Control
DMA/
Interrupt
Request
Bus
Interface
RTSI Bus
Interface
RTSI Connector
IRQ
DMA
EEPROM
Data
Analog
Input
Control
DAQ-STC
Bus
Interface
Generic
Bus
Interface
EEPROM
EEPROM
Control
DAQ-
APE
MINIMITE
Interface
DMA
Interface
I/O
Bus
Interface
Bus
PCI
Control
Address/Data
Address
PCI Connector
Figure 2-3. PCI-6023E, PCI-6024E, and PCI-6025E Block Diagram
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National Instruments Corporation 2-3 PCI E Series RLPM
Chapter 2 Theory of Operation
Voltage
REF
(8)*
Analog
Muxes
(8)*
Calibration
Mux
DACs
2
Trigger
PFI / Trigger
Timing
Digital I/O (8)
Trigger Level
I/O Connector
* (32) for the PCI-6033E
Mux Mode
Selection
Switches
Analog
Trigger
Circuitry
Calibration
DACs
+
NI-PGIA
Gain
Amplifier
–
2
3
Trigger
Counter/
Timing I/O
Digital I/O
Configuration
Memory
Analog Input
Timing/Control
DAQ - STC
Analog Output
Timing/Control
16-Bit
Sampling
A/D
Converter
AI Control
IRQ
DMA/
Interrupt
Request
Bus
Interface
RTSI Bus
Interface
ADC
FIFO
DMA
Data (16)
Analog
Input
Control
DAQ-STC
Bus
Interface
Analog
Output
Control
Generic
Bus
Interface
EEPROM
EEPROM
Control
MIO
Interface
Interface
Bus
Interface
RTSI Bus
Figure 2-4. PCI-6032E and PCI-6033E Block Diagram
MITE
DMA
I/O
PCI
Bus
Interface
Control
Address/Data
Address (5)
PCI Bus
PCI E Series RLPM 2-4
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National Instruments Corporation
Chapter 2 Theory of Operation
Voltage
REF
(8)
Analog
Muxes
(8)
Calibration
Mux
PFI / Trigger
Timing
I/O Connector
Digital I/O (8)
DAC0
DAC1
Mux Mode
Selection
Switches
4
Calibration
DACs
+
Programmable
Gain
Amplifier
–
Calibration
DACs
2
2
16-Bit
Configuration
Memory
Sampling
A/D
Converter
ADC
FIFO
AI Control
IRQ
Data (16)
DMA
Trigger
Counter/
Timing I/O
Digital I/O
Analog Input
Timing/Control
DAQ - STC
Analog Output
Timing/Control
AO Control
Data (16)
DMA/
Interrupt
Request
Bus
Interface
RTSI Bus
Interface
RTSI Bus
Figure 2-5. PCI-MIO-16XE-50 Block Diagram
Analog
Input
Control
DAQ-STC
Bus
Interface
Analog
Output
Control
Generic
Bus
Interface
EEPROM
EEPROM
Control
Interface
MIO
MITE
Interface
DMA
Interface
I/O
Bus
Interface
PCI
Bus
Control
Address/Data
Address (5)
PCI Bus
The following major components make up the PCI E Series boards:
• PCI bus interface circuitry with Plug and Play capability (MITE)
• Analog input circuitry
• Analog trigger circuitry
• Analog output circuitry
• Digital I/O circuitry
• Timing I/O circuitry (DAQ-STC)
• RTSI bus interface circuitry
The internal data and control buses interconnect the components. Notice
that the DA Q-STC is the timing engine that provides precise timing signals
for the analog input and output operations. The timing I/O circuitry
information in this manual is skeletal in nature and is sufficient in most
cases. For register-level programming information, refer to the DAQ-STC
Technical Reference Manual.
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National Instruments Corporation 2-5 PCI E Series RLPM
Chapter 2 Theory of Operation
PCI Interface Circuitry
The PCI E Series interface circuitry consists of a PCI interface chip and
a digital control logic chip. The PCI interface chip provides a mechanism
for the PCI E Series to communicate with the PCI bus. The digital control
logic chip connects the PCI interface chip with the rest of the board. The
PCI E Series is fully com pliant with PCI Local Bus Specification,
Revision 2.0. Therefore, the base memory address and the interrupt level
for the board are stored inside the PCI interface chip at power on. You do
not need to set any switches or jumpers. The PCI bus is capable of 8-bit,
16-bit, or 32-bit transfers, but PCI E Series boards use only 8-bit or
16-bit transfers.
The bus-mastering capabilities of the MITE provides high-speed data
transfer between the board and system memory. The MITE contains three
DMA channels that can be used simultaneously for data transfer with
analog input, analog output, and the general-purpose counters. The MITE
can control the PCI bus and transfer the data without interrupting the
host processor.
The DAQ-STC can generate interrupts from over 20 sources and can route
these interrupts to the INTA line on the PCI bus interface. Using two
interrupt lines, such as INTB, INTC or INTD, is not permitted for the
PCI E Series since each function in the PCI E Series does not have its own
configuration space. PCI E Series boards have the DAQ-STC IRQOUT0
line connected to the MITE interrupt input. Therefore, when setting up
interrupts you must route all interrupts through IRQOUT0. See the
DAQ-STC Technical Reference Manual for more information.
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Data/Address Address
Chapter 2 Theory of Operation
Interface Control
Arbitration
System
PCI Bus
INTA
Figure 2-6. PCI Bus Interface Circuitry Block Diagram
Analog Input and Timing Circuitry
The PCI E Series boards have 16 and 64 analog input channels and a timing
core within the DAQ-STC that is dedicated to analog input operation.
Figure 2-7 shows a general block diagram for the analog input circuitry.
MITE
PCI
Interface
Chip
Data
Control
Interrupt
DAQ-STC
IRQOUT0
Control/Data
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AISense
ACH0
ACH1
ACH2
ACH3
ACH4
ACH5
ACH6
ACH7
ACH8
ACH9
ACH10
…
…
…
…
ACH15*
Input Multiplexer
Calibration
Sources
AIGND
Cal Mux
Mode
Selection
Channel
Type
Calibration
DACs
Dither
PGIA
ADC FIFO
Gain
Polarity
Convert
Channel
Number
*ACH63 for PCI-6071E, PCI-6031E, and PCI-6033E
Figure 2-7. Analog Input and Data Acquisition Circuitry Block Diagram
Analog Input Circuitry
The general model for analog input on the PCI E Series boards
includes input multiplexer, multipl e xer mode selection switches,
a software-programmable gain instrumentation amplifier, calibration
hardware, a sampling ADC, a 16-bit wide data FIFO, and a configuration
memory.
The configuration memory defines the parameters to use for each
conversion. Each entry in the conf iguration memory includes channel type,
channel number, bank, gain, polarity, dither, general trigger, and last
channel. The configuration memory is a 512-entry deep FIFO that is
initialized prior to the start of the acquisition sequence. It can be
incremented after every conversion, allowing the analog input
configuration to vary on a per conversion basis. Once the FIFO is empty,
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Chapter 2 Theory of Operation
the DAQ-STC asserts the FIFO retransmit signal, which restores the FIFO
data to its original state.
The channel type field indicates the resource type to be used during
the conversion and controls the multiplexer mode selection switches.
These resources include calibration channels, analog input channels in
differential, referenced single-ended, or nonreferenced single-ended mode,
or a ghost channel. The ghost channel type indicates that a conversion
should occur but that the data should not be stored in the data FIFO. This
type is useful for multirate scanning, which is described later in
this chapter.
The channel number indicates which channel of the specified type will be
used during the conversion, while the bank field indicates which bank of
16 channels is active. This bank field is used on boards that hav e more than
16 channels. These bits control the input multiplexers.
The programmable gain instrumentation amplifier (PGIA) serves two
purposes on the PCI E Series boards. The PGIA applies gain to the input
signal, amplifying an analog input signal before sampling and conversion
to increase measurement resolution and accuracy. This gain is determined
by the gain field in the configuration memory. It also provides polarity
selection for the input signal, which is also controlled by the configuration
memory . In unipolar mode, the input range includes only positive voltages.
In bipolar mode, the input signal may also be a negative voltage. The
PGIA provides gains shown in Table 2-1.
Table 2-1. PGIA Gain Set Verses Board
Gain
PCI-MIO-16E-1
PCI-MIO-16E-4
PCI-6071E
PCI-6052E
PCI-MIO-16XE-50
PCI-MIO-16XE-50
PCI-6031E
PCI-6032E
PCI-6033E
PCI-6023E
PCI-6024E
PCI-6025E
0.5 ✓ — — ✓
1 ✓ ✓ ✓ ✓
2 ✓ ✓ ✓ —
5 ✓ — ✓ —
10 ✓ ✓ ✓ ✓
20 ✓ — ✓ —
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Chapter 2 Theory of Operation
Table 2-1. PGIA Gain Set Verses Board (Continued)
Gain
PCI-MIO-16E-1
PCI-MIO-16E-4
PCI-6071E
PCI-6052E
PCI-MIO-16XE-50
PCI-MIO-16XE-50
PCI-6031E
PCI-6032E
PCI-6033E
PCI-6023E
PCI-6024E
PCI-6025E
50 ✓ — ✓ —
100 ✓ ✓ ✓ ✓
The dither circuitry adds approximately 0.5 LSB rms of white Gaussian
noise to the signal being converted by the ADC. This addition is useful
for applications, such as calibration, involving averaging to increase the
resolution of the board to more than the resolution of the ADC. In such
applications, which are often lower frequency in nature, adding the dither
decreases noise modulation and improves differential linearity. Dither
should be disabled for high-speed applications not involving averaging
because it would only add noise. When taking DC measurements, such as
when calibrating the board, you should enable dither and average about
1,000 points to take a single reading. This process removes the effects of
quantization, reduces measurement noise, and improves resolution. Notice
that dither cannot be disabled on the PCI-MIO-16XE-50,
PCI-MIO-16XE-10, PCI-6031E, PCI-6032E, PCI-6052E, or PCI-6033E.
The last channel bit is used to indicate that this is the last conversion in a
scan. The DAQ-STC will end the scan on the conversion with this bit set.
The PCI E Series boards use sampling, successive approximation ADCs
with 12 or 16 bits of resolution with maximum conversion rates between
50 µs and 800 ns. The converter can resolve its input range into 4,096
different steps for the 12-bit ADC and 65,536 for the 16-bit ADC. The input
range of the 12-bit boards is ±5 V in bipolar mode and 0 to +10 V in
unipolar mode. These modes correspond to ranges of –2,048 to 2,047 in
unipolar mode and 0 to 4,095 in bipolar mode. The input range of the 16-bit
boards is ±10 V in bipolar mode and 0 to +10 V in unipolar mode. These
modes correspond to ranges of –32,768 to 32,767 in bipolar mode and 0 to
65,535 in unipolar mode.
The PCI E Series boards include a 16-bit wide FIFO to buffer the analog
input data. This buffering will increase the maximum rate that the analog
input can sustain during continuous acquisition. The FIFO is 2,048 words
deep on the PCI-MIO-16XE-50, and 512 words deep on the other
PCI E Series boards. The DAQ-STC shifts the data into the FIFO from the
ADC when the conversion is complete. This buffering allows the ADC to
begin a new con version ev en though the data has not yet been read from the
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Chapter 2 Theory of Operation
board. This buffering also pr o vides more time for the soft war e or DMA to
respond and read the analog input data from the board. If the FIFO is full
and another conversion completes, an error condition called FIFO overflow
occurs and the data from that conversion is lost. The FIFO not empty,
half-full, and full flags are available to generate interrupts or DMA requests
for the data transfer.
Measurement reliability is assured through the onboard calibration
circuitry of the board. This circuitry uses an internal, stable 5 V reference
that is measured at the factory against a higher accuracy reference; its
value is then stored in the EEPROM. With this stored reference value,
the board can be recalibrated at any time under any number of different
environmental conditions in order to remove errors caused by time and
temperature drift. The EEPROM stores calibration constants that can be
read and then written to calibration DACs that adjust input offset, output
offset, and gain errors associated with the analog input section. When the
board leaves the factory, the upper one-fourth of the EEPROM is protected
and cannot be overwritten. The lower three-fourths is unprotected, and the
top fourth of that can be used to store alternate calibration constants for the
different conditions under which you use the board.
Data Acquisition Timing Circuitry
This section describes the different methods of acquiring A/D data from a
single channel or multiple channels.
From this section through the end of this manual, you are assumed to have
a working knowledge of the DAQ-STC features. These features are
explained in the DAQ-STC Technical Reference Manual. If you have not
read the functional description of each DAQ-STC module, you must do so
before completing this register-level programmer manual.
Single-Read Timing
To acquire data from the ADC, initiate a single conversion and read the
resulting value from the ADC FIFO buffer after the conversion is complete.
You can generate a single conversion in three different ways—apply an
active pulse to the CONVERT* pin of the I/O connector, generate a falling
edge on the sample-interval counter of the DAQ-STC, or strobe the
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CONVERT*
ADC_BUSY*
SHIFTIN*
appropriate bit in a register in the PCI E Series register set. Any one of
these operations will generate the timing shown in Figure 2-8.
Figure 2-8. ADC Timing
When SHIFTIN* shifts the ADC value into the ADC FIFO buffer, the
AI_FIFO_Empty_St bit in the status register is cleared, which indicates
that valid data is av ailable to be read. Single conversion timing of this type
is appropriate for reading channel data on an ad hoc basis. However , if you
need a sequence of conversions, the time interval between successive
conversions is not constant because it relies on the softw are to generate the
conversions. For finely timed conversions that require triggering and
gating, you must program the boards to automatically generate timed
signals that initiate and gate conversions. This is known as a data
acquisition (DAQ) sequence.
Data Acquisition Sequence Timing
The following counters are used for a data acquisition sequence:
• Scan interval (SI) 24 bits
• Sample interval (SI2) 16 bits
• Divide by (DIV) 16 bits
• Scan counter (SC) 24 bits
This section presents a concise summary of only the most important
features of your board. For a complete description of all the analog input
modes and features of the PCI E Series boards, refer to the DAQ-STC
Technical Reference Manual.
The most basic timing signal in the analog input model is the CONVERT*
signal. A group of precisely timed CONVERT* pulses is a SCAN. The
sequence of channels selected in each conversion in a SCAN is
programmed in the configuration memory prior to starting the operation.
The SI2 counter is a 16-bit counter in the DAQ-STC. This counter
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Chapter 2 Theory of Operation
determines the interval between CONVERT* pulses. It can be programmed
for a maximum interval of 3.3 ms and a minimum interval of 50 ns. If
alternate slow timebases are used, the maximum interval is 0.65 s. Each
time the counter reaches terminal count (TC), a CONVERT* pulse is
generated. Alternatively, CONVERT* pulses could be given externally.
A SCAN sequence is started by the ST AR T pulse, which is generated by the
TC of the SI counter. This counter is a 24-bit counter that determines the
time between the start of each SCAN. The minimum duration is 50 ns and
the maximum duration is 0.8 s when the internal 20 MHz timebase is used.
If the internal 100 kHz timebase is used, the maximum is 167 s. The ST ART
pulse triggers the SI2 counter to generate CONVERT* pulses. With each
conversion, the conf iguration memory advances by one and selects the next
set of analog input conditions—channel number, gain, polarity, etc. A
STOP pulse ends the SCAN sequence. This STOP could be generated in
two ways—either by using the LASTCHANNEL bit in the configuration
memory or by programming the 16-bit DIV counter to count the number of
conversions per SCAN and using the terminal count of the DIV counter as
a STOP pulse.
The SC is a 24-bit counter that counts the number of scans. The data
acquisition sequence can be programmed to stop when the terminal count
of this counter is reached. Notice that the START and STOP signals could
also be supplied externally.
Example 1: To acquire 50 scans, with each scan consisting of one sample
on channel 0 at gain 50, one sample on channel 5 at gain 2, and one sample
on channel 3 at gain 10, with a SCAN interval of 100 µs and a sample
interval of 10 µs, program your configuration memory as follows:
1. Channel 0, gain 50
2. Channel 5, gain 2
3. Channel 3, gain 10, last channel
You should program SI2 for 10 µs, SI for 100 µs, and SC for 50 scans.
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START
(TC of SI)
Figure 2-9 shows the timing for each scan in Example 1.
100 µs
10 µs
CONVERT
STOP
(last channel
or DIV TC)
Channel 0 Channel 5
Channel 3
Figure 2-9. Timing of Scan in Example 1
The START pulse starts each scan. The first CONVERT pulse samples
channel 0, the second CONVERT pulse samples channel 5, and the third
CONVERT pulse samples channel 3. The STOP pulse ends the scan.
Example 1 allows you to sample all three channels at a rate of 10 kS/s per
channel (100 µs sample interval period). To achieve different rates for
different channels, you must do multirate scanning.
Multirate Scanning without Using Ghost
Example 2: To sample channel 0 at 10 kS/s and channel 1 at 5 kS/s, both at
gain 1 with 50 scans, program the configuration memory as follows:
1. Channel 0, gain 1
2. Channel 1, gain 1, last channel
3. Channel 0, gain 1, last channel
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Chapter 2 Theory of Operation
Program SI for 100 µs, SI2 for 10 µs. Figure 2-10 shows the timing
sequence for two scans.
Sampling Rate
Channel 0: Channel 1 = 2:1
START
CONVERT
Channel 0Channel 0 Channel 1
STOP
Figure 2-10. Multirate Scanning of Two Channels
This sequence of two scans is repeated 25 times to complete the acquisition.
Notice that channel 0 is sampled once every 100 µs. Hence, its sampling
rate is 10 kS/s, whereas channel 1 is sampled once every 200 µs. Its rate is
5 kS/s. Similarly, you could implement an y 1:x ratio of sampling rates. The
1
effective scan interval of the slower channel will be at the rate of the
-- -
x
faster channel. This implementation requires x scan sequences in the
configuration memory.
Also, you can implement a 1:1:x or 1:x:mx ratio for three channels, where
m is a non-negative integer. Figures 2-11, 2-12, and 2-13 show timing
sequences for different ratios. In these figures, the numbers above the
CONVERT pulses indicate the channels sampled in that conversion.
Sampling Rates
Channel 0: Channel 1 = 5:1
START
CONVERT
STOP
0
Figure 2-11. Multirate Scanning of Two Channels with 1:
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National Instruments Corporation 2-15 PCI E Series RLPM
00
0
001
x
Sampling Rate
Chapter 2 Theory of Operation
Sampling Rates
Channel 0: Channel 1: Channel 2 = 3:1:1
START
CONVERT
STOP
Sampling Rates
Channel 0: Channel 1: Channel 2 = 4:2:1
START
CONVERT
0 0 01 2
Figure 2-12. Multirate Scanning of Two Channels with 3:1:1 Sampling Rate
Here, channel 0 is sampled three times, whereas channels 1 and 2 are
sampled once every three scans.
0
000121
STOP
Figure 2-13. Multirate Scanning of Three Channels with 4:2:1 Sampling Rate
Multirate Scanning Using Ghost
If the ghost option in the configuration memory is set, that conversion
occurs but the data is not stored in the analog input FIFO. In other words,
a conversion is performed and the data is thrown away. By using this
option, multirate scanning with ratios such as x:y are possible, within the
limits imposed by the size of the configuration memory.
Figures 2-14 and 2-16 illustrate the advantages of using the ghost feature.
Figure 2-15 shows Example 3 timing, and Figure 2-16 shows the same
example using ghost.
Example 3: channel 1: channel 0 = 2:3 (without ghost).
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Chapter 2 Theory of Operation
Sampling Rates
Channel 0: Channel 1 = 3:2
Start
Convert
0
t
1
t
1
0
0
Figure 2-14. Multirate Scanning without Ghost
In Example 3, channel 0 is sampled correctly. Although channel 1 is
sampled twice, it does not yield a 50% duty cycle. This type of acquisition
will result in imprecise rates. Figure 2-15 shows the relative occurrences of
convert pulses in Figure 2-14.
Channel 1, Example 3
t2t
Convert
t
Figure 2-15. Occurrences of Conversion on Channel 1 in Example 3
To rectify the problem, use ghost as illustrated in Figure 2-16.
Start
Convert
01 01 01 01 01 01
Figure 2-16. Successive Scans Using Ghost
The shaded conversions are ghost conversions. The short arrows indicate
channel 0 samples and the long arrows indicate channel 1 samples that are
actually stored in the FIFOs.
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National Instruments Corporation 2-17 PCI E Series RLPM
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