National Instruments PC-DIO-96/PnP Owners Manual

PC-DIO-96/PnP

User Manual

Digital I/O Board for ISA

September 1996 Edition

Part Number 320289C-01

© Copyright 1990, 1996 National Instruments Corporation. All Rights Reserved.

Internet Support

GPIB:

[e-mail]

DAQ:

[e-mail]

VXI:

[e-mail]

LabVIEW:
LabWindows:
HiQ:
VISA:
Lookout:

[e-mail]

[e-mail]

[e-mail]

[e-mail]

[e-mail]

E-mail:
FTP Site:
Web Address:

[e-mail]

ftp.natinst.com

http://www.natinst.com

Bulletin Board Support

BBS United States: [phone] or [phone]
BBS United Kingdom: 01635 551422
BBS France: 01 48 65 15 59

FaxBack Support

[phone]

Telephone Support (U.S.)

Tel: [phone]
Fax: [phone]

International Offices

Australia 03 9879 5166, Austria 0662 45 79 90 0, Belgium 02 757 00 20,
Canada (Ontario) 905 785 0085, Canada (Québec) 514 694 8521,
Denmark 45 76 26 00, Finland 90 527 2321, France 01 48 14 24 24,
Germany 089 741 31 30, Hong Kong 2645 3186, Israel 03 5734815, Italy 02 413091,
Japan 03 5472 2970, Korea 02 596 7456, Mexico 95 800 010 0793, Netherlands 0348 433466,
Norway 32 84 84 00, Singapore 2265886, Spain 91 640 0085, Sweden 08 730 49 70,
Switzerland 056 200 51 51, Taiwan 02 377 1200, U.K. 01635 523545

National Instruments Corporate Headquarters

6504 Bridge Point Parkway Austin, TX 78730-5039 Tel: [phone]

Important Information

Warranty

Copyright

Trademarks

The PC-DIO-96/PnP is warranted against defects in materials and workmanship for a period of one year from the date
of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace
equipment that proves to be defective during the warranty period. This warranty includes parts and labor.

The media on which you receive National Instruments software are warranted not to fail to execute programming
instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as evidenced
by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do
not execute programming instructions if National Instruments receives notice of such defects during the warranty
period. National Instruments does not warrant that the operation of the software shall be uninterrupted or error free.

A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside
of the package before any equipment will be accepted for warranty work. National Instruments will pay the shipping
costs of returning to the owner parts which are covered by warranty.

National Instruments believes that the information in this manual is accurate. The document has been carefully
reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves
the right to make changes to subsequent editions of this document without prior notice to holders of this edition. The
reader should consult National Instruments if errors are suspected. In no event shall National Instruments be liable for
any damages arising out of or related to this document or the information contained in it.

XCEPT AS SPECIFIED HEREIN

E

SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE

C

USTOMER’S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL

I

NSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER
WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS, OR INCIDENTAL OR
CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY THEREOF

Instruments will apply regardless of the form of action, whether in contract or tort, including negligence. Any action
against National Instruments must be brought within one year after the cause of action accrues. National Instruments
shall not be liable for any delay in performance due to causes beyond its reasonable control. The warranty provided
herein does not cover damages, defects, malfunctions, or service failures caused by owner’s failure to follow the
National Instruments installation, operation, or maintenance instructions; owner’s modification of the product;
owner’s abuse, misuse, or negligent acts; and power failure or surges, fire, flood, accident, actions of third parties, or
other events outside reasonable control.

Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical,
including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part,
without the prior written consent of National Instruments Corporation.

LabVIEW®, NI-DAQ®, and SCXI™ are trademarks of National Instruments Corporation.
Product and company names listed are trademarks or trade names of their respective companies.

, N

ATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR IMPLIED, AND

. N

ATIONAL INSTRUMENTS

. This limitation of the liability of National

.

WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS

National Instruments products are not designed with components and testing intended to ensure a level of reliability
suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving
medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the
part of the user or application designer. Any use or application of National Instruments products for or involving
medical or clinical treatment must be performed by properly trained and qualified medical personnel, and all traditional
medical safeguards, equipment, and procedures that are appropriate in the particular situation to prevent serious injury
or death should always continue to be used when National Instruments products are being used. National Instruments
products are NOT intended to be a substitute for any form of established process, procedure, or equipment used to
monitor or safeguard human health and safety in medical or clinical treatment.

About This Manual

Organization of This Manual ........................................................................................ ix

Conventions Used in This Manual ...............................................................................x

National Instruments Documentation ........................................................................... xii

Related Documentation ................................................................................................xiii

Customer Communication ............................................................................................ xiii

Chapter 1
Introduction

About the PC-DIO-96/PnP ........................................................................................... 1-1

What You Need to Get Started ..................................................................................... 1-2

Software Programming Choices ................................................................................... 1-3

LabVIEW and LabWindows/CVI Application Software .............................. 1-3

NI-DAQ Driver Software ............................................................................... 1-3

Register-Level Programming ......................................................................... 1-5

Optional Equipment ...................................................................................................... 1-5

Custom Cabling .............................................................................................. 1-5

Unpacking ..................................................................................................................... 1-7

Table

of

Contents

Chapter 2
Installation and Configuration

Installation .................................................................................................................... 2-1

Hardware Configuration ............................................................................................... 2-3

Plug and Play .................................................................................................. 2-3

Base I/O Address and Interrupt Selection ....................................... 2-3

Non-Plug and Play .........................................................................................2-3

Chapter 3
Signal Connections

I/O Connector Pin Description .....................................................................................3-1

I/O Connector Signal Connection Descriptions ...........................................................3-3

Port C Pin Assignments ................................................................................. 3-4

Cable Assembly Connectors ......................................................................................... 3-4

© National Instruments Corporation v PC-DIO-96/PnP User Manual

Table of Contents

Digital I/O Signal Connections .....................................................................................3-7

Power Connections ........................................................................................................3-9

Digital I/O Power-up State Selection ............................................................................3-9

High DIO Power-up State ...............................................................................3-9

Low DIO Power-up State ...............................................................................3-11

Timing Specifications ...................................................................................................3-12

Mode 1 Input Timing ......................................................................................3-14

Mode 1 Output Timing ...................................................................................3-15

Mode 2 Bidirectional Timing .........................................................................3-16

Chapter 4
Theory of Operation

Data Transceivers ..........................................................................................................4-2

PC I/O Channel Control Circuitry .................................................................................4-2

Plug and Play Circuitry .................................................................................................4-2

Interrupt Control Circuitry ............................................................................................4-2

82C55A Programmable Peripheral Interface ................................................................4-3

82C53 Programmable Interval Timer ...........................................................................4-3

Digital I/O Connector ....................................................................................................4-4

Appendix A
Specifications

Appendix B
OKI 82C55A Data Sheet

Appendix C
OKI 82C53 Data Sheet

Appendix D
Register-Level Programming

Appendix E
Using Your PC-DIO-96 (Non-PnP) Board

Appendix F
Customer Communication

PC-DIO-96/PnP User Manual vi © National Instruments Corporation

Glossary
Index
Figures

Figure 1-1. The Relationship between the Programming Environment,

Figure 2-1. PC-DIO-96PnP Parts Locator Diagram ................................................ 2-1

Figure 3-1. Digital I/O Connector Pin Assignments ............................................... 3-2

Figure 3-2. Cable Assembly Connector Pin Assignments for Pins 1 through 50

Figure 3-3. Cable Assembly Connector Pin Assignments for Pins 51 through 100

Figure 3-4. Digital I/O Connections ........................................................................ 3-8

Figure 3-5. DIO Channel Configured for High DIO Power-up State

Figure 3-6. DIO Channel Configured for Low DIO Power-up State

Table of Contents

NI-DAQ, and Your Hardware .............................................................. 1-4

of the PC-DIO-96/PnP I/O Connector .................................................. 3-5

of the PC-DIO-96/PnP I/O Connector .................................................. 3-6

with External Load ................................................................................ 3-10

with External Load ................................................................................ 3-11

Figure 4-1. PC-DIO-96PnP Block Diagram ............................................................ 4-1

Figure D-1. Control Word Formats for the 82C55A ................................................ D-5

Figure D-2. Control Word Format for the 82C53 .................................................... D-7

Figure D-3. Port C Pin Assignments, Mode 1 Input ................................................ D-16

Figure D-4. Port C Pin Assignments, Mode 1 Output .............................................. D-19

Figure D-5. Port A Configured as a Bidirectional Data Bus in Mode 2 .................. D-21

Figure D-6. Port C Pin Assignments, Mode 2 .......................................................... D-23

Figure E-1. PC-DIO-96 Block Diagram ..................................................................E-2

Figure E-2. PC-DIO-96 Parts Locator Diagram ...................................................... E-3

Figure E-3. Example Base I/O Address Switch Settings ......................................... E-6

Figure E-4. Interrupt Jumper Setting for IRQ5 (Default Setting) ............................ E-9

© National Instruments Corporation vii PC-DIO-96/PnP User Manual

Table of Contents

Tables

Table 3-1. Port C Signal Assignments ....................................................................3-4

Table 3-2. Timing Signal Descriptions ...................................................................3-13

Table D-1. PC-DIO-96/PnP Address Map ..............................................................D-2

Table D-2. Port C Set/Reset Control Words ............................................................D-6

Table D-3. Mode 0 I/O Configurations ...................................................................D-12

Table E-1. Comparison of Characteristics ..............................................................E-1

Table E-2. PC-DIO-96 Factory-Set Switch and Jumper Settings ...........................E-4

Table E-3. Switch Settings with Corresponding Base I/O Address and

Base I/O Address Space ........................................................................E-7

PC-DIO-96/PnP User Manual viii © National Instruments Corporation

This manual describes the mechanical and electrical aspects of the
PC-DIO-96/PnP and contains information concerning its operation and
programming.

The PC-DIO-96PnP is a member of the National Instruments PC Series
of I/O channel expansion boards for ISA computers. These boards are
designed for high-performance data acquisition and control for
applications in laboratory testing, production testing, and industrial
process monitoring and control.

This manual also applies to the PC-DIO-96, a non-Plug and Play device.
The boards are identical except for the differences listed in Appendix E,

Using Your PC-DIO-96 (Non-PnP) Board

Organization of This Manual

About

This

Manual

.

The

PC-DIO-96/PnP User Manual

• Chapter 1,
you need to get started; describes software programming choices,
optional equipment, and custom cables; and explains how to
unpack the PC-DIO-96/PnP.

• Chapter 2,
and configure the PC-DIO-96PnP board.

• Chapter 3,
signal connection instructions for the PC-DIO-96/PnP I/O
connector.

• Chapter 4,
the PC-DIO-96PnP board and explains the operation of each
functional unit making up the PC-DIO-96PnP.

• Appendix A,
PC-DIO-96/PnP.

• Appendix B,
data sheet for the OKI 82C55A (OKI Semiconductor) CMOS

© National Instruments Corporation ix PC-DIO-96/PnP User Manual

Introduction

Installation and Configuration

Signal Connections

Theory of Operation

Specifications

OKI 82C55A Data Sheet,

is organized as follows:

, describes the PC-DIO-96/PnP; lists what

, describes how to install

, includes timing specifications and

, contains a functional overview of

, lists the specifications of the

contains the manufacturer

About This Manual

programmable peripheral interface. This interface is used on the
PC-DIO-96/PnP board.

• Appendix C,
data sheet for the OKI 82C53 integrated circuit (OKI
Semiconductor). This circuit is used on the PC-DIO-96/PnP board.

• Appendix D,
address and function of each of the PC-DIO-96/PnP control and
status registers. This appendix also includes important information
about register-level programming the PC-DIO-96/PnP along with
program examples written in C and assembly language.

• Appendix E,
the differences between the PC-DIO-96PnP and PC-DIO-96
boards, the PC-DIO-96 board configuration, and the installation of
the PC-DIO-96 into your computer.

• Appendix F,
to request help from National Instruments or to comment on our
products.

• The

• The

Glossary

used in this manual, including abbreviations, acronyms, metric
prefixes, mnemonics, and symbols.

Index

the page where you can find each one.

OKI 82C53 Data Sheet,

Register-Level Programming

Using Your PC-DIO-96 (Non-PnP) Board

Customer Communication

contains an alphabetical list and description of terms

alphabetically lists the topics in this manual, including

contains the manufacturer

, describes in detail the

, describes

, contains forms you can use

Conventions Used in This Manual

The following conventions are used in this manual:

82C53 82C53 refers to the OKI 82C53 (OKI Semiconductor) CMOS

programmable interval timer.

82C55A 82C55A refers to the OKI 82C55A (OKI Semiconductor) CMOS

programmable peripheral interface.

< > Angle brackets containing numbers separated by an ellipses represent a

range of values associated with a bit or signal name (for example,
ACH<0..7>).

bold

bold italic

italic

PC-DIO-96/PnP User Manual x © National Instruments Corporation

Bold text denotes the names of menus, menu items, or dialog box
buttons or options.

Bold italic text denotes a note, caution, or warning.
Italic text denotes emphasis, a cross reference, or an introduction to a

key concept.

About This Manual

monospace Text in this font denotes text or characters that are to be literally input

from the keyboard, sections of code, programming examples, and
syntax examples. This font is also used for the proper names of disk
drives, paths, directories, programs, subprograms, subroutines, device
names, functions, operations, variables, filenames, and extensions, and
for statements and comments taken from program code.

NI-DAQ NI-DAQ refers to the NI-DAQ software for PC compatibles unless

otherwise noted.

PC-DIO-96/PnP PC-DIO-96/PnP refers to both the Plug and Play and non-Plug and Play

compatible versions of the board.

PC-DIO-96PnP PC-DIO-96PnP refers to the Plug and Play version of the

PC-DIO-96/PnP.

PC-DIO-96 PC-DIO-96 refers to the non-Plug and Play version of the

PC-DIO-96/PnP.

PnP PnP (Plug and Play) refers to a device that is fully compatible with the

industry standard Plug and Play ISA Specification. All bus-related
configuration is performed through software, freeing the user from
manually configuring jumpers or switches to set the product’s base
address and interrupt level. Plug and Play systems automatically
arbitrate and assign system resources to a PnP product.

non-PnP Non-PnP (non-Plug and Play) refers to a device that requires a user to

configure the product’s base address and interrupt level with switches
and jumpers. This configuration must be performed prior to installing
the product in the computer.

PPI x PPI x, where the x is replaced by A, B, C, or D, refers to one of the four

programmable peripheral interface (PPI) chips on the PC-DIO-96/PnP.

SCXI SCXI stands for Signal Conditioning eXtensions for Instrumentation

and is a National Instruments product line designed to perform front­end signal conditioning for National Instruments plug-in DAQ boards.

Abbreviations, acronyms, metric prefixes, mnemonics, and symbols are
listed in the Glossary.

© National Instruments Corporation xi PC-DIO-96/PnP User Manual

About This Manual

National Instruments Documentation

The PC-DIO-96/PnP User Manual is one piece of the documentation
set for your data acquisition (DAQ) system. You could have any of
several types of manuals, depending on the hardware and software in
your system. Use the different types of manuals you have as follows:

• Getting Started with SCXI—If you are using SCXI, this is the first
manual you should read. It gives an overview of the SCXI system
and contains the most commonly needed information for the
modules, chassis, and software.

• Your SCXI hardware user manuals—If you are using SCXI, read
these manuals next for detailed information about signal
connections and module configuration. They also explain in greater
detail how the module works and contain application hints.

• Your DAQ hardware user manuals—These manuals have detailed
information about the DAQ hardware that plugs into or is
connected to your computer. Use these manuals for hardware
installation and configuration instructions, specification
information about your DAQ hardware, and application hints.

• Software documentation—Examples of software documentation
you may have are the LabVIEW, LabWindows
documentation sets. After you set up your hardware system, use
either the application software (LabVIEW or LabWindows/CVI)
documentation or the NI-DAQ documentation to help you write
your application. If you have a large and complicated system, it is
worthwhile to look through the software documentation before you
configure your hardware.

• Accessory installation guides or manuals—If you are using
accessory products, read the terminal block and cable assembly
installation guides or accessory board user manuals. They explain
how to physically connect the relevant pieces of the system.
Consult these guides when you are making your connections.

• SCXI Chassis User Manual—If you are using SCXI, read this
manual for maintenance information on the chassis and installation
instructions.

®

/CVI, and NI-DAQ

PC-DIO-96/PnP User Manual xii © National Instruments Corporation

Related Documentation

If you are a register-level programmer, the following documents
contain information that you may find helpful as you read this manual:

• Your computer technical reference manual

• Plug and Play ISA Specification

Customer Communication

National Instruments wants to receive your comments on our products
and manuals. We are interested in the applications you develop with our
products, and we want to help if you have problems with them. To make
it easy for you to contact us, this manual contains comment and
configuration forms for you to complete. These forms are in
Appendix F, Customer Communication, at the end of this manual.

About This Manual

© National Instruments Corporation xiii PC-DIO-96/PnP User Manual

Chapter

Introduction

This chapter describes the PC-DIO-96/PnP; lists what you need to get
started; describes software programming choices, optional equipment,
and custom cables; and explains how to unpack the PC-DIO-96/PnP.

About the PC-DIO-96/PnP

Thank you for purchasing the National Instruments PC-DIO-96/PnP.

PnP refers to the Plug and Play technology used in this board. See the
Conventions Used in this Manual section in About This Manual for an

explanation. The PC-DIO-96/PnP is a 96-bit, parallel, digital I/O
interface for ISA computers. Four 82C55A programmable peripheral
interface (PPI) chips control the 96 bits of digital I/O. The 82C55A can
operate in either a unidirectional or bidirectional mode and can generate
interrupt requests to the host computer. You can program the 82C55A
for almost any 8-bit or 16-bit digital I/O application. All digital I/O
communication is through a standard, 100-pin, male connector. The
PC-DIO-96/PnP also includes an 82C53 counter/timer that can send
periodic interrupts to the host system.

1

If you have the non-PnP version of the PC-DIO-96/PnP, see
Appendix E, Using Your PC-DIO-96 (Non-PnP) Board, for the
differences between the PnP version and the non-PnP version.

You can use the PC-DIO-96/PnP in a wide range of digital I/O
applications. With the PC-DIO-96/PnP, you can interface any PC to any
of the following:

• Other computers
– Another PC with a National Instruments PC-DIO-96/PnP,

PC-DIO-24, or AT-DIO-32F

– IBM Personal System/2 with a National Instruments

MC-DIO-24 or MC-DIO-32F

© National Instruments Corporation 1-1 PC-DIO-96/PnP User Manual

Chapter 1 Introduction

Note: The PC-DIO-96/PnP cannot sink sufficient current to drive the

– Macintosh II with a National Instruments NB-DIO-24,

NB-DIO-32F, or PCI-DIO-96

– Any other computer with an 8-bit or 16-bit parallel interface

• Centronics-compatible printers and plotters

• Panel meters

• Instruments and test equipment with BCD readouts and/or controls

• Optically isolated, solid-state relays and I/O module mounting
racks

SSR-OAC-5 and SSR-OAC-5A output modules. However, it can drive the
SSR-ODC-5 output module and all SSR input modules available from
National Instruments.

If you need to drive an SSR-OAC-5 or SSR-OAC-5A, you can either use a
non-inverting digital buffer chip between the PC-DIO-96/PnP and the SSR
backplane, or you can use a DIO-23F or MIO Series board with
appropriate connections (for example, SC-205X and cables).

With the PC-DIO-96/PnP, a PC can serve as a digital I/O system
controller for laboratory testing, production testing, and industrial
process monitoring and control.

Detailed specifications of the PC-DIO-96/PnP are in Appendix A,
Specifications.

What You Need to Get Started

To set up and use your PC-DIO-96/PnP, you will need the following:

❑ PC-DIO-96/PnP board
❑ PC-DIO-96/PnP User Manual
❑ One of the following software packages and documentation:

NI-DAQ for PC Compatibles
LabVIEW for Windows
LabWindows/CVI

❑ Your computer

PC-DIO-96/PnP User Manual 1-2 © National Instruments Corporation

Software Programming Choices

There are several options to choose from when programming your
National Instruments DAQ and SCXI hardware. You can use
LabVIEW, LabWindows/CVI, NI-DAQ, or register-level
programming. NI-DAQ version 4.6.1 or earlier supports LabWindows
for DOS.

LabVIEW and LabWindows/CVI Application Software

LabVIEW and LabWindows/CVI are innovative program development
software packages for data acquisition and control applications.
LabVIEW uses graphical programming, whereas LabWindows/CVI
enhances traditional programming languages. Both packages include
extensive libraries for data acquisition, instrument control, data
analysis, and graphical data presentation.

LabVIEW features interactive graphics, a state-of-the-art user
interface, and a powerful graphical programming language. The
LabVIEW Data Acquisition VI Library, a series of VIs for using
LabVIEW with National Instruments DAQ hardware, is included with
LabVIEW. The LabVIEW Data Acquisition VI Library is functionally
equivalent to the NI-DAQ software.

Chapter 1 Introduction

LabWindows/CVI features interactive graphics, a state-of-the-art user
interface, and uses the ANSI standard C programming language. The
LabWindows/CVI Data Acquisition Library, a series of functions for
using LabWindows/CVI with National Instruments DAQ hardware, is
included with the NI-DAQ software kit. The LabWindows/CVI Data
Acquisition Library is functionally equivalent to the NI-DAQ software.

Using LabVIEW or LabWindows/CVI software will greatly reduce the
development time for your data acquisition and control application.

NI-DAQ Driver Software

The NI-DAQ driver software is included at no charge with all National
Instruments DAQ hardware. NI-DAQ is not packaged with SCXI or
accessory products, except for the SCXI-1200. NI-DAQ has an
extensive library of functions that you can call from your application
programming environment. These functions include routines for analog
input (A/D conversion), buffered data acquisition (high-speed A/D
conversion), analog output (D/A conversion), waveform generation,

© National Instruments Corporation 1-3 PC-DIO-96/PnP User Manual

Chapter 1 Introduction

digital I/O, counter/timer operations, SCXI, RTSI, self-calibration,
messaging, and acquiring data to extended memory.

NI-DAQ has both high-level DAQ I/O functions for maximum ease of
use and low-level DAQ I/O functions for maximum flexibility and
performance. Examples of high-level functions are streaming data to
disk or acquiring a certain number of data points. An example of a low­level function is writing directly to registers on the DAQ device.
NI-DAQ does not sacrifice the performance of National Instruments
DAQ devices because it lets multiple devices operate at their peak
performance.

NI-DAQ also internally addresses many of the complex issues between
the computer and the DAQ hardware such as programming interrupts
and DMA controllers. NI-DAQ maintains a consistent software
interface among its different versions so that you can change platforms
with minimal modifications to your code. Whether you are using
conventional programming languages, LabVIEW, or
LabWindows/CVI, your application uses the NI-DAQ driver software,
as illustrated in Figure 1-1.

Conventional 
Programming 

Environment 

(PC, Macintosh, or 

Sun SPARCstation)



DAQ or 

SCXI Hardware

LabVIEW 

(PC, Macintosh, or 

Sun SPARCstation)

NI-DAQ

Driver Software

LabWindows/CVI

(PC or 

Sun SPARCstation)

Personal 

Computer

or

Workstation





Figure 1-1. The Relationship between the Programming Environment,

NI-DAQ, and Your Hardware

PC-DIO-96/PnP User Manual 1-4 © National Instruments Corporation

Register-Level Programming

The final option for programming any National Instruments DAQ
hardware is to write register-level software. Writing register-level
programming software can be very time-consuming and inefficient, and
is not recommended for most users.

Even if you are an experienced register-level programmer, consider
using NI-DAQ, LabVIEW, or LabWindows/CVI to program your
National Instruments DAQ hardware. Using the NI-DAQ, LabVIEW, or
LabWindows/CVI software is easier than, and as flexible as, register­level programming, and can save weeks of development time.

Optional Equipment

National Instruments offers a variety of products to use with your
PC-DIO-96/PnP board, including cables, connector blocks, and other
accessories, as follows:

• Cables and cable assemblies

• Connector blocks and unshielded 50-pin screw terminals

• SCXI modules and accessories for isolating, amplifying, exciting,
and multiplexing signals for relays and analog output. With SCXI
you can condition and acquire up to 3,072 channels.

• Low channel count signal conditioning modules, boards, and
accessories, including conditioning for strain gauges and RTDs,
simultaneous sample and hold, and relays.

Chapter 1 Introduction

For more specific information about these products, refer to your
National Instruments catalog or call the office nearest you.

Custom Cabling

National Instruments offers cables and accessories for you to prototype
your application or to use if you frequently change board
interconnections.

You can interface the PC-DIO-96/PnP to a wide range of printers,
plotters, test instruments, I/O racks and modules, screw terminal panels,
and almost any device with a parallel interface. The PC-DIO-96/PnP
digital I/O connector is a standard, 100-pin header connector. Adapters
for this header connector expand the interface to four 50-pin ribbon
cables, each of which has the pinout of a PC-DIO-24. The pin
assignments of the expansion cables are compatible with the standard

© National Instruments Corporation 1-5 PC-DIO-96/PnP User Manual

Chapter 1 Introduction

24-channel I/O module mounting racks (such as those manufactured by
Opto 22 and Gordos).

The CB-100 cable termination accessory is available from National
Instruments for use with the PC-DIO-96/PnP board. This kit includes
two 50-conductor, flat-ribbon cables and a connector block. You can
attach signal input and output wires to screw terminals on the connector
block and therefore connect signals to the PC-DIO-96/PnP I/O
connector.

The CB-100 is useful for initial prototyping of an application or in
situations where PC-DIO-96/PnP interconnections are frequently
changed. Once a final field wiring scheme has been developed,
however, you may want to develop your own cable. This section
contains information for the design of custom cables.

The PC-DIO-96/PnP I/O connector is a 100-pin, Centronics-style, male,
ribbon-cable header connector. The manufacturer and the appropriate
part number for this connector is as follows:

• Robinson Nugent (part number P50E-100P1-RR1-TG)
The mating connector for the PC-DIO-96/PnP is a 100-position,

polarized, Centronics-style, female, ribbon-socket connector with
strain relief. National Instruments uses a polarized (keyed) connector to
prevent inadvertent upside-down connection to the PC-DIO-96/PnP.
This 100-pin connector attaches to two 50-pin cables, each of which can
be connected to a 50-pin connector on the other end. The recommended
manufacturer and the appropriate part number for the 100-pin mating
connector is as follows:

• Robinson Nugent (part number P50E-100S-TG)
The recommended manufacturer part numbers for 50-pin, female,

ribbon-socket connectors suitable for use with the preceding connector
are:

• Electronic Products Division/3M (part number 3425-7650)

• T&B/Ansley Corporation (part number 609-5041CE)

PC-DIO-96/PnP User Manual 1-6 © National Instruments Corporation

Unpacking

Chapter 1 Introduction

Recommended manufacturers and the appropriate part numbers for the
standard ribbon cable (50-conductor, 28 AWG, stranded) that can be
used with both the 100-pin and the 50-pin connectors are:

• Electronic Products Division/3M (part number 3365/50)

• T&B/Ansley Corporation (part number 171-50)

Your PC-DIO-96/PnP board is shipped in an antistatic package to
prevent electrostatic damage to the board. Electrostatic discharge can
damage several components on the board. To avoid such damage in
handling the board, take the following precautions:

• Ground yourself via a grounding strap or by holding a grounded
object.

• Touch the antistatic package to a metal part of your computer
chassis before removing the board from the package.

• Remove the board from the package and inspect the board for loose
components or any other sign of damage. Notify National
Instruments if the board appears damaged in any way. Do not
install a damaged board into your computer.

• Never touch the exposed pins of connectors.

© National Instruments Corporation 1-7 PC-DIO-96/PnP User Manual

Installation and

Chapter

Configuration

This chapter describes how to install and configure the PC-DIO-96PnP
board.

Installation

Note: You should install your driver software before installing your hardware.

Refer to your NI-DAQ release notes for software installation instructions.

2



21

 

3

1 Serial Number 2W1 3F1

Figure 2-1. PC-DIO-96PnP Parts Locator Diagram

© National Instruments Corporation 2-1 PC-DIO-96/PnP User Manual

Chapter 2 Installation and Configuration

Note: The PC-DIO-96PnP uses 100 kΩ resistors for polarity selection at power-

up. These signals are pulled up to VCC (+5 VDC, factory default) or pulled
down to GND by selection of jumper W1. The location of W1 is shown in
Figure 2-1. For more information, see the Digital I/O Power-up State
Selection section in Chapter 3, Signal Connections.

You can install the PC-DIO-96PnP in any available expansion slot in
your computer. The following are general installation instructions, but
consult your computer user manual or technical reference manual for
specific instructions and warnings.

1. Turn off and unplug your computer.

2. Remove the top cover or access port to the I/O channel.

3. Remove the expansion slot cover on the back panel of the
computer.

4. Insert the PC-DIO-96PnP board into any 8-bit or 16-bit slot. It may
be a tight fit, but do not force the board into place.

5. Screw the mounting bracket of the PC-DIO-96PnP board to the
back panel rail of the computer.

6. Visually verify your installation.

7. Replace the cover.

8. Plug in and turn on your computer.

Your PC-DIO-96PnP is now installed.

PC-DIO-96/PnP User Manual 2-2 © National Instruments Corporation

Hardware Configuration

Plug and Play

The PC-DIO-96PnP is fully compatible with the industry-standard
Intel/Microsoft Plug and Play Specification. A Plug and Play system
arbitrates and assigns resources through software, freeing you from
manually setting switches and jumpers. These resources include the
board base I/O address and interrupt channels. Each PC-DIO-96PnP is
configured at the factory to request these resources from the Plug and
Play Configuration Manager.

The Configuration Manager receives all of the resource requests at
startup, compares the available resources to those requested, and
assigns the available resources as efficiently as possible to the Plug and
Play boards. Application software can query the Configuration
Manager to determine the resources assigned to each board without
your involvement. The Plug and Play software is installed as a device
driver or as an integral component of the computer BIOS.

Base I/O Address and Interrupt Selection

To change base I/O address or interrupt selection, refer to the NI-DAQ
Configuration Utility online help file. You can configure the
PC-DIO-96PnP to use base addresses in the range of 100 to 3E0 hex.
Each board occupies 16 bytes of address space and must be located on
a 16-byte boundary. Therefore, valid addresses include 100, 110,
120…, 3E0 hex.

Chapter 2 Installation and Configuration

The PC-DIO-96PnP can use interrupt channels 3, 4, 5, 6, 7, and 9.

Non-Plug and Play

To configure the non-Plug and Play PC-DIO-96 board, refer to
Appendix E, Using Your PC-DIO-96 (Non-PnP) Board.

© National Instruments Corporation 2-3 PC-DIO-96/PnP User Manual

Chapter

Signal Connections

This chapter includes timing specifications and signal connection
instructions for the PC-DIO-96/PnP I/O connector.

Warning: Connections that exceed any of the maximum ratings of input or output

signals on the PC-DIO-96/PnP can damage the board and the computer.
The description of each signal in this section includes information about
maximum input ratings. National Instruments is NOT liable for any
damages resulting from any such signal connections.

I/O Connector Pin Description

Figure 3-1 shows the pin assignments for the PC-DIO-96/PnP digital
I/O connector.

3

© National Instruments Corporation 3-1 PC-DIO-96/PnP User Manual

Chapter 3 Signal Connections

APC7 CPC7
BPC7 DPC7
APC6 CPC6
BPC6 DPC6
APC5 CPC5
BPC5 DPC5
APC4 CPC4
BPC4 DPC4
APC3 CPC3
BPC3 DPC3
APC2 CPC2
BPC2 DPC2
APC1 CPC1
BPC1 DPC1
APC0 CPC0
BPC0 DPC0
APB7 CPB7
BPB7 DPB7
APB6 CPB6
BPB6 DPB6
APB5 CPB5
BPB5 DPB5
APB4 CPB4
BPB4 DPB4
APB3 CPB3
BPB3 DPB3
APB2 CPB2
BPB2 DPB2
APB1 CPB1
BPB1 DPB1
APB0 CPB0
BPB0 DPB0
APA7 CPA7
BPA7 DPA7
APA6 CPA6
BPA6 DPA6
APA5 CPA5
BPA5 DPA5
APA4 CPA4
BPA4 DPA4
APA3 CPA3
BPA3 DPA3
APA2 CPA2
BPA2 DPA2
APA1 CPA1
BPA1 DPA1
APA0 CPA0
BPA0 DPA0

+5 V +5 V

GND GND

151
252
353
454
555
656
757
858

959
10 60
11 61
12 62
13 63
14 64
15 65
16 66
17 67
18 68
19 69
20 70
21 71
22 72
23 73
24 74
25 75
26 76
27 77
28 78
29 79
30 80
31 81
32 82
33 83
34 84
35 85
36 86
37 87
38 88
39 89
40 90
41 91
42 92
43 93
44 94
45 95
46 96
47 97
48 98
49 99
50 100

Figure 3-1. Digital I/O Connector Pin Assignments

PC-DIO-96/PnP User Manual 3-2 © National Instruments Corporation

Chapter 3 Signal Connections

I/O Connector Signal Connection Descriptions

Pin Signal Name Description

1, 3, 5, 7, 9, 11, 13, 15 APC<7..0> Bidirectional Data Lines for Port C of

PPI A—APC7 is the MSB, APC0 the LSB.

17, 19, 21, 23, 25, 27, 29, 31 APB<7..0> Bidirectional Data Lines for Port B of

PPI A—APB7 is the MSB, APB0 the LSB.

33, 35, 37, 39, 41, 43, 45, 47 APA<7..0> Bidirectional Data Lines for Port A of

PPI A—APA7 is the MSB, APA0 the LSB.

2, 4, 6, 8, 10, 12, 14, 16 BPC<7..0> Bidirectional Data Lines for Port C of

PPI B—BPC7 is the MSB, BPC0 the LSB.

18, 20, 22, 24, 26, 28, 30, 32 BPB<7..0> Bidirectional Data Lines for Port B of

PPI B—BPB7 is the MSB, BPB0 the LSB.

34, 36, 38, 40, 42, 44, 46, 48 BPA<7..0> Bidirectional Data Lines for Port A of

PPI B—BPA7 is the MSB, BPA0 the LSB.

51, 53, 55, 57, 59, 61, 63, 65 CPC<7..0> Bidirectional Data Lines for Port C of

PPI C—CPC7 is the MSB, CPC0 the LSB.

67, 69, 71, 73, 75, 77, 79, 81 CPB<7..0> Bidirectional Data Lines for Port B of

PPI C—CPB7 is the MSB, CPB0 the LSB.

83, 85, 87, 89, 91, 93, 95, 97 CPA<7..0> Bidirectional Data Lines for Port A of

PPI C—CPA7 is the MSB, CPA0 the LSB.

52, 54, 56, 58, 60, 62, 64, 66 DPC<7..0> Bidirectional Data Lines for Port C of

PPI D—DPC7 is the MSB, DPC0 the LSB.

68, 70, 72, 74, 76, 78, 80, 82 DPB<7..0> Bidirectional Data Lines for Port B of

PPI D—DPB7 is the MSB, DPB0 the LSB.

84, 86, 88, 90, 92, 94, 96, 98 DPA<7..0> Bidirectional Data Lines for Port A of

PPI D—DPA7 is the MSB, DPA0 the LSB.

49, 99 (see note below) +5 V +5 Volts—These pins are connected to the

computer’s +5 VDC supply.

50, 100 GND Ground—These pins are connected to the

computer’s ground signal.

Note: Pins 49 and 99 are connected to the +5 V PC power supply via a 1 A self-resetting

fuse.

© National Instruments Corporation 3-3 PC-DIO-96/PnP User Manual

Chapter 3 Signal Connections

Port C Pin Assignments

The signals assigned to port C depend on the mode in which the
82C55A is programmed. In mode 0, port C is considered as two 4-bit
I/O ports. In modes 1 and 2, port C is used for status and handshaking
signals with zero, two, or three lines available for general-purpose
input/output. The following table summarizes the signal assignments of
port C for each programmable mode. Consult Appendix D, Register-
Level Programming, for programming information.

Warning: During programming, note that each time a port is configured, output

ports A and C are reset to 0, and output port B is undefined.

Table 3-1. Port C Signal Assignments

Programming

Mode

Mode 0
Mode 1 Input
Mode 1 Output
Mode 2

PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

I/O I/O I/O I/O I/O I/O I/O I/O

I/O I/O IBF

OBFA* ACKA* I/O I/O INTR

OBFA* ACKA* IBF

Group A Group B

A

A

* Indicates that the signal is active low

Cable Assembly Connectors

The cable assembly referred to in Optional Equipment in Chapter 1,
Introduction, is an assembly of two 50-pin cables and three connectors.

Both cables are joined to a single connector on one end and to
individual connectors on the free ends. The 100-pin connector that joins
the two cables plugs into the I/O connector of the PC-DIO-96/PnP. The
other two connectors are 50-pin connectors, one of which is connected
to pins 1 through 50 and the other is connected to pins 51 through 100
of the PC-DIO-96/PnP I/O connector. The cable with the label on it is
connected to pins 1 through 50. Figures 3-2 and 3-3 show the pin
assignments for the 50-pin connectors on the cable assembly.

STBA* INTR

STBA* INTR

STBB* IBFB

A

ACKB* OBFB* INTR

A

I/O I/O I/O

A

INTR

B

B

B

PC-DIO-96/PnP User Manual 3-4 © National Instruments Corporation

Chapter 3 Signal Connections

APC7
APC6

APC5
APC4

APC3

APC2
APC1
APC0

APB7

APB6
APB5

APB4
APB3

APB2

APB1
APB0
APA7

APA6

APA5

APA4

APA3

APA2

APA1

APA0

+5 V

12
34
56
78

910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

BPC7
BPC6
BPC5
BPC4
BPC3
BPC2
BPC1
BPC0

BPB7
BPB6

BPB5
BPB4
BPB3
BPB2
BPB1
BPB0
BPA7
BPA6
BPA5
BPA4
BPA3
BPA2
BPA1
BPA0
GND

Figure 3-2. Cable Assembly Connector Pin Assignments for Pins 1 through 50

of the PC-DIO-96/PnP I/O Connector

© National Instruments Corporation 3-5 PC-DIO-96/PnP User Manual

Chapter 3 Signal Connections

CPC7

CPC6

CPC5
CPC4

CPC3
CPC2

CPC1
CPC0

CPB7

CPB6
CPB5

CPB4
CPB3
CPB2

CPB1
CPB0
CPA7

CPA6
CPA5

CPA4
CPA3
CPA2

CPA1
CPA0

+5 V

12
34
56
78

910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

DPC7
DPC6
DPC5
DPC4
DPC3
DPC2
DPC1
DPC0

DPB7
DPB6

DPB5
DPB4
DPB3
DPB2
DPB1
DPB0
DPA7
DPA6
DPA5
DPA4
DPA3
DPA2
DPA1
DPA0
GND

Figure 3-3. Cable Assembly Connector Pin Assignments for Pins 51 through 100

of the PC-DIO-96/PnP I/O Connector

PC-DIO-96/PnP User Manual 3-6 © National Instruments Corporation

Digital I/O Signal Connections

Pins 1 through 48 and pins 51 through 98 of the I/O connector are digital
I/O signal pins. The following specifications and ratings apply to the
digital I/O lines.

Absolute maximum voltage rating -0.5 to +5.5 V with respect to GND
Digital input specifications (referenced to GND):
Input logic high voltage 2.2 V min 5.3 V max
Input logic low voltage -0.3 V min 0.8 V max
Maximum input current

(0 < Vin < 5 V) -1.0 µA min 1.0 µA max
Digital output specifications (referenced to GND):
Output logic high voltage 3.7 V min 5.0 V max

at I
Output logic low voltage 0.0 V min 0.4 V max

at I

= -2.5 mA

out

= 2.5 mA

ou

t

Chapter 3 Signal Connections

Output current 2.5 mA min —
at VOL = 0.5 V

Output current 2.5 mA min —
at VOH = 2.7 V

Figure 3-4 depicts signal connections for three typical digital I/O
applications.

© National Instruments Corporation 3-7 PC-DIO-96/PnP User Manual

Chapter 3 Signal Connections

+5 V

LED

+5 V

TTL Signal

Switch *

I/O Connector

41
43
45
47

67
69
71
73

+5 V

Jumper
Selectable (W1)

100 kΩ100 kΩ 100 kΩ 100 kΩ

PPI A

Port A

APA<3..0>

100 kΩ 100 kΩ 100 kΩ 100 kΩ

PPI C

Port B 

CPB<7..4>

50, 100

GND

PC-DIO-96/PnP

* Complex switch circuitry is not shown in order to simplify the figure.

Figure 3-4. Digital I/O Connections

In Figure 3-4, PPI A, port A is configured for digital output, and PPI C,
port B is configured for digital input. Digital input applications include
receiving TTL signals and sensing external device states such as the
state of the switch in Figure 3-4. Digital output applications include
sending TTL signals and driving external devices such as the LED
shown in Figure 3-4.

PC-DIO-96/PnP User Manual 3-8 © National Instruments Corporation

Power Connections

Pins 49 and 99 of the I/O connector are connected to the +5 V supply
from the PC power supply. These pins are referenced to GND and can
be used to power external digital circuitry. This +5 V supply has a 1 A
protection fuse in series. This fuse is self-resetting. Simply remove the
circuit causing the heavy current load and the fuse will reset itself. For
more information on these output pins, see Output Signals in
Appendix A, Specifications.

Power rating 0.5 A per pin at +5 V ±10%

Warning: Under no circumstances should these +5 V power pins be connected

directly to ground or to any other voltage source on the PC-DIO-96/PnP or
any other device. Doing so may damage the PC-DIO-96/PnP and the PC.
National Instruments is
connection.

NOT liable for damage resulting from such a

Digital I/O Power-up State Selection

You may want to power up the PC-DIO-96/PnP’s digital I/O lines in a
user-defined state. The PC-DIO-96/PnP facilitates user-configurable
pull-up or pull-down. Each DIO channel is connected to a 100 kΩ
resistor and can be pulled high or low using jumper W1. You can use
W1 to pull all 96 DIO lines high or low. However, if all lines are high,
you may want to pull some lines low. To do this properly, you must
understand the nature of the drive current on those lines and adhere to
TTL logic levels.

Chapter 3 Signal Connections

High DIO Power-up State

If you select the pulled-high mode, each DIO line will be pulled to VCC
(+5 VDC) with a 100 kΩ resistor. If you want to pull a specific line low,
connect between that line and ground a pull-down resistor (RL) whose
value will give you a maximum of 0.4 VDC. The DIO lines provide a
maximum of 2.5 mA at 3.7 V in the high state. Use the largest possible
resistor so that you do not use more current than necessary to perform
the pull-down task.

Also, make sure the resistor’s value is not so large that leakage current
from the DIO line along with the current from the 100 kΩ pull-up
resistor drives the voltage at the resistor above a TTL low level of

0.4 VDC.

© National Instruments Corporation 3-9 PC-DIO-96/PnP User Manual

Chapter 3 Signal Connections

PC-DIO-96/PnP

82C55

Figure 3-5. DIO Channel Configured for High DIO Power-up State with External Load

100 kΩ

+5 V

GND

Digital I/O Line

R

L

Example:
At power up, the board is configured for input and, by default, all DIO
lines are high. To pull one channel low, follow these steps:

1. Install a load (RL). Remember that the smaller the resistance, the
greater the current consumption and the lower the voltage (V).

2. Using the following formula, calculate the largest possible load to
maintain a logic low level of 0.4 V and supply the maximum
driving current (I).

V = I * R

⇒ RL = V / I, where:

L

V= 0.4 V ;Voltage across R

L

I = 46 µA + 10 µA ; 4.6 V across the 100 kΩ pull-up

resistor and 10 µA from 82C55
leakage current

Therefore:

RL = 7.1 kΩ ;0.4 V / 56 µA

This resistor value, 7.1 kΩ, provides a maximum of 0.4 V on the DIO
line at power up. You can substitute smaller resistor values, but they
will draw more current, leaving less drive current for other circuitry
connected to this line. The 7.1 kΩ resistor reduces the amount of a logic
high source current by 0.4 mA with a 2.8 V output.

PC-DIO-96/PnP User Manual 3-10 © National Instruments Corporation

Low DIO Power-up State

If you select pulled-low mode, each DIO line will be pulled to GND
(0 VDC) using a 100 kΩ resistor. If you want to pull a specific line high,
connect a pull-up resistor that will give you a minimum of 2.8 VDC.
The DIO lines are capable of sinking a maximum of 2.5 mA at 0.4 V in
the low state. Use the largest possible resistance value so that you do
not to use more current than necessary to perform the pull-up task.

Also, make sure the pull-up resistor value is not so large that leakage
current from the DIO line along with the current from the 100 kΩ pull­down resistor brings the voltage at the resistor below a TTL high level
of 2.8 VDC.

Chapter 3 Signal Connections

PC-DIO-96/PnP

82C55

100 kΩ

GND

Figure 3-6. DIO Channel Configured for Low DIO Power-up State with External Load

+5 V

R

L

Digital I/O Line

© National Instruments Corporation 3-11 PC-DIO-96/PnP User Manual

Chapter 3 Signal Connections

Example:
At power up, the board is configured for input and jumper W1 is set in
the low DIO power-up state, which means all DIO lines are pulled low.
If you want to pull one channel high, follow these steps:

1. Install a load (RL). Remember that the smaller the resistance, the
greater the current consumption and the lower the voltage (V).

2. Using the following formula, calculate the largest possible load to
maintain a logic high level of 2.8 V and supply the maximum sink
current (I).

V = I * RL ⇒ RL = V / I, where:

V = 2.2 V ;voltage across R
I = 28 µA + 10 µA ; 2.8 V across the 100 kΩ pull-up

resistor and 10 µA from 82C55
leakage current

Therefore:

RL = 5.7 kΩ ;2.2 V / 38 µA

This resistor value, 5.7 kΩ, provides a minimum of 2.8 V on the DIO
line at power up. You can substitute smaller resistor values but they will
draw more current, leaving less sink current for other circuitry
connected to this line. The 5.7 kΩ resistor will reduce the amount of a
logic low sink current by 0.8 mA with a 0.4 V output.

L

Timing Specifications

This section lists the timing specifications for handshaking with the
PC-DIO-96/PnP. The handshaking lines STB* and IBF synchronize
input transfers. The handshaking lines OBF* and ACK* synchronize
output transfers.

The signals in Table 3-2 are used in the timing diagrams later in this
chapter.

PC-DIO-96/PnP User Manual 3-12 © National Instruments Corporation

Chapter 3 Signal Connections

Table 3-2. Timing Signal Descriptions

Name Type Description

STB* Input Strobe Input—A low signal on this handshaking line loads data

into the input latch.

IBF Output Input Buffer Full—A high signal on this handshaking line indicates

that data has been loaded into the input latch. This is an input
acknowledge signal.

ACK* Input Acknowledge Input—A low signal on this handshaking line

indicates that the data written to the port has been accepted. This
signal is a response from the external device indicating that it has
received the data from the PC-DIO-96/PnP.

OBF* Output Output Buffer Full—A low signal on this handshaking line

indicates that data has been written to the port.

INTR Output Interrupt Request—This signal becomes high when the 82C55A

requests service during a data transfer. The appropriate interrupt
enable bits must be set to generate this signal.

RD* Internal Read Signal—This signal is the read signal generated from the

control lines of the computer I/O expansion bus.

WR* Internal Write Signal—This signal is the write signal generated from the

control lines of the computer I/O expansion bus.

DATA Bidirectional Data Lines at the Specified Port—This signal indicates the

availability of data on the data lines at a port that is in the output
mode. If the port is in the input mode, this signal indicates when the
data on the data lines should be valid.

© National Instruments Corporation 3-13 PC-DIO-96/PnP User Manual

Chapter 3 Signal Connections

Mode 1 Input Timing

The following figure illustrates the timing specifications for an input
transfer in mode 1.

T1

T2

T4

STB*

T7

IBF

T6

INTR

RD*

T3

T5

DATA

Name Description Minimum Maximum

T1 STB* pulse width 100 –
T2 STB* = 0 to IBF = 1 – 150
T3 Data before STB* = 1 20 –
T4 STB* = 1 to INTR = 1 – 150
T5 Data after STB* = 1 50 –
T6 RD* = 0 to INTR = 0 – 200
T7 RD* = 1 to IBF = 0 – 150

All timing values are in nanoseconds.

PC-DIO-96/PnP User Manual 3-14 © National Instruments Corporation

Mode 1 Output Timing

The following figure illustrates the timing specifications for an output
transfer in mode 1.

WR*

OBF*

INTR

Chapter 3 Signal Connections

T3

T4

T1

T6

ACK*

T5

DATA

T2

Name Description Minimum Maximum

T1 WR* = 0 to INTR = 0 – 250
T2 WR* = 1 to output – 200
T3 WR* = 1 to OBF* = 0 – 150
T4 ACK* = 0 to OBF* = 1 – 150
T5 ACK* pulse width 100 –
T6 ACK* = 1 to INTR = 1 – 150

All timing values are in nanoseconds.

© National Instruments Corporation 3-15 PC-DIO-96/PnP User Manual

Chapter 3 Signal Connections

Mode 2 Bidirectional Timing

The following figure illustrates the timing specifications for
bidirectional transfers in mode 2.

T1

WR*

OBF*

INTR

ACK*

STB*

T4

IBF

RD*

T2

T6

T7

T3

T10

T5

T8

T9

DATA

Name Description Minimum Maximum

T1 WR* = 1 to OBF* = 0 – 150
T2 Data before STB* = 1 20 –
T3 STB* pulse width 100 –
T4 STB* = 0 to IBF = 1 – 150
T5 Data after STB* = 1 50 –
T6 ACK* = 0 to OBF = 1 – 150
T7 ACK* pulse width 100 –
T8 ACK* = 0 to output – 150
T9 ACK* = 1 to output float 20 250

T10 RD* = 1 to IBF = 0 – 150

All timing values are in nanoseconds.

PC-DIO-96/PnP User Manual 3-16 © National Instruments Corporation

Chapter

Theory of Operation

This chapter contains a functional overview of the PC-DIO-96PnP
board and explains the operation of each functional unit making up the
PC-DIO-96PnP.

The block diagram in Figure 4-1 illustrates the key functional
components of the PC-DIO-96PnP board.

8

8

8

PC I/O Channel

16

6

+5 VDC

Data 

Transceivers

PC I/O Channel 
Control Circuitry

Plug and Play

PC I/O

Address

Interrupt
Circuitry

Interrupt

Control

Circuitry

INT

82C55A PPI

82C55A PPI

82C55A PPI

82C55A PPI

82C53 Timer

1 A Fuse

Port A
Port B
Port C

Port A
Port B

Port C
Port A

Port B
Port C

Port A
Port B
Port C

4

8
8
8

8
8

8
8

8
8

8
8

8

Digital I/O Connector

Figure 4-1. PC-DIO-96PnP Block Diagram

© National Instruments Corporation 4-1 PC-DIO-96/PnP User Manual

Chapter 4 Theory of Operation

The PC I/O channel consists of an address bus, a data bus, interrupt
lines, and several control and support signals.

Data Transceivers

The data transceivers control the sending and receiving of data to and
from the PC I/O channel.

PC I/O Channel Control Circuitry

The I/O channel control circuitry monitors and transmits the PC
I/O channel control and support signals. The control signals identify
transfers as read or write, memory or I/O, and 8-bit, 16-bit, or 32-bit
transfers. The PC-DIO-96PnP uses only 8-bit transfers.

Plug and Play Circuitry

The board’s Plug and Play circuitry automatically arbitrates and assigns
system resources. All bus-related configuration, such as setting the
board’s base address and interrupt level, is performed through software.

Interrupt Control Circuitry

The interrupt channel used by the PC-DIO-96PnP is selected by the
Plug and Play circuitry. Two software-controlled registers determine
which devices, if any, generate interrupts. Each of the four 82C55A
devices has two interrupt lines, PC3 and PC0, connected to the interrupt
circuitry.

PC-DIO-96/PnP User Manual 4-2 © National Instruments Corporation

Chapter 4 Theory of Operation

The 82C53 device has two of its three counter output signals connected
to the interrupt circuitry. Any of these 10 signals can interrupt the host
computer if the interrupt circuitry is enabled and the corresponding
enable bit is set (see Appendix D, Register-Level Programming, for
more information). Normally, PC3 and/or PC0 of the 82C55A devices
are controlled by the handshaking circuitry; however, either of these
two lines can be configured for input and used as external interrupts. An
interrupt occurs on the low-to-high transition of the signal line. Refer to
Appendix D, Register-Level Programming, Appendix B, OKI 82C55A
Data Sheet, or Appendix C, OKI 82C53 Data Sheet, for more detailed
information.

82C55A Programmable Peripheral Interface

The four 82C55A PPI chips are the heart of the PC-DIO-96PnP. Each
of these chips has 24 programmable I/O pins that represent three 8-bit
ports: PA, PB, and PC. Each port can be programmed as an input or an
output port. The 82C55A has three modes of operation: simple I/O
(mode 0), strobed I/O (mode 1), and bidirectional I/O (mode 2). In
modes 1 and 2, the three ports are divided into two groups: group A and
group B. Each group has eight data bits and four control and status bits
from port C (PC). Modes 1 and 2 use handshaking signals from port C
to synchronize data transfers. Refer to Appendix D, Register-Level
Programming, or to Appendix B, OKI 82C55A Data Sheet, for more
detailed information.

82C53 Programmable Interval Timer

The 82C53 Programmable Interval Timer generates timed interrupt
requests to the host computer. The 82C53 has three 16-bit counters,
which can each be used in one of six different modes. The
PC-DIO-96PnP uses two of the counters to generate interrupt requests;
the third counter is not used and is not accessible to the user. Refer to
Appendix D, Register-Level Programming, or to Appendix C, OKI
82C53 Data Sheet, for more detailed information.

© National Instruments Corporation 4-3 PC-DIO-96/PnP User Manual

Chapter 4 Theory of Operation

Digital I/O Connector

All digital I/O is transmitted through a standard, 100-pin, male
connector. Pins 49 and 99 are connected to +5 V through a protection
fuse (F1). See Figure 2-1 in Chapter 2, Installation and Configuration,
for its location. This +5 V supply is often required to operate I/O
module mounting racks. Pins 50 and 100 are connected to ground. See
the Optional Equipment section in Chapter 1, Introduction, as well as
Chapter 2, Installation and Configuration, and Chapter 3, Signal
Connections, for additional information.

PC-DIO-96/PnP User Manual 4-4 © National Instruments Corporation

Appendix

Specifications

This appendix lists the specifications of the PC-DIO-96/PnP. These
specifications are typical at 25° C, unless otherwise stated. The
operating temperature range is 0° to 70° C.

Digital I/O

Number of channels...........................96 I/O

Compatibility.....................................TTL

Absolute max voltage rating .............. -0.5 to +5.5 V with respect to

Handshaking......................................Requires 1 port

Power-on state ...................................Configured as inputs, high

Data transfers .....................................Interrupts, programmed I/O

Digital logic levels.............................

A

GND

(jumper selectable)

Level Min Max

Input low voltage

Input high voltage

Input low current

(Vin= 0.8 V)

Input high current

(Vin= 2.4 V)

Output low voltage

(I

= 2.5 mA)

out

Output high voltage

(I

= -2.5 mA)

out

Input current

(0 < Vin < 5 V)

-0.3 V

2.2 V
—

—

0 V

3.7 V

-1.0 µA 1.0 µA

0.8 V

5.3 V

-1.0 µA

1.0 µA

0.4 V

5.0 V

©

National Instruments Corporation A-1 PC-DIO-96/PnP User Manual

Appendix A Specifications

Note: The total combined current output from pins 49 and 99 may be limited by

Note: The upper limit on maximum transfer rates is constrained primarily by the

Output signals

Pin 49 (at +5 V) .......................... 0.5 A max

Pin 99 (at +5 V) .......................... 0.5 A max

the available current from your computer power supply. To determine the
available current, subtract the maximum power consumption of the board
from the maximum current per slot. The difference, if less than 1 A, is the
maximum combined current available to pins 49 and 99. If the difference
is equal to or greater than 1 A, the maximum current available is restricted
by the limitations of the connector, as shown previously. If your external
circuitry requires 0.5 to 1 A of current, connect pins 49 and 99 in parallel
to distribute the current.

Transfer rates .................................... Up to 780 kbytes/s

software and operating system rather than hardware interface for
non-DMA boards such as the PC-DIO-96/PnP. The maximum transfer rate
listed here was obtained using inline assembly C code on a 90 MHz
Pentium-based computer. Transfer rates will be significantly lower under
typical high-level software environments and will vary.

Power Requirement

+5 VDC (±10%)................................ 0.45 A typ, 1 A max

Physical

Dimensions ....................................... 16.5 by 9.9 cm (6.5 by 3.9 in.)

I/O connector .................................... 100-pin male, ribbon-cable

Environment

Operating temperature....................... 0° to 70° C

Storage temperature........................... -55° to 150° C

Relative humidity.............................. 5% to 90% noncondensing

PC-DIO-96/PnP User Manual A-2

©

National Instruments Corporation

Appendix

OKI 82C55A Data Sheet

This appendix contains the manufacturer data sheet for the
OKI 82C55A* (OKI Semiconductor) CMOS programmable peripheral
interface. This interface is used on the PC-DIO-96/PnP board.

B

* Copyright © OKI Semiconductor 1993. Reprinted with permission of copyright

owner. All rights reserved. OKI Semiconductor Data Book Microprocessor,
Seventh Edition, March 1993.

©

National Instruments Corporation B-1 PC-DIO-96/PnP User Manual

Appendix

OKI 82C53 Data Sheet

This appendix contains the manufacturer data sheet for the OKI 82C53*
integrated circuit (OKI Semiconductor). This circuit is used on the
PC-DIO-96/PnP board.

C

* Copyright © OKI Semiconductor 1995. Reprinted with permission of copyright

owner. All rights reserved. OKI Semiconductor Data Book Microprocessor, Eighth
Edition, January 1995.

©

National Instruments Corporation C-1 PC-DIO-96/PnP User Manual

Register-Level

Appendix

Programming

This appendix describes in detail the address and function of each of the
PC-DIO-96/PnP control and status registers. This appendix also
includes important information about register-level programming on
the PC-DIO-96/PnP along with program examples written in C and
assembly language.

Note: If you plan to use a programming software package such as

LabWindows/CVI or NI-DAQ with your PC-DIO-96/PnP board, you need
not read this appendix.

Introduction

Note: You can configure your PC-DIO-96/PnP board to use base addresses in the

range of 100 to 3E0 hex. Your PC-DIO-96/PnP board occupies 16 bytes of
address space and must be located on a 16-byte boundary. Therefore, valid
addresses include 100, 110, 120..., 3E0 hex. The base I/O address is
software configured and does not require you to manually change any
settings on the board. For more information on configuring the
PC-DIO-96PnP, see Chapter 2, Installation and Configuration.

D

The three 8-bit ports of the 82C55A are divided into two groups of 12
signals each: group A and group B. One 8-bit control word selects the
mode of operation for each group. The group A control bits configure
port A (A7 through A0) and the upper 4 bits (nibble) of port C (C7
through C4). The group B control bits configure port B (B7 through B0)
and the lower nibble of port C (C3 through C0). These configuration
bits are defined in the Register Description for the 82C55A section later
in this appendix. Because there are four 82C55A PPI devices on the
board, they are referenced as PPI A, PPI B, PPI C, and PPI D when
differentiation is required.

The three 16-bit counters of the 82C53 are accessed through individual
data ports and controlled by one 8-bit control word. The control word
selects how the counter data ports are accessed and what mode the

©

National Instruments Corporation D-1 PC-DIO-96/PnP User Manual

Appendix D Register-Level Programming

counter uses. The configuration bits are defined in the Register
Description for the 82C53 section later in this appendix.

In addition to the 82C55A devices and the 82C53 device, there are two
registers that select which onboard signals are capable of generating
interrupts. There are two interrupt signals from each of the four 82C55A
devices and two interrupt signals from the 82C53 device. Individual
enable bits select which of these 10 signals can generate interrupts.
Also, a master enable signal determines whether the board can actually
send a request to the host computer. The configuration bits for these
registers are defined in the Register Description for the Interrupt
Control Registers section later in this appendix.

Register Map

The following table lists the address map for the PC-DIO-96/PnP.

Table D-1. PC-DIO-96/PnP Address Map

Register Name Offset Address

Size Type

(Hex)

82C55A Register Group
PPI A
PORTA Register 00 8-bit Read-and-write
PORTB Register 01 8-bit Read-and-write
PORTC Register 02 8-bit Read-and-write
CNFG Register 03 8-bit Write-only
PPI B
PORTA Register 04 8-bit Read-and-write
PORTB Register 05 8-bit Read-and-write
PORTC Register 06 8-bit Read-and-write
CNFG Register 07 8-bit Write-only

PC-DIO-96/PnP User Manual D-2

©

National Instruments Corporation

Appendix D Register-Level Programming

Table D-1. PC-DIO-96/PnP Address Map (Continued)

Register Name Offset Address

Size Type

(Hex)

PPI C
PORTA Register 08 8-bit Read-and-write
PORTB Register 09 8-bit Read-and-write
PORTC Register 0A 8-bit Read-and-write
CNFG Register 0B 8-bit Write-only
PPI D
PORTA Register 0C 8-bit Read-and-write
PORTB Register 0D 8-bit Read-and-write
PORTC Register 0E 8-bit Read-and-write
CNFG Register 0F 8-bit Write-only
82C53 Register Group
PORTA Register 10 8-bit Read-and-write
PORTB Register 11 8-bit Read-and-write
PORTC Register 12 8-bit Read-and-write
CNFG Register 13 8-bit Write-only
Interrupt Control Register Group
Register 1 14 8-bit Write-only
Register 2 15 8-bit Write-only

©

National Instruments Corporation D-3 PC-DIO-96/PnP User Manual

Appendix D Register-Level Programming

Register Descriptions

The register descriptions for the devices on the PC-DIO-96/PnP,
including the 82C55A, the 82C53, and each of the interrupt control
registers, are given on the pages that follow.

Register Description for the 82C55A

Figure D-1 shows the two control word formats used to completely
program the 82C55A. The control word flag determines which control
word format is being programmed. When the control word flag is 1,
bits 6 through 0 select the I/O characteristics of the 82C55A ports.
These bits also select the mode in which the ports are operating (that is,
mode 0, mode 1, or mode 2). When the control word flag is 0, bits 3
through 0 select the bit set/reset format of port C.

PC-DIO-96/PnP User Manual D-4

©

National Instruments Corporation

Appendix D Register-Level Programming

Group A Group B

D2 D1 D0D5 D4 D3D7 D6

Control Word
Flag

1 = mode set
Mode Selection


00 = mode 0
01 = mode 1
1X = mode 2

Port A


1 = input
0 = output

Port C


(high nibble)
1 = input
0 = output



Control Word
Flag


0 = bit set/reset

Unused

a. Mode Set Word Format

D6 D5

D4

b. Bit Set/Reset Word Format



Port C

(low nibble)
1 = input
0 = output

Port B

1 = input

0 = output

Mode Selection



0 = mode 0

1 = mode 1

D2 D1 D0D3D7



Bit Set/Reset

1 = set
0 = reset

Bit Select

(000)
(001)
(010)
:
:
(111)

Figure D-1. Control Word Formats for the 82C55A

Warning: During programming, note that each time a port is configured, output

ports A and C are reset to 0, and output port B is undefined.

©

National Instruments Corporation D-5 PC-DIO-96/PnP User Manual

Appendix D Register-Level Programming

Table D-2 shows the control words for setting or resetting each bit in
port C. Notice that bit 7 of the control word is cleared when
programming the set/reset option for the bits of port C.

Table D-2. Port C Set/Reset Control Words

Bit Number Bit Set Control

0 0xxx0001 0xxx0000 xxxxxxxb
1 0xxx0011 0xxx0010 xxxxxxbx
2 0xxx0101 0xxx0100 xxxxxbxx
3 0xxx0111 0xxx0110 xxxxbxxx
4 0xxx1001 0xxx1000 xxxbxxxx
5 0xxx1011 0xxx1010 xxbxxxxx
6 0xxx1101 0xxx1100 xbxxxxxx
7 0xxx1111 0xxx1110 bxxxxxxx

Register Description for the 82C53

Figure D-2 shows the control word format used to completely program
the 82C53. Bits 7 and 6 of the control word select the counter to be
programmed. Bits 5 and 4 select the mode by which the count data is
written to and read from the selected counter. Bits 3, 2, and 1 select the
mode for the selected counter. Bit 0 selects whether the counter counts
in binary or BCD format.

Word

Bit Reset

Control Word

The Bit Set or

Reset in Port C

PC-DIO-96/PnP User Manual D-6

©

National Instruments Corporation

Appendix D Register-Level Programming

Counter Select
00 = counter 0
01 = counter 1
10 = counter 2
11 = illegal

Access Mode
00 = latch counter value
01 = access LSB only
10 = access MSB only
11 = access LSB, then MSB

D6 D5

D4

D2 D1 D0D3D7

Figure D-2. Control Word Format for the 82C53

Register Description for the Interrupt Control Registers

There are two interrupt control registers on the PC-DIO-96/PnP. One of
these registers has individual enable bits for the two interrupt lines from
each of the 82C55A devices. The other register has a master interrupt
enable bit and two bits for the timed interrupt circuitry. Of the latter two
bits, one bit enables counter interrupts, while the other selects counter 0
or counter 1. The bit maps and signal definitions are listed as follows.

BCD

1 = count in BCD
0 = count in binary

Mode Select
000 = mode 0
001 = mode 1
010 = mode 2
011 = mode 3
100 = mode 4
101 = mode 5
110 = mode 2
111 = mode 3

©

National Instruments Corporation D-7 PC-DIO-96/PnP User Manual

Appendix D Register-Level Programming

Interrupt Control Register 1

D7 D6 D5 D4 D3 D2 D1 D0

DIRQ1 DIRQ0 CIRQ1 CIRQ0 BIRQ1 BIRQ0 AIRQ1 AIRQ0

Bit Name Description

7 DIRQ1 PPI D Interrupt Request for Port B—If this bit and the

INTEN bit in Interrupt Control Register 2 are both set,
PPI D sends an interrupt, INTRB, to the host
computer. If this bit is cleared, PPI D does not send
the interrupt INTRB to the host computer, regardless
of the setting of INTEN.

6 DIRQ0 PPI D Interrupt Request for Port A—If this bit and the

INTEN bit in Interrupt Control Register 2 are both set,
PPI D sends an interrupt, INTRA, to the host
computer. If this bit is cleared, PPI D does not send
the interrupt INTRA to the host computer, regardless
of the setting of INTEN.

5 CIRQ1 PPI C Interrupt Request for Port B—If this bit and the

INTEN bit in Interrupt Control Register 2 are both set,
PPI C sends an interrupt, INTRB, to the host
computer. If this bit is cleared, PPI C does not send the
interrupt INTRB to the host computer, regardless of
the setting of INTEN.

4 CIRQ0 PPI C Interrupt Request for Port A—If this bit and the

INTEN bit in Interrupt Control Register 2 are both set,
PPI C sends an interrupt, INTRA, to the host
computer. If this bit is cleared, PPI C does not send the
interrupt INTRA to the host computer, regardless of
the setting of INTEN.

3 BIRQ1 PPI B Interrupt Request for Port B—If this bit and the

INTEN bit in Interrupt Control Register 2 are both set,
PPI B sends an interrupt, INTRB, to the host
computer. If this bit is cleared, PPI B does not send the
interrupt INTRB to the host computer, regardless of
the setting of INTEN.

PC-DIO-96/PnP User Manual D-8

©

National Instruments Corporation

Appendix D Register-Level Programming

Bit Name Description (Continued)

2 BIRQ0 PPI B Interrupt Request for Port A—If this bit and the

INTEN bit in Interrupt Control Register 2 are both set,
PPI B sends an interrupt, INTRA, to the host
computer. If this bit is cleared, PPI B does not send the
interrupt INTRA to the host computer, regardless of
the setting of INTEN.

1 AIRQ1 PPI A Interrupt Request for Port B—If this bit and the

INTEN bit in Interrupt Control Register 2 are both set,
PPI A sends an interrupt, INTRB, to the host
computer. If this bit is cleared, PPI A does not send
the interrupt INTRB to the host computer, regardless
of the setting of INTEN.

0 AIRQ0 PPI A Interrupt Request for Port A—If this bit and the

INTEN bit in Interrupt Control Register 2 are both set,
PPI A sends an interrupt, INTRA, to the host
computer. If this bit is cleared, PPI A does not send
the interrupt INTRA to the host computer, regardless
of the setting of INTEN.

©

National Instruments Corporation D-9 PC-DIO-96/PnP User Manual

Appendix D Register-Level Programming

Interrupt Control Register 2

D7 D6 D5 D4 D3 D2 D1 D0

X X X X X INTEN CTRIRQ CTR1

Bit Name Description

7–3 X Don’t Care Bit.
2 INTEN Global Interrupt Enable Bit—If this bit is set, the

PC-DIO-96/PnP can interrupt the host computer. If
this bit is cleared, the PnP version of this board cannot
interrupt the host computer. With the non-PnP
version, the interrupt line is put into high-impedance
mode, so other devices can use the interrupt channel
selected by jumper W1.

1 CTRIRQ Counter Interrupt Enable Bit—If this bit is set, the

82C53 counter outputs can interrupt the host
computer. If this bit is cleared, the counter outputs
have no effect.

0 CTR1 Counter 1 Enable Bit—If this bit is set, the output

from counter 1 of the 82C53 is connected to the
interrupt request circuitry. In this mode, counter 0 of
the 82C53 acts as a frequency scaler for counter 1,
which generates the interrupt. If CTR1 is cleared, the
output from counter 0 of the 82C53 is connected to the
interrupt request circuitry. In this mode, counter 0
generates the interrupt. For more information, see the
section later in this chapter on programming interrupts
using the 82C53.

PC-DIO-96/PnP User Manual D-10

©

National Instruments Corporation

Appendix D Register-Level Programming

Programming Considerations for the 82C55A

Modes of Operation for the 82C55A

The three basic modes of operation for the 82C55A are as follows:

• Mode 0—Basic I/O

• Mode 1—Strobed I/O

• Mode 2—Bidirectional bus
The 82C55A also has a single bit set/reset feature for port C, which is

programmed by the 8-bit control word. For additional information, refer
to Appendix B, OKI 82C55A Data Sheet.

Mode 0

This mode can be used for simple input and output operations for each
of the ports. No handshaking is required; data is simply written to or
read from a specified port.

Mode 0 has the following features:

• Two 8-bit ports (A and B) and two 4-bit ports (upper and lower
nibbles of port C).

• Any port can be input or output.

• Outputs are latched, but inputs are not latched.

Mode 1

This mode transfers data that is synchronized by handshaking signals.
Ports A and B use the eight lines of port C to generate or receive the
handshake signals. This mode divides the ports into two groups
(group A and group B) and includes the following features:

• Each group contains one 8-bit data port (port A or port B) and one
4-bit control/data port (upper or lower nibble of port C).

• The 8-bit data ports can be either input or output, both of which are
latched.

• The 4-bit ports are used for control and status of the 8-bit data ports.

• Interrupt generation and enable/disable functions are available.

©

National Instruments Corporation D-11 PC-DIO-96/PnP User Manual

Appendix D Register-Level Programming

Mode 2

This mode can be used for communication over a bidirectional 8-bit
bus. Handshaking signals are used in a manner similar to mode 1.
Mode 2 is available for use in group A only (port A and the upper nibble
of port C). Other features of this mode include the following:

• One 8-bit bidirectional port (port A) and a 5-bit control/status port
(port C).

• Latched inputs and outputs.

• Interrupt generation and enable/disable functions.

Single Bit Set/Reset Feature

Any of the eight bits of port C can be set or reset with one control word.
This feature generates control signals for port A and port B when these
ports are operating in mode 1 or mode 2.

Mode 0—Basic I/O

Mode 0 can be used for simple I/O functions (no handshaking) for each
of the three ports. Each port can be assigned as an input or an output
port. The 16 possible I/O configurations are shown in Table D-3. Notice
that bit 7 of the control word is set when programming the mode of
operation for each port.

Table D-3. Mode 0 I/O Configurations

Control Word Group A Group B

Number Bit

Port A Port C

1

Port B Port C

76543210

0 10000000 Output Output Output Output
1 10000001 Output Output Output Input
2 10000010 Output Output Input Output
3 10000011 Output Output Input Input
4 10001000 Output Input Output Output
5 10001001 Output Input Output Input
6 10001010 Output Input Input Output
7 10001011 Output Input Input Input
8 10010000 Input Output Output Output

PC-DIO-96/PnP User Manual D-12

©

National Instruments Corporation

2

Appendix D Register-Level Programming

Table D-3. Mode 0 I/O Configurations (Continued)

Control Word Group A Group B

Number Bit

Port A Port C

1

Port B Port C

2

76543210

9 10010001 Input Output Output Input
10 10010010 Input Output Input Output
11 10010011 Input Output Input Input
12 10011000 Input Input Output Output
13 10011001 Input Input Output Input
14 10011010 Input Input Input Output
15 10011011 Input Input Input Input

1

Upper nibble of port C

2

Lower nibble of port C

Mode 0 Programming Example

The following example shows how to configure PPI A for various
combinations of mode 0 input and output. This code is strictly an
example and is not intended to be used without modification in a
practical situation.

Main() {
#define BASE_ADDRESS 0x180 /* Board located at address 180 */

#define APORTAoffset 0x00 /* Offset for PPI A, port A */
#define APORTBoffset 0x01 /* Offset for PPI A, port B */
#define APORTCoffset 0x02 /* Offset for PPI A, port C */
#define ACNFGoffset 0x03 /* Offset for PPI A, CNFG */

unsigned int porta, portb, portc, cnfg;
char valread; /* Variable to store data read from a port */

/* Calculate register addresses */
porta = BASE_ADDRESS + APORTAoffset;
portb = BASE_ADDRESS + APORTBoffset;
portc = BASE_ADDRESS + APORTCoffset;
cnfg = BASE_ADDRESS + ACNFGoffset;

©

National Instruments Corporation D-13 PC-DIO-96/PnP User Manual

Appendix D Register-Level Programming

/* EXAMPLE 1*/
outp(cnfg,0x80); /* Ports A, B, and C are outputs. */

outp(porta,0x12); /* Write data to port A. */
outp(portb,0x34); /* Write data to port B. */
outp(portc,0x56); /* Write data to port C. */

/* EXAMPLE 2*/
outp(cnfg,0x90); /* Port A is input; ports B and C are outputs. */

outp(portb,0x22); /* Write data to port B. */
outp(portc,0x55); /* Write data to port C. */
valread = inp(porta); /* Read data from port A. */

/* EXAMPLE 3 */
outp(cnfg,0x82); /* Ports A and C are outputs;

port B is an input. */
/* EXAMPLE 4 */
outp(cnfg,0x89); /* Ports A and B are outputs;

port C is an input. */
}

Mode 1—Strobed Input

In mode 1, the digital I/O bits are divided into two groups: group A and
group B. Each of these groups contains one 8-bit port and one 4-bit
control/data port. The 8-bit port can be either an input or an output port,
and the 4-bit port is used for control and status information for the 8-bit
port. The transfer of data is synchronized by handshaking signals in the
4-bit port.

The control word written to the CNFG Register to configure port A for
input in mode 1 is shown as follows. Bits PC6 and PC7 of port C can be
used as extra input or output lines.

PC-DIO-96/PnP User Manual D-14

©

National Instruments Corporation

Appendix D Register-Level Programming

1

D6 D5

0

D4

1/0

D2 D1 D0D3D7

X

Port C bits PC6 and PC7

1 = input
0 = output

X11

X

The control word written to the CNFG Register to configure port B for
input in mode 1 is shown as follows. Notice that port B does not have
extra input or output lines from port C.

1

D6 D5

X

X

D4

X11X

D2 D1 D0D3D7

X

During a mode 1 data read transfer, the status of the handshaking lines
and interrupt signals can be obtained by reading port C. The port C
status-word bit definitions for an input transfer are shown as follows.

Port C status-word bit definitions for input (port A and port B):

D7 D6 D5 D4 D3 D2 D1 D0

I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB

Bit Name Description

7–6 I/O Input/Output—These bits can be used for general-

purpose I/O when port A is in mode 1 input. If these
bits are configured for output, the port C bit set/reset
function must be used to manipulate them.

5 IBFA Input Buffer for Port A—A high setting indicates that

data has been loaded into the input latch for port A.

4 INTEA Interrupt Enable Bit for Port A—Setting this bit

enables interrupts from port A of the 82C55A. This bit
is controlled by setting/resetting PC4.

3 INTRA Interrupt Request Status for Port A—When INTEA

and IBFA are high, this bit is high, indicating that an
interrupt request is pending for port A.

©

National Instruments Corporation D-15 PC-DIO-96/PnP User Manual

Appendix D Register-Level Programming

Bit Name Description (Continued)

2 INTEB Interrupt Enable Bit for Port B—Setting this bit

1 IBFB Input Buffer for Port B—A high setting indicates that

0 INTRB Interrupt Request Status for Port B—When INTEB

At the digital I/O connector, port C has the following pin assignments
when in mode 1 input. Notice that the status of STBA* and the status of
STBB* are not included in the port C status word.

enables interrupts from port B of the 82C55A. This bit
is controlled by setting/resetting PC2.

data has been loaded into the input latch for port B.

and IBFB are high, this bit is high, indicating that an
interrupt request is pending for port B.

PC7
PC6

Group A

Group B

Figure D-3. Port C Pin Assignments, Mode 1 Input

PC5
PC4
PC3
PC2
PC1
PC0

I/O
I/O

IBFA
STBA*
INTRA
STBB*

IBFB

INTRB

Mode 1 Input Programming Example

The following example shows how to configure PPI A for various
combinations of mode 1 input. This code is strictly an example and is
not intended to be used without modification in a practical situation.

Main() {
#define BASE_ADDRESS 0x180 /* Board located at address 180 */

#define APORTAoffset 0x00 /* Offset for PPI A, port A */
#define APORTBoffset 0x01 /* Offset for PPI A, port B */
#define APORTCoffset 0x02 /* Offset for PPI A, port C */
#define ACNFGoffset 0x03 /* Offset for PPI A, CNFG */

PC-DIO-96/PnP User Manual D-16

©

National Instruments Corporation

Appendix D Register-Level Programming

unsigned int porta, portb, portc, cnfg;
char valread; /* Variable to store data read from a port */

/* Calculate register addresses */
porta = BASE_ADDRESS + APORTAoffset;

portb = BASE_ADDRESS + APORTBoffset;
portc = BASE_ADDRESS + APORTCoffset;
cnfg = BASE_ADDRESS + ACNFGoffset;

/* EXAMPLE 1–port A input */
outp(cnfg,0xB0); /* Port A is an input in mode 1. */

while (!(inp(portc) & 0x20)); /* Wait until IBFA is set,

indicating that data has been
loaded in port A. */

valread = inp(porta); /* Read the data from port A. */
/* EXAMPLE 2–Port B input */
outp(cnfg,0x86); /* Port B is an input in mode 1. */

while (!(inp(portc) & 0x02)); /* Wait until IBFB is set,

indicating that data has been
loaded in port B. */

valread = inp(portb);
}

Mode 1—Strobed Output

The control word written to the CNFG Register to configure port A for
output in mode 1 is shown as follows. Bits PC4 and PC5 of port C can
be used as extra input or output lines.

1

D6 D5

0

D4

The control word written to the CNFG Register to configure port B for
output in mode 1 is shown as follows. Notice that port B does not have
extra input or output lines from port C.

©

National Instruments Corporation D-17 PC-DIO-96/PnP User Manual

1/0

D2 D1 D0D3D7

X

Port C bits PC4 and PC5

1 = input
0 = output

X10

X

Appendix D Register-Level Programming

1

D6 D5
X

X

D4

X10X

D2 D1 D0D3D7

X

During a mode 1 data write transfer, the status of the handshaking lines
and interrupt signals can be obtained by reading port C. Notice that the
bit definitions are different for a write and a read transfer.

Port C status-word bit definitions for output (port A and port B):

D7 D6 D5 D4 D3 D2 D1 D0

OBFA* INTEA I/O I/O INTRA INTEB OBFB* INTRB

Bit Name Description

7 OBFA* Output Buffer for Port A—A low setting indicates that

the CPU has written data to port A.

6 INTEA Interrupt Enable Bit for Port A—Setting this bit

enables interrupts from port A of the 82C55A. This bit
is controlled by setting/resetting PC6.

5–4 I/O Input/Output—These bits can be used for general-

purpose I/O when port A is in mode 1 output. If these
bits are configured for output, the port C bit set/reset
function must be used to manipulate them.

3 INTRA Interrupt Request Status for Port A—When INTEA

and OBFA* are high, this bit is high, indicating that an
interrupt request is pending for port A.

2 INTEB Interrupt Enable Bit for Port B—Setting this bit

enables interrupts from port B of the 82C55A. This bit
is controlled by setting/resetting PC2.

1 OBFB* Output Buffer for Port B—A low setting indicates that

the CPU has written data to port B.

0 INTRB Interrupt Request Status for Port B—When INTEB

and OBFB* are high, this bit is high, indicating that an
interrupt request is pending for port B.

PC-DIO-96/PnP User Manual D-18

©

National Instruments Corporation

Appendix D Register-Level Programming

At the digital I/O connector, port C has the following pin assignments
when in mode 1 output. Notice that the status of ACKA* and the status
of ACKB* are not included when port C is read.

Group A

Group B

PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0

OBFA*

ACKA*

I/O

I/O
INTRA
ACKB*
OBFB*
INTRB

Figure D-4. Port C Pin Assignments, Mode 1 Output

Mode 1 Output Programming Example

The following example shows how to configure PPI A for various
combinations of mode 1 output. This code is strictly an example and is
not intended to be used without modification in a practical situation.

Main() {
#define BASE_ADDRESS 0x180 /* Board located at address 180 */

#define APORTAoffset 0x00 /* Offset for PPI A, port A */
#define APORTBoffset 0x01 /* Offset for PPI A, port B */
#define APORTCoffset 0x02 /* Offset for PPI A, port C */
#define ACNFGoffset 0x03 /* Offset for PPI A, CNFG */

unsigned int porta, portb, portc, cnfg;
char valread; /* Variable to store data read from a port */

/* Calculate register addresses */
porta = BASE_ADDRESS + APORTAoffset;

portb = BASE_ADDRESS + APORTBoffset;
portc = BASE_ADDRESS + APORTCoffset;
cnfg = BASE_ADDRESS + ACNFGoffset;

©

National Instruments Corporation D-19 PC-DIO-96/PnP User Manual

Appendix D Register-Level Programming

/* EXAMPLE 1–port A output */
outp(cnfg,0xA0); /* Port A is an output in mode 1.*/

while (!(inp(portc) & 0x80)); /* Wait until OBFA* is set,

indicating that the data last
written to port A has been
read.*/

outp(porta,0x12); /* Write data to port A. */
/* EXAMPLE 2–port B output */
outp(cnfg,0x84); /* Port B is an output in mode 1.*/

while (!(inp(portc) & 0x02)); /* Wait until OBFB* is set,

indicating that the data last
written to port B has been

read.*/
outp(portb,0x34); /* Write the data to port B. */
}

PC-DIO-96/PnP User Manual D-20

©

National Instruments Corporation

Mode 2—Bidirectional Bus

Mode 2 has an 8-bit bus that can transfer both input and output data
without changing the configuration. The data transfers are synchronized
with handshaking lines in port C. This mode uses only port A; however,
port B can be used in either mode 0 or mode 1 while port A is configured
for mode 2.

The control word written to the CNFG Register to configure port A as
a bidirectional data bus in mode 2 is shown as follows. If port B is
configured for mode 0, then PC2, PC1, and PC0 of port C can be used
as extra input or output lines.

Appendix D Register-Level Programming

1

D6 D5

X

D4

X

D2 D1 D0D3D7

X1

1/0

1/0

1/0

Port C
(PC2-PC0)

1 = input
0 = output

Port B

1 = input
0 = output

Group B Mode

0 = mode 0
1 = mode 1

Figure D-5. Port A Configured as a Bidirectional Data Bus in Mode 2

During a mode 2 data transfer, the status of the handshaking lines and
interrupt signals can be obtained by reading port C. The port C status­word bit definitions for a mode 2 transfer are shown as follows.

©

National Instruments Corporation D-21 PC-DIO-96/PnP User Manual

Appendix D Register-Level Programming

Port C status-word bit definitions for bidirectional data path (port A
only):

D7 D6 D5 D4 D3 D2 D1 D0

OBFA* INTE1 IBFA INTE2 INTRA I/O I/O I/O

Bit Name Description

7 OBFA* Output Buffer for Port A—A low setting indicates that

the CPU has written data to port A.

6 INTE1 Interrupt Enable Bit for Port A Output Interrupts—

Setting this bit enables output interrupts from port A
of the 82C55A. This bit is controlled by
setting/resetting PC6.

5 IBFA Input Buffer for Port A—A high setting indicates that

data has been loaded into the input latch of port A.

4 INTE2 Interrupt Enable Bit for Port A Input Interrupts—

Setting this bit enables input interrupts from port A of
the 82C55A. This bit is controlled by setting/resetting
PC4.

3 INTRA Interrupt Request Status for Port A—If INTE1 and

IBFA are high, then this bit is high, indicating that an
interrupt request is pending for port A input transfers.
If INTE2 and OBFA* are high, then this bit is high,
indicating that an interrupt request is pending for
port A output transfers.

2–0 I/O Input/Output—These bits can be used for general-

purpose I/O lines if group B is configured for mode 0.
If group B is configured for mode 1, refer to the bit
explanations shown in the preceding mode 1 sections.

PC-DIO-96/PnP User Manual D-22

©

National Instruments Corporation

Appendix D Register-Level Programming

At the digital I/O connector, port C has the following pin assignments
when in mode 2. Notice that the status of STBA* and the status of
ACKA* are not included in the port C status word.

Group A

Group B

PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0

OBFA*

ACKA*

IBFA

STBA*

INTRA

#
#
#

# The three port C lines associated with group B function are based on the

mode selected for group B; that is, if group B is configured for mode 0,
PC2-PC0 function as general-purpose input/output, but if group B is
configured for mode 1 input or output, PC2-PC0 function as handshaking
lines as shown in the preceding mode 1 sections.

Figure D-6. Port C Pin Assignments, Mode 2

Mode 2 Programming Example

The following example shows how to configure PPI A for mode 2 input
and output and how to use the handshaking signals to control data flow.
This code is strictly an example and is not intended to be used without
modification in a practical situation.

Main() {
#define BASE_ADDRESS 0x180 /* Board located at address 180 */

#define APORTAoffset 0x00 /* Offset for PPI A, port A */
#define APORTBoffset 0x01 /* Offset for PPI A, port B */
#define APORTCoffset 0x02 /* Offset for PPI A, port C */
#define ACNFGoffset 0x03 /* Offset for PPI A, CNFG */

unsigned int porta, portb, portc, cnfg;
char valread; /* Variable to store data read from a port */

©

National Instruments Corporation D-23 PC-DIO-96/PnP User Manual

Appendix D Register-Level Programming

/* Calculate register addresses */
porta = BASE_ADDRESS + APORTAoffset;

portb = BASE_ADDRESS + APORTBoffset;
portc = BASE_ADDRESS + APORTCoffset;
cnfg = BASE_ADDRESS + ACNFGoffset;

/* EXAMPLE 1*/
outp(cnfg,0xC0); /* Port A is in mode 2. */

while (!(inp(portc) & 0x80)); /* Wait until OBFA* is set,

indicating that the data last

written to port A has been read.

*/
outp(porta,0x67); /* Write the data to port A. */
while (!(inp(portc) & 0x20)); /* Wait until IBFA is set,

indicating that data is

available in port A to be read.

*/
valread = inp(porta); /* Read data from port A. */
}

Interrupt Programming Examples for the 82C55A

The following examples show the process required to enable interrupts
for several different operating modes. The interrupt handling routines
and interrupt installation routines for the 82C55A are not included;
however, sample routines for the 82C53 are included later in the
appendix. These routines can be modified to function for the 82C55A.
Consult your computer’s technical reference manual for additional
information. Also, if you generate interrupts with the PC3 or PC0 lines
of the 82C55A devices, you must maintain the active high level until the
interrupt service routine is entered. Otherwise, the host computer
considers the interrupt a spurious interrupt and routes the request to the
channel responsible for handling spurious interrupts. To prevent this
problem, try using some other I/O bit to send feedback to the device
generating the interrupt. In this way, the interrupting device can be
signaled that the interrupt service routine has been entered. For further
information on using PC3 and PC0 for interrupts, see the Interrupt
Handling section later in this appendix.

Main() {
#define BASE_ADDRESS 0x180 /* Board located at address 180 */

#define APORTAoffset 0x00 /* Offset for PPI A, port A */
#define APORTBoffset 0x01 /* Offset for PPI A, port B */
#define APORTCoffset 0x02 /* Offset for PPI A, port C */

PC-DIO-96/PnP User Manual D-24

©

National Instruments Corporation

Appendix D Register-Level Programming

#define ACNFGoffset 0x03 /* Offset for PPI A, CNFG */
#define IREG1offset 0x14 /* Offset for Interrupt Reg. 1 */
#define IREG2offset 0x15 /* Offset for Interrupt Reg. 2 */

unsigned int porta, portb, portc, cnfg, ireg1, ireg2;
char valread; /* Variable to store data read from a port */

/* Calculate register addresses */
porta = BASE_ADDRESS + APORTAoffset;

portb = BASE_ADDRESS + APORTBoffset;
portc = BASE_ADDRESS + APORTCoffset;
cnfg = BASE_ADDRESS + ACNFGoffset;
ireg1 = BASE_ADDRESS + IREG1offset;
ireg2 = BASE_ADDRESS + IREG2offset;

/* EXAMPLE 1–Set up interrupts for mode 1 input for port A. Enable the

appropriate interrupt bits. */

outp(cnfg,0xB0); /* Port A is an input in mode 1. */
outp(cnfg,0x09); /* Set PC4 to enable interrupts from 82C55A. */
outp(ireg1,0x01); /* Set AIRQ0 to enable PPI A, port A interrupts. */
outp(ireg2,0x04); /* Set INTEN bit. */

/* EXAMPLE 2–Set up interrupts for mode 1 input for port B. Enable the

appropriate interrupt bits. */

outp(cnfg,0x86); /* Port B is an input in mode 1. */
outp(cnfg,0x05); /* Set PC2 to enable interrupts from 82C55A. */
outp(ireg1,0x02); /* Set AIRQ1 to enable PPI A, port B interrupts. */
outp(ireg2,0x04); /* Set INTEN bit. */

/* EXAMPLE 3–Set up interrupts for mode 1 output for port A. Enable the

appropriate interrupt bits. */

outp(cnfg,0xA0); /* Port A is an output in mode 1. */
outp(cnfg,0x0D); /* Set PC6 to enable interrupts from 82C55A. */
outp(ireg1,0x01); /* Set AIRQ0 to enable PPI A, port A interrupts. */
outp(ireg2,0x04); /* Set INTEN bit. */

/* EXAMPLE 4–Set up interrupts for mode 1 output for port B. Enable the

appropriate interrupt bits. */

outp(cnfg,0x84); /* Port B is an output in mode 1. */
outp(cnfg,0x05); /* Set PC2 to enable interrupts from 82C55A. */
outp(ireg1,0x02); /* Set AIRQ1 to enable PPI A, port B interrupts. */
outp(ireg2,0x04); /* Set INTEN bit. */

©

National Instruments Corporation D-25 PC-DIO-96/PnP User Manual

Appendix D Register-Level Programming

/* EXAMPLE 5–Set up interrupts for mode 2 output transfers. Enable the

appropriate interrupt bits. */

outp(cnfg,0xC0); /* Mode 2 output. */
outp(cnfg,0x0D); /* Set PC6 to enable interrupts from 82C55A. */
outp(ireg1,0x01); /* Set AIRQ0 to enable PPI A, port A interrupts. */
outp(ireg2,0x04); /* Set INTEN bit. */

/* EXAMPLE 6–Set up interrupts for mode 2 input transfers. Enable the

appropriate interrupt bits. */

outp(cnfg,0xD0); /* Mode 2 input. */
outp(cnfg,0x09); /* Set PC4 to enable interrupts from 82C55A. */
outp(ireg1,0x01); /* Set AIRQ0 to enable PPI A, port A interrupts. */
outp(ireg2,0x04); /* Set INTEN bit. */
}

Programming Considerations for the 82C53

A general overview of the 82C53 and how it is configured on the
PC-DIO-96/PnP are presented as follows. This section also includes an
in-depth example of handling interrupts generated by the 82C53.

General Information

The 82C53 contains three counter/timers, each of which can operate in
one of six different modes. As the PC-DIO-96/PnP is designed,
however, only counter 0 and counter 1 are configured for operation;
counter 2 is not connected, nor is it available on the external I/O
connector. In addition, counter 0 and counter 1 are wired to the interrupt
circuitry in such a way that only four of the modes are available for use.

The source for counter 0 is a 2 MHz clock. If counter 0 is used for
interrupting the host computer, configure the counter for rate
generation, or mode 2. If counter 1 is used for interrupting the host
computer, counter 0 is used as a frequency scaler which feeds the source
input for counter 1. In this case, configure both counters for rate
generation, or mode 2. To determine the time between pulses generated
by counter 0, multiply the load value by 500 ns (1/(2 MHz)). To
determine the time between pulses generated by counter 1, multiply the
load value by the time between pulses of counter 0. A sample
configuration procedure is presented in the next section.

PC-DIO-96/PnP User Manual D-26

©

National Instruments Corporation

Appendix D Register-Level Programming

Interrupt Programming Example for the 82C53

An in-depth example of handling interrupts generated by the 82C53 is
presented as follows. The main program is presented in C, while sample
interrupt routines are presented in assembly language.

Main() {
#define BASE_ADDRESS 0x180 /* Board located at address 180 */

#define CTR0offset 0x10 /* Offset for counter 0 */
#define CTR1offset 0x11 /* Offset for counter 1 */
#define CTRCNFGoffset 0x13 /* Offset for 82C53 CNFG */
#define IREG1offset 0x14 /* Offset for Interrupt Reg. 1 */
#define IREG2offset 0x15 /* Offset for Interrupt Reg. 2 */

#define channel 5 /* Interrupt channel selected */
#define use_ctr1 0 /* 0 for ctr0, 1 for ctr1 */

#define ctr0_data 10000 /* Pulse every 5 msec */
#define ctr1_data 1000 /* Pulse every 5 sec */

unsigned int ctr0, ctr1, cnfg, ireg1, ireg2;
/* Calculate register addresses */
ctr0 = BASE_ADDRESS + CTR0offset;

ctr1 = BASE_ADDRESS + CTR1offset;
cnfg = BASE_ADDRESS + CTRCNFGoffset;
ireg1 = BASE_ADDRESS + IREG1offset;
ireg2 = BASE_ADDRESS + IREG2offset;

/* Disable interrupts */
outp(ireg1,0x00); /* Disable all 82C55A interrupts */

outp(ireg2,0x00); /* Disable counter interrupts */
/* Set up the counter modes--do not write out the counter load values at this

time, as this starts the counter. */

outp(cnfg,0x34); /* Set counter 0 to mode 2 */
if (use_ctr1) {
outp(cnfg,0x74); /* Set counter 1 to mode 2 */
outp(ireg2,0x07); /* Enable interrupts, enable counter interrupts,

and select counter 1's output */
}
else outp(ireg2, 0x06); /* Enable interrupts, enable counter interrupts,

and select counter 0's output */
/* At this point, you should install your interrupt service routine using the

interrupt channel selected. */

/* install_isr(channel,...); */

©

National Instruments Corporation D-27 PC-DIO-96/PnP User Manual