The PC-DIO-24 is warranted against defects in materials and workmanship for a period of one year from the date of
shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace
equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
The media on which you receive National Instruments software are warranted not to fail to execute programming
instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as
evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace software
media that do not execute programming instructions if National Instruments receives notice of such defects during
the warranty period. National Instruments does not warrant that the operation of the software shall be uninterrupted
or error free.
A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the
outside of the package before any equipment will be accepted for warranty work. National Instruments will pay the
shipping costs of returning to the owner parts which are covered by warranty.
National Instruments believes that the information in this manual is accurate. The document has been carefully
reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments
reserves the right to make changes to subsequent editions of this document without prior notice to holders of this
edition. The reader should consult National Instruments if errors are suspected. In no event shall National
Instruments be liable for any damages arising out of or related to this document or the information contained in it.
EXCEPT AS SPECIFIED HEREIN, NATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR
IMPLIED, AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS
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owner's failure to follow the National Instruments installation, operation, or maintenance instructions; owner's
modification of the product; owner's abuse, misuse, or negligent acts; and power failure or surges, fire, flood,
accident, actions of third parties, or other events outside reasonable control.
Copyright
Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or
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Product and company names listed are trademarks or trade names of their respective companies.
WARNING REGARDING MEDICAL AND CLINICAL USE
OF NATIONAL INSTRUMENTS PRODUCTS
National Instruments products are not designed with components and testing intended to ensure a level of reliability
suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving
medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the
part of the user or application designer. Any use or application of National Instruments products for or involving
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National Instruments products are NOT intended to be a substitute for any form of established process, procedure, or
equipment used to monitor or safeguard human health and safety in medical or clinical treatment.
FCC/DOC Radio Frequency Interference Compliance
This equipment generates and uses radio frequency energy and, if not installed and used in strict accordance with the
instructions in this manual, may cause interference to radio and television reception. This equipment has been tested
and found to comply with the following two regulatory agencies:
Federal Communications Commission
This device complies with Part 15 of the Federal Communications Commission (FCC) Rules for a Class A digital
device. Operation is subject to the following two conditions:
1.This device may not cause harmful interference in commercial environments.
2.This device must accept any interference received, including interference that may cause undesired operation.
Canadian Department of Communications
This device complies with the limits for radio noise emissions from digital apparatus set out in the Radio
Interference Regulations of the Canadian Department of Communications (DOC).
Le présent appareil numérique n’émet pas de bruits radioélectriques dépassant les limites applicables aux appareils
numériques de classe A prescrites dans le règlement sur le brouillage radioélectrique édicté par le ministère des
communications du Canada.
Instructions to Users
These regulations are designed to provide reasonable protection against harmful interference from the equipment to
radio reception in commercial areas. Operation of this equipment in a residential area is likely to cause harmful
interference, in which case the user will be required to correct the interference at his own expense.
There is no guarantee that interference will not occur in a particular installation. However, the chances of
interference are much less if the equipment is installed and used according to this instruction manual.
If the equipment does cause interference to radio or television reception, which can be determined by turning the
equipment on and off, one or more of the following suggestions may reduce or eliminate the problem.
•Operate the equipment and the receiver on different branches of your AC electrical system.
•Move the equipment away from the receiver with which it is interfering.
•Reorient or relocate the receiver’s antenna.
•Be sure that the equipment is plugged into a grounded outlet and that the grounding has not been defeated with a
cheater plug.
Notice to user: Changes or modifications not expressly approved by National Instruments could void the user’s
authority to operate the equipment under the FCC Rules.
If necessary, consult National Instruments or an experienced radio/television technician for additional suggestions.
The following booklet prepared by the FCC may also be helpful: How to Identify and Resolve Radio-TVInterference Problems. This booklet is available from the U.S. Government Printing Office, Washington, DC
20402, Stock Number 004-000-00345-4.
Contents
About This Manual............................................................................................................. xi
Organization of This Manual ......................................................................................... xi
Conventions Used in This Manual................................................................................. xii
National Instruments Documentation ............................................................................ xii
Related Documentation.................................................................................................. xiii
Customer Communication ............................................................................................. xiii
Chapter 1
Introduction
About the PC-DIO-24 .................................................................................................... 1-1
What You Need to Get Started ...................................................................................... 1-2
This manual describes the mechanical and electrical aspects of the PC-DIO-24 and contains
information concerning its operation and programming. The PC-DIO-24 is a 24-bit parallel,
digital I/O interface designed around an 82C55A programmable peripheral interface (PPI). The
PC-DIO-24 is a member of the National Instruments PC Series of PC I/O Channel expansion
boards for the IBM PC computer family. These boards are designed for low-cost data acquisition
and control for applications in laboratory testing, production testing, and industrial process
monitoring and control.
This manual describes installation, basic programming considerations, and theory of operation
for the PC-DIO-24. The example programs included are written in C.
Organization of This Manual
The PC-DIO-24 User Manual is organized as follows:
•Chapter 1, Introduction, describes the PC-DIO-24, lists what you need to get started,
describes software programming choices, optional equipment, and custom cables, and
explains how to unpack the PC-DIO-24.
•Chapter 2, Configuration and Installation, describes how to configure and install the
PC-DIO-24, including I/O connector signal descriptions, handshake timing diagrams, and
cabling instructions.
•Chapter 3, Theory of Operation, contains a functional overview of the PC-DIO-24 board and
explains the operation of each functional unit making up the PC-DIO-24.
•Chapter 4, Register-Level Programming, describes in detail the address and function of each
of the PC-DIO-24 control and status registers. This chapter also includes important
information related to register-level programming the PC-DIO-24.
•Appendix A, Specifications, lists the specifications for the PC-DIO-24 board.
•Appendix B, I/O Connector, describes the pinout and signal names for the I/O connector on
the PC-DIO-24.
•Appendix C, OKI 82C55A Data Sheet, contains the manufacturer data sheet for the
OKI 82C55A (OKI Semiconductor) CMOS programmable peripheral interface. This
interface is used on the PC-DIO-24 board.
•Appendix D, Customer Communication, contains forms you can use to request help from
National Instruments or to comment on our products.
•The Glossary contains an alphabetical list and description of terms used in this manual,
including abbreviations, acronyms, metric prefixes, mnemonics, symbols, and terms.
•The Index alphabetically lists the topics in this manual, including the page where you can
find each one.
Conventions Used in This Manual
The following conventions are used in this manual.
boldBold text denotes menus, menu items, or dialog box buttons or options.
bold italicBold italic text denotes a note, caution, or warning.
italicItalic text denotes emphasis, a cross reference, or an introduction to a key
concept.
monospaceLowercase text in this font denotes text or characters that are to be literally
input from the keyboard, sections of code, programming examples, and
syntax examples. This font is also used for the proper names of disk
drives, paths, directories, programs, subprograms, subroutines, device
names, functions, variables, filenames, and extensions, and for statements
and comments taken from program code.
NI-DAQNI-DAQ refers to the NI-DAQ software for PC compatibles unless
otherwise noted.
PCPC refers to the IBM PC/XT, the IBM PC AT, and compatible computers
unless otherwise noted.
SCXISCXI stands for Signal Conditioning eXtensions for Instrumentation and
is a National Instruments product line designed to perform front-end signal
conditioning for National Instruments plug-in DAQ boards.
< >Angle brackets containing numbers separated by an ellipses represent a
range, signal, or port (for example, ACH<0..7> stands for ACH0 through
ACH7).
Abbreviations, acronyms, metric prefixes, mnemonics, and symbols are listed in the Glossary.
National Instruments Documentation
The PC-DIO-24 User Manual is one piece of the documentation set for your data acquisition
(DAQ) system. You could have any of several types of manuals, depending on the hardware and
software in your system. Use the different types of manuals you have as follows:
•Getting Started with SCXI—If you are using SCXI, this is the first manual you should read.
It gives an overview of the SCXI system and contains the most commonly needed
information for the modules, chassis, and software.
•Your SCXI hardware user manuals—If you are using SCXI, read these manuals next for
detailed information about signal connections and module configuration. They also explain
in greater detail how the module works and contain application hints.
•Your DAQ hardware user manuals—These manuals have detailed information about the
DAQ hardware that plugs into or is connected to your computer. Use these manuals for
hardware installation and configuration instructions, specification information about your
DAQ hardware, and application hints.
•Software manuals—Examples of software manuals you may have are the LabVIEW and
LabWindows
NI-DAQ supports LabWindows for DOS). After you set up your hardware system, use either
the application software (LabVIEW or LabWindows/CVI) manuals or the NI-DAQ manuals
to help you write your application. If you have a large and complicated system, it is
worthwhile to look through the software manuals before you configure your hardware.
•Accessory installation guides or manuals—If you are using accessory products, read the
terminal block and cable assembly installation guides or accessory board user manuals. They
explain how to physically connect the relevant pieces of the system. Consult these guides
when you are making your connections.
®
/CVI manual sets and the NI-DAQ manuals (a 4.6.1 or earlier version of
•SCXI chassis manuals—If you are using SCXI, read these manuals for maintenance
information on the chassis and installation instructions.
Related Documentation
The following documents contain information that you may find helpful as you read this manual:
•IBM Personal Computer AT Technical Reference manual
•IBM Personal Computer XT Technical Reference manual
Customer Communication
National Instruments wants to receive your comments on our products and manuals. We are
interested in the applications you develop with our products, and we want to help if you have
problems with them. To make it easy for you to contact us, this manual contains comment and
configuration forms for you to complete. These forms are in Appendix D, Customer
This chapter describes the PC-DIO-24, lists what you need to get started, describes software
programming choices, optional equipment, and custom cables, and explains how to unpack the
PC-DIO-24.
About the PC-DIO-24
Thank you for purchasing the National Instruments PC-DIO-24. The PC-DIO-24 is a low cost,
24-bit parallel, digital I/O interface for the PC. An OKI 82C55A PPI controls the 24 bits of
digital I/O. The 82C55A is very flexible and powerful when interfacing with peripheral
equipment, can operate in either a unidirectional or bidirectional bus mode, and can generate
interrupt request outputs. The 82C55A can be programmed for almost any 8-bit or 16-bit digital
I/O application. All digital I/O is through a standard 50-pin male connector. The pin
assignments for this connector are compatible with standard 24-channel digital I/O applications.
The PC-DIO-24 can be used in a wide range of digital I/O applications. With the PC-DIO-24, a
PC can be interfaced to any of the following.
•Other computers
-Another PC with a National Instruments PC-DIO-24 or AT-DIO-32F
-IBM Personal System/2 with a National Instruments MC-DIO-24 or MC-DIO-32F
-Apple Macintosh II with a National Instruments NB-DIO-24 or NB-DIO-32F
-Any other computer with an 8-bit or 16-bit parallel interface
•Centronics-compatible printers and plotters
•Panel meters
•Instruments and test equipment with BCD readouts and/or controls
•Opto-isolated solid-state relays (SSRs) and I/O module mounting racks
Note: The PC-DIO-24 cannot sink sufficient current to drive the SSR-OAC-5 and
SSR-OAC-5A output modules. However, it can drive the SSR-ODC-5 output module
and all SSR input modules available from National Instruments.
If you need to drive a SSR-OAC-5 or SSR-OAC-5A, you can either use a non-inverting
digital buffer chip between the PC-DIO-24 and the SSR backplane, or you can use a
DIO-23F or MIO Series board with appropriate connections (e.g., SC-205X and
cables).
With the PC-DIO-24, the PC can serve as a digital I/O system controller for laboratory testing,
production testing, and industrial process monitoring and control.
Detailed specifications of the PC-DIO-24 are in Appendix A, Specifications.
What You Need to Get Started
To set up and use your PC-DIO-24, you will need the following:
PC-DIO-24 board
PC-DIO-24 User Manual
One of the following software packages and documentation:
NI-DAQ for PC compatibles
LabVIEW for Windows
LabWindows/CVI for Windows
Your computer
Software Programming Choices
There are several options to choose from when programming your National Instruments DAQ
and SCXI hardware. You can use LabVIEW, LabWindows/CVI, or NI-DAQ. A 4.6.1 or earlier
version of NI-DAQ supports LabWindows for DOS.
LabVIEW and LabWindows/CVI Application Software
LabVIEW and LabWindows/CVI are innovative program development software packages for
data acquisition and control applications. LabVIEW uses graphical programming, whereas
LabWindows/CVI enhances traditional programming languages. Both packages include
extensive libraries for data acquisition, instrument control, data analysis, and graphical data
presentation.
LabVIEW features interactive graphics, a state-of-the-art user interface, and a powerful graphical
programming language. The LabVIEW Data Acquisition VI Library, a series of VIs for using
LabVIEW with National Instruments DAQ hardware, is included with LabVIEW. The LabVIEW
Data Acquisition VI Libraries are functionally equivalent to the NI-DAQ software.
LabWindows/CVI features interactive graphics, a state-of-the-art user interface, and uses the
ANSI standard C programming language. The LabWindows/CVI Data Acquisition Library, a
series of functions for using LabWindows/CVI with National Instruments DAQ hardware, is
included with the NI-DAQ software kit. The LabWindows/CVI Data Acquisition libraries are
functionally equivalent to the NI-DAQ software.
Using LabVIEW or LabWindows/CVI software will greatly reduce the development time for
your data acquisition and control application.
The NI-DAQ driver software is included at no charge with all National Instruments DAQ
hardware. NI-DAQ is not packaged with SCXI or accessory products, except for the SCXI-1200.
NI-DAQ has an extensive library of functions that you can call from your application
programming environment. These functions include routines for analog input (A/D conversion),
buffered data acquisition (high-speed A/D conversion), analog output (D/A conversion),
waveform generation, digital I/O, counter/timer operations, SCXI, RTSI, self-calibration,
messaging, and acquiring data to extended memory.
NI-DAQ has both high-level DAQ I/O functions for maximum ease of use and low-level DAQ
I/O functions for maximum flexibility and performance. Examples of high-level functions are
streaming data to disk or acquiring a certain number of data points. An example of a low-level
function is writing directly to registers on the DAQ device. NI-DAQ does not sacrifice the
performance of National Instruments DAQ devices because it lets multiple devices operate at
their peak performance.
NI-DAQ also internally addresses many of the complex issues between the computer and the
DAQ hardware such as programming interrupts and DMA controllers. NI-DAQ maintains a
consistent software interface among its different versions so that you can change platforms with
minimal modifications to your code. Figure 1-1 illustrates the relationship between NI-DAQ and
LabVIEW and LabWindows/CVI.
Conventional
Programming
Environment
(PC, Macintosh, or
Sun SPARCstation)
DAQ or
SCXI Hardware
LabVIEW
(PC, Macintosh, or
Sun SPARCstation)
NI-DAQ
Driver Software
LabWindows/CVI
(PC or Sun
SPARCstation)
Personal
Computer or
Workstation
Figure 1-1. The Relationship between the Programming Environment,
The final option for programming any National Instruments DAQ hardware is to write registerlevel software. Writing register-level programming software can be very time-consuming and
inefficient, and is not recommended for most users.
Even if you are an experienced register-level programmer, consider using NI-DAQ, LabVIEW,
or LabWindows/CVI to program your National Instruments DAQ hardware. Using the NI-DAQ,
LabVIEW, or LabWindows/CVI software is easier than, and as flexible as, register-level
programming, and can save weeks of development time.
Optional Equipment
National Instruments offers a variety of products to use with your PC-DIO-24 board, including
cables, connector blocks, and other accessories, as follows:
•Cables and cable assemblies, shielded and ribbon
•Connector blocks, shielded and unshielded 50-pin screw terminals
•Signal conditioning eXtensions for Instrumentation (SCXI) modules and accessories for
isolating, amplifying, exciting, and multiplexing signals for relays and analog output. With
SCXI you can condition and acquire up to 3,072 channels.
•Low channel count signal conditioning modules, boards, and accessories, including
conditioning for strain gauges and RTDs, simultaneous sample and hole, and relays.
For more specific information about these products, refer to your National Instruments catalog or
call the office nearest you.
Custom Cables
National Instruments offers cables and accessories for you to prototype your application or to use
if you frequently change board interconnections.
If you want to develop your own cable, however, the following guidelines may be useful:
The PC-DIO-24 I/O connector is a 50-pin male ribbon-cable header. The manufacturer part
numbers used by National Instruments for this header are as follows:
•Electronic Products Division/3M (part number 3596-5002)
•T&B/Ansley Corporation (part number 609-5007)
The mating connector for the PC-DIO-24 is a 50-position, polarized, ribbon socket connector
with strain relief. National Instruments uses a polarized (keyed) connector to prevent inadvertent
upside-down connection to the PC-DIO-24. Recommended manufacturer part numbers for this
mating connector are as follows:
•Electronic Products Division/3M (part number 3425-7650)
•T&B/Ansley Corporation (part number 609-5041CE)
The standard ribbon cable (50-conductor, 28 AWG, stranded) that can be used with these
connectors is as follows:
•Electronic Products Division/3M (part number 3365/50)
•T&B/Ansley Corporation (part number 171-50)
Recommended manufacturer part numbers for the 50-pin edge connector for connecting to a
module rack with an edge connector are as follows:
•Electronic Products Division/3M (part number 3415-0001)
•T&B Ansley Corporation (part number 609-5015M)
A polarizing key can be plugged into these edge connectors to prevent inadvertent upside-down
connection to the I/O module rack. The location of this key varies from rack to rack. Consult
the specification for the rack you intend to use for the location of any polarizing key. The
recommended manufacturer part numbers for this polarizing key are as follows:
•Electronic Products Division/3M (part number 3439-2)
•T&B Ansley Corporation (part number 609-0005)
If you plan to use the PC-DIO-24 for a communications application, you may need shielded
cables to meet FCC requirements. The PC-DIO-24 I/O bracket has been designed so that the
shield of the I/O cable can be grounded through the computer chassis when a mating connector
such as the following is used:
•AMP Special Industries (part number 2-746483-2)
Many varieties of shielded ribbon cable are available to work with the mating connector listed
previously. One type of shielded cable encloses a standard ribbon cable with a shielded jacket.
Recommended manufacturers and the appropriate part numbers for this type of cable are as
follows:
•Belden Electronic Wire and Cable (part number 9L28350)
Your PC-DIO-24 board is shipped in an antistatic package to prevent electrostatic damage to the
board. Electrostatic discharge can damage several components on the board. To avoid such
damage in handling the board, take the following precautions:
•Ground yourself via a grounding strap or by holding a grounded object.
•Touch the antistatic package to a metal part of your PC chassis before removing the board
from the package.
•Remove the board from the package and inspect the board for loose components or any other
sign of damage. Notify National Instruments if the board appears damaged in any way. Donot install a damaged board into your computer.
This chapter describes how to configure and install the PC-DIO-24, including I/O connector
signal descriptions, handshake timing diagrams, and cabling instructions.
Board Configuration
The PC-DIO-24 contains one DIP switch and two jumpers to configure the base I/O address and
interrupts, respectively. The PC-DIO-24 also contains one fuse to protect the +5 V power
output. Figure 2-1 shows the location of jumper sets W1 and W2, DIP switch U2, and the
fuse F1.
The PC-DIO-24 is configured at the factory to a base I/O address of hex 210, to use interrupt
enable line PC4, and to use interrupt level 5. These settings (shown in Table 2-1) are suitable for
most systems. However, if your system has other hardware at this base I/O address, interrupt
enable line, or interrupt level, you need to change these settings on the PC-DIO-24 (as described
in the following pages) or on the other hardware. Record your settings in the PC-DIO-24Hardware and Software Configuration Form in Appendix D, Customer Communication.
Table 2-1. PC-DIO-24 Factory-Set Jumper and Switch Settings
Base I/O AddressHex 210
(factory setting)
Interrupt Enable LinePC4
(factory setting)
Interrupt LevelInterrupt level 5 selected
(factory setting)
A9A8A7A6A5A4A3
1 2 3 4 5 6 7 8
U2
(The black side indicates the side that
is pushed down.)
The base I/O address for the PC-DIO-24 is determined by the switches at position U2 (see
Figure 2-1). The switches are set at the factory for the I/O address hex 210. With this default
setting, the PC-DIO-24 uses the I/O address space hex 210 through 213.
Note: Verify that this space is not already used by other equipment installed in your
computer. If any equipment in your computer uses this I/O address space, you must
change the base I/O address for the PC-DIO-24 or for the other device.
Each switch in U2 corresponds to one of the address lines A9 through A2. Thus, the range for
possible base I/O address settings is hex 000 through 3FC. Base I/O address values hex 000
through 0FF are reserved for system use. Base I/O values hex 100 through 3FF are available on
the I/O channel. A1 and A0 are used by the PC-DIO-24 to decode the onboard registers. On the
U2 DIP switches, press the side marked OFF to select a binary value of 1 for the corresponding
address bit. Press the other side of the switch to select a binary value of 0 for the corresponding
address bit. Figure 2-2 shows two possible switch settings. The black side indicates the side that
is pushed down.
A9
A8
A7
A6
A5
A4
A3
A2
12345678
O
N
O
F
F
U2
A. Switches Set to Default Setting (Base I/O Address Hex 210)
A8
A7
A6
U2
A5
A4
A3
A2
A9
12345678
O
N
O
F
F
B. Switches Set to Base I/O Address Hex 278
Figure 2-2. Example Base I/O Address Switch Settings
There are two sets of jumpers for interrupt selection on the PC-DIO-24 board. W1 is used for
selecting the interrupt enable line. W2 is for selecting the interrupt level. The location of these
jumpers is shown in Figure 2-1.
Interrupt Enable Settings
To enable interrupt requests from the PC-DIO-24, you must set jumper W1 to select PC2, PC4,
or PC6 as the active low interrupt enable line. When the interrupt enable line is logic low,
interrupts are enabled from the PC-DIO-24 board. Refer to Chapter 4, Register-LevelProgramming, for the suggested interrupt enable line setting for each digital I/O mode of
operation. If W1 is set to N/C, all interrupt requests from the PC-DIO-24 are disabled.
Figure 2-3 shows the possible jumper settings for W1. The board is shipped with this jumper set
to PC4; therefore, interrupt requests from the board are enabled and controlled by PC4.
W1
PC6
PC4
PC2
N/C
INT
(Default Factory Setting)
W1
INT
PC6
PC4
PC2
N/C
W1
INT
PC6
PC4
PC2
N/C
W1
PC6
PC4
PC2
N/C
INT
Figure 2-3. Jumper Settings–PC6, PC4, PC2, and N/C
Interrupt Level Settings
The PC-DIO-24 board can connect to any one of the six interrupt lines of the PC I/O Channel:
IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, or IRQ9. You select the interrupt line by setting a jumper on
W2. To use the interrupt capability of the board, you must select an interrupt line and place the
jumper in the appropriate position. The default interrupt line is IRQ5. To change to another line,
remove the jumper from IRQ5 and place it on the pins for another request line. Figure 2-4 shows
the default factory setting for IRQ5.
IRQ
W2
345679
Figure 2-4. Interrupt Jumper Setting for IRQ5 (Factory Setting)
The PC-DIO-24 can share interrupt lines with other devices by using a tristate driver to drive its
selected interrupt lines.
Installation
The PC-DIO-24 can be installed in any unused 8-bit or 16-bit expansion slot in your computer.
After you make any necessary changes and verify the switch and jumper settings, record the
settings in the PC-DIO-24 Hardware and Software Configuration Form in Appendix D,
Customer Communication. You are now ready to install the PC-DIO-24.
The following are general installation instructions, but consult the user manual or technical
reference manual of your personal computer for specific instructions and warnings.
1.Turn off your computer.
2.Remove the top cover or access port to the I/O channel.
3.Remove the expansion slot cover on the back panel of the computer.
4.Insert the PC-DIO-24 in an unused 8-bit or 16-bit slot. It may be a tight fit, but do not force
the board into place.
5.Screw the mounting bracket of the PC-DIO-24 to the back panel rail of the computer.
6.Check the installation.
7.Replace the cover to the computer.
The PC-DIO-24 board is now installed and ready for operation.
Figure 2-5 shows the pin assignments for the PC-DIO-24 digital I/O connector.
Warning: Connections that exceed any of the maximum ratings of input or output signals on
the PC-DIO-24 may result in damage to the PC-DIO-24 board and to the PC.
Maximum ratings for each signal are given in this chapter under the discussion of
that signal. National Instruments is not liable for any damages resulting from any
such signal connections.
1, 3, 5, 7, 9, 11, 13,15PC<7..0>Port C—Bidirectional data lines for port C. PC7 is the MSB,
PC0 the LSB.
17, 19, 21, 23, 25,
27, 29, 31
33, 35, 37, 39, 41,
43, 45, 47
49 (see note below)+5 V+5 Volts—This pin provides +5 VDC.
All even-numbered
pins
Note: Pin 49 is connected to the +5 V PC power supply via a 1 A fuse. A replacement fuse is available from
Allied Electronics, part number 845-2007, or Littelfuse, part number 251001.
PB<7..0>Port B—Bidirectional data lines for port B. PB7 is the MSB,
PB0 the LSB.
PA<7..0>Port A—Bidirectional data lines for port B. PA7 is the MSB,
PA0 the LSB.
GNDGround—These signals are connected to the PC ground signal.
The absolute maximum voltage input rating is -0.5 to +5.5 V with respect to GND.
Port C Pin Assignments
The signals assigned to port C depend on the mode in which the 82C55A is programmed. In
mode 0, port C is considered two 4-bit I/O ports. In modes 1 and 2, port C is used for status and
handshaking signals with two or three I/O bits mixed in. Table 2-2 summarizes the signal
assignments of port C for each programmable mode. See Chapter 4, Register-LevelProgramming, for register-level programming information.
Warning:During programming, note that each time a port is configured, output ports A
and C are reset to 0, and output port B is undefined.
This section lists the timing specifications for handshaking with the PC-DIO-24. The
handshaking lines STB* and IBF synchronize input transfers. The handshaking lines OBF* and
ACK* synchronize output transfers.
The following signals are used in the timing diagrams on the subsequent pages.
NameSignal
Direction
STB*InputStrobe Input—A low signal on this handshaking line loads data into the input
IBFOutputInput Buffer Full—A high signal on this handshaking line indicates that data
ACK*InputAcknowledge Input—A low signal on this handshaking line indicates that
OBF*OutputOutput Buffer Full—A low signal on this handshaking line indicates that
INTROutputInterrupt Request—This signal becomes high when the 82C55A is
RD*InternalRead Signal—This signal is the read signal generated from the control lines
WR*InternalWrite Signal—This signal is the write signal generated from the control lines
DATABidirectionalData Lines at the Selected Port—This signal indicates when the data on the
Description
latch.
has been loaded into the input latch. This is an input acknowledge signal.
the data written from the selected port has been accepted. This signal is a
response from the external device that it has received the data from the
PC-DIO-24.
data has been written from the selected port.
requesting service during a data transfer. The appropriate interrupt enable
bits must be set to generate this signal.
of the PC.
of the PC.
data lines at a selected port is or should be available.
This chapter contains a functional overview of the PC-DIO-24 board and explains the operation
of each functional unit making up the PC-DIO-24.
The block diagram in Figure 3-1 illustrates the key functional components of the PC-DIO-24
board.
Address
Decoder
PA
Bus
Transceivers
82C55A
PPI
/
8
PB
/
8
PC
/
8
I/O Connector
PC3
PC0
PC I/O Channel
+5 V
PC I/O
Channel
Control
Circuitry
Interrupt
Control
Circuitry
1 A Fuse
Figure 3-1. PC-DIO-24 Block Diagram
The PC I/O Channel consists of an address bus, a data bus, interrupt lines, and several control
and support signals. Control and data transfers to the system microprocessor are asynchronous.
The base address used by the board is determined by an onboard switch setting. The address on
the PC I/O Channel bus is monitored by the address decoder. If the address on the bus matches
the selected I/O base address of the board, the board is enabled and the corresponding register on
the PC-DIO-24 is accessed.
Bus Transceivers
The bus transceivers control the sending and receiving of data lines to and from the PC I/O
Channel.
PC I/O Channel Control Circuitry
This circuitry monitors and transmits the PC I/O Channel control and support signals. The
control signals identify transfers as read or write, configuration or I/O, and 8-bit or 16-bit. The
PC-DIO-24 only uses 8-bit transfers.
82C55A Programmable Peripheral Interface
The 82C55A PPI is the heart of the PC-DIO-24. This chip has 24 programmable I/O pins that
represent three 8-bit ports—PA, PB, and PC. Each port can be programmed as an input or an
output port. The 82C55A has three modes of operation—simple I/O (mode 0), strobed I/O
(mode 1), and bidirectional I/O (mode 2). In modes 1 and 2, the three ports are divided into two
groups—group A and group B. Each group has eight data bits and four control and status bits
from port C (PC). Modes 1 and 2 use handshaking signals from port C to synchronize data
transfers. Refer to Chapter 4, Register-Level Programming, or to Appendix C, OKI82C55AData Sheet, for more detailed information.
Interrupt Control Circuitry
The interrupt level used by the PC-DIO-24 is selected by the onboard jumper W2. Another
onboard jumper, W1, is used to enable interrupts from the PC-DIO-24. The setting for W1
selects PC2, PC4, or PC6 as the active low interrupt enable signal. Selecting N/C for W1
disables interrupts from the PC-DIO-24. When the onboard jumpers are set to enable interrupts,
the 82C55A can be programmed to generate an interrupt request by setting INTRA for group A
or INTRB for group B. When interrupts are enabled for group A, an active high signal on the
PC3 line generates an interrupt request. When interrupts are enabled for group B, an active high
signal on the PC0 line generates an interrupt request.
Digital I/O Connector
All digital I/O is transmitted through a standard 50-pin male connector. The pin assignments for
the I/O connector are compatible with standard 24-channel digital I/O applications. All even
pins on this connector are attached to logic ground, and pin 49 is connected to +5 V through a
protection fuse (F1), which is often required to operate I/O module mounting racks. See
Chapter 2, Configuration and Installation, for additional information.
This chapter describes in detail the address and function of each of the PC-DIO-24 control and
status registers. This chapter also includes important information related to register-level
programming the PC-DIO-24.
The PC-DIO-24 is a parallel, digital I/O board designed around the OKI 82C55A integrated
circuit. The 82C55A is a general-purpose peripheral interface containing 24 programmable I/O
pins. These pins represent the three 8-bit I/O ports (A, B, and C) of the 82C55A. These ports
can be programmed as two groups of 12 signals or as three individual 8-bit ports. This chapter
includes register-level programming information for the PC-DIO-24, along with program examples
written in C.
Note: If you plan to use a programming software package such as LabWindows/CVI or
NI-DAQ with your PC-DIO-24 board, you need not read this chapter.
Introduction
The three 8-bit ports are divided into two groups—group A and group B (two groups of 12
signals). One 8-bit configuration (or control) word determines the mode of operation for each
group. The group A control bits configure port A<0..7> and the upper 4 bits (nibble) of
port C<4..7>. The group B control bits configure port B<0..7> and the lower nibble of
port C<0..3>. These configuration bits are defined later in this chapter.
82C55A Modes of Operation
The three basic modes of operation for the 82C55A are as follows:
•Mode 0 – Basic I/O
•Mode 1 – Strobed I/O
•Mode 2 – Bidirectional bus
The 82C55A also has a single bit set/reset feature for port C. The 8-bit control word also
programs this function. For additional information, refer to Appendix C, OKI 82C55A Data
This mode can be used for simple input and output operations for each of the ports. No
handshaking is required; data is simply written to or read from a selected port.
Mode 0 has the following features:
•Two 8-bit ports (A and B) and two 4-bit ports (upper and lower nibble of port C).
•Any port can be input or output.
•Outputs are latched, but inputs are not latched.
Mode 1
This mode transfers data that is synchronized by handshaking signals. ports A and B use the
eight lines of port C to generate or receive the handshake signals. This mode divides the ports
into two groups (group A and group B):
•Each group contains one 8-bit data port (port A or port B) and one 4-bit control/data port
(upper or lower nibble of port C).
•The 8-bit data ports can be either input or output, both of which are latched.
•The 4-bit ports are used for control and status of the 8-bit data ports.
•Interrupt generation and enable and/or disable functions are available.
Mode 2
This mode can be used for communication over a bidirectional 8-bit bus. Handshaking signals
are used in a manner similar to mode 1. Interrupt generation and enable and/or disable functions
are also available. Other features of this mode include the following:
•Used in group A only (port A and upper nibble of port C).
•One 8-bit bidirectional port (port A) and a 5-bit control status port (port C).
•Latched inputs and outputs.
Single Bit Set/Reset Feature
Any of the eight bits of port C can be set or reset with one control word. This feature generates
status and control for port A and port B when operating in mode 1 or mode 2.
Figure 4-1 shows the two control-word formats used to completely program the 82C55A. The
Control Word Flag determines which control-word format is being programmed. When the
Control Word Flag is 1, bits 0 through 6 determine the I/O characteristics of the 82C55A ports
and the mode in which they are operating (that is, mode 0, mode 1, or mode 2). When the
Control Word Flag is 0, bits 3 through 0 determine the bit set/reset format of port C.
Warning:During programming, note that each time a port is configured, output ports A
and C are reset to 0, and output port B is undefined.
Table 4-2 shows the control words for setting or resetting each bit in port C. Notice that bit 7 of
the control word is cleared when programming the set/reset option for the bits of port C.
Mode 0 can be used for simple I/O functions for each of the three ports with no handshaking.
Each port can be assigned as an input or an output port. The 16 possible I/O configurations are
shown in Table 4-3. Notice that bit 7 of the control word is set when programming the mode of
operation for each port.
#define BASE_ADDRESS0x210/* Board located at address 210 */
#define PORTAoffset0x00/* Offset for port A */
#define PORTBoffset0x01/* Offset for port B */
#define PORTCoffset0x02/* Offset for port C */
#define CNFGoffset0x03/* Offset for CNFG */
register unsigned int porta, portb, portc, cnfg;
char valread;/* Variable to store data read from a
/* EXAMPLE 1*/
outp(cnfg,0x80);/* Ports A, B, and C are outputs. */
outp(porta,0x12);/* Write data to port A. */
outp(portb,0x34);/* Write data to port B. */
outp(portc,0x56);/* Write data to port C. */
/* EXAMPLE 2*/
outp(cnfg,0x90);/* Port A is input; ports B and C are
outputs. */
outp(portb,0x22);/* Write data to port B. */
outp(portc,0x55);/* Write data to port C. */
valread = inp(porta);/* Read data from port A. */
/* EXAMPLE 3 */
outp(cnfg,0x82);/* Ports A and C are outputs; port B
is an input. */
/* EXAMPLE 4 */
outp(cnfg,0x89);/* Ports A and B are outputs; port C
is an input. */
}
Mode 1–Strobed Input
In mode 1, the digital I/O bits are divided into two groups—group A and group B. Each of these
groups contains one 8-bit port and one 4-bit control/data port. The 8-bit port can be either an
input or an output, and the 4-bit port is used for control and status information for the 8-bit port.
The transfer of data is synchronized by handshaking signals in the 4-bit port.
The control word written to the CNFG Register to configure port A for input in mode 1 is shown
as follows. Bits PC6 and PC7 of port C can be used as extra input or output lines.
7654 3210
10111/0XXX
Port C bits PC6 and PC7
1 = input
0 = output
The control word written to the CNFG Register to configure port B for input in mode 1 is shown
as follows. Notice that port B does not have extra input or output lines from port C.
During a mode 1 data read transfer, the status of the handshaking lines and interrupt signals can
be obtained by reading port C. The port C status-word bit definitions for an input transfer are
shown as follows.
The following are the port C status-word bit definitions for input (port A and port B).
76543210
I/OI/OIBFAINTEAINTRAINTEBIBFBINTRB
BitNameDescription
7–6I/OInput/Output—Extra I/O status lines when port A is in mode 1
input.
5IBFAInput Buffer Full for Port A—High indicates that data has been
loaded into the input latch for port A.
4INTEAInterrupt Enable Bit for Port A—Enables interrupts from the
82C55A for port A. Controlled by bit set/reset of PC4.
3INTRAInterrupt Request Status for Port A—When INTEA is high and
IBFA is high, this bit is high, indicating that an interrupt request is
asserted.
2INTEBInterrupt Enable Bit for Port B—Enables interrupts from the
82C55A for port B. Controlled by bit set/reset of PC2.
1IBFBInput Buffer Full for Port B—High indicates that data has been
loaded into the input latch for port B.
0INTRBInterrupt Request Status for Port B—When INTEB is high and
IBFB is high, this bit is high, indicating that an interrupt request is
asserted.
At the digital I/O connector, port C has the following pin assignments when in mode 1 input.
Notice that the status of STBA* and STBB* are not included in the port C status word.
#define BASE_ADDRESS0x210/* Board located at address 210. */
#define PORTAoffset0x00/* Offset for port A */
#define PORTBoffset0x01/* Offset for port B */
#define PORTCoffset0x02/* Offset for port C */
#define CNFGoffset0x03/* Offset for CNFG */
register unsigned int porta, portb, portc, cnfg;
char valread;/* Variable to store data read from a
outp(cnfg,0xB0);/* Port A is an input in mode 1. */
while (!(inp(portc) & 0x20));/* Wait until IBFA is set, indicating that
data has been loaded in port A. */
valread = inp(porta);/* Read the data from port A. */
/* EXAMPLE 2–port B input */
outp(cnfg,0x86);/* Port B is an input in mode 1. */
while (!(inp(portc) & 0x02));/* Wait until IBFB is set, indicating that
data has been loaded in port B. */
valread = inp(portb);
}
Mode 1–Strobed Output
The control word written to the CNFG Register to configure port A for output in mode 1 is
shown as follows. Bits PC4 and PC5 of port C can be used as extra input or output lines when
port A uses mode 1 output.
The control word written to the CNFG Register to configure port B for output in mode 1 is
shown as follows. Notice that port B does not have extra input or output lines from port C.
76543210
1 XXXX10X
During a mode 1 data write transfer, the status of the handshaking lines and interrupt signals can
be obtained by reading port C. Notice that the bit definitions are different for a write and a read
transfer.
The following are the port C status-word bit definitions for output (port A and port B).
7 6543210
OBFA*INTEAI/OI/OINTRAINTEBOBFB*INTRB
BitNameDescription
7OBFA*Output Buffer Full for Port A—Low indicates that the CPU has
written data to port A.
6INTEAInterrupt Enable Bit for Port A—If this bit is high, interrupts are
enabled from the 82C55A for port A. Controlled by bit set/reset of
PC6.
5–4I/OInput/Output—Extra I/O status line when port A is in mode 1
output.
3INTRAInterrupt Request Status for Port A—When INTEA is high and
OBFA* is high, this bit is high, indicating that an interrupt request
is asserted.
2INTEBInterrupt Enable Bit for Port B—If this bit is high, interrupts are
enabled from the 82C55A for port B. Controlled by bit set/reset of
PC2.
1OBFB*Output Buffer Full for Port B—Low indicates that the CPU has
written data out to port B.
0INTRBInterrupt Request Status for Port B—When INTEB is high and
OBFB* is high, this bit is high, indicating that an interrupt request
is asserted.
At the digital I/O connector, port C has the following pin assignments when in mode 1 output.
Notice that the status of ACKA* and ACKB* is not included when port C is read.
Group A
Group B
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
OBFA*
ACKA*
I/O
I/O
INTRA
ACKB*
OBFB*
INTRB
Mode 1 Output Programming Example
Main() {
#define BASE_ADDRESS0x210/* Board located at address 210. */
#define PORTAoffset0x00/* Offset for port A */
#define PORTBoffset0x01/* Offset for port B */
#define PORTCoffset0x02/* Offset for port C */
#define CNFGoffset0x03/* Offset for CNFG */
register unsigned int porta, portb, portc, cnfg;
char valread;/* Variable to store data read from a
Mode 2 has an 8-bit bus that can transfer both input and output without changing the
configuration. The data transfers are synchronized with handshaking lines in port C. This mode
uses only port A; however, port B can be used in either mode 0 or mode 1 while port A is
configured for mode 2.
The control word written to the CNFG Register to configure port A as a bidirectional data bus in
mode 2 is shown as follows. If port B is configured for mode 0, then PC2, PC1, and PC0 of
port C can be used as extra input or output lines.
76543210
11XXX1/01/01/0
Port C bits PC2,PC1,PC0
1 = input
0 = output
Port B direction
1 = input
0 = output
Group B Mode
0 = mode 0
1 = mode 1
During a mode 2 data transfer, the status of the handshaking lines and interrupt signals can be
obtained by reading port C. The port C status-word bit definitions for a mode 2 transfer are
shown as follows.
The following are the port C status-word bit definitions for bidirectional data path (port A only).
76543210
OBFA*INTE1IBFAINTE2INTRAI/OI/OI/O
BitNameDescription
7OBFA*Output Buffer Full—Low indicates that the CPU has written data
to port A.
6INTE1Interrupt Enable Bit for Output—If this bit is set, interrupts are
enabled from the 82C55A for OBFA*. Controlled by bit set/reset of
PC6.
5IBFAInput Buffer Full—High indicates that data has been loaded into
4INTE2Interrupt Enable Bit for Input—If this bit is set, interrupts are
enabled from the 82C55A for IBFA. Controlled by bit set/reset of
PC4.
3INTRAInterrupt Request Status—If INTE1 is high and IBFA is high, this
bit is high, indicating that an interrupt request is asserted for input
transfers. If INTE2 is high and OBFA* is high, this bit is high,
indicating that an interrupt request is asserted for output transfers.
2–0I/OInput/Output—Extra I/O status lines available if port B is not
configured for mode 1.
At the digital I/O connector, port C has the following pin assignments when in mode 2.
Group A
Group B
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
OBFA*
ACKA*
IBFA
STBA*
INTRA
I/O
or
Hand-
shaking
Mode 2 Programming Example
Main() {
#define BASE_ADDRESS0x210/* Board located at address 210. */
#define PORTAoffset 0x00/* Offset for port A */
#define PORTBoffset 0x01/* Offset for port B */
#define PORTCoffset 0x02/* Offset for port C */
#define CNFGoffset 0x03/* Offset for CNFG */
register unsigned int porta, portb, portc, cnfg;
char valread;/* Variable to store data read from a
outp(cnfg,0xC0);/* Port A is in mode 2. */
while (!(inp(portc) & 0x80));/* Wait until OBFA* is set,
indicating that the data last
written to port A has been
read.*/
outp(porta,0x67);/* Write the data to port A. */
while (!(inp(portc) & 0x20));/* Wait until IBFA is set, indicating
that data is available in port A to
be read. */
valread = inp(porta);/* Read data from port A. */
}
Interrupt Programming Examples
The following examples show the process required to enable interrupts for several different
operating modes. The interrupt handling routines and interrupt installation routines are not
included. See the IBM Personal Computer AT Technical Reference manual for additional
information.
Main() {
#define BASE_ADDRESS0x210/* Board located at address 210. */
#define PORTAoffset 0x00/* Offset for port A */
#define PORTBoffset 0x01/* Offset for port B */
#define PORTCoffset 0x02/* Offset for port C */
#define CNFGoffset 0x03/* Offset for CNFG */
register unsigned int porta, portb, portc, cnfg;
char valread;/* Variable to store data read from a
/* EXAMPLE 3–Set up interrupts for mode 1 output for port A. Select PC4 as
the interrupt enable bit. */
outp(cnfg,0xA0);/* Port A is an output in mode 1. */
outp(cnfg,0x0D);/* Set PC6 to enable interrupts from
82C55A. */
outp(cnfg,0x0C);/* Clear PC4 to enable interrupts. */
/* EXAMPLE 4–Set up interrupts for mode 1 output for port B. Select PC4 as
the interrupt enable bit. */
outp(cnfg,0x84);/* Port B is an output in mode 1. */
outp(cnfg,0x05);/* Set PC2 to enable interrupts from
82C55A. */
outp(cnfg,0x08);/* Clear PC4 to enable interrupts. */
/* EXAMPLE 5–Set up interrupts for mode 2 output transfers. Select PC2 as the
interrupt enable bit. */
outp(cnfg,0xC0);/* mode 2 output */
outp(cnfg,0x0D);/* Set PC6 to enable interrupts from
82C55A. */
outp(cnfg,0x04);/* Clear PC2 to enable interrupts. */
/* EXAMPLE 6–Set up interrupts for mode 2 input transfers. Select PC2 as the
interrupt enable bit. */
outp(cnfg,0xD0);/* mode 2 input */
outp(cnfg,0x09);/* Set PC4 to enable interrupts from
82C55A. */
outp(cnfg,0x04);/* Clear PC2 to enable interrupts. */
}
Interrupt Handling
A jumper setting on the PC-DIO-24 selects the signal that is used for the interrupt enable signal.
If jumper W1 is set to N/C, interrupts are disabled. Jumper W1 can be used to select PC2, PC4,
or PC6 as the active low interrupt enable signal. For example, if PC2 is selected, interrupts are
enabled if PC2 is logic low. If PC2 is logic high, interrupts from the PC-DIO-24 are disabled.
The following table summarizes which signal should be used as the interrupt enable for all mode
combinations.
The recommended jumper settings for W1 are as follows.
•PC6 — If port A is in mode 1 input.
•PC4 — If port A is in mode 1 output.
•PC2 — If port A is in mode 2 (port B is not in mode 1).
To enable interrupts from the PC-DIO-24, select PC2, PC4, or PC6 as the active low interrupt
enable signal. Initially, set the selected bit high to disable unwanted interrupts.
Program the PC-DIO-24 for the I/O mode desired. To enable interrupts from the 82C55A, set
either the INTEA or the INTEB bit to enable interrupts from port A or port B, respectively. In
mode 2, set either INTE1 or INTE2 for interrupts on input or output transfers. After interrupts
have been enabled from the 82C55A, clear the selected interrupt enable bit to enable interrupts
from the PC-DIO-24.
An external signal can be used to interrupt the PC-DIO-24 when port A or port B is in mode 0.
Select PC2, PC4, or PC6 as the interrupt enable bit and clear the selected bit to enable interrupts.
Connect the external signal that should trigger an interrupt to either PC3 or PC0. When the
external signal becomes logic high, an interrupt request occurs. To disable the external signal
interrupt, set the selected interrupt enable bit to logic high.
This appendix lists the specifications for the PC-DIO-24 board. These specifications are typical at 25° C, unless
otherwise stated. The operating temperature range is 0° to 70° C.
Digital I/O
Number of channels .................................................... 24 I/O
Dimensions.................................................................. 17.5 by 9.9 cm (6.9 in. by 3.9 in.)
I/O connector............................................................... 50-pin male ribbon-cable connector
Power Requirement (from PC I/O Channel)
Typ power ................................................................... 0.10 A at 5 VDC (±10%)
Max power .................................................................. 0.16 A at 5 VDC (±10%)
Transfer Rates
The maximum average transfer rates for the PC-DIO-24 are shown as follows. The code used to make the
measurements follows the table. The assembly language code was assembled as inline assembly C code using
version 8.00 of the Microsoft Optimizing C Compiler. The C code was compiled using version 8.00 of the
Microsoft Optimizing C Compiler.
Table A-1. Maximum Average Transfer Rates for the PC-DIO-24
BusCPUCPU SpeedAssemblyC
AT (ISA16)486DX4100 MHz410 kbytes/s330 kbytes/s
Assembly language code:
movcx, 64; Count out 64 transfers
movdx, 0180h; The port to access
loop:
lodsb; Assume ds:si points to buffer of data
outdx, al; Send the data
adddx, 0014h; Add offset to base address for Ireg1
inal, dx; Dummy read from Ireg1
subdx, 0014h; Restore base address
; The previous four lines are not
; necessary for measuring transfer rates
deccx; Decrement the loop counter
jnzshort loop; See if we need to loop
C code:
address = 0x0180;/* The port address */
ireg1address = address + 0x0014;
for (i = 0; i < 64; i++) {/* Loop 64 times */
outp(address, *data++);/* Send data */
inp(ireg1address);
This appendix contains the manufacturer data shee t for the OK I
Semiconductor 82C55A CMOS programma ble per iphe ral
interface(PPI). This interface is used on the DAQCard-DIO-24.
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The problem is
List any error messages
The following steps will reproduce the problem
PC-DIO-24 Hardware and Software
Configuration Form
Record the settings and revisions of your hardware and software on the line to the right of each item. Complete a
new copy of this form each time you revise your software or hardware configuration, and use this form as a
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National Instruments encourages you to comment on the documentation supplied with our products. This
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Title:PC-DIO-24 User Manual
Edition Date:September 1995
Part Number:320288B-01
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(figures), 4-7
Port C pin assignments (figure), 4-8
Port C status-word bit definitions, 4-8
programming example, 4-9
purpose and use, 4-2
mode 1 strobed output, 4-9 to 4-11
control words written to CNFG register
(figure), 4-9 to 4-10
Port C pin assignments (figure), 4-11
Port C status-word bit definitions, 4-10
programming example, 4-11
purpose and use, 4-2
mode 2 bidirectional bus, 4-12 to 4-14
control word written to CNFG Register
(figure), 4-12
Port C pin assignments (figure), 4-13
Port C status-word bit definitions, 4-12
to 4-13
programming example, 4-13 to 4-14
purpose and use, 4-2
mode 2 bidirectional timing, 2-11
OBFA* bit, Port C, 4-10
OBFB* bit, Port C, 4-10, 4-12
OKI 82C55A Programmable Peripheral
Interface
capabilities, 1-1
data sheet, C-1 to C-17
modes of operation, 4-1 to 4-2
mode 0, 4-2
mode 1, 4-2
mode 2, 4-2
single bit set/reset feature, 4-2
overview, 3-2
optional equipment for PC-DIO-24, 1-4
to 1-5
register-level programming, 1-4
theory of operation, 3-1 to 3-2
unpacking, 1-6
physical specifications, A-2
Port C
pin assignments
description, 2-7
mode 1 input (figure), 4-8
mode 1 output (figure), 4-11
mode 2 bidirectional bus
(figure), 4-13
signal assignments (table), 2-7
set/reset control words (table), 4-5
status-word bit definitions
mode 1 strobed input, 4-8
mode 1 strobed output, 4-10
mode 2 bidirectional bus (figure),
4-12 to 4-13
power requirements (from PC I/O
channel), A-2
programming. See register-level
programming.
R
P
PA<7..0> signal (table), 2-7
parts locator diagram, 2-2
PB<7..0> signal (table), 2-7
PC I/O channel control circuitry, 3-2
PC<7..0> signal (table), 2-7
PC-DIO-24
block diagram, 3-1
custom cables, 1-4 to 1-5
driving SSR-OAC-5 or SSR-OAC-5A
(note), 1-1
getting started, 1-2
interfacing with other devices, 1-1
optional equipment, 1-4 to 1-5
overview, 1-1 to 1-2
parts locator diagram, 2-2
software programming choices, 1-2.
to 1-4
control words written to CNFG
register (figure), 4-9 to 4-10
Port C pin assignments (figure), 4-11
Port C status-word bit
definitions, 4-10
programming example, 4-11
mode 2 bidirectional bus, 4-12 to 4-14
control word written to CNFG
Register (figure), 4-12
Port C pin assignments (figure), 4-13
Port C status-word bit definitions,
4-12 to 4-13
programming example, 4-13 to 4-14
register descriptions, 4-3 to 4-5
control word formats (figure), 4-4
Port C set/reset control words
(table), 4-5
single-bit set/reset feature, 4-4 to 4-5
register map, 4-3
S
signal connections
descriptions (table), 2-7
I/O connector pin description
(figure), 2-6
Port C pin assignments