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Connecting to Power Source........................................................................... 3-4
Appendix A
Specifications
Appendix B
Pinouts
Appendix C
Technical Support and Professional Services
Glossary
Index
NI PXIe-1075 User Manualvini.com
About This Manual
The NI PXIe-1075 User Manual describes the features of the NI PXIe-1075
chassis and contains information about configuring the chassis, installing
the modules, and operating the chassis.
Conventions
The following conventions are used in this manual:
»The » symbol leads you through nested menu items and dialog box options
to a final action. The sequence File»Page Setup»Options directs you to
pull down the File menu, select the Page Setup item, and select Options
from the last dialog box.
This icon denotes a note, which alerts you to important information.
This icon denotes a caution, which advises you of precautions to take to
avoid injury, data loss, or a system crash. When this symbol is marked on
the product, refer to the Read Me First: Safety and Radio-Frequency Interference document, shipped with the product, for precautions to take.
boldBold text denotes items that you must select or click in the software, such
as menu items and dialog box options. Bold text also denotes parameter
names.
italicItalic text denotes variables, emphasis, a cross-reference, or an introduction
to a key concept. Italic text also denotes text that is a placeholder for a word
or value that you must supply.
monospaceText in this font denotes text or characters that you should enter from the
keyboard, sections of code, programming examples, and syntax examples.
This font is also used for the proper names of disk drives, paths, directories,
programs, subprograms, subroutines, device names, functions, operations,
variables, filenames, and extensions.
•PCI Express Base Specification, Revision 1.1, PCI Special Interest
Group
•PXI-5 PXI Express Hardware Specification, Revision 1.0,
PXI Systems Alliance
NI PXIe-1075 User Manualviiini.com
Getting Started
This chapter describes the key features of the NI PXIe-1075 chassis and
lists the kit contents and optional equipment you can order from National
Instruments.
Unpacking
Carefully inspect the shipping container and the chassis for damage. Check
for visible damage to the metal work. Check to make sure all handles,
hardware, and switches are undamaged. Inspect the inner chassis for any
possible damage, debris, or detached components. If damage appears to
have been caused during shipment, file a claim with the carrier. Retain the
packing material for possible inspection and/or reshipment.
What You Need to Get Started
The NI PXIe-1075 chassis kit contains the following items:
1
❑ NI PXIe-1075 chassis
❑ Filler panels
❑ AC power cable—refer to Table 1-1 for AC power cables
❑ NI PXIe-1075 User Manual
❑ Software media with PXI Platform Services 2.0 or higher
❑ Read Me First: Safety and Electromagnetic Compatibility
For 100–120 VAC installation, use the NI cable part numbers listed in
Table 1-2, which are rated for 125 V/15 A.
Table 1-2. AC Power Cable Part Numbers for 100–120 VAC Installation
CountryNI Part Number
North America763830-01
Japan763841-01
Note NI PXI-1075 chassis ordered in North America or Japan ship with the proper cables
by default.
If you are missing any of the items listed in Table 1-1 or Table 1-2, or if you
have the incorrect AC power cable, contact National Instruments.
Key Features
The NI PXIe-1075 chassis combines a high-performance 18-slot
PXI Express backplane with a high-output power supply and a structural
design that has been optimized for maximum usability in a wide range
of applications. The chassis’ modular design ensures a high level of
maintainability, resulting in a very low mean time to repair (MTTR).
The NI PXIe-1075 chassis fully complies with the PXI-5 PXI Express Hardware Specification, offering advanced timing and synchronization
features.
NI PXIe-1075 User Manual1-2ni.com
Chapter 1Getting Started
The key features of the NI PXIe-1075 chassis include the following:
High Performance for Instrumentation Requirements
•Up to 1 GB/s (single direction) per PXI Express slot dedicated
bandwidth (x4 PCIe)
•38 W per slot cooling meets increased PXIe cooling requirements
•Low-jitter internal 10 MHz reference clock for PXI slots with
± 25 ppm stability
•Low-jitter internal 100 MHz reference clock for PXIe slots with
± 25 ppm stability
•8 hybrid slots for supporting existing PXI instruments
•Quiet operation for 0 to 30 °C at 43.6 dBA
•Variable speed fan controller optimizes cooling and acoustic emissions
•Remote power-inhibit control
•Complies with PXI and CompactPCI Specifications
High Reliability
•0 to 55 °C extended temperature range
•Power supply, temperature, and fan monitoring
•HALT tested for increased reliability
•Field replaceable power supply shuttle
Multi-Chassis Support
•PXIe System Timing Slot for tight synchronization across chassis
Figures 1-1 and 1-2 show the key features of the NI PXIe-1075 chassis
front and back panels. Figure 1-1 shows the front view of the
NI PXIe-1075. Figure 1-2 shows the rear view of the NI PXIe-1075.
7 PXI Express Peripheral Slots (8x)
8 PXI Express System Timing Slot
9 PXI Express System Controller Slot
10 Power Inhibit Switch
11 Power Inhibit Switch LED
12 System Controller Expansion Slots
3
NI PXIe-1075
Figure 1-1. Front View of the NI PXIe-1075 Chassis
4
5
NI PXIe-1075 User Manual1-4ni.com
Chapter 1Getting Started
7
3
2
1
4
5
6
9
8
10
11
12
4
1 Universal AC Input
2 Push-Reset Circuit Breaker
3 Chassis Ground Screw
4 Air Filter Retainer Screws
5 Power Supply Shuttle ID Label
6 10 MHz REF OUT BNC
7 10 MHz REF IN BNC
Optional Equipment
Contact National Instruments to order the following options for the
NI PXIe-1075 chassis.
EMC Filler Panels
Optional EMC filler panel kits are available from National Instruments.
Rack Mount Kit
There are two optional kits for mounting the PXIe-1075 chassis into a rack.
The first option is a pair of mounting brackets for use on the front of the
chassis. The second option is a rear rack mount kit. The rear rack mount kit
differs from the front kit to allow for easier installation into the rack.
For more information, refer to Figure A-3, NI Chassis Rack Mount Kit
Components.
14
8 Remote Inhibit and Voltage Monitoring Connector
9 Inhibit Mode Selector Switch
10 Fan Speed Selector Switch
11 Power Supply Shuttle Mounting Screws (10x)
12 Power Supply Shuttle Handle (2x)
13 Power Supply Shuttle
14 Air Filter Retainer
Refer to Figure 1-3 for an overview of the NI PXIe-1075 architecture.
Link #2
x4
Link #1
1
0
PEX8533
x4
PCIe Switch
8
2
HHHHHHHH
23456789101112131415161718
PLX
x1
1
x4
10
9
x4
x4
PCIe/PCI
Bridge
1
PEX8525
PCIe Switch
8
2
Link #3
x4
0
PLX
x4
10
9
x4
x4x4x4x4x4x4
PLX
PEX8533
x4
PCIe Switch
8
91
x4
0
Figure 1-3. NI PXIe-1075 Backplane Architecture
Link #4
x4
2
x1
2
x4
10
PCIe/PCI
Bridge
PLX
PEX8533
x4
PCIe Switch
0
1
x4
10
x4
9
8
NI PXIe-1075 User Manual1-6ni.com
System Controller Slot
The system controller slot is Slot 1 of the chassis and is a 4-Link
configuration system slot as defined by the CompactPCI Express and
PXI Express specifications. It has three system controller expansion slots
for system controller modules that are wider than one slot. These slots
allow the system controller to expand to the left to prevent the system
controller from using peripheral slots.
The backplane routes each of the system slots’ x4 PCI Express (PCIe) links
to a PCIe switch. The four (4) PCIe switches have x4 PCIe links routed to
each peripheral slot as well as x1 links to two (2) PCIe-to-PCI bridges
providing 32-bit/33 MHz PCI busses to the hybrid slots. Refer to
Figure 1-3 for the connectivity of PCIe and PCI.
By default, the system controller will control the power supply with the
PS_ON# signals. A logic low on this line will turn the power supply on.
Note The Inhibit Mode switch on the rear of the chassis must be in the Default position
for the system controller to have control of the power supply. Refer to the Inhibit Mode
Switch section of Chapter 2, Installation and Configuration, for details about the Inhibit
Mode switch.
Chapter 1Getting Started
Hybrid Peripheral Slots
The chassis provides eight hybrid peripheral slots as defined by the PXI-5
PXI Express Hardware Specification: slots 2–5 and slots 15–18. A hybrid
peripheral slot can accept the following peripheral modules:
•A PXI Express Peripheral with x4 or x1 PCI Express link to the system
slot or through a PCIe switch to the system slot.
•A CompactPCI Express Type-2 Peripheral with x4 or x1 PCI Express
link to the system slot or through a PCIe switch to the system slot.
•A hybrid-compatible PXI Peripheral module that has been modified by
replacing the J2 connector with an XJ4 connector installed in the upper
eight rows of J2. Refer to the PXI Express Specification for details. The
PXI Peripheral communicates through the backplane’s 32-bit PCI bus.
•A CompactPCI 32-bit peripheral on the backplane’s 32-bit PCI bus.
The hybrid peripheral slots provide full PXI Express functionality and
32-bit PXI functionality except for PXI Local Bus. The hybrid peripheral
slot only connects to PXI Local Bus 6 left and right.
There are eight (8) PXI Express peripheral slots: slots 6–9 and 11–14
(=8 slots). PXI Express peripheral slots can accept the following modules:
•A PXI Express Peripheral with x4 or x1 PCI Express link to the system
slot or through a PCIe switch to the system slot.
•A CompactPCI Express Type-2 Peripheral with x4 or x1 PCI Express
link to the system slot or through a PCIe switch to the system slot.
System Timing Slot
The System Timing Slot is slot 10. The system timing slot will accept the
following peripheral modules:
•A PXI Express System Timing Module with x4 or x1 PCI Express link
to the system slot through a PCIe switch.
•A PXI Express Peripheral with x4 or x1 PCI Express link to the system
slot through a PCIe switch.
•A CompactPCI Express Type-2 Peripheral with x4 or x1 PCI Express
link to the system slot through a PCIe switch.
The system timing slot has 3 dedicated differential pairs (PXIe_DSTAR)
connected from the TP1 and TP2 connectors to the XP3 connector for each
PXI Express peripheral or hybrid peripheral slot, as well as routed back to
the XP3 connector of the system timing slot as shown in Figure 1-4. The
PXIe_DSTAR pairs can be used for high-speed triggering, synchronization
and clocking. Refer to the PXI Express Specification for details.
The system timing slot also has a single-ended (PXI Star) trigger connected
to every slot. Refer to Figure 1-4 for details.
The system timing slot has a pin (PXI_CLK10_IN) through which a system
timing module may source a 10MHz clock to which the backplane will
phase-lock. Refer to the System Reference Clock section for details.
The system timing slot has a pin (PXIe_SYNC_CTRL) through which a
system timing module can control the PXIe_SYNC100 timing. Refer to the
PXI Express Specification and the PXIe_SYNC_CTRL section of this
chapter for details.
NI PXIe-1075 User Manual1-8ni.com
Star 8
PXI
PXI Star 7PXI Star 17
PXI Star 6PXI Star 16
PXIe_DStar 5
PXIe_DStar 6
HHHHHHHH
23456789101112131415161718
1
PXI Local Bus
Chapter 1Getting Started
PXI Star 5PXI Star 15
PXI Star 4PXI Star 14
PXI Star 3PXI Star 13
PXI Star 2PXI Star 12
PXI Star 1PXI Star 11
PXI Star 0PXI Star 10
PXIe_DStar 8
PXIe_DStar 0
PXIe_DStar 9
0
PXIe_DStar 10
PXIe_DStar 11
PXIe_DStar 12
PXIe_DStar 16
PXIe_DStar 13
PXIe_DStar 7
PXIe_DStar 4
PXIe_DStar 3
PXIe_DStar 2
PXIe_DStar 1
Figure 1-4. PXIe_DSTAR and PXI Star Connectivity Diagram
The PXI backplane local bus is a daisy-chained bus that connects each
peripheral slot with adjacent peripheral slots to the left and right.
PXIe_DStar 14
PXIe_DStar 15
The backplane routes PXI Local Bus 6 between adjacent PXI slots. The left
local bus 6 from slot 1 is not routed anywhere and the right local bus signal
from slot 18 is not routed anywhere.
Local bus signals may range from high-speed TTL signals to analog signals
as high as 42 V.
Initialization software uses the configuration information specific to each
adjacent peripheral module to evaluate local bus compatibility.
PXI Trigger Bus
All slots on the same PXI bus segment share eight PXI trigger lines. You
can use these trigger lines in a variety of ways. For example, you can use
triggers to synchronize the operation of several different PXI peripheral
modules. In other applications, one module located in the system timing
slot can control carefully timed sequences of operations performed on other
modules in the system. Modules can pass triggers to one another, allowing
precisely timed responses to asynchronous external events the system is
monitoring or controlling.
Note Although any trigger line may be routed in either direction, it cannot be routed in
more than one direction at a time.
The PXI trigger lines from adjacent PXI trigger bus segments can be routed
in either direction across the PXI trigger bridges. Refer to Figure 1-5 for the
connectivity diagram. This allows you to send trigger signals to, and
receive trigger signals from, every slot in the chassis. Static trigger routing
(user-specified line and directional assignments) can be configured through
Measurement & Automation Explorer (MAX). Dynamic routing of triggers
(automatic line assignments) is supported through certain National
Instruments drivers like NI-DAQmx.
PXI
Trigger
Bridge
HHHHHHHH
23456789101112131415161718
1
System Reference Clock
The PXIe-1075 chassis supplies PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 to every peripheral slot with an independent driver for
each signal.
An independent buffer (having a source impedance matched to the
backplane and a skew of less than 1 ns between slots) drives PXI_CLK10
to each peripheral slot. You can use this common reference clock signal to
synchronize multiple modules in a measurement or control system.
PXI Trigger Bus Segment 2 (Slots 7-12)PXI Trigger Bus Segment 1 (Slots 1-6)PXI Trigger Bus Segment 3 (Slots 13-18)
0
PXI
Trigger
Bridge
Figure 1-5. PXI Trigger Bus Connectivity Diagram
NI PXIe-1075 User Manual1-10ni.com
Chapter 1Getting Started
An independent buffer drives PXIe_CLK100 to each peripheral slot. These
clocks are matched in skew to less than 100 ps. The differential pair must
be terminated on the peripheral with LVPECL termination for the buffer to
drive PXIe_CLK100 so that when there is no peripheral or a peripheral that
does not connect to PXIe_CLK100, there is no clock being driven on the
pair to that slot. Refer to Figure 1-6 for a termination example.
CLK100 +
CLK100 –
50 Ω50 Ω
47 Ω0.01 µF
Figure 1-6. CLK100 Termination
+
–
An independent buffer drives PXIe_SYNC100 to each peripheral slot. The
differential pair must be terminated on the peripheral with LVPECL
termination for the buffer to drive PXIe_SYNC100 so that when there is
no peripheral or a peripheral that does not connect to PXIe_SYNC100,
there is no SYNC100 signal being driven on the pair to that slot. Refer to
Figure 1-6 for a termination example.
In summary, PXI_CLK10 is driven to every slot. PXIE_CLK100 and
PXIE_SYNC100 are driven to every peripheral slot.
PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 have the default timing
relationship described in Figure 1-7.
0123 45678 90123 45678 90123 45678 9
PXIe_CLK100
PXI_CLK10
PXIe_SYNC100
Figure 1-7. System Reference Clock Default Behavior
To synchronize the system to an external clock, you can drive PXI_CLK10
from an external source through the PXI_CLK10_IN pin on the System
Timing Slot. Refer to Table B-5, XP4 Connector Pinout for the System
Timing Slot, for the pinout. When a 10MHz clock is detected on this pin,
the backplane automatically phase-locks the PXI_CLK10, PXIe_CLK100,
and PXIe_SYNC100 signals to this external clock and distributes these
signals to the slots. Refer to Appendix A, Specifications, for the
specification information for an external clock provided on the
PXI_CLK10_IN pin of the system timing slot.
You also can drive a 10MHz clock on the 10 MHz REF IN connector on
the rear of the chassis. Refer to Figure 1-2 for the location of this connector.
When a 10MHz clock is detected on this connector, the backplane
automatically phase-locks the PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 signals to this external clock and distributes these signals
to the slots. Refer to Appendix A, Specifications, for the specification
information for an external clock provided on the 10 MHz REF IN
connector on the rear panel of the chassis.
If the 10 MHz clock is present on both the PXI_CLK10_IN pin of the
System Timing Slot and the 10 MHz REF IN connector on the rear of the
chassis, the signal on the System Timing Slot is selected. Refer to Table 1-3
which explains how the 10 MHz clocks are selected by the backplane.
Table 1-3. Backplane External Clock Input Truth Table
System Timing Slot
PXI_CLK10_IN
Rear Chassis Panel
10 MHz REF IN
Backplane PXI_CLK10,
PXIe_CLK100 and PXIe_SYNC100
No clock presentNo clock presentBackplane generates its own clocks
No clock present10 MHz clock presentPXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to
Rear Chassis Panel—10 MHz REF IN
10 MHz clock presentNo clock presentPXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to
System Timing Slot— PXI_CLK10_IN
10 MHz clock present10 MHz clock presentPXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to
System Timing Slot—PXI_CLK10__IN
NI PXIe-1075 User Manual1-12ni.com
PXIe_SYNC_CTRL
Chapter 1Getting Started
A copy of the backplane’s PXI_CLK10 is exported to the 10 MHz REF
OUT connector on the rear of the chassis. Refer to Figure 1-2 for the
location of this connector. This clock is driven by an independent buffer.
Refer to Appendix A, Specifications, for the specification information for
the 10 MHz REF OUT signal on the rear panel of the chassis.
PXIe_SYNC100 is by default a 10 ns pulse synchronous to PXI_CLK10.
The frequency of PXIe_SYNC100 is 10/n MHz, where n is a positive
integer. The default for n is 1, giving PXIe_SYNC100 a 100 ns period.
However, the backplane allows n to be programmed to other integers. For
instance, setting n = 3 gives a PXIe_SYNC100 with a 300ns period while
still maintaining its phase relationship to PXI_CLK10. The value for n may
be set to any positive integer from 1 to 255.
The system timing slot has a control pin for PXIe_SYNC100 called
PXIe_SYNC_CTRL for use when n > 1. Refer to Table B-6, XP3
Connector Pinout for the System Timing Slot, for system timing slot pinout.
Refer to Appendix A, Specifications, for the PXIe_SYNC_CTRL input
specifications.
By default, a high-level detected by the backplane on the
PXIe_SYNC_CTRL pin causes a synchronous restart for the
PXIe_SYNC100 signal. On the next PXI_CLK10 edge the
PXIe_SYNC100 signal will restart. This will allow several chassis to have
their PXIe_SYNC100 in phase with each other. Refer to Figure 1-8 for
timing details with this method.
PXI_CLK10
PXIe_SYNC_CTRL
PXIe_SYNC100
SYNC100 Divider
Restarted Here
Figure 1-8. PXIe_SYNC100 at 3.33 MHz Using PXIe_SYNC_CTRL as Restart
This chapter describes how to prepare and operate the NI PXIe-1075
chassis.
Before connecting the chassis to a power source, read this chapter and
the Read Me First: Safety and Radio-Frequency Interference document
included with your kit.
Safety Information
Caution Before undertaking any troubleshooting, maintenance, or exploratory procedure,
carefully read the following caution notices.
This equipment contains voltage hazardous to human life and safety, and is
capable of inflicting personal injury.
•Chassis Grounding—The chassis requires a connection from the
premise wire safety ground to the chassis ground. The earth safety
ground must be connected during use of this equipment to minimize
shock hazards. Refer to the Connecting Safety Ground section for
instructions on connecting safety ground.
•Live Circuits—Operating personnel and service personnel must not
remove protective covers when operating or servicing the chassis.
Adjustments and service to internal components must be undertaken
by qualified service technicians. During service of this product,
the mains connector to the premise wiring must be disconnected.
Dangerous voltages may be present under certain conditions;
use extreme caution.
•Explosive Atmosphere—Do not operate the chassis in conditions
where flammable gases are present. Under such conditions, this
equipment is unsafe and may ignite the gases or gas fumes.
•Part Replacement—Only service this equipment with parts that are
exact replacements, both electrically and mechanically. Contact
National Instruments for replacement part information. Installation of
parts with those that are not direct replacements may cause harm to
personnel operating the chassis. Furthermore, damage or fire may
occur if replacement parts are unsuitable.
•Modification—Do not modify any part of the chassis from its original
condition. Unsuitable modifications may result in safety hazards.
Chassis Cooling Considerations
The NI PXIe-1075 chassis is designed to operate on a bench or in an
instrument rack. Regardless of the configuration you must provide the
cooling clearances as outlined in the following sections.
Providing Adequate Clearance
The primary cooling exhaust vent for the NI PXIe-1075 is on the top of the
chassis. The primary intake vent is on the rear of the chassis where the air
is filtered as it enters the power supply shuttle. The secondary intake and
exhaust vents are located along the sides of the chassis. Adequate clearance
between the chassis and surrounding equipment or blockages must be
maintained to ensure proper cooling of the chassis power supply as well
as the modules plugged into the chassis. These clearances are outlined in
Figure 2-1. The vent locations for the NI PXIe-1075 chassis are shown
in Figure 2-2. Failure to provide these clearances may result in
thermal-related failures in the chassis or modules.
1 Primary Air Exhaust Vent
2 Air Filter
3 Primary Air Intake Vent
3 Secondary Air Intake/Exhaust Vents
(both sides)
Figure 2-2. NI PXIe-1075 Vents
Chassis Ambient Temperature Definition
The chassis fan control system uses intake air temperature as the input for
controlling fan speeds when in Auto Fan Speed mode. Because of this, the
chassis ambient temperature is defined as the temperature that exists just
outside of the fan intake vents on the rear of the chassis. Note that this
temperature may be higher than ambient room temperature depending on
the surrounding equipment and/or blockages present. It is the user’s
NI PXIe-1075 User Manual2-4ni.com
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