National Instruments NI cDAQ-9181, NI cDAQ-9188, NI cDAQ-9184, NI cDAQ-9191 User Manual

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Page 1

NI cDAQTM-9181/9184/9188/9191

User Manual

NI CompactDAQ Ethernet and Ethernet/Wireless Chassis

NI cDAQ-9181/9184/9188/9191 User Manual

February 2017 372780K-01

Page 2

Support

Worldwide Technical Support and Product Information

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For further support information, refer to the NI Services appendix. To comment on NI documentation, refer to the NI website at ni.com/info and enter the Info Code feedback.

Page 3

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Page 5

Chapter 1 Getting Started with the cDAQ Chassis

Safety Guidelines.............................................................................................................. 1-3

Electromagnetic Compatibility Guidelines ...................................................................... 1-3

Special Guidelines for Marine Applications ............................................................ 1-4

Hardware Symbol Definitions .......................................................................................... 1-4

Unpacking......................................................................................................................... 1-5

Installing the cDAQ Chassis............................................................................................. 1-5

Wiring Power to the cDAQ Chassis ................................................................................. 1-13

Troubleshooting Chassis Connectivity............................................................................. 1-14

Reserving the Chassis in MAX ........................................................................................ 1-15

QoS Priority...................................................................................................................... 1-15

Mounting the cDAQ Chassis............................................................................................ 1-16

Using the cDAQ Chassis on a Desktop .................................................................... 1-17

NI 9901 Desktop Kit for cDAQ-9184/9188 Chassis........................................ 1-17

Mounting the cDAQ Chassis on a Panel .................................................................. 1-17

cDAQ-9181/9191 ............................................................................................. 1-18

cDAQ-9184/9188 ............................................................................................. 1-21

Mounting the cDAQ Chassis on a DIN Rail ............................................................ 1-23

cDAQ-9181/9191 ............................................................................................. 1-24

cDAQ-9184/9188 ............................................................................................. 1-25

cDAQ Chassis Features .................................................................................................... 1-26

Chassis Grounding Screw......................................................................................... 1-26

LEDs......................................................................................................................... 1-26

Ethernet Port ............................................................................................................. 1-28

Ethernet LEDs .................................................................................................. 1-28

Ethernet Cabling ............................................................................................... 1-29

Reset Button ............................................................................................................. 1-30

Power Connector ...................................................................................................... 1-30

PFI BNC Connectors ................................................................................................

Antenna..................................................................................................................... 1-30

Cables and Accessories .................................................................................................... 1-31

Removing Modules from the cDAQ Chassis ................................................................... 1-31

Using the cDAQ Chassis .................................................................................................. 1-32

C Series Module ....................................................................................................... 1-32

Parallel versus Serial DIO Modules ................................................................. 1-33

cDAQ Module Interface ........................................................................................... 1-33

STC3......................................................................................................................... 1-33

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Contents

Chapter 2 Analog Input

Analog Input Triggering Signals ...................................................................................... 2-1

Analog Input Timing Signals............................................................................................ 2-2

AI Sample Clock Signal ........................................................................................... 2-2

Routing the Sample Clock to an Output Terminal ........................................... 2-2

AI Sample Clock Timebase Signal ........................................................................... 2-2

AI Convert Clock Signal Behavior For Analog Input Modules ............................... 2-3

Scanned Modules.............................................................................................. 2-3

Simultaneous Sample-and-Hold Modules ........................................................ 2-3

Sigma-Delta Modules .......................................................................................2-3

Slow Sample Rate Modules.............................................................................. 2-4

AI Start Trigger Signal ............................................................................................. 2-5

Using a Digital Source ...................................................................................... 2-5

Using an Analog Source ................................................................................... 2-5

Routing AI Start Trigger to an Output Terminal .............................................. 2-5

AI Reference Trigger Signal..................................................................................... 2-5

Using a Digital Source ...................................................................................... 2-6

Using an Analog Source ................................................................................... 2-6

Routing the Reference Trigger Signal to an Output Terminal.......................... 2-6

AI Pause Trigger Signal............................................................................................ 2-7

Using a Digital Source ...................................................................................... 2-7

Using an Analog Source ................................................................................... 2-7

Getting Started with AI Applications in Software ............................................................ 2-7

Chapter 3 Analog Output

Analog Output Data Generation Methods ........................................................................3-1

Software-Timed Generations .................................................................................... 3-1

Hardware-Timed Generations................................................................................... 3-2

Buffered Analog Output ................................................................................... 3-2

Analog Output Triggering Signals.................................................................................... 3-3

Analog Output Timing Signals ......................................................................................... 3-3

AO Sample Clock Signal .......................................................................................... 3-3

Routing AO Sample Clock to an Output Terminal........................................... 3-4

AO Sample Clock Timebase Signal ......................................................................... 3-4

AO Start Trigger Signal ............................................................................................3-4

Using a Digital Source ...................................................................................... 3-4

Using an Analog Source ................................................................................... 3-4

Routing AO Start Trigger Signal to an Output Terminal ................................. 3-4

AO Pause Trigger Signal .......................................................................................... 3-5

Using a Digital Source ...................................................................................... 3-5

Using an Analog Source ................................................................................... 3-6

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NI cDAQ-9181/9184/9188/9191 User Manual

Minimizing Glitches on the Output Signal....................................................................... 3-6

Getting Started with AO Applications in Software .......................................................... 3-6

Chapter 4 Digital Input/Output and PFI

Digital Input/Output ......................................................................................................... 4-1

Serial DIO versus Parallel DIO Modules ................................................................. 4-1

Static DIO ................................................................................................................. 4-2

Digital Input.............................................................................................................. 4-2

Digital Input Triggering Signals....................................................................... 4-2

Digital Input Timing Signals ............................................................................ 4-2

Digital Input Filters .......................................................................................... 4-6

Getting Started with DI Applications in Software............................................ 4-7

Change Detection Event ........................................................................................... 4-7

Routing Change Detection Event to an Output Terminal................................. 4-7

Change Detection Acquisition.......................................................................... 4-7

Digital Output ........................................................................................................... 4-8

Digital Output Data Generation Methods......................................................... 4-8

Digital Output Triggering Signals .................................................................... 4-10

Digital Output Timing Signals ......................................................................... 4-10

Getting Started with DO Applications in Software .......................................... 4-13

Digital Input/Output Configuration for NI 9401 ...................................................... 4-13

PFI .................................................................................................................................... 4-13

PFI Filters ................................................................................................................. 4-13

Chapter 5 Counters

Counter Timing Engine .................................................................................................... 5-2

Counter Input Applications .............................................................................................. 5-3

Counting Edges......................................................................................................... 5-3

Single Point (On-Demand) Edge Counting ...................................................... 5-3

Buffered (Sample Clock) Edge Counting......................................................... 5-4

Controlling the Direction of Counting.............................................................. 5-5

Pulse-Width Measurement ....................................................................................... 5-5

Single Pulse-Width Measurement .................................................................... 5-6

Implicit Buffered Pulse-Width Measurement................................................... 5-6

Sample Clocked Buffered Pulse-Width Measurement ..................................... 5-6

Pulse Measurement................................................................................................... 5-7

Single Pulse Measurement................................................................................ 5-8

Implicit Buffered Pulse Measurement .............................................................. 5-8

Sample Clocked Buffered Pulse Measurement ................................................ 5-8

Semi-Period Measurement ....................................................................................... 5-9

Single Semi-Period Measurement .................................................................... 5-9

Implicit Buffered Semi-Period Measurement................................................... 5-10

Pulse versus Semi-Period Measurements ......................................................... 5-10

Page 8

Contents

Frequency Measurement........................................................................................... 5-11

Low Frequency with One Counter.................................................................... 5-11

High Frequency with Two Counters................................................................. 5-12

Large Range of Frequencies with Two Counters .............................................5-12

Sample Clocked Buffered Frequency Measurement ........................................ 5-13

Choosing a Method for Measuring Frequency ................................................. 5-14

Which Method Is Best?..................................................................................... 5-16

Period Measurement ................................................................................................. 5-18

Position Measurement...............................................................................................5-19

Measurements Using Quadrature Encoders...................................................... 5-19

Channel Z Behavior .................................................................................................. 5-20

Measurements Using Two Pulse Encoders....................................................... 5-21

Buffered (Sample Clock) Position Measurement ............................................. 5-21

Two-Signal Edge-Separation Measurement ............................................................. 5-21

Single Two-Signal Edge-Separation Measurement .......................................... 5-22

Implicit Buffered Two-Signal Edge-Separation Measurement ........................5-22

Sample Clocked Buffered Two-Signal Separation Measurement .................... 5-23

Counter Output Applications ............................................................................................ 5-24

Simple Pulse Generation........................................................................................... 5-24

Single Pulse Generation .................................................................................... 5-24

Single Pulse Generation with Start Trigger ...................................................... 5-25

Pulse Train Generation ............................................................................................. 5-25

Finite Pulse Train Generation ........................................................................... 5-25

Retriggerable Pulse or Pulse Train Generation................................................. 5-26

Continuous Pulse Train Generation .................................................................. 5-27

Buffered Pulse Train Generation ...................................................................... 5-28

Finite Implicit Buffered Pulse Train Generation .............................................. 5-28

Continuous Buffered Implicit Pulse Train Generation ..................................... 5-29

Finite Buffered Sample Clocked Pulse Train Generation ................................ 5-29

Continuous Buffered Sample Clocked Pulse Train Generation ....................... 5-30

Frequency Generation............................................................................................... 5-30

Using the Frequency Generator ........................................................................ 5-30

Frequency Division................................................................................................... 5-31

Pulse Generation for ETS ......................................................................................... 5-32

Counter Timing Signals .................................................................................................... 5-32

Counter n Source Signal ........................................................................................... 5-33

Routing a Signal to Counter n Source ..............................................................5-33

Routing Counter n Source to an Output Terminal ............................................5-34

Counter n Gate Signal............................................................................................... 5-34

Routing a Signal to Counter n Gate .................................................................. 5-34

Routing Counter n Gate to an Output Terminal ............................................... 5-34

Counter n Aux Signal ............................................................................................... 5-35

Routing a Signal to Counter n Aux...................................................................5-35

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NI cDAQ-9181/9184/9188/9191 User Manual

Counter n A, Counter n B, and Counter n Z Signals ................................................ 5-35

Routing Signals to A, B, and Z Counter Inputs................................................ 5-35

Routing Counter n Z Signal to an Output Terminal ......................................... 5-35

Counter n Up_Down Signal ..................................................................................... 5-35

Counter n HW Arm Signal ....................................................................................... 5-35

Routing Signals to Counter n HW Arm Input .................................................. 5-36

Counter n Sample Clock Signal................................................................................ 5-36

Using an Internal Source .................................................................................. 5-36

Using an External Source ................................................................................. 5-37

Routing Counter n Sample Clock to an Output Terminal ................................ 5-37

Counter n Internal Output and Counter n TC Signals .............................................. 5-37

Routing Counter n Internal Output to an Output Terminal .............................. 5-37

Frequency Output Signal .......................................................................................... 5-37

Routing Frequency Output to a Terminal ......................................................... 5-37

Default Counter/Timer Routing........................................................................................ 5-37

Counter Triggering ........................................................................................................... 5-38

Other Counter Features..................................................................................................... 5-38

Cascading Counters .................................................................................................. 5-38

Prescaling.................................................................................................................. 5-39

Synchronization Modes ............................................................................................ 5-39

80 MHz Source Mode....................................................................................... 5-39

External or Internal Source Less than 20 MHz ................................................ 5-40

Chapter 6 Digital Routing and Clock Generation

Digital Routing .................................................................................................................6-1

Clock Routing...................................................................................................................6-1

80 MHz Timebase .................................................................................................... 6-2

20 MHz Timebase .................................................................................................... 6-2

100 kHz Timebase .................................................................................................... 6-2

Appendix A cDAQ-9191 Regulatory Information

Appendix B Where to Go from Here

Appendix C NI Services

Index

Page 10

Getting Started with the cDAQ Chassis

This chapter provides a cDAQ chassis overview and lists information about mounting the chassis and installing C Series modules.

The one-slot NI CompactDAQ cDAQ-9181, four-slot CompactDAQ cDAQ-9184, and eight-slot CompactDAQ cDAQ-9188 Ethernet chassis and the one-slot CompactDAQ cDAQ-9191 Ethernet/wireless chassis are designed for use with C Series modules. The cDAQ chassis are capable of measuring a broad range of analog and digital I/O signals and sensors. For module specifications, refer to the documentation included with your C Series module(s) or go

ni.com/manuals.

Figure 1-1 shows the cDAQ-9181/9191 chassis.

Figure 1-1. cDAQ-9181/9191 Chassis

1 (cDAQ-9191) Antenna and Antenna Connector 2 Power Connector 3 Ethernet Port, 10/100 and LINK/ACT LEDs 4 Reset Button

5 POWER, STATUS, and ACTIVE LEDs 6 (cDAQ-9191) Wireless Signal Strength LEDs 7 Chassis Grounding Screw 8 Module Slot

Page 11

Chapter 1 Getting Started with the cDAQ Chassis

123 45

NI cDAQ-9188

NI CompactDAQ

Figure 1-2 shows the cDAQ-9184 chassis.

Figure 1-2. cDAQ-9184 Chassis

NI cDAQ-9184

NI CompactDAQ

1 Chassis Grounding Screw 2 Installed C Series Module 3 Module Slots 4 Ethernet Port, LINK/ACT and 10/100/1000 LEDs

Figure 1-3 shows the cDAQ-9188 chassis.

Figure 1-3. cDAQ-9188 Chassis

5 Power Connector 6 Reset Button

7 POWER, STATUS, and ACTIVE LEDs

1 Chassis Grounding Screw 2 Installed C Series Module 3 Module Slots 4 Power Connector

5 Reset Button 6 PFI 0 and PFI 1 BNC Connectors 7 Ethernet Port, LINK/ACT and 10/100/1000 LEDs 8 POWER, STATUS, and ACTIVE LEDs

1-2 | ni.com

Page 12

NI cDAQ-9181/9184/9188/9191 User Manual

Safety Guidelines

Caution Do not operate the NI cDAQ-9181/9184/9188/9191 chassis in a manner

not specified in these operating instructions. Product misuse can result in a hazard. You can compromise the safety protection built into the product if the product is damaged in any way. If the product is damaged, return it to National Instruments for repair.

Note Because some C Series modules may have more stringent certification

standards than the NI cDAQ-9181/9184/9188/9191 chassis, the combined system may be limited by individual component restrictions. Refer to the specifications document for your cDAQ chassis for more details.

Hot Surface This icon denotes that the component may be hot. Touching this

component may result in bodily injury.

Electromagnetic Compatibility Guidelines

This product was tested and complies with the regulatory requirements and limits for electromagnetic compatibility (EMC) stated in the product specifications. These requirements and limits provide reasonable protection against harmful interference when the product is operated in the intended operational electromagnetic environment.

This product is intended for use in industrial locations. However, harmful interference may occur in some installations or when the product is connected to a peripheral device or a test object. To minimize interference with radio and television reception and prevent unacceptable performance degradation, install and use this product in strict accordance with the instructions in the product documentation.

Furthermore, any modifications to the product not expressly approved by National Instruments could void your authority to operate it under your local regulatory rules.

Caution To ensure the specified EMC performance, operate this product only with

shielded cables and accessories.

Caution To ensure the specified EMC performance, the length of any I/O cable

connected to a BNC PFI port must be no longer than 30 m (100 ft).

Caution To ensure the specified EMC performance, do not connect the power input

to a DC mains supply or to any supply requiring a connecting cable longer than 3 m (10 ft). A DC mains supply is a local DC electricity supply network in the infrastructure of a site or building.

Page 13

Chapter 1 Getting Started with the cDAQ Chassis

⬉ᄤֵᙃѻક∵ᶧ᥻ࠊㅵ⧚ࡲ⊩ ˄Ё೑ ˅

Ё೑ᅶ᠋

National Instruments

ヺড়Ё೑⬉ᄤֵᙃѻકЁ䰤ࠊՓ⫼ᶤѯ᳝ᆇ⠽䋼ᣛҸ

(RoHS)

Ǆ݇Ѣ

National InstrumentsЁ೑RoHS

ড়㾘ᗻֵᙃˈ䇋ⱏᔩ

ni.com/

environment/rohs_china

(For information about China RoHS compliance,

go to

ni.com/environment/rohs_china

Special Guidelines for Marine Applications

Some products are Lloyd’s Register (LR) Type Approved for marine (shipboard) applications. To verify Lloyd’s Register certification for a product, visit

ni.com/certification and

search for the LR certificate, or look for the Lloyd’s Register mark on the product label.

Caution In order to meet the EMC requirements for marine applications, install the

product in a shielded enclosure with shielded and/or filtered power and input/output ports. In addition, take precautions when designing, selecting, and installing measurement probes and cables to ensure that the desired EMC performance is attained.

Hardware Symbol Definitions

The following symbols are marked on your cDAQ chassis.

Caution When this symbol is marked on a product, refer to the Safety Guidelines

section for information about precautions to take.

ESD When this symbol is marked on a product, the product could be damaged if

subjected to Electrostatic Discharge (ESD) on the connector pins of any I/O port. To prevent damage, industry-standard ESD prevention measures must be employed during installation, maintenance, and operation.

EU Customers At the end of the product life cycle, all products must be sent to

a WEEE recycling center. For more information about WEEE recycling centers, National Instruments WEEE initiatives, and compliance with WEEE Directive 2002/96/EC on Waste and Electronic Equipment, visit

weee

ni.com/environment/

1-4 | ni.com

Page 14

NI cDAQ-9181/9184/9188/9191 User Manual

Unpacking

The cDAQ chassis ships in an antistatic package to prevent electrostatic discharge (ESD). ESD can damage several components on the device.

Caution Never touch the exposed pins of connectors.

To avoid ESD damage in handling the chassis, take the following precautions:

• Ground yourself with a grounding strap or by touching a grounded object.

• Touch the antistatic package to a metal part of your computer chassis before removing the chassis from the package.

Remove the chassis from the package and inspect it for loose components or any other signs of damage. Notify NI if the device appears damaged in any way. Do not install a damaged chassis.

Store the chassis in the antistatic package when the chassis is not in use.

Installing the cDAQ Chassis

The cDAQ chassis and C Series module(s) are packaged separately. For an interactive demonstration of how to install the cDAQ chassis, go to

cdaqinstall.

You will need the following items to set up the cDAQ chassis:

• Power adapter or power connector (packaged with the cDAQ chassis)

• Shielded straight through Category 5 Ethernet cable

• Antenna (packaged with the cDAQ-9191 chassis)

• Screwdriver (packaged with the cDAQ chassis)

• Host computer running Windows

• Application software (such as LabVIEW), if not already installed

• NI-DAQmx driver (packaged with the cDAQ chassis)

• Power supply (if using the power connector instead of the power adapter)

• Number 1 and number 2 Phillips screwdrivers

• C Series module(s)

ni.com/info and enter

You can either use a shielded straight through Category 5 Ethernet cable or an Ethernet crossover cable to connect the cDAQ chassis directly to your computer.

Page 15

Chapter 1 Getting Started with the cDAQ Chassis

Refer to Figure 1-1, 1-2, or 1-3 while completing the following assembly steps.

1. Install the application software (if applicable), as described in the installation instructions that accompany your software.

2. Install NI-DAQmx. Insert the software media. If the NI-DAQmx installer does not open automatically, select Start»Run. Enter x:\autorun.exe, where x is the drive letter. Complete the instructions.

3. Register your NI hardware online at

ni.com/register when prompted.

4. The last dialog box opens with the following options.

• Restart Later to install more NI software or documentation.

• Shut Down or Restart if you are ready to install your device.

• Restart if you are using a system running the LabVIEW Real-Time Module.

Download NI-DAQmx to the target using MAX. Refer to the MAX Remote Systems Help by selecting Help»Help Topics»Remote Systems in MAX.

5. If you have problems installing your software, go to

Note Table 1-1 lists the earliest NI-DAQmx support version for each cDAQ

ni.com/support/daqmx.

Ethernet and wireless chassis.

Table 1-1. cDAQ Chassis NI-DAQmx Software Support

cDAQ Chassis Earliest NI-DAQmx Version Support

cDAQ-9181 NI-DAQmx 9.3

cDAQ-9184 NI-DAQmx 9.6

cDAQ-9188 NI-DAQmx 9.2

cDAQ-9191 NI-DAQmx 9.4

The NI-DAQmx software is included on the disk shipped with your kit and is available for download at

ni.com/support. The documentation for NI-DAQmx is available after

installation from Start»All Programs»National Instruments»NI-DAQmx. Other NI documentation is available from ni.com/manuals.

6. (Optional) Mount the cDAQ chassis to a panel, wall, or DIN rail, or attach the desktop mounting kit, as described in the Mounting the cDAQ Chassis section.

7. Attach a ring lug to a 1.31 mm

(16 AWG) or larger wire. Connect the ring lug to the chassis ground terminal using the chassis grounding screw as shown in Figure 1-4. Attach the other end of the wire to the grounding electrode system of your facility. Refer to the Chassis

Grounding Screw section for more information about making this connection.

1-6 | ni.com

Page 16

NI cDAQ-9181/9184/9188/9191 User Manual

Note If you use shielded cabling to connect to a C Series module with a plastic

connector, you must attach the cable shield to the chassis grounding terminal using

1.31 mm

(16 AWG) or larger wire. Use shorter wire for better EMC performance.

Figure 1-4. Ring Lug Attached to Chassis Ground Terminal

8. Make sure that no signals are connected to the C Series module.

9. Align the C Series module with the cDAQ chassis slot.

10. Squeeze both C Series module latches, insert the module into the module slot, and press until both latches lock the module in place.

11. Wire the C Series module as indicated in the C Series module documentation.

Note Connect I/O cable shields to the chassis grounding screw, shown in

Figure 1-4, unless otherwise specified in the C Series module documentation. Refer to the Chassis Grounding Screw section for more information about making this connection.

12. Connect one end of the Ethernet cable to the Ethernet port on the chassis, and the other end directly to your computer or any network connection on the same subnet as your computer. Refer to the Ethernet Cabling section for information about the Ethernet cable.

13. (cDAQ-9191) If you want to connect the cDAQ-9191 to a wireless network, attach the supplied antenna.

14. Power the chassis using the included power adapter or other 9 V DC to 30 V DC power source. The cDAQ chassis requires an external power supply that meets the specifications listed in the specifications document for your cDAQ chassis. For information about wiring your external power source, refer to the Wiring Power to the cDAQ Chassis section

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Chapter 1 Getting Started with the cDAQ Chassis

Caution When operating the cDAQ-9181/9184/9188/9191 in hazardous locations,

you must use the power connector with a power supply rated for hazardous locations. The power supply included in the cDAQ-9181/9184/9188/9191 kit is not hazardous locations-certified. Visit

ni.com to find hazardous locations-certified power

supplies.

The POWER and STATUS LEDs light. The POWER LED lights as long as power is being supplied to the cDAQ chassis. The STATUS LED turns off after firmware boots. Refer to the LEDs section for information about the LEDs on the cDAQ chassis.

15. (cDAQ-9191) If you want to connect the cDAQ-9191 to a wireless network, complete the following steps:

a. Double-click the NI MAX icon, on the desktop to open Measurement & Automation

Explorer (MAX). Expand Devices and Interfaces»Network Devices.

b. Select the chassis and click the Network Settings tab. If your chassis is not listed,

refer to the Finding a Network DAQ Device in MAX topic in the Measurement & Automation Explorer Help for NI-DAQmx.

c. Select your country.

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NI cDAQ-9181/9184/9188/9191 User Manual

d. Select a wireless network in one of the following ways:

• To connect to an existing wireless network, select Connect to wireless network as the Wireless Mode.

Figure 1-5. Connecting to a Wireless Network

Before connecting to an enterprise network, you may first need to upload a certificate by clicking Certificate Management. Contact your IT department if you are unsure of your network settings or configuration details.

Note For EAP-TLS authentication, you must also upload a private key file with

client certificate.

Click Wireless Network to search for and select a network from the scanned list, or select Other Network and enter settings. Click Save to apply network selection changes.

• To establish an ad-hoc network, select Create a Wireless Network.

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Chapter 1 Getting Started with the cDAQ Chassis

Note To set a QoS Priority for the cDAQ chassis, click More Settings and select a

priority from the list. The default QoS priority is Normal, which should be sufficient for most applications.

e. Click the Save button. The Wireless Adapter wlan0 section displays the network

search status:

Scanning, Associating, and Connected to <network>.

f. Click the Settings tab and verify that the chassis has a wireless IP address (along with

the Ethernet IP address); if the System State reads

Connected - Running, the

cDAQ chassis is connected to the wireless network.

Figure 1-6. Chassis Connected - Running on Ethernet and Wireless Networks

1 Ethernet IP Address 2 Wireless IP Address

Note Establishing a network connection may take several seconds.

Note For more information about MAX configuration for the cDAQ-9191, refer to

the Configuring the Wireless Settings for an NI cDAQ-919x topic in the Measurement & Automation Explorer Help for NI-DAQmx.

NI recommends setting QoS Priority to Normal if you are connecting to an existing wireless network. Setting the QoS Priority to High or Critical might affect the performance of other devices on your wireless network. Refer to the QoS Priority section for more information.

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16. To add the chassis, double-click the NI MAX icon on the desktop to open MAX. Expand Devices and Interfaces»Network Devices.

• If the wired or wireless connection is on your local subnet, the chassis automatically

appears in the list of available devices. Right-click the cDAQ chassis and select Add Device.

• If neither connection is on your local subnet, right-click Network Devices and select

Find Network NI-DAQmx Devices.

• If you know the chassis IP address, such as 192.168.0.2, enter it into the Add Device

Manually field, and click the + button.

Otherwise, enter the hostname of the chassis. The default hostname is cDAQ91xx-<serial number>, where the xx represents the last two digits of your cDAQ chassis model number.

The cDAQ chassis icon changes from grey to blue, indicating that it is recognized and present on the network.

Figure 1-7. MAX Icons and States

1 Discovered, But Not Added to the Network 2 Recognized, Present, and Reserved on the Network

If your chassis does not appear in Available Devices, click Refresh List. If the chassis still does not appear, try the following:

• If you connected the cDAQ chassis directly to your computer, ensure your network

card is configured to obtain an IP address automatically, then click Refresh List.

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Chapter 1 Getting Started with the cDAQ Chassis

Note If you connected the cDAQ chassis directly to your computer, the setup time

may be longer. Wait 30 to 60 seconds after the STATUS LED turns off, then click Refresh List.

• Contact your system administrator to confirm that the network is working and that a firewall is not interfering with discovery. For additional troubleshooting resources for the cDAQ chassis, refer to the Troubleshooting Chassis Connectivity section of this manual and the Finding a Network DAQ Device in MAX topic in the Measurement & Automation Explorer Help for NI-DAQmx.

(cDAQ-9191) Disconnect the Ethernet cable from cDAQ-9191 chassis if you connected

17. the chassis to a wireless network in step 15.

Note Your computer must be connected to a network that can access the chassis at

its wireless IP.

18.

(cDAQ-9191) Verify that the cDAQ-9191 chassis is connected to the wireless network by

clicking the Refresh button in MAX and verifying that the Ethernet IP address is and the wireless IP address remains the same as in step 15.

Figure 1-8. Chassis Connected - Running on Wireless Network

0.0.0.0

1 Ethernet IP Address 2 Wireless IP Address

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NI cDAQ-9181/9184/9188/9191 User Manual

19. If the cDAQ chassis is not reserved automatically, select the chassis and click the Reserve Chassis button. Refer to the Reserving the Chassis in MAX section for more information.

20. Self-test your chassis in MAX by expanding Devices and Interfaces, right-clicking NI cDAQ-<model number>, and selecting Self-Test. Self-test performs a brief test to

determine successful chassis installation. When the self-test finishes, a message indicates successful verification or if an error occurred. If an error occurs, refer to

support/daqmx

21. Run a Test Panel in MAX by expanding Devices and Interfaces» NI cDAQ-<model number>, right-clicking your C Series module, and selecting Test Panels to open a test

panel for the selected module.

If the test panel displays an error message, refer to ni.com/support.

Click Close to exit the test panel.

Note When in use, the cDAQ chassis may become warm to the touch. This is

normal.

ni.com/

Wiring Power to the cDAQ Chassis

Caution To ensure the specified EMC performance, do not connect the power input

to a DC mains supply or to any supply requiring a connecting cable longer than 3 m (10 ft). A DC mains supply is a local DC electricity supply network in the infrastructure of a site or building.

The cDAQ chassis requires an external power source as described in the Power Requirements section of the specifications document for your cDAQ chassis. Some suggested NI power supplies are listed in Table 1-8. The cDAQ chassis filters and regulates the supplied power and provides power to all of the modules. The green POWER LED on the front panel identifies when the power input is in use.

Complete the following steps to connect a power source to the cDAQ chassis.

1. Make sure the power source is turned off.

2. If connected, loosen the connector screw flanges and remove the power screw terminal connector plug from the cDAQ chassis. Figure 1-9 shows the terminal screws, which secure the wires in the screw terminals, and the connector screw flanges, which secure the connector plug on the front panel.

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Chapter 1 Getting Started with the cDAQ Chassis

Figure 1-9. Power Screw Terminal Connector Plug

1 V (Positive) Terminal Screw 2 C (Negative) Terminal Screw

Caution Do not tighten or loosen the terminal screws on the power connector while

3 Connector Screw Flanges

the power is on.

3. Connect the positive lead of the power source to the V terminal of the power connector plug and tighten the terminal screw.

4. Connect the negative lead of the power source to the C terminal of the power screw terminal connector plug and tighten the terminal screw.

5. Install the power connector plug on the front panel of the cDAQ chassis and tighten the connector screw flanges.

6. Turn on the external power source(s).

If the power source is connected to the power connector using long wiring with high DC resistance, the voltage at the power connector may be significantly lower than the specified voltage of the power source.

The C terminal is not connected to chassis ground. You can connect the C terminal to chassis ground externally. Refer to the Power Requirements section of the specifications document for your cDAQ chassis for information about the power supply input range. Refer to the Safety Voltages section of the specifications document for your cDAQ chassis for information about the maximum voltage from terminal to chassis ground.

Troubleshooting Chassis Connectivity

If your cDAQ chassis becomes disconnected from the network, try the following:

• After moving the chassis to a new network, NI-DAQmx may lose connection to the chassis. In this case, click Reconnect to provide NI-DAQmx with the new hostname or IP address.

• The cDAQ chassis icon indicates whether it is recognized and present on the network. If a connected chassis appears as disconnected in the configuration tree in MAX, select Self-Test or Reset Chassis. If successful, the chassis icon changes to blue.

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NI cDAQ-9181/9184/9188/9191 User Manual

Figure 1-10. MAX Icons and States

1 Recognized, but Disconnected from the Network, Unreserved, or Reserved by Another Host 2 Recognized, Present, and Reserved on the Network

For additional troubleshooting resources for the cDAQ chassis, refer to the Finding a Network DAQ Device in MAX topic in the Measurement & Automation Explorer Help for NI-DAQmx.

Reserving the Chassis in MAX

When the cDAQ chassis is connected to a network, multiple users can access the chassis. To perform any DAQ functionality on the C Series modules, including reset chassis and self-test, you must reserve the cDAQ chassis in MAX. Figure 1-10 depicts the chassis state icons in MAX: an unreserved chassis or chassis reserved by another host appear with an X and reserved chassis appear as blue. Only one user at a time can reserve the cDAQ chassis.

If the cDAQ chassis was not reserved automatically after it was added (Add Device), you can reserve the cDAQ chassis in MAX by expanding Devices and Interfaces»Network Devices, selecting the chassis, and clicking the Reserve Chassis button. The Override Reservation dialog box appears when you attempt to explicitly reserve a chassis. Agreeing to override the reservation forces the cDAQ chassis to be reserved by the current user.

QoS Priority

(cDAQ-9191) The QoS Priority sets the priority for the data transferred over the wireless

network adapter when the wireless device is sharing the channel with one or more devices. There are four priorities: Disabled, Normal, High, and Critical, as described in Table 1-2. The default is Normal.

Table 1-2. QoS Priority

MAX Option QoS 802.11e Standard

Disabled Disabled —

Normal (default) Enabled Best effort

High Enabled Video

Critical Enabled Vo i c e

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Chapter 1 Getting Started with the cDAQ Chassis

You can set or update the QoS Priority at any time when connected to a wireless network. In MAX, expand Devices and Interfaces»Network Devices, select the chassis, click the Network Settings tab, click More Settings, and select a priority.

NI recommends setting the QoS Priority to Normal if you are connecting to an existing wireless network. Setting the QoS Priority to High or Critical might affect the performance of other devices on your wireless network.

When using the wireless QoS feature, verify that WMM/QoS is enabled in your access point/ router settings.

Note Ad Hoc networks do not support wireless QoS.

Mounting the cDAQ Chassis

You can use the cDAQ chassis on a desktop or mount it to a panel, wall, or DIN rail. For accessory ordering information, refer to the pricing section of your cDAQ chassis product page

ni.com.

Caution Your installation must meet the following requirements:

• Allows 25.4 mm (1 in.) of clearance above and below the cDAQ chassis for air circulation.

• Allows at least 50.8 mm (2 in.) of clearance in front of the modules for common connector cabling such as the 10-terminal detachable screw terminal connector and, as needed, up to 88.9 mm (3.5 in.) of clearance in front of the modules for other types of cabling.

For more information about cabling clearances for C Series modules, refer to

ni.com/info and enter the Info Code cseriesconn.

Caution To maintain product performance and accuracy specifications when the

ambient temperature is between 45 °C and 55 °C, you must mount the chassis to a metal panel or surface using the screw holes or the panel mount kit. DIN mounting limits the device to 45 °C maximum ambient operating temperature. Measure the ambient temperature at each side of the CompactDAQ system 63.5 mm (2.5 in.) from the side and 25.4 mm (1 in.) from the rear cover of the system. For further information about mounting configurations, go to

cdaqmounting.

Code

(cDAQ-9181/9191) The NI 9925 outdoor IP 54 enclosure for cDAQ-9181/9191 chassis offers

ni.com/info and enter the Info

protection from industrial and outdoor environments and supplies IP 54 rated power, wireless antenna, Ethernet, and I/O connections.

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Using the cDAQ Chassis on a Desktop

You can use the cDAQ chassis on a desktop. cDAQ-9184/9188 users can also install an optional desktop mounting kit.

Caution Do not stack cDAQ chassis.

Caution (cDAQ-9191) This transmitter must not be co-located or operated in

conjunction with any other antenna or transmitter.

NI 9901 Desktop Kit for cDAQ-9184/9188 Chassis

The NI 9901 desktop mounting kit includes two metal feet you can install on the sides of the cDAQ chassis for desktop use. With this kit, you can tilt the cDAQ chassis for convenient access to the module connectors. When you install the two metal feet, the two existing screws on the back side and I/O end of the chassis must be removed, as shown in Figure 1-11. After removing the screws, replace them with the screws included in the NI 9901 desktop mounting kit. The cDAQ-9184 uses two M3 × 20 screws. The cDAQ-9188 uses two M3 × 14 screws.

Figure 1-11. NI 9901 Desktop Mounting Kit

You must mount the chassis before installing the C Series modules.

Mounting the cDAQ Chassis on a Panel

Caution To maintain product performance and accuracy specifications when the

ambient temperature is between 45 °C and 55 °C, you must mount the chassis to a metal panel or surface using the screw holes or the panel mount kit. Measure the ambient temperature at each side of the CompactDAQ system 63.5 mm (2.5 in.) from the side and 25.4 mm (1 in.) from the rear cover of the system. For further information about mounting configurations, go to

cdaqmounting.

Code

ni.com/info and enter the Info

Page 27

Chapter 1 Getting Started with the cDAQ Chassis

You can use a panel mount kit to mount the cDAQ chassis on a panel, or mount directly to the panel with your own screws. For kit accessory ordering information, refer to the pricing section of your cDAQ chassis product page at

ni.com.

cDAQ-9181/9191

You can panel mount the cDAQ chassis with or without a panel mount kit.

Note The threaded holes on cDAQ chassis for panel or DIN rail mounting cannot

be used more than five times. Unscrewing and reinstalling the screws into the chassis will produce a compromised connection between the panel and cDAQ chassis.

Caution Remove the C Series module(s) from the cDAQ chassis before you mount

the chassis to the panel. After the cDAQ chassis is mounted, you can reinsert the C Series module(s).

• Panel Mounting with a Panel Mount Kit—Use the NI 9903 panel mount kit to mount the cDAQ chassis on a panel. Align the panel mount accessory on the cDAQ chassis and attach the accessory to the chassis with the two FLH #6-32 × 5/16 in. screws (included in the kit), as shown in Figure 1-12. You must use these screws because they are the correct depth and thread for the panel.

You can then attach the cDAQ chassis to a wall or panel with the two holes or the four keyholes with M4, M5, No. 8, or No. 10 panhead screws. National Instruments does not provide these screws with the chassis. Refer to Figure 1-13 for panel mount accessory dimensions.

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NI cDAQ-9181/9184/9188/9191 User Manual

101.6 mm (4.00 in.)

59.7 mm

(2.35 in.)

38.1 mm (1.5 in.)

14.0 mm (0.55 in.)

118.1 mm (4.65 in.)

POWER

STATUS

ACTIVE

Figure 1-12. Installing the cDAQ-9181/9191 Panel Mount Kit

Figure 1-13. NI 9903 Panel Mount Accessory Dimensions

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Chapter 1 Getting Started with the cDAQ Chassis

• Panel Mounting without a Panel Mount Kit—Threaded holes are located in the cDAQ chassis for mounting it to a panel. Use two standard #6-32 UNC-2B machine screws with a maximum threaded engagement length of 4.83 mm (0.190 in.) to go through the panel and into the back of the chassis, as shown in Figure 1-14. National Instruments does not provide these screws with the chassis. Refer to the specifications document for your cDAQ chassis for mounting dimensions.

Figure 1-14. Panel Mounting the cDAQ-9181/9191 without a Panel Mount Kit

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NI cDAQ-9181/9184/9188/9191 User Manual

cDAQ-9184/9188

You can panel mount the cDAQ chassis with or without a panel mount kit:

• Panel Mounting with a Panel Mount Kit—Use the NI 9904 panel mount kit to mount the cDAQ-9184 chassis on a panel. Use the NI 9905 panel mount kit to mount the cDAQ-9188 chassis on a panel.

Caution Remove the C Series module(s) from the cDAQ chassis before you mount

the chassis to the panel. After the cDAQ chassis is mounted, you can reinsert the C Series module(s).

Align the cDAQ chassis on the panel mount accessory and attach the chassis to the accessory with two screws (included in the kit), as shown in Figure 1-15. The cDAQ-9184 uses two M4 × 22 screws. The cDAQ-9188 uses two M4 × 17 screws. You must use these screws because they are the correct depth and thread for the panel.

You can then attach the panel mount accessory to a wall or panel with the two holes or the four keyholes with M4, M5, No. 8, or No. 10 panhead screws. National Instruments does not provide these screws with the chassis. Refer to the documentation included with the panel mount kit for more detailed dimensions.

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Chapter 1 Getting Started with the cDAQ Chassis

87654321

28.1 mm (1.11 in.)

48.1 mm (1.90 in.)

88.1 mm

(3.47 in.)

330.2 mm (13.00 in.)

NI cDAQ-9188

NI CompactDAQ

27.30 mm (1.08 in.)

29.49 mm (1.16 in.)

88.1 mm (3.47 in.)

34.95 mm

(9.25 in.)

NI cDAQ-8184

NI CompactDAQ

Figure 1-15. cDAQ-9184/9188 Panel Mount Dimensions and Installation

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NI cDAQ-9181/9184/9188/9191 User Manual

• Panel Mounting without a Panel Mount Kit—You can mount the cDAQ chassis directly on a flat surface using the mounting holes. Align the chassis on the surface. Then, fasten the chassis to the surface using two screws as shown in Figure 1-16. The cDAQ-9184 uses two M4 or No. 8 flathead screws. The cDAQ-9188 uses two M4 or No. 8 panhead screws. National Instruments does not provide these screws with the chassis.

Figure 1-16. Mounting the cDAQ Chassis Directly on a Flat Surface

NI cDAQ-9184

NI CompactDAQ

Refer to the specifications document for your cDAQ chassis for mounting dimensions.

Caution Make sure that no modules are in the chassis before removing it from the

surface.

Mounting the cDAQ Chassis on a DIN Rail

Caution To maintain product performance and accuracy specifications when the

You can use a DIN rail kit to mount the cDAQ chassis to a standard DIN rail. For kit accessory ordering information, refer to the pricing section of your cDAQ chassis product page at ni.com.

ni.com/info and enter the Info

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Chapter 1 Getting Started with the cDAQ Chassis

cDAQ-9181/9191

The NI 9913 DIN rail mounting kit contains one clip for mounting the cDAQ chassis on a standard 35 mm DIN rail. Fasten the DIN rail clip to the cDAQ chassis using two FLH #6-32 × 5/16 in. screws (included in the kit) with a number 2 Phillips screwdriver, as shown in Figure 1-17.

Note The threaded holes on cDAQ-9181/9191 chassis for panel or DIN rail

mounting cannot be used more than five times. Unscrewing and reinstalling the DIN rail clip will produce a compromised connection between the DIN rail clip and cDAQ chassis.

Figure 1-17. cDAQ-9181/9191 DIN Rail Clip Installation

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NI cDAQ-9181/9184/9188/9191 User Manual

Clip the chassis onto the DIN rail with the larger lip of the DIN rail clip positioned up, as shown in Figure 1-18.

Figure 1-18. DIN Rail Clip Parts Locator Diagram

1 DIN Rail Clip 2DIN Rail Spring 3 DIN Rail

Caution Remove the module before removing the chassis from the DIN rail.

cDAQ-9184/9188

Use the NI 9912 DIN rail kit to mount the cDAQ-9184 chassis on a DIN rail. Use the NI 9915 DIN rail kit with the cDAQ-9188 chassis on a DIN rail.

Each DIN rail mounting kit contains one clip for mounting the chassis on a standard 35 mm DIN rail. To mount the chassis on a DIN rail, fasten the DIN rail clip to the chassis using a number 2 Phillips screwdriver and two screws included in the kit. The cDAQ-9184 uses two M4 × 22 screws. The cDAQ-9188 uses two M4 × 17 screws.

Make sure the DIN rail kit is installed as shown in Figure 1-19. Clip the chassis onto the DIN rail with the larger lip of the DIN clip positioned up, as shown in Figure 1-18. When the DIN rail kit is properly installed, the cDAQ chassis is centered on the DIN rail.

Figure 1-19. cDAQ-9184/9188 DIN Rail Installation

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Chapter 1 Getting Started with the cDAQ Chassis

Caution Remove the module(s) before removing the chassis from the DIN rail.

cDAQ Chassis Features

The cDAQ chassis features a chassis grounding screw, LEDs, reset button, Ethernet port, and power connector. The cDAQ-9188 chassis also features two PFI BNC connectors. The cDAQ-9191 chassis also features an antenna and antenna connector. Refer to Figure 1-1, 1-2, or 1-3 for locations of the cDAQ chassis features.

Chassis Grounding Screw

Caution To ensure the specified EMC performance, the cDAQ chassis must be

connected to the grounding electrode system of your facility using the chassis ground terminal.

The wire should be 1.31 mm2 (16 AWG) or larger solid copper wire with a maximum length of

1.5 m (5 ft). Attach the wire to the earth ground of the facility’s power system. For more information about earth ground connections, refer to the KnowledgeBase document, Grounding for Test and Measurement Devices, by going to

emcground.

Note If you use shielded cabling to connect to a C Series module with a plastic

connector, you must attach the cable shield to the chassis grounding terminal using

1.31 mm

(16 AWG) or larger wire. Use shorter wire for better EMC performance.

ni.com/info and entering the Info Code

LEDs

The statuses for the POWER, STATUS, and ACTIVE LED indicators on the cDAQ chassis are listed in Table 1-3.

The cDAQ-9191 also features four wireless signal strength LED indicators. Refer to Table 1-4 for the wireless signal strength LED patterns.

Table 1-3. LED State/Chassis Status

LED Color LED State Chassis Status

POWER Green On Power on

Off Power off

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Table 1-3. LED State/Chassis Status (Continued)

LED Color LED State Chassis Status

STATUS Ye ll o w On Chassis firmware booting, updating, or

resetting to factory default

Off Normal operation

3 Blinks Firmware image corrupted, update

firmware through recovery utility. To download the recovery utility, go to

ni.com/info and enter the Info Code

cdaqrecoveryutility.

ACTIVE Green On A DAQ task is running on the chassis

Off A DAQ task is not running on the chassis

Table 1-4. Wireless Signal Strength LED State/Chassis Status

LED State LED Pattern Chassis Status

LED 1 on, LEDs 2 through 4 off Connected to network

with poor strength

LEDs 1 and 2 on, LEDs 3 and 4 off Connected to network

with fair strength

LEDs 1 through 3 on, LED 4 off Connected to network

with good strength

LEDs 1 through 4 on Connected to network

with excellent strength

LEDs 1 through 4 off Wireless disabled

LEDs 1 through 4 blinking

Searching for network

in succession

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Chapter 1 Getting Started with the cDAQ Chassis

Ethernet Port

The cDAQ-9181/9191 chassis has one dual-speed RJ-45 Ethernet port, as shown in Figure 1-1. The cDAQ-9184/9188 chassis has one tri-speed RJ-45 Ethernet port, as shown in Figure 1-2 or 1-3. You can use a shielded straight through Category 5 Ethernet cable to connect one end to the RJ-45 Ethernet port on the chassis, and the other end directly to your computer or any network connection on the same subnet as your computer.

Ethernet LEDs

The Ethernet port has two LEDs—10/100/1000 (or 10/100)2 and LINK/ACT—described in Table 1-5.

Table 1-5. Ethernet LED Indications

LED Color LED State Chassis Status

10/100 or 10/100/1000

LINK/ACT Green On Ethernet link

10/100 LED on the cDAQ-9181/9191; 10/100/1000 LED on the cDAQ-9184/9188.

†

10/100 LED on the cDAQ-9181/9191 lights yellow at 100 Mbps; 10/100/1000 LED on the

cDAQ-9184/9188 lights green at 100 Mbps.

Ye ll o w On (cDAQ-9184/9188) Connected at

Green or

†

Ye ll o w

On Connected at 100 Mbps

— Off No Ethernet connection or 10 Mbps

Off No Ethernet connection

Blinking Ethernet activity

1000 Mbps

connection

You can either use a shielded straight through Category 5 Ethernet cable or an Ethernet crossover cable to

connect the cDAQ chassis directly to your computer.

10/100 LED on the cDAQ-9181/9191; 10/100/1000 LED on the cDAQ-9184/9188.

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NI cDAQ-9181/9184/9188/9191 User Manual

Ethernet Cabling

Table 1-6 shows the shielded Ethernet cable wiring connections for both straight through and crossover cables.

Table 1-6. Ethernet Cable Wiring Connections

Connector 2

Pin Connector 1

Straight Through Crossover

1 white/orange white/orange white/green

2 orange orange green

3 white/green white/green white/orange

4 blue blue blue

5 white/blue white/blue white/blue

6 green green orange

7 white/brown white/brown white/brown

8 brown brown brown

Connector 1 Connector 2

Pin 1

Pin 1 Pin 8Pin 8

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Chapter 1 Getting Started with the cDAQ Chassis

Reset Button

The cDAQ chassis is equipped with a reset button.

Pressing the reset button results in the following chassis responses:

• When pressed for less than five seconds, the chassis reboots with the current configuration.

• When pressed for five seconds or longer, the STATUS LED lights. When released, the chassis reboots into factory default mode, which returns the chassis user configuration to the factory-set defaults listed in Table 1-7.

Table 1-7. cDAQ Chassis Default Settings

Attribute Value

Hostname cDAQ91xx-<serial number>

IP DHCP or Link Local

Comment Empty

NI Auth User name = admin

Password = no password required

Power Connector

Refer to the specifications document for your cDAQ chassis for information about the power connector on the cDAQ chassis.

PFI BNC Connectors

(cDAQ-9188) Refer to the PFI section of Chapter 4, Digital Input/Output and PFI, for

information about the BNC connectors for PFI 0 and PFI 1.

Antenna

(cDAQ-9191) Refer to the NI cDAQ-9191 Specifications for information about the antenna on

the cDAQ-9191 chassis.

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NI cDAQ-9181/9184/9188/9191 User Manual

Cables and Accessories

Table 1-8 contains information about cables and accessories available for the cDAQ chassis. For a complete list of cDAQ chassis accessories and ordering information, refer to the pricing section of the cDAQ-9181/9184/9188/9191 product page at

Table 1-8. cDAQ Chassis Cables and Accessories

Accessory Part Number cDAQ Chassis

NI 9901 desktop mounting kit 779473-01 cDAQ-9184/9188

NI 9903 panel mount kit 781722-01 cDAQ-9181/9191

NI 9904 panel mount kit 779097-01 cDAQ-9184

NI 9905 panel mount kit 779558-01 cDAQ-9188

NI 9912 DIN rail mounting kit 779019-01 cDAQ-9184

NI 9913 DIN rail mounting kit 781740-01 cDAQ-9181/9191

NI 9915 DIN rail mounting kit 779018-01 cDAQ-9188

NI 9925 IP enclosure 781723-01 cDAQ-9181/9191

ni.com.

2-pos screw terminal kit for power supply connection, qty 4

CAT-5E Ethernet cable, shielded, (2 m, 5 m, and 10 m lengths)

780702-01 All

151733-02/05/10 All

Removing Modules from the cDAQ Chassis

Complete the following steps to remove a C Series module from the chassis.

1. Make sure that no I/O-side power is connected to the module. If the system is in a nonhazardous location, the chassis power can be on when you remove modules.

2. Squeeze the latches on both sides of the module and pull the module out of the chassis.

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Chapter 1 Getting Started with the cDAQ Chassis

STC3

Ethernet/ Wireless

Network

C Series

Module x

Series

Module 1

PFI 1

(cDAQ-9188)

cDAQ

Module

Interface

PFI 0

(cDAQ-9188)

Using the cDAQ Chassis

The cDAQ system consists of three parts: C Series module(s), the cDAQ module interface, and the STC3, as shown in Figure 1-20. These components digitize signals, perform D/A conversions to generate analog output signals, measure and control digital I/O signals, and provide signal conditioning.

Figure 1-20. cDAQ Chassis Block Diagram

Hardwar

ata

C Series Module

National Instruments C Series modules provide built-in signal conditioning and screw terminal, spring terminal, BNC, D-SUB, or RJ-50 connectors. A wide variety of I/O types are available, allowing you to customize the cDAQ system to meet your application needs.

C Series modules are hot-swappable and automatically detected by the cDAQ chassis. I/O channels are accessible using the NI-DAQmx driver software.

Because the modules contain built-in signal conditioning for extended voltage ranges or industrial signal types, you can usually make your wiring connections directly from the C Series modules to your sensors/actuators. In most cases, the C Series modules provide isolation from channel-to-earth ground and channel-to-channel.

For more information about which C Series modules are compatible with the cDAQ chassis, go

ni.com/info and enter the Info Code rdcdaq.

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NI cDAQ-9181/9184/9188/9191 User Manual

Parallel versus Serial DIO Modules

Digital module capabilities are determined by the type of digital signals that the module is capable of measuring or generating.

• Serial digital modules are designed for signals that change slowly and are accessed by software-timed reads and writes.

• Parallel digital modules are for signals that change rapidly and are updated by either software-timed or hardware-timed reads and writes.

For more information about digital modules, refer to Chapter 4, Digital Input/Output and PFI.

cDAQ Module Interface

The cDAQ module interface manages data transfers between the STC3 and the C Series modules. The interface also handles autodetection, signal routing, and synchronization.

STC3

The STC3 features independent high-speed data streams; flexible AI, AO, and DIO sample timing, triggering, PFI signals for multi-device synchronization, flexible counter/timers with hardware gating, digital waveform acquisition and generation, and static DIO.

• AI, AO, and DIO Sample Timing—The STC3 contains advanced AI, AO, and DIO timing engines. A wide range of timing and synchronization signals are available through the PFI lines. Refer to the following sections for more information about the configuration of these signals:

– The Analog Input Timing Signals section of Chapter 2, Analog Input

– The Analog Output Timing Signals section of Chapter 3, Analog Output

– The Digital Input Timing Signals section of Chapter 4, Digital Input/Output and PFI

– The Digital Output Timing Signals section of Chapter 4, Digital Input/Output and PFI

• Triggering Modes—The cDAQ chassis supports different trigger modes, such as start trigger, reference trigger, and pause trigger with analog, digital, or software sources. Refer to the following sections for more information:

– The Analog Input Triggering Signals section of Chapter 2, Analog Input

– The Analog Output Triggering Signals section of Chapter 3, Analog Output

–The Digital Input Triggering Signals section of Chapter 4, Digital Input/Output and PFI

–The Digital Output Triggering Signals section of Chapter 4, Digital Input/Output and PFI

• Independent Data Streams—The cDAQ-9181/9191 supports six independent high-speed data streams, which allow for up to six simultaneous hardware-timed tasks, such as analog input, analog output, buffered counter/timers, and hardware-timed digital input/output.

The cDAQ-9184/9188 supports seven independent high-speed data streams, which allow for up to seven simultaneous hardware-timed tasks, such as analog input, analog output, buffered counter/timers, and hardware-timed digital input/output.

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Chapter 1 Getting Started with the cDAQ Chassis

• PFI Signals—The PFI signals provide access to advanced features such as triggering, synchronization, and counter/timers. You can also enable a programmable debouncing filter on each PFI signal that, when enabled, samples the input on each rising edge of a filter clock. PFI signals are available through parallel digital input and output modules installed in up to two chassis slots and through the two PFI terminals provided on the cDAQ-9188 chassis. Refer to the PFI section of Chapter 4, Digital Input/Output and PFI, for more information.

• Flexible Counter/Timers—The cDAQ chassis includes four general-purpose 32-bit counter/timers that can be used to count edges, measure pulse-widths, measure periods and frequencies, and perform position measurements (encoding). In addition, the counter/timers can generate pulses, pulse trains, and square waves with adjustable frequencies. You can access the counter inputs and outputs using parallel digital modules installed in up to two slots, or by using the two chassis PFI terminals provided on the cDAQ-9188 chassis. Refer to Chapter 5, Counters, for more information.

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Page 44

Analog Input

To perform analog input measurements, insert a supported analog input C Series module into any slot on the cDAQ chassis. The measurement specifications, such as number of channels, channel configuration, sample rate, and gain, are determined by the type of C Series module used. For more information and wiring diagrams, refer to the documentation included with your C Series modules.

(cDAQ-9184/9188) The cDAQ-9184/9188 has three AI timing engines, which means that

three analog input tasks can be running at a time on a chassis. An analog input task can include channels from multiple analog input modules. However, channels from a single module cannot be used in multiple tasks.

Multiple timing engines allow the cDAQ-9184/9188 to run up to three analog input tasks simultaneously, each using independent timing and triggering configurations. The three AI timing engines are ai, te0, and te1.

Analog Input Triggering Signals

A trigger is a signal that causes an action, such as starting or stopping the acquisition of data. When you configure a trigger, you must decide how you want to produce the trigger and the action you want the trigger to cause. The cDAQ chassis supports internal software triggering, external digital triggering, and analog triggering.

Three triggers are available: Start Trigger, Reference Trigger, and Pause Trigger. An analog or digital trigger can initiate these three trigger actions. Up to two C Series parallel digital input modules can be used in any chassis slot to supply a digital trigger. To find your module triggering options, refer to the documentation included with your C Series modules. For more information about using digital modules for triggering, refer to Chapter 4, Digital Input/Output and PFI.

Refer to the AI Start Trigger Signal, AI Reference Trigger Signal, and AI Pause Trigger Signal sections for more information about the analog input trigger signals.

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Chapter 2 Analog Input

Analog Input Timing Signals

The cDAQ chassis features the following analog input timing signals:

• AI Sample Clock Signal*

• AI Sample Clock Timebase Signal

• AI Start Trigger Signal*

• AI Reference Trigger Signal*

• AI Pause Trigger Signal*

Signals with an * support digital filtering. Refer to the PFI Filters section of Chapter 4, Digital

Input/Output and PFI, for more information.

Refer to the AI Convert Clock Signal Behavior For Analog Input Modules section for AI Convert Clock signals and the cDAQ chassis.

AI Sample Clock Signal

A sample consists of one reading from each channel in the AI task. Sample Clock signals the start of a sample of all analog input channels in the task. Sample Clock can be generated from external or internal sources as shown in Figure 2-1.

Figure 2-1. AI Sample Clock Timing Options

PFI

Analog Comparison Event

PFI

Analog Comparison

Event

20 MHz Timebase

80 MHz Timebase

100 kHz Timebase

Ctr n Internal Output

Sigma-Delta Module Internal Output

AI Sample Clock

Timebase

Programmable

Clock

Divider

AI Sample Clock

Routing the Sample Clock to an Output Terminal

You can route Sample Clock to any output PFI terminal. Sample Clock is an active high pulse by default.

AI Sample Clock Timebase Signal

The AI Sample Clock Timebase signal is divided down to provide a source for Sample Clock. AI Sample Clock Timebase can be generated from external or internal sources. AI Sample Clock Timebase is not available as an output from the chassis.

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NI cDAQ-9181/9184/9188/9191 User Manual

AI Convert Clock Signal Behavior For Analog Input Modules

Refer to the Scanned Modules, Simultaneous Sample-and-Hold Modules, Sigma-Delta Modules, and Slow Sample Rate Modules sections for information about the AI Convert Clock signal and C Series analog input modules.

Scanned Modules

Scanned C Series analog input modules contain a single A/D converter and a multiplexer to select between multiple input channels. When the cDAQ Module Interface receives a Sample Clock pulse, it begins generating a Convert Clock for each scanned module in the current task. Each Convert Clock signals the acquisition of a single channel from that module. The Convert Clock rate depends on the module being used, the number of channels used on that module, and the system Sample Clock rate.

The driver chooses the fastest conversion rate possible based on the speed of the A/D converter for each module and adds 10 µs of padding between each channel to allow for adequate settling time. This scheme enables the channels to approximate simultaneous sampling. If the AI Sample Clock rate is too fast to allow for 10 µs of padding, NI-DAQmx selects a conversion rate that spaces the AI Convert Clock pulses evenly throughout the sample. NI-DAQmx uses the same amount of padding for all the modules in the task. To explicitly specify the conversion rate, use the ActiveDevs and AI Convert Clock Rate properties using the DAQmx Timing property node or functions.

Simultaneous Sample-and-Hold Modules

Simultaneous sample-and-hold (SSH) C Series analog input modules contain multiple A/D converters or circuitry that allows all the input channels to be sampled at the same time. These modules sample their inputs on every Sample Clock pulse.

Sigma-Delta Modules

Sigma-delta C Series analog input modules function much like SSH modules, but use A/D converters that require a high-frequency oversample clock to produce accurate, synchronized data. Some sigma-delta modules in the cDAQ chassis automatically share a single oversample clock to synchronize data from all the modules that support an external oversample clock timebase when they all share the same task. (DSA modules are an example). The cDAQ chassis supports a maximum of two synchronization pulse signals configured for your system. This limits the system to two tasks with different oversample clock timebases.

The oversample clock is used as the AI Sample Clock Timebase. While most modules supply a common oversample clock frequency (12.8 MHz), some modules, such as the NI 9234, supply a different frequency. When sigma-delta modules with different oversample clock frequencies are used in an analog input task, the AI Sample Clock Timebase can use any of the available frequencies; by default, the fastest available is used. The sampling rate of all modules in the system is an integer divisor of the frequency of the AI Sample Clock Timebase.

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Chapter 2 Analog Input

When one or more sigma-delta modules are in an analog input task, the sigma-delta modules also provide the signal used as the AI Sample Clock. This signal is used to cause A/D conversion for other modules in the system, just as the AI Sample Clock does when a sigma-delta module is not being used.

When sigma-delta modules are in an AI task, the chassis automatically issues a synchronization pulse to each sigma-delta modules that resets their ADCs at the same time. Because of the filtering used in sigma-delta A/D converters, these modules usually exhibit a fixed input delay relative to non-sigma-delta modules in the system. This input delay is specified in the C Series module documentation.

Slow Sample Rate Modules

(cDAQ-9184/9188) Some C Series analog input modules are specifically designed for

measuring signals that vary slowly, such as temperature. Because of their slow rate, it is not appropriate for these modules to constrain the AI Sample Clock to operate at or slower than their maximum rate. When using such a module in the cDAQ chassis, the maximum Sample Clock rate can run faster than the maximum rate for the module. When operating at a rate faster than these slow rate modules can support, the slow rate module returns the same point repeatedly, until a new conversion completes. In a hardware-timed task, the first point is acquired when the task is committed. The second point is acquired after the start trigger as shown in Figure 2-2.

Figure 2-2. Sample Clock Timing Example

StartTrigger

1st A/D Conversion 2nd A/D Conversion 3rd A/D Conversion

Data from

A/D Conversion

(Slow Module)

SampleClock

Data Returned

to AI Task

AA ABB BC

For example, if running an AI task at 1 kHz using a module with a maximum rate of 10 Hz, the slow module returns 100 samples of the first point, followed by 100 samples of the second point, etc. Other modules in the task will return 1,000 new data points per second, which is normal. When performing a single-point acquisition, no points are repeated. To avoid this behavior, use multiple AI timing engines, and assign slow sample rate modules to a task with a rate at or slower than their maximum rate.

Refer to C Series Support in NI-DAQmx for more information. To access this document, go to

ni.com/info and enter the Info Code rdcdaq.

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NI cDAQ-9181/9184/9188/9191 User Manual

AI Start Trigger Signal

Use the Start Trigger signal to begin a measurement acquisition. A measurement acquisition consists of one or more samples. If you do not use triggers, begin a measurement with a software command. Once the acquisition begins, configure the acquisition to stop in one of the following ways:

• When a certain number of points has been sampled (in finite mode)

• After a hardware reference trigger (in finite mode)

• With a software command (in continuous mode)

An acquisition that uses a start trigger (but not a reference trigger) is sometimes referred to as a posttriggered acquisition. That is, samples are measured only after the trigger.

When you are using an internal sample clock, you can specify a default delay from the start trigger to the first sample.

Using a Digital Source

To use the Start Trigger signal with a digital source, specify a source and a rising or falling edge. Use the following signals as the source:

• Any PFI terminal

• Counter n Internal Output

The source also can be one of several other internal signals on your cDAQ chassis. Refer to the Device Routing in MAX topic in the NI-DAQmx Help or the LabVIEW Help for more information.

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is called the Analog Comparison Event. When you use an analog trigger source for Start Trigger, the acquisition begins on the first rising edge of the Analog Comparison Event signal.

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

Routing AI Start Trigger to an Output Terminal

You can route the Start Trigger signal to any output PFI terminal. The output is an active high pulse.

AI Reference Trigger Signal

Use Reference Trigger to stop a measurement acquisition. To use a reference trigger, specify a buffer of finite size and a number of pretrigger samples (samples that occur before the reference trigger). The number of posttrigger samples (samples that occur after the reference trigger) desired is the buffer size minus the number of pretrigger samples.

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Chapter 2 Analog Input

Once the acquisition begins, the cDAQ chassis writes samples to the buffer. After the cDAQ chassis captures the specified number of pretrigger samples, the cDAQ chassis begins to look for the reference trigger condition. If the reference trigger condition occurs before the cDAQ chassis captures the specified number of pretrigger samples, the chassis ignores the condition.

If the buffer becomes full, the cDAQ chassis continuously discards the oldest samples in the buffer to make space for the next sample. This data can be accessed (with some limitations) before the cDAQ chassis discards it. Refer to the KnowledgeBase document, Can a Pretriggered Acquisition be Continuous?, for more information. To access this KnowledgeBase, go to

ni.com/info and enter the Info Code rdcanq.

When the reference trigger occurs, the cDAQ chassis continues to write samples to the buffer until the buffer contains the number of posttrigger samples desired. Figure 2-3 shows the final buffer.

Figure 2-3. Reference Trigger Final Buffer

Reference Trigger

Pretrigger Samples

Complete Buffer

Posttrigger Samples

Using a Digital Source

To use Reference Trigger with a digital source, specify a source and a rising or falling edge. Either PFI or one of several internal signals on the cDAQ chassis can provide the source. Refer to the Device Routing in MAX topic in the NI-DAQmx Help or the LabVIEW Help for more information.

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is called the Analog Comparison Event.

When you use an analog trigger source, the acquisition stops on the first rising or falling edge of the Analog Comparison Event signal, depending on the trigger properties.

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

Routing the Reference Trigger Signal to an Output Terminal

You can route Reference Trigger to any output PFI terminal. Reference Trigger is active high by default.

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NI cDAQ-9181/9184/9188/9191 User Manual

AI Pause Trigger Signal

You can use the Pause Trigger to pause and resume a measurement acquisition. The internal sample clock pauses while the external trigger signal is active and resumes when the signal is inactive. You can program the active level of the pause trigger to be high or low.

Using a Digital Source

To use the Pause Trigger, specify a source and a polarity. The source can be either from PFI or one of several other internal signals on your cDAQ chassis. Refer to the Device Routing in MAX topic in the NI-DAQmx Help or the LabVIEW Help for more information.

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is called the Analog Comparison Event.

When you use an analog trigger source, the internal sample clock pauses when the Analog Comparison Event signal is low and resumes when the signal goes high (or vice versa).

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

Note Pause triggers are only sensitive to the level of the source, not the edge.

Getting Started with AI Applications in Software

You can use the cDAQ chassis in the following analog input applications:

• Single-point acquisition

• Finite acquisition

• Continuous acquisition

For more information about programming analog input applications and triggers in software, refer to the NI-DAQmx Help or the LabVIEW Help for more information.

Page 51

Analog Output

To generate analog output, insert an analog output C Series module in any slot on the cDAQ chassis. The generation specifications, such as the number of channels, channel configuration, update rate, and output range, are determined by the type of C Series module used. For more information, refer to the documentation included with your C Series module(s).

On a single analog output C Series module, you can assign any number of channels to either a hardware-timed task or a software-timed (single-point) task. However, you cannot assign some channels to a hardware-timed task and other channels (on the same module) to a software-timed task.

(cDAQ-9184/9188) Any hardware-timed task or software-timed task can have channels from

multiple modules in the same chassis.

Analog Output Data Generation Methods

When performing an analog output operation, you either can perform software-timed or hardware-timed generations. Hardware-timed generations must be buffered.

Software-Timed Generations

With a software-timed generation, software controls the rate at which data is generated. Software sends a separate command to the hardware to initiate each DAC conversion. In NI-DAQmx, software-timed generations are referred to as on-demand timing. Software-timed generations are also referred to as immediate or static operations. They are typically used for writing out a single value, such as a constant DC voltage.

The following considerations apply to software-timed generations:

• If any AO channel on a module is used in a hardware-timed (waveform) task, no channels on that module can be used in a software-timed task

• You can configure software-timed generations to simultaneously update

• Only one simultaneous update task can run at a time

• A hardware-timed AO task and a simultaneous update AO task cannot run at the same time

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Chapter 3 Analog Output

Hardware-Timed Generations

With a hardware-timed generation, a digital hardware signal controls the rate of the generation. This signal can be generated internally on the chassis or provided externally.

Hardware-timed generations have several advantages over software-timed acquisitions:

• The time between samples can be much shorter

• The timing between samples is deterministic

• Hardware-timed acquisitions can use hardware triggering

Hardware-timed AO operations on the cDAQ chassis must be buffered.

Buffered Analog Output

A buffer is a temporary storage in computer memory for generated samples. In a buffered generation, data is moved from a host buffer to the cDAQ chassis onboard FIFO before it is written to the C Series modules.

One property of buffered I/O operations is sample mode. The sample mode can be either finite or continuous:

• Finite—Finite sample mode generation refers to the generation of a specific, predetermined number of data samples. After the specified number of samples is written out, the generation stops.

• Continuous—Continuous generation refers to the generation of an unspecified number of samples. Instead of generating a set number of data samples and stopping, a continuous generation continues until you stop the operation. There are three different continuous generation modes that control how the data is written. These modes are regeneration, onboard regeneration, and non-regeneration:

– In regeneration mode, you define a buffer in host memory. The data from the buffer is

continually downloaded to the FIFO to be written out. New data can be written to the host buffer at any time without disrupting the output. There is no limitation on the number of waveform channels supported by regeneration mode.

– With onboard regeneration, the entire buffer is downloaded to the FIFO and

regenerated from there. After the data is downloaded, new data cannot be written to the FIFO. To use onboard regeneration, the entire buffer must fit within the FIFO size. The advantage of using onboard regeneration is that it does not require communication with the main host memory once the operation is started, which prevents problems that may occur due to excessive bus traffic or operating system latency. There is a limit of 16 waveform channels for onboard regeneration.

– With non-regeneration, old data is not repeated. New data must continually be written

to the buffer. If the program does not write new data to the buffer at a fast enough rate to keep up with the generation, the buffer underflows and causes an error. There is no limitation on the number of waveform channels supported by non-regeneration.

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NI cDAQ-9181/9184/9188/9191 User Manual

Programmable

Clock

Divider

AO Sample Clock

Timebase

PFI

Analog Comparison Event

Ctr

Internal Output

AO Sample Clock

Analog Comparison

Event

20 MHz Timebase

80 MHz Timebase

PFI

100 kHz Timebase

Analog Output Triggering Signals

Analog output supports two different triggering actions: AO Start Trigger and AO Pause Trigger.

An analog or digital trigger can initiate these actions. Up to two C Series parallel digital input modules can be used in any chassis slot to supply a digital trigger. An analog trigger can be supplied by some C Series analog modules.

Refer to the AO Start Trigger Signal and AO Pause Trigger Signal sections for more information about the analog output trigger signals.

Analog Output Timing Signals

The cDAQ chassis features the following AO (waveform generation) timing signals:

• AO Sample Clock Signal*

• AO Sample Clock Timebase Signal

• AO Start Trigger Signal*

• AO Pause Trigger Signal*

Signals with an * support digital filtering. Refer to the PFI Filters section of Chapter 4, Digital

Input/Output and PFI, for more information.

AO Sample Clock Signal

The AO sample clock (ao/SampleClock) signals when all the analog output channels in the task update. AO Sample Clock can be generated from external or internal sources as shown in Figure 3-1.

Figure 3-1. Analog Output Timing Options

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Chapter 3 Analog Output

Routing AO Sample Clock to an Output Terminal

You can route AO Sample Clock to any output PFI terminal. AO Sample Clock is active high by default.

AO Sample Clock Timebase Signal

The AO Sample Clock Timebase (ao/SampleClockTimebase) signal is divided down to provide a source for AO Sample Clock. AO Sample Clock Timebase can be generated from external or internal sources, and is not available as an output from the chassis.

AO Start Trigger Signal

Use the AO Start Trigger (ao/StartTrigger) signal to initiate a waveform generation. If you do not use triggers, you can begin a generation with a software command. If you are using an internal sample clock, you can specify a delay from the start trigger to the first sample. For more information, refer to the NI-DAQmx Help.

Using a Digital Source

To use AO Start Trigger, specify a source and a rising or falling edge. The source can be one of the following signals:

• A pulse initiated by host software

• Any PFI terminal

• AI Reference Trigger

• AI Start Trigger

The source also can be one of several internal signals on the cDAQ chassis. Refer to the Device Routing in MAX topic in the NI-DAQmx Help or the LabVIEW Help for more information.

You also can specify whether the waveform generation begins on the rising edge or falling edge of AO Start Trigger.

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is called the Analog Comparison Event, depending on the trigger properties.

When you use an analog trigger source, the waveform generation begins on the first rising or falling edge of the Analog Comparison Event signal, depending on the trigger properties. The analog trigger circuit must be configured by a simultaneously running analog input task.

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

Routing AO Start Trigger Signal to an Output Terminal

You can route AO Start Trigger to any output PFI terminal. The output is an active high pulse.

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NI cDAQ-9181/9184/9188/9191 User Manual

Pause Trigger

Sample Clock

AO Pause Trigger Signal

Use the AO Pause Trigger signal (ao/PauseTrigger) to mask off samples in a DAQ sequence. When AO Pause Trigger is active, no samples occur, but AO Pause Trigger does not stop a sample that is in progress. The pause does not take effect until the beginning of the next sample.

When you generate analog output signals, the generation pauses as soon as the pause trigger is asserted. If the source of the sample clock is the onboard clock, the generation resumes as soon as the pause trigger is deasserted, as shown in Figure 3-2.

Figure 3-2. AO Pause Trigger with the Onboard Clock Source

Pause Trigger

Sample Clock

If you are using any signal other than the onboard clock as the source of the sample clock, the generation resumes as soon as the pause trigger is deasserted and another edge of the sample clock is received, as shown in Figure 3-3.

Figure 3-3. AO Pause Trigger with Other Signal Source

Using a Digital Source

To use AO Pause Trigger, specify a source and a polarity. The source can be a PFI signal or one of several other internal signals on the cDAQ chassis.

You also can specify whether the samples are paused when AO Pause Trigger is at a logic high or low level. Refer to the Device Routing in MAX topic in the NI-DAQmx Help or the LabVIEW Help for more information.

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Chapter 3 Analog Output

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is called the Analog Comparison Event, depending on the trigger properties.

When you use an analog trigger source, the samples are paused when the Analog Comparison Event signal is at a high or low level, depending on the trigger properties. The analog trigger circuit must be configured by a simultaneously running analog input task.

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

Minimizing Glitches on the Output Signal

When you use a DAC to generate a waveform, you may observe glitches on the output signal. These glitches are normal; when a DAC switches from one voltage to another, it produces glitches due to released charges. The largest glitches occur when the most significant bit of the DAC code changes. You can build a lowpass deglitching filter to remove some of these glitches, depending on the frequency and nature of the output signal. Go to information about minimizing glitches.

ni.com/support for more

Getting Started with AO Applications in Software

You can use the cDAQ chassis in the following analog output applications:

• Single-point (on-demand) generation

• Finite generation

• Continuous generation

• Waveform generation

For more information about programming analog output applications and triggers in software, refer the LabVIEW Help or to the NI-DAQmx Help.

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Digital Input/Output and PFI

This chapter describes the digital input/output (DIO) and Programmable Function Interface (PFI) functionality available on the cDAQ chassis. Refer to the Digital Input/Output and PFI sections.

Digital Input/Output

To use digital I/O, insert a digital I/O C Series module into any slot on the cDAQ chassis. The I/O specifications, such as number of lines, logic levels, update rate, and line direction, are determined by the type of C Series module used. For more information, refer to the documentation included with your C Series module(s).

Serial DIO versus Parallel DIO Modules

Serial digital modules have more than eight lines of digital input/output. They can be used in any chassis slot and can perform the following tasks:

• Software-timed and hardware-timed digital input/output tasks

Parallel digital modules can be used in any chassis slot and can perform the following tasks:

• Software-timed and hardware-timed digital input/output tasks

• Counter/timer tasks (can be used in up to two slots)

• Accessing PFI signal tasks (can be used in up to two slots)

• Filter digital input signals

Software-timed and hardware-timed digital input/output tasks have the following restrictions:

• You cannot use parallel and serial modules together on the same hardware-timed task.

• You cannot use serial modules for triggering.

• You cannot do both static and timed tasks at the same time on a single serial module.

• You can only do hardware timing in one direction at a time on a serial bidirectional module.

To determine the capability of digital modules supported by the cDAQ chassis, go to

and enter the Info Code rdcdaq.

info

ni.com/

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Chapter 4 Digital Input/Output and PFI

Static DIO

Each of the DIO lines can be used as a static DI or DO line. You can use static DIO lines to monitor or control digital signals on some C Series modules. Each DIO line can be individually configured as a digital input (DI) or digital output (DO), if the C Series module being used allows such configuration.

All samples of static DI lines and updates of static DO lines are software-timed.

Digital Input

You can acquire digital waveforms using either parallel or serial digital modules. The DI waveform acquisition FIFO stores the digital samples. The cDAQ chassis samples the DIO lines on each rising or falling edge of the DI Sample Clock signal.

Digital Input Triggering Signals

A trigger is a signal that causes an action, such as starting or stopping the acquisition of data. When you configure a trigger, you must decide how you want to produce the trigger and the action you want the trigger to cause. The cDAQ chassis supports three types of digital triggering: internal software digital triggering, external digital triggering, and internal digital triggering.

Three triggers are available: Start Trigger, Reference Trigger, and Pause Trigger. An analog or digital trigger can initiate these three trigger actions. Up to two C Series parallel digital input modules can be used in any chassis slot to supply a digital trigger. To find your module triggering options, refer to the documentation included with your C Series modules. For more information about using analog modules for triggering, refer to the Analog Input Triggering Signals section of Chapter 2, Analog Input, and the Analog Output Triggering Signals section of Chapter 3,

Analog Output.

Refer to the DI Start Trigger Signal, DI Reference Trigger Signal, and DI Pause Trigger Signal sections for more information about the digital input trigger signals.

Digital Input Timing Signals

The cDAQ chassis features the following digital input timing signals:

• DI Sample Clock Signal*

• DI Sample Clock Timebase Signal

• DI Start Trigger Signal*

• DI Reference Trigger Signal*

• DI Pause Trigger Signal*

Signals with an * support digital filtering. Refer to the PFI Filters section for more information.

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Programmable

Clock

Divider

DI Sample Clock

Timebase

PFI

Analog Comparison Event

Ctr

Internal Output

DI Sample Clock

Sigma-Delta Module Internal Output

Analog Comparison

Event

20 MHz Timebase

80 MHz Timebase

PFI

100 kHz Timebase

DI Sample Clock Signal

Use the DI Sample Clock (di/SampleClock) signal to sample digital I/O on any slot using parallel digital modules, and store the result in the DI waveform acquisition FIFO. If the cDAQ chassis receives a DI Sample Clock signal when the FIFO is full, it reports an overflow error to the host software.

A sample consists of one reading from each channel in the DI task. DI Sample Clock signals the start of a sample of all digital input channels in the task. DI Sample Clock can be generated from external or internal sources as shown in Figure 4-1.

Figure 4-1. DI Sample Clock Timing Options

Routing DI Sample Clock to an Output Terminal

You can route DI Sample Clock to any output PFI terminal.

DI Sample Clock Timebase Signal

The DI Sample Clock Timebase (di/SampleClockTimebase) signal is divided down to provide a source for DI Sample Clock. DI Sample Clock Timebase can be generated from external or internal sources. DI Sample Clock Timebase is not available as an output from the chassis.

Using an Internal Source

To use DI Sample Clock with an internal source, specify the signal source and the polarity of the signal. Use the following signals as the source:

• AI Sample Clock

• AO Sample Clock

• Counter n Internal Output

• Frequency Output

• DI Change Detection Output

Several other internal signals can be routed to DI Sample Clock. Refer to the Device Routing in MAX topic in the NI-DAQmx Help or the LabVIEW Help for more information.

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Using an External Source

You can route the following signals as DI Sample Clock:

• Any PFI terminal

• Analog Comparison Event (an analog trigger)

You can sample data on the rising or falling edge of DI Sample Clock.

Routing DI Sample Clock to an Output Terminal

You can route DI Sample Clock to any output PFI terminal. The PFI circuitry inverts the polarity of DI Sample Clock before driving the PFI terminal.

DI Start Trigger Signal

Use the DI Start Trigger (di/StartTrigger) signal to begin a measurement acquisition. A measurement acquisition consists of one or more samples. If you do not use triggers, begin a measurement with a software command. Once the acquisition begins, configure the acquisition to stop in one of the following ways:

• When a certain number of points has been sampled (in finite mode)

• After a hardware reference trigger (in finite mode)

• With a software command (in continuous mode)

An acquisition that uses a start trigger (but not a reference trigger) is sometimes referred to as a posttriggered acquisition. That is, samples are measured only after the trigger.

When you are using an internal sample clock, you can specify a delay from the start trigger to the first sample.

Using a Digital Source

To use DI Start Trigger with a digital source, specify a source and a rising or falling edge. Use the following signals as the source:

• Any PFI terminal

• Counter n Internal Output

The source also can be one of several other internal signals on the cDAQ chassis. Refer to the Device Routing in MAX topic in the NI-DAQmx Help or the LabVIEW Help for more information.

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is called the Analog Comparison Event. When you use an analog trigger source for DI Start Trigger, the acquisition begins on the first rising edge of the Analog Comparison Event signal.

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

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Routing DI Start Trigger to an Output Terminal

You can route DI Start Trigger to any output PFI terminal. The output is an active high pulse.

DI Reference Trigger Signal

Use a reference trigger (di/ReferenceTrigger) signal to stop a measurement acquisition. To use a reference trigger, specify a buffer of finite size and a number of pretrigger samples (samples that occur before the reference trigger). The number of posttrigger samples (samples that occur after the reference trigger) desired is the buffer size minus the number of pretrigger samples.

Once the acquisition begins, the cDAQ chassis writes samples to the buffer. After the cDAQ chassis captures the specified number of pretrigger samples, the chassis begins to look for the reference trigger condition. If the reference trigger condition occurs before the cDAQ chassis captures the specified number of pretrigger samples, the chassis ignores the condition.

ni.com/info and enter the Info Code rdcanq.

When the reference trigger occurs, the cDAQ chassis continues to write samples to the buffer until the buffer contains the number of posttrigger samples desired. Figure 4-2 shows the final buffer.

Figure 4-2. Reference Trigger Final Buffer

Reference Trigger

Pretrigger Samples

Complete Buffer

Posttrigger Samples

Using a Digital Source

To use DI Reference Trigger with a digital source, specify a source and a rising or falling edge. Either PFI or one of several internal signals on the cDAQ chassis can provide the source. Refer to the Device Routing in MAX topic in the NI-DAQmx Help or the LabVIEW Help for more information.

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Chapter 4 Digital Input/Output and PFI

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is called the Analog Comparison Event.

When you use an analog trigger source, the acquisition stops on the first rising or falling edge of the Analog Comparison Event signal, depending on the trigger properties.

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

Routing DI Reference Trigger Signal to an Output Terminal

You can route DI Reference Trigger to any output PFI terminal. Reference Trigger is active high by default.

DI Pause Trigger Signal

You can use the DI Pause Trigger (di/PauseTrigger) signal to pause and resume a measurement acquisition. The internal sample clock pauses while the external trigger signal is active and resumes when the signal is inactive. You can program the active level of the pause trigger to be high or low.

Using a Digital Source

To use DI Pause Trigger, specify a source and a polarity. The source can be either from PFI or one of several other internal signals on your cDAQ chassis. Refer to the Device Routing in MAX topic in the NI-DAQmx Help or the LabVIEW Help for more information.

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is called the Analog Comparison Event.

When you use an analog trigger source, the internal sample clock pauses when the Analog Comparison Event signal is low and resumes when the signal goes high (or vice versa).

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

Note Pause triggers are only sensitive to the level of the source, not the edge.

Digital Input Filters

When performing a hardware-timed task, you can enable a programmable debouncing filter on the digital input lines of a parallel DIO module. All lines on a module must share the same filter configuration. When the filter is enabled, the chassis samples the inputs with a user-configured Filter Clock derived from the chassis timebase. This is used to determine whether a pulse is propagated to the rest of the system. However, the filter also introduces jitter onto the input signal.

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In NI-DAQmx, the filter is programmed by setting the minimum pulse width, Tp1, that will pass the filter, and is selectable in 25 ns increments. The appropriate Filter Clock is selected by the driver. Pulses of length less than 1/2 Tp will be rejected, and the filtering behavior of lengths between 1/2 Tp and 1 Tp are not defined because they depend on the phase of the Filter Clock relative to the input signal.

Figure 4-3 shows an example of low-to-high transitions of the input signal. High-to-low transitions work similarly.

Assume that an input terminal has been low for a long time. The input terminal then changes from low to high, but glitches several times. When the filter clock has sampled the signal high on consecutive rising edges, the low-to-high transition is propagated to the rest of the circuit.

Figure 4-3. Filter Example

Digital Input P0.x

Filter Clock

Filtered Input

11 211 21

Getting Started with DI Applications in Software

You can use the cDAQ chassis in the following digital input applications:

• Single-point acquisition

• Finite acquisition

• Continuous acquisition

For more information about programming digital input applications and triggers in software, refer to the NI-DAQmx Help or the LabVIEW Help for more information.

Change Detection Event

The Change Detection Event is the signal generated when a change on the rising or falling edge lines is detected by the change detection task.

Routing Change Detection Event to an Output Terminal

You can route ChangeDetectionEvent to any output PFI terminal.

Change Detection Acquisition

You can configure lines on parallel digital modules to detect rising or falling edges. When one or more of these lines sees the edge specified for that line, the cDAQ chassis samples all the lines in the task. The rising and falling edge lines do not necessarily have to be in the task.

Tp is a nominal value; the accuracy of the chassis timebase and I/O distortion will affect this value.

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Chapter 4 Digital Input/Output and PFI

Change detection acquisitions can be buffered or nonbuffered:

• Nonbuffered Change Detection Acquisition—In a nonbuffered acquisition, data is transferred from the cDAQ chassis directly to a PC buffer.

• Buffered Change Detection Acquisition—A buffer is a temporary storage in computer memory for acquired samples. In a buffered acquisition, data is stored in the cDAQ chassis onboard FIFO then transferred to a PC buffer. Buffered acquisitions typically allow for much faster transfer rates than nonbuffered acquisitions because data accumulates and is transferred in blocks, rather than one sample at a time.

Digital Output

To generate digital output, insert a digital output C Series module in any slot on the cDAQ chassis. The generation specifications, such as the number of channels, channel configuration, update rate, and output range, are determined by the type of C Series module used. For more information, refer to the documentation included with your C Series module(s).

With parallel digital output modules (formerly known as hardware-timed modules), you can do multiple software-timed tasks on a single module, as well as mix hardware-timed and software-timed digital output tasks on a single module. On serial digital output modules, (formerly known as static digital output modules), you cannot mix hardware-timed and software-timed tasks, but you can run multiple software-timed tasks.

You may have a hardware-timed task or a software-timed task include channels from multiple modules, but a hardware-timed task may not include a mix of channels from both parallel and serial modules.

Digital Output Data Generation Methods

When performing a digital output operation, you either can perform software-timed or hardware-timed generations. Hardware-timed generations must be buffered.

Software-Timed Generations

With a software-timed generation, software controls the rate at which data is generated. Software sends a separate command to the hardware to initiate each digital generation. In NI-DAQmx, software-timed generations are referred to as on-demand timing. Software-timed generations are also referred to as immediate or static operations. They are typically used for writing out a single value.

For software-timed generations, if any DO channel on a serial digital module is used in a hardware-timed task, no channels on that module can be used in a software-timed task.

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Hardware-Timed Generations

With a hardware-timed generation, a digital hardware signal controls the rate of the generation. This signal can be generated internally on the chassis or provided externally.

Hardware-timed generations have several advantages over software-timed acquisitions:

• The time between samples can be much shorter.

• The timing between samples is deterministic.

• Hardware-timed acquisitions can use hardware triggering.

Hardware-timed DO operations on the cDAQ chassis must be buffered.

Buffered Digital Output

One property of buffered I/O operations is sample mode. The sample mode can be either finite or continuous:

• Finite—Finite sample mode generation refers to the generation of a specific, predetermined number of data samples. After the specified number of samples is written out, the generation stops.

– In regeneration mode, you define a buffer in host memory. The data from the buffer is

continually downloaded to the FIFO to be written out. New data can be written to the host buffer at any time without disrupting the output.

– With onboard regeneration, the entire buffer is downloaded to the FIFO and

Note (cDAQ-9188) Install parallel DO modules in slots 1 through 4 to maximize

accessible FIFO size because using a module in slots 5 through 8 will reduce the accessible FIFO size.

– With non-regeneration, old data is not repeated. New data must continually be written

to the buffer. If the program does not write new data to the buffer at a fast enough rate to keep up with the generation, the buffer underflows and causes an error.

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Chapter 4 Digital Input/Output and PFI

Digital Output Triggering Signals

Digital output supports two different triggering actions: DO Start Trigger and DO Pause Trigger.

A digital or analog trigger can initiate these actions. Any PFI terminal can supply a digital trigger, and some C Series analog modules can supply an analog trigger. For more information, refer to the documentation included with your C Series module(s).

Refer to the DO Start Trigger Signal and DO Pause Trigger Signal sections for more information about the digital output trigger signals.

Digital Output Timing Signals

The cDAQ chassis features the following DO timing signals:

• DO Sample Clock Signal*

• DO Sample Clock Timebase Signal

• DO Start Trigger Signal*

• DO Pause Trigger Signal*

Signals with an * support digital filtering. Refer to the PFI Filters section for more information.

DO Sample Clock Signal

The DO Sample Clock (do/SampleClock) signals when all the digital output channels in the task update. DO Sample Clock can be generated from external or internal sources as shown in Figure 4-4.

Figure 4-4. Digital Output Timing Options

PFI

Analog Comparison

Event

20 MHz Timebase

80 MHz Timebase

100 kHz Timebase

DO Sample Clock

Timebase

Analog Comparison Event

Internal Output

Ctr

Programmable

Clock

Divider

DO Sample Clock

Routing DO Sample Clock to an Output Terminal

You can route DO Sample Clock to any output PFI terminal. DO Sample Clock is active high by default.

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DO Sample Clock Timebase Signal

The DO Sample Clock Timebase (do/SampleClockTimebase) signal is divided down to provide a source for DO Sample Clock. DO Sample Clock Timebase can be generated from external or internal sources, and is not available as an output from the chassis.

DO Start Trigger Signal

Use the DO Start Trigger (do/StartTrigger) signal to initiate a waveform generation. If you do not use triggers, you can begin a generation with a software command. If you are using an internal sample clock, you can specify a delay from the start trigger to the first sample. For more information, refer to the NI-DAQmx Help.

Using a Digital Source

To use DO Start Trigger, specify a source and a rising or falling edge. The source can be one of the following signals:

• A pulse initiated by host software

• Any PFI terminal

• AI Reference Trigger

• AI Start Trigger

The source also can be one of several internal signals on the cDAQ chassis. Refer to the Device Routing in MAX topic in the NI-DAQmx Help or the LabVIEW Help for more information.

You also can specify whether the waveform generation begins on the rising edge or falling edge of DO Start Trigger.

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is called the Analog Comparison Event, depending on the trigger properties.

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

Routing DO Start Trigger Signal to an Output Terminal

You can route DO Start Trigger to any output PFI terminal. The output is an active high pulse.

DO Pause Trigger Signal

Use the DO Pause Trigger signal (do/PauseTrigger) to mask off samples in a DAQ sequence. When DO Pause Trigger is active, no samples occur, but DO Pause Trigger does not stop a sample that is in progress. The pause does not take effect until the beginning of the next sample.

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Chapter 4 Digital Input/Output and PFI

Pause Trigger

Sample Clock

When you generate digital output signals, the generation pauses as soon as the pause trigger is asserted. If the source of the sample clock is the onboard clock, the generation resumes as soon as the pause trigger is deasserted, as shown in Figure 4-5.

Figure 4-5. DO Pause Trigger with the Onboard Clock Source

Pause Trigger

Sample Clock

Figure 4-6. DO Pause Trigger with Other Signal Source

Using a Digital Source

To use DO Pause Trigger, specify a source and a polarity. The source can be a PFI signal or one of several other internal signals on the cDAQ chassis.

You also can specify whether the samples are paused when DO Pause Trigger is at a logic high or low level. Refer to the Device Routing in MAX topic in the NI-DAQmx Help or the LabVIEW Help for more information.

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is called the Analog Comparison Event, depending on the trigger properties.

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

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Getting Started with DO Applications in Software

You can use the cDAQ chassis in the following digital output applications:

• Single-point (on-demand) generation

• Finite generation

• Continuous generation

For more information about programming digital output applications and triggers in software, refer the LabVIEW Help or to the NI-DAQmx Help.

Digital Input/Output Configuration for NI 9401

When you change the configuration of lines on a NI 9401 digital module between input and output, NI-DAQmx temporarily reserves all of the lines on the module for communication to send the module a line configuration command. For this reason, you must reserve the task in advance through the DAQmx Control Task before any task has started. If another task or route is actively using the module, to avoid interfering with the other task, NI-DAQmx generates an error instead of sending the line configuration command. During the line configuration command, the output lines are maintained without glitching.

PFI

You can configure channels of a parallel digital module as Programmable Function Interface (PFI) terminals. The cDAQ-9188 chassis also provides two terminals for PFI. Up to two digital modules can be used to access PFI terminals in a single chassis.

You can configure each PFI individually as the following:

• Timing input signal for AI, AO, DI, DO, or counter/timer functions

• Timing output signal from AI, AO, DI, DO, or counter/timer functions

PFI Filters

You can enable a programmable debouncing filter on each PFI signal. When the filter is enabled, the chassis samples the inputs with a user-configured Filter Clock derived from the chassis timebase. This is used to determine whether a pulse is propagated to the rest of the circuit. However, the filter also introduces jitter onto the PFI signal.

The following is an example of low-to-high transitions of the input signal. High-to-low transitions work similarly.

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Chapter 4 Digital Input/Output and PFI

Assume that an input terminal has been low for a long time. The input terminal then changes from low to high, but glitches several times. When the Filter Clock has sampled the signal high on N consecutive edges, the low-to-high transition is propagated to the rest of the circuit. The value of N depends on the filter setting, as shown in Table 4-1.

Table 4-1. Selectable PFI Filter Settings

Min Pulse

Width

Filter Setting Filter Clock Jitter

Pass

Max Pulse Width*

to Not Pass

112.5 ns (short) 80 MHz 12.5 ns 112.5 ns 100 ns

6.4 μs

80 MHz 12.5 ns 6.4 μs 6.3875 μs

(medium)

2.56 ms (high) 100 kHz 10 μs 2.56 ms 2.55 ms

Custom User-configurable 1 Filter

Clock

user

- (1 Filter Clock

user

period)

period

Pulse widths are nominal values; the accuracy of the chassis timebase and I/O distortion will affect

these values.

On power up, the filters are disabled. Figure 4-7 shows an example of a low-to-high transition on an input that has a custom filter set to N = 5.

Figure 4-7. PFI Filter Example

PFI Terminal

Filter Clock

Filtered Input

12314123 45

Filtered input goes high when terminal is sampled high on five consecutive filter clocks.

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Counter 0

Counter 0 Source (Counter 0 Timebase)

Counter 0 Aux

Counter 0 HW Arm

Counter 0 A

Counter 0 B (Counter 0 Up_Down)

Counter 0 Z

Counter 0 Gate

Counter 0 Internal Output

Counter 0 TC

Input Selection Muxes

Frequency Generator

Frequency Output Timebase Freq Out

Input Selection Muxes

Embedded Ctr0

FIFO

Counter 0 Sample Clock

Counters

The cDAQ chassis has four general-purpose 32-bit counter/timers and one frequency generator. The general-purpose counter/timers can be used for many measurement and pulse generation applications. Figure 5-1 shows the cDAQ chassis Counter 0 and the frequency generator. All four counters on the cDAQ chassis are identical.

Figure 5-1. Chassis Counter 0 and Frequency Generator

Counters have eight input signals, although in most applications only a few inputs are used.

For information about connecting counter signals, refer to the Default Counter/Timer Routing section.

Each counter has a FIFO that can be used for buffered acquisition and generation. Each counter also contains an embedded counter (Embedded Ctrn) for use in what are traditionally two-counter measurements and generations. The embedded counters cannot be programmed independent of the main counter; signals from the embedded counters are not routable.

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Chapter 5 Counters

Counter Timing Engine

Unlike analog input, analog output, digital input, and digital output, the cDAQ chassis counters do not have the ability to divide down a timebase to produce an internal counter sample clock. For sample clocked operations, an external signal must be provided to supply a clock source. The source can be any of the following signals:

• AI Sample Clock

• AI Start Trigger

• AI Reference Trigger

• AO Sample Clock

• DI Sample Clock

• DI Start Trigger

• DO Sample Clock

•CTR n Internal Output

• Freq Out

• PFI

• Change Detection Event

• Analog Comparison Event

Not all timed counter operations require a sample clock. For example, a simple buffered pulse width measurement latches in data on each edge of a pulse. For this measurement, the measured signal determines when data is latched in. These operations are referred to as implicit timed operations. However, many of the same measurements can be clocked at an interval with a sample clock. These are referred to as sample clocked operations. Table 5-1 shows the different options for the different measurements.

Table 5-1. Counter Timing Measurements

Measurement

Implicit

Timing Support

Sample Clocked

Timing Support

Buffered Edge Count No Yes

Buffered Pulse Width Ye s Yes

Buffered Pulse Ye s Yes

Buffered Semi-Period Ye s No

Buffered Frequency Yes Ye s

Buffered Period Ye s Yes

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Counter Armed

SOURCE

Counter Value105432

Table 5-1. Counter Timing Measurements (Continued)

Implicit

Measurement

Buffered Position No Ye s

Buffered Two-Signal Edge Separation Ye s Ye s

Timing Support

Sample Clocked

Timing Support

Counter Input Applications

The following sections list the various counter input applications available on the cDAQ chassis:

• Counting Edges

• Pulse-Width Measurement

• Pulse Measurement

• Semi-Period Measurement

• Frequency Measurement

• Period Measurement

• Position Measurement

Counting Edges

In edge counting applications, the counter counts edges on its Source after the counter is armed. You can configure the counter to count rising or falling edges on its Source input. You also can control the direction of counting (up or down), as described in the Controlling the Direction of

Counting section. The counter values can be read on demand or with a sample clock.

Refer to the following sections for more information about edge counting options:

• Single Point (On-Demand) Edge Counting

• Buffered (Sample Clock) Edge Counting

Single Point (On-Demand) Edge Counting

With single point (on-demand) edge counting, the counter counts the number of edges on the Source input after the counter is armed. On-demand refers to the fact that software can read the counter contents at any time without disturbing the counting process. Figure 5-2 shows an example of single point edge counting.

Figure 5-2. Single Point (On-Demand) Edge Counting

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Chapter 5 Counters

Counter Armed

SOURCE

Pause Trigger

(Pause When Low)

Counter Value

100 5432

You also can use a pause trigger to pause (or gate) the counter. When the pause trigger is active, the counter ignores edges on its Source input. When the pause trigger is inactive, the counter counts edges normally.

You can route the pause trigger to the Gate input of the counter. You can configure the counter to pause counting when the pause trigger is high or when it is low. Figure 5-3 shows an example of on-demand edge counting with a pause trigger.

Figure 5-3. Single Point (On-Demand) Edge Counting with Pause Trigger

Buffered (Sample Clock) Edge Counting

With buffered edge counting (edge counting using a sample clock), the counter counts the number of edges on the Source input after the counter is armed. The value of the counter is sampled on each active edge of a sample clock and stored in the FIFO. The STC3 transfers the sampled values to host memory using a high-speed data stream.

The count values returned are the cumulative counts since the counter armed event. That is, the sample clock does not reset the counter. You can configure the counter to sample on the rising or falling edge of the sample clock.

Figure 5-4 shows an example of buffered edge counting. Notice that counting begins when the counter is armed, which occurs before the first active edge on Sample Clock.

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(Sample on Rising Edge)

Figure 5-4. Buffered (Sample Clock) Edge Counting

Counter Armed

Sample Clock

SOURCE

Counter Value

Buffer

10763 452

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Controlling the Direction of Counting

In edge counting applications, the counter can count up or down. You can configure the counter to do the following:

• Always count up

• Always count down

• Count up when the Counter 0 B input is high; count down when it is low

For information about connecting counter signals, refer to the Default Counter/Timer Routing section.

Pulse-Width Measurement

In pulse-width measurements, the counter measures the width of a pulse on its Gate input signal. You can configure the counter to measure the width of high pulses or low pulses on the Gate signal.

You can route an internal or external periodic clock signal (with a known period) to the Source input of the counter. The counter counts the number of rising (or falling) edges on the Source signal while the pulse on the Gate signal is active.

You can calculate the pulse width by multiplying the period of the Source signal by the number of edges returned by the counter.

A pulse-width measurement will be accurate even if the counter is armed while a pulse train is in progress. If a counter is armed while the pulse is in the active state, it will wait for the next transition to the active state to begin the measurement.

Refer to the following sections for more information about cDAQ chassis pulse-width measurement options:

• Single Pulse-Width Measurement

• Implicit Buffered Pulse-Width Measurement

• Sample Clocked Buffered Pulse-Width Measurement

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Chapter 5 Counters

SOURCE

GATE

Counter Value

Latched Value

Single Pulse-Width Measurement

With single pulse-width measurement, the counter counts the number of edges on the Source input while the Gate input remains active. When the Gate input goes inactive, the counter stores the count in the FIFO and ignores other edges on the Gate and Source inputs. Software then reads the stored count.

Figure 5-5 shows an example of a single pulse-width measurement.

Figure 5-5. Single Pulse-Width Measurement

Implicit Buffered Pulse-Width Measurement

An implicit buffered pulse-width measurement is similar to single pulse-width measurement, but buffered pulse-width measurement takes measurements over multiple pulses.

The counter counts the number of edges on the Source input while the Gate input remains active. On each trailing edge of the Gate signal, the counter stores the count in the counter FIFO. The STC3 transfers the sampled values to host memory using a high-speed data stream.

Figure 5-6 shows an example of an implicit buffered pulse-width measurement.

Sample Clocked Buffered Pulse-Width Measurement

A sample clocked buffered pulse-width measurement is similar to single pulse-width measurement, but buffered pulse-width measurement takes measurements over multiple pulses correlated to a sample clock.

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Figure 5-6. Implicit Buffered Pulse-Width Measurement

GATE

SOURCE

Counter Value

Buffer

10 3

212

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Pulse

Source

Sample Clock

2 342

2 2

Buffer

The counter counts the number of edges on the Source input while the Gate input remains active. On each sample clock edge, the counter stores the count in the FIFO of the last pulse width to complete. The STC3 transfers the sampled values to host memory using a high-speed data stream.

Figure 5-7 shows an example of a sample clocked buffered pulse-width measurement.

Figure 5-7. Sample Clocked Buffered Pulse-Width Measurement

Note If a pulse does not occur between sample clocks, an overrun error occurs.

For information about connecting counter signals, refer to the Default Counter/Timer Routing section.

Pulse Measurement

In pulse measurements, the counter measures the high and low time of a pulse on its Gate input signal after the counter is armed. A pulse is defined in terms of its high and low time, high and low ticks or frequency and duty cycle. This is similar to the pulse-width measurement, except that the inactive pulse is measured as well.

You can route an internal or external periodic clock signal (with a known period) to the Source input of the counter. The counter counts the number of rising (or falling) edges occurring on the Source input between two edges of the Gate signal.

You can calculate the high and low time of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter.

Refer to the following sections for more information about cDAQ chassis pulse measurement options:

• Single Pulse Measurement

• Implicit Buffered Pulse Measurement

• Sample Clocked Buffered Pulse Measurement

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Chapter 5 Counters

Counter Armed

Gate

Source

710

Latched

Value

987654321564321

Single Pulse Measurement

Single (on-demand) pulse measurement is equivalent to two single pulse-width measurements on the high (H) and low (L) ticks of a pulse, as shown in Figure 5-8.

Figure 5-8. Single (On-Demand) Pulse Measurement

Implicit Buffered Pulse Measurement

In an implicit buffered pulse measurement, on each edge of the Gate signal, the counter stores the count in the FIFO. The STC3 transfers the sampled values to host memory using a high-speed data stream.

The counter begins counting when it is armed. The arm usually occurs between edges on the Gate input but the counting does not start until the desired edge. You can select whether to read the high pulse or low pulse first using the StartingEdge property in NI-DAQmx.

Figure 5-9 shows an example of an implicit buffered pulse measurement.

Figure 5-9. Implicit Buffered Pulse Measurement

Counter Armed

Gate

Source

Buffer

42 4

4 4

4 2

4 44 6 2

2 2

Sample Clocked Buffered Pulse Measurement

A sample clocked buffered pulse measurement is similar to single pulse measurement, but a buffered pulse measurement takes measurements over multiple pulses correlated to a sample clock.

The counter performs a pulse measurement on the Gate. On each sample clock edge, the counter stores the high and low ticks in the FIFO of the last pulse to complete. The STC3 transfers the sampled values to host memory using a high-speed data stream.

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Counter

Armed

Gate

Source

HL 2

Sample

Clock

Buffer

Figure 5-10 shows an example of a sample clocked buffered pulse measurement.

Figure 5-10. Sample Clocked Buffered Pulse Measurement

Note If a pulse does not occur between sample clocks, an overrun error occurs.

For information about connecting counter signals, refer to the Default Counter/Timer Routing section.

Semi-Period Measurement

In semi-period measurements, the counter measures a semi-period on its Gate input signal after the counter is armed. A semi-period is the time between any two consecutive edges on the Gate input.

You can calculate the semi-period of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter.

Refer to the following sections for more information about semi-period measurement options:

• Single Semi-Period Measurement

• Implicit Buffered Semi-Period Measurement

Refer to the Pulse versus Semi-Period Measurements section for information about the differences between semi-period measurement and pulse measurement.

Single Semi-Period Measurement

Single semi-period measurement is equivalent to single pulse-width measurement.

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Chapter 5 Counters

1 2

SOURCE

GATE

Counter Value

Buffer

1 3

Counter

Armed

Starting

Edge

Implicit Buffered Semi-Period Measurement

In implicit buffered semi-period measurements, on each edge of the Gate signal, the counter stores the count in the FIFO. The STC3 transfers the sampled values to host memory using a high-speed data stream.

The counter begins counting when it is armed. The arm usually occurs between edges on the Gate input. You can select whether to read the first active low or active high semi period using the CI.SemiPeriod.StartingEdge property in NI-DAQmx.

Figure 5-11 shows an example of an implicit buffered semi-period measurement.

Figure 5-11. Implicit Buffered Semi-Period Measurement

For information about connecting counter signals, refer to the Default Counter/Timer Routing section.

Pulse versus Semi-Period Measurements

In hardware, pulse measurement and semi-period are the same measurement. Both measure the high and low times of a pulse. The functional difference between the two measurements is how the data is returned. In a semi-period measurement, each high or low time is considered one point of data and returned in units of seconds or ticks. In a pulse measurement, each pair of high and low times is considered one point of data and returned as a paired sample in units of frequency and duty cycle, high and low time or high and low ticks. When reading data, 10 points in a semi-period measurement will get an array of five high times and five low times. When you read 10 points in a pulse measurement, you get an array of 10 pairs of high and low times.

Also, pulse measurements support sample clock timing while semi-period measurements do not.

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Gate

Source

123 … N

Single Period

Measurement

…

Period of fx =

Frequency of fx =

Interval Measured

Frequency Measurement

You can use the counters to measure frequency in several different ways. Refer to the following sections for information about cDAQ chassis frequency measurement options:

• Low Frequency with One Counter

• High Frequency with Two Counters

• Large Range of Frequencies with Two Counters

• Sample Clocked Buffered Frequency Measurement

Low Frequency with One Counter

For low frequency measurements with one counter, you measure one period of your signal using a known timebase.

You can route the signal to measure (fx) to the Gate of a counter. You can route a known timebase (fk) to the Source of the counter. The known timebase can be an onboard timebase, such as 80 MHz Timebase, 20 MHz Timebase, or 100 kHz Timebase, or any other signal with a known rate.

You can configure the counter to measure one period of the gate signal. The frequency of fx is the inverse of the period. Figure 5-12 illustrates this method.

Figure 5-12. Low Frequency with One Counter

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Chapter 5 Counters

Pulse

Gate

Source

12… N

Pulse-Width

Measurement

T =

Frequency of fx =

Width of

Pulse

Width of Pulse (T )

High Frequency with Two Counters

For high frequency measurements with two counters, you measure one pulse of a known width using your signal and derive the frequency of your signal from the result.

Note Counter 0 is always paired with Counter 1. Counter 2 is always paired with

Counter 3.

In this method, you route a pulse of known duration (T) to the Gate of a counter. You can generate the pulse using a second counter. You also can generate the pulse externally and connect it to a PFI terminal. You only need to use one counter if you generate the pulse externally.

Route the signal to measure (fx) to the Source of the counter. Configure the counter for a single pulse-width measurement. If you measure the width of pulse T to be N periods of fx, the frequency of fx is N/T.

Figure 5-13 illustrates this method. Another option is to measure the width of a known period instead of a known pulse.

Figure 5-13. High Frequency with Two Counters

Large Range of Frequencies with Two Counters

By using two counters, you can accurately measure a signal that might be high or low frequency. This technique is called reciprocal frequency measurement. When measuring a large range of frequencies with two counters, you generate a long pulse using the signal to measure. You then measure the long pulse with a known timebase. The cDAQ chassis can measure this long pulse more accurately than the faster input signal.

Note Counter 0 is always paired with Counter 1. Counter 2 is always paired with

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Counter 3.

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Source Out

Counter 0

Source

Gate

Out

Counter 1

Signal to

Measure (fx)

Signal of Known

Frequency (fk)

CTR_0_SOURCE

(Signal to Measure)

CTR_0_OUT

(CTR_1_GATE)

CTR_1_SOURCE

Interval

to Measure

0123 … N

You can route the signal to measure to the Source input of Counter 0, as shown in Figure 5-14. Assume this signal to measure has frequency fx. NI-DAQmx automatically configures Counter 0 to generate a single pulse that is the width of N periods of the source input signal.

Figure 5-14. Large Range of Frequencies with Two Counters

Next, route the Counter 0 Internal Output signal to the Gate input of Counter 1. You can route a signal of known frequency (fk) to the Counter 1 Source input. Configure Counter 1 to perform a single pulse-width measurement. Suppose the result is that the pulse width is J periods of the fk clock.

From Counter 0, the length of the pulse is N/fx. From Counter 1, the length of the same pulse is J/fk. Therefore, the frequency of fx is given by fx = fk *(N/J).

Sample Clocked Buffered Frequency Measurement

Sample clocked buffered point frequency measurements can either be a single frequency measurement or an average between sample clocks. Use CI.Freq.EnableAveraging to set the behavior. For buffered frequency, the default is True.

A sample clocked buffered frequency measurement with CI.Freq.EnableAveraging set to True uses the embedded counter and a sample clock to perform a frequency measurement. For each sample clock period, the embedded counter counts the signal to measure (fx) and the primary counter counts the internal time-base of a known frequency (fk). Suppose T1 is the number of ticks of the unknown signal counted between sample clocks and T2 is the number of ticks counted of the known timebase as shown in Figure 5-15. The frequency measured is:

fx = fk * (T1/T2)

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Chapter 5 Counters

Figure 5-15. Sample Clocked Buffered Frequency Measurement (Averaging)

Counter Armed

S1 S2 S3

Gate

(fx)

Source

(fk)

Sample

Clock

Buffer

121

6106

T1 T2

17 210

When CI.Freq.EnableAveraging is set to false, the frequency measurement returns the frequency of the pulse just before the sample clock. This single measurement is a single frequency measurement and is not an average between clocks as shown in Figure 5-16.

Figure 5-16. Sample Clocked Buffered Frequency Measurement (Non-Averaging)

Counter Armed

Gate

T1 T2

1 2 1

Source

Sample

Clock

Latched

Values

646

6 4

6 4 6

With sample clocked frequency measurements, ensure that the frequency to measure is twice as fast as the sample clock to prevent a measurement overflow.

Choosing a Method for Measuring Frequency

The best method to measure frequency depends on several factors including the expected frequency of the signal to measure, the desired accuracy, how many counters are available, and how long the measurement can take. For all frequency measurement methods, assume the following:

fx is the frequency to be measured if no error

fk is the known source or gate frequency

measurement time (T) is the time it takes to measure a single sample

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gating period

-------------------------------

--- -

----

---- 1–×

------------------------------ -×

fk fx–

-------------- -×

Nfkfx–×

-------------------------×

fx fs

---- 1–×

------------------------------ -

fk fx–

-------------- -

fk fx

----

Nfkfx–×

-------------------------

Divide down (N) is the integer to divide down measured frequency, only used in

large range two counters

fs is the sample clock rate, only used in sample clocked frequency

measurements

Here is how these variables apply to each method, summarized in Table 5-2.

• One counter—With one counter measurements, a known timebase is used for the source frequency (fk). The measurement time is the period of the frequency to be measured, or 1/fx.

• Two counter high frequency—With the two counter high frequency method, the second counter provides a known measurement time. The gate frequency equals 1/measurement time.

• Two counter large range—The two counter larger range measurement is the same as a one counter measurement, but now the user has an integer divide down of the signal. An internal timebase is still used for the source frequency (fk), but the divide down means that the measurement time is the period of the divided down signal, or N/fx where N is the divide down.

• Sample clocked—For sample clocked frequency measurements, a known timebase is counted for the source frequency (fk). The measurement time is the period of the sample clock (fs).

Table 5-2. Frequency Measurement Methods

Two Counter

One

Var iable Sample Clocked

Counter

fk Known timebase Known

High

Frequency

Large Range

Known timebase

timebase

Measureme

gating period

nt time

Max.

frequency error

Max. error %

Note: Accuracy equations do not take clock stability into account. Refer to the specifications document for your cDAQ chassis for information about clock stability.

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Chapter 5 Counters

Which Method Is Best?

This depends on the frequency to be measured, the rate at which you want to monitor the frequency and the accuracy you desire. Take for example, measuring a 50 kHz signal. Assuming that the measurement times for the sample clocked (with averaging) and two counter frequency measurements are configured the same, Table 5-3 summarizes the results.

Table 5-3. 50 kHz Frequency Measurement Methods

Two Counter

Var iable

Sample

Clocked

One Counter

High

Frequency

Large Range

fx 50,000 50,000 50,000 50,000

fk 80 M 80 M 1,000 80 M

Measurement

1 .02 1 1

time (mS)

N — — — 50

Max. frequency

.638 31.27 1,000 .625

error (Hz)

Max. error % .00128 .0625 2 .00125

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NI cDAQ-9181/9184/9188/9191 User Manual

From this, you can see that while the measurement time for one counter is shorter, the accuracy is best in the sample clocked and two counter large range measurements. For another example, Table 5-4 shows the results for 5 MHz.

Table 5-4. 5 MHz Frequency Measurement Methods

Two Counter

Var iable

Sample

Clocked

One Counter

High

Frequency

Large Range

fx 5 M 5 M 5 M 5 M

fk 80 M 80 M 1,000 80 M

Measurement

1 .0002 1 1

time (mS)

N — — — 5,000

Max.

62.51 333 k 1,000 62.50 Frequency error (Hz)

Max. Error % .00125 6.67 .02 .00125

Again the measurement time for the one counter measurement is lowest but the accuracy is lower. Note that the accuracy and measurement time of the sample clocked and two counter large range are almost the same. The advantage of the sample clocked method is that even when the frequency to measure changes, the measurement time does not and error percentage varies little. For example, if you configured a large range two counter measurement to use a divide down of 50 for a 50 k signal, then you would get the accuracy measurement time and accuracy listed in Table 5-3. But if your signal ramped up to 5 M, then with a divide down of 50, your measurement time is 0.01 ms, but your error is now 0.125%. The error with a sample clocked frequency measurement is not as dependent on the measured frequency so at 50 k and 5 M with a measurement time of 1 ms the error percentage is still close to 0.00125%. One of the disadvantages of a sample clocked frequency measurement is that the frequency to be measured must be at least twice the sample clock rate to ensure that a full period of the frequency to be measured occurs between sample clocks.

• Low frequency measurements with one counter is a good method for many applications. However, the accuracy of the measurement decreases as the frequency increases.

• High frequency measurements with two counters is accurate for high frequency signals. However, the accuracy decreases as the frequency of the signal to measure decreases. At very low frequencies, this method may be too inaccurate for your application. Another disadvantage of this method is that it requires two counters (if you cannot provide an external signal of known width). An advantage of high frequency measurements with two counters is that the measurement completes in a known amount of time.

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Chapter 5 Counters

• Measuring a large range of frequencies with two counters measures high and low frequency signals accurately. However, it requires two counters, and it has a variable sample time and variable error % dependent on the input signal.

Table 5-5 summarizes some of the differences in methods of measuring frequency.

Table 5-5. Frequency Measurement Method Comparison

Measures

High

Frequency

Signals

Accurately

Measures Low

Frequency

Signals

Accurately

Method

Number

Counters

Used

Number of

Measurements

Returned

Low frequency

1 1 Poor Good

with one counter

High frequency

1 or 2 1 Good Poor with two counters

Large range of

2 1 Good Good frequencies with two counters

Sample clocked

1 1 Good Good (averaged)

For information about connecting counter signals, refer to the Default Counter/Timer Routing section.

Period Measurement

In period measurements, the counter measures a period on its Gate input signal after the counter is armed. You can configure the counter to measure the period between two rising edges or two falling edges of the Gate input signal.

You can calculate the period of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter.

Period measurements return the inverse results of frequency measurements. Refer to the

Frequency Measurement section for more information.

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NI cDAQ-9181/9184/9188/9191 User Manual

Position Measurement

You can use the counters to perform position measurements with quadrature encoders or two-pulse encoders. You can measure angular position with X1, X2, and X4 angular encoders. Linear position can be measured with two-pulse encoders. You can choose to do either a single point (on-demand) position measurement or a buffered (sample clock) position measurement. You must arm a counter to begin position measurements.

Refer to the following sections for more information about the cDAQ chassis position measurement options:

• Measurements Using Quadrature Encoders

• Measurements Using Two Pulse Encoders

• Buffered (Sample Clock) Position Measurement

Measurements Using Quadrature Encoders

The counters can perform measurements of quadrature encoders that use X1, X2, or X4 encoding. A quadrature encoder can have up to three channels—channels A, B, and Z.

• X1 Encoding—When channel A leads channel B in a quadrature cycle, the counter increments. When channel B leads channel A in a quadrature cycle, the counter decrements. The amount of increments and decrements per cycle depends on the type of encoding—X1, X2, or X4.

Figure 5-17 shows a quadrature cycle and the resulting increments and decrements for X1 encoding. When channel A leads channel B, the increment occurs on the rising edge of channel A. When channel B leads channel A, the decrement occurs on the falling edge of channel A.

Figure 5-17. X1 Encoding

Ch A Ch B

Counter Value

• X2 Encoding—The same behavior holds for X2 encoding except the counter increments or decrements on each edge of channel A, depending on which channel leads the other. Each cycle results in two increments or decrements, as shown in Figure 5-18.

Figure 5-18. X2 Encoding

7 7 6 5

Ch A

Ch B

Counter Value

56 8 97 56

9 7

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Chapter 5 Counters

Ch A

Ch B

Counter Value5 6 8 910 1011 1112 1213 137

568 79

Ch A

Ch B

Counter Value

A = 0 B = 0 Z = 1

Ch Z

Max Timebase

021743

• X4 Encoding—Similarly, the counter increments or decrements on each edge of channels A and B for X4 encoding. Whether the counter increments or decrements depends on which channel leads the other. Each cycle results in four increments or decrements, as shown in Figure 5-19.

Figure 5-19. X4 Encoding

Channel Z Behavior

Some quadrature encoders have a third channel, channel Z, which is also referred to as the index channel. A high level on channel Z causes the counter to be reloaded with a specified value in a specified phase of the quadrature cycle. You can program this reload to occur in any one of the four phases in a quadrature cycle.

Channel Z behavior—when it goes high and how long it stays high—differs with quadrature encoder designs. You must refer to the documentation for your quadrature encoder to obtain timing of channel Z with respect to channels A and B. You must then ensure that channel Z is high during at least a portion of the phase you specify for reload. For instance, in Figure 5-20, channel Z is never high when channel A is high and channel B is low. Thus, the reload must occur in some other phase.

In Figure 5-20, the reload phase is when both channel A and channel B are low. The reload occurs when this phase is true and channel Z is high. Incrementing and decrementing takes priority over reloading. Thus, when the channel B goes low to enter the reload phase, the increment occurs first. The reload occurs within one maximum timebase period after the reload phase becomes true. After the reload occurs, the counter continues to count as before. The figure illustrates channel Z reload with X4 decoding.

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Figure 5-20. Channel Z Reload with X4 Decoding

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NI cDAQ-9181/9184/9188/9191 User Manual

Ch A

Ch B

3102 4

Count

Buffer

Sample Clock

(Sample on Rising Edge)

Counter Armed

Measurements Using Two Pulse Encoders

The counter supports two pulse encoders that have two channels—channels A and B.

The counter increments on each rising edge of channel A. The counter decrements on each rising edge of channel B, as shown in Figure 5-21.

Figure 5-21. Measurements Using Two Pulse Encoders

Ch A

Ch B

Counter Value

2 3 54 344

For information about connecting counter signals, refer to the Default Counter/Timer Routing section.

Buffered (Sample Clock) Position Measurement

With buffered position measurement (position measurement using a sample clock), the counter increments based on the encoding used after the counter is armed. The value of the counter is sampled on each active edge of a sample clock. The STC3 transfers the sampled values to host memory using a high-speed data stream. The count values returned are the cumulative counts since the counter armed event; that is, the sample clock does not reset the counter. You can route the counter sample clock to the Gate input of the counter. You can configure the counter to sample on the rising or falling edge of the sample clock.

Figure 5-22 shows an example of a buffered X1 position measurement.

Figure 5-22. Buffered Position Measurement

Two-Signal Edge-Separation Measurement

Two-signal edge-separation measurement is similar to pulse-width measurement, except that there are two measurement signals—Aux and Gate. An active edge on the Aux input starts the counting and an active edge on the Gate input stops the counting. You must arm a counter to begin a two edge separation measurement.

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Chapter 5 Counters

AUX

Counter

Armed

000123 4567880 8

Measured Interval

GATE

SOURCE

Counter Value

Latched Value

After the counter has been armed and an active edge occurs on the Aux input, the counter counts the number of rising (or falling) edges on the Source. The counter ignores additional edges on the Aux input.

The counter stops counting upon receiving an active edge on the Gate input. The counter stores the count in the FIFO.

You can configure the rising or falling edge of the Aux input to be the active edge. You can configure the rising or falling edge of the Gate input to be the active edge.

Use this type of measurement to count events or measure the time that occurs between edges on two signals. This type of measurement is sometimes referred to as start/stop trigger measurement, second gate measurement, or A-to-B measurement.

Refer to the following sections for more information about the cDAQ chassis edge-separation measurement options:

• Single Two-Signal Edge-Separation Measurement

• Implicit Buffered Two-Signal Edge-Separation Measurement

• Sample Clocked Buffered Two-Signal Separation Measurement

Single Two-Signal Edge-Separation Measurement

With single two-signal edge-separation measurement, the counter counts the number of rising (or falling) edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal. The counter then stores the count in the FIFO and ignores other edges on its inputs. Software then reads the stored count.

Figure 5-23 shows an example of a single two-signal edge-separation measurement.

Figure 5-23. Single Two-Signal Edge-Separation Measurement

Implicit Buffered Two-Signal Edge-Separation Measurement

Implicit buffered and single two-signal edge-separation measurements are similar, but implicit buffered measurement measures multiple intervals.

The counter counts the number of rising (or falling) edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal. The counter then stores

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NI cDAQ-9181/9184/9188/9191 User Manual

the count in the FIFO. On the next active edge of the Gate signal, the counter begins another measurement. The STC3 transfers the sampled values to host memory using a high-speed data stream.

Figure 5-24 shows an example of an implicit buffered two-signal edge-separation measurement.

Figure 5-24. Implicit Buffered Two-Signal Edge-Separation Measurement

AUX

GATE

SOURCE

Counter Value

Buffer

123 123 123

3 3

3 3 3

Sample Clocked Buffered Two-Signal Separation Measurement

A sample clocked buffered two-signal separation measurement is similar to single two-signal separation measurement, but buffered two-signal separation measurement takes measurements over multiple intervals correlated to a sample clock. The counter counts the number of rising (or falling) edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal. The counter then stores the count in the FIFO on a sample clock edge. On the next active edge of the Gate signal, the counter begins another measurement. The STC3 transfers the sampled values to host memory using a high-speed data stream.

Figure 5-25 shows an example of a sample clocked buffered two-signal separation measurement.

Figure 5-25. Sample Clocked Buffered Two-Signal Separation Measurement

Sample

Clock

AUX

GATE

SOURCE

Counter Value

Buffer

123 12 3 123

3 3

Note If an active edge on the Gate and an active edge on the Aux do not occur

between sample clocks, an overrun error occurs.

For information about connecting counter signals, refer to the Default Counter/Timer Routing section.

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Chapter 5 Counters

SOURCE

OUT

Counter Armed

Counter Output Applications

The following sections list the various counter output applications available on the cDAQ chassis:

• Simple Pulse Generation

• Pulse Train Generation

• Frequency Generation

• Frequency Division

• Pulse Generation for ETS

Simple Pulse Generation

Refer to the following sections for more information about the cDAQ chassis simple pulse generation options:

• Single Pulse Generation

• Single Pulse Generation with Start Trigger

Single Pulse Generation

The counter can output a single pulse. The pulse appears on the Counter n Internal Output signal of the counter.

You can specify a delay from when the counter is armed to the beginning of the pulse. The delay is measured in terms of a number of active edges of the Source input.

You can specify a pulse width. The pulse width is also measured in terms of a number of active edges of the Source input. You also can specify the active edge of the Source input (rising or falling).

Figure 5-26 shows a generation of a pulse with a pulse delay of four and a pulse width of three (using the rising edge of Source).

Figure 5-26. Single Pulse Generation

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NI cDAQ-9181/9184/9188/9191 User Manual

Single Pulse Generation with Start Trigger

The counter can output a single pulse in response to one pulse on a hardware Start Trigger signal. The pulse appears on the Counter n Internal Output signal of the counter.

You can specify a delay from the Start Trigger to the beginning of the pulse. You also can specify the pulse width. The delay is measured in terms of a number of active edges of the Source input.

You can specify a pulse width. The pulse width is also measured in terms of a number of active edges of the Source input. You can also specify the active edge of the Source input (rising and falling).

Figure 5-27 shows a generation of a pulse with a pulse delay of four and a pulse width of three (using the rising edge of Source).

Figure 5-27. Single Pulse Generation with Start Trigger

GATE

(Start Trigger)

SOURCE

OUT

Pulse Train Generation

Refer to the following sections for more information about the cDAQ chassis pulse train generation options:

• Finite Pulse Train Generation

• Retriggerable Pulse or Pulse Train Generation

• Continuous Pulse Train Generation

• Buffered Pulse Train Generation

• Finite Implicit Buffered Pulse Train Generation

• Continuous Buffered Implicit Pulse Train Generation

• Finite Buffered Sample Clocked Pulse Train Generation

• Continuous Buffered Sample Clocked Pulse Train Generation

Finite Pulse Train Generation

This function generates a train of pulses with programmable frequency and duty cycle for a predetermined number of pulses. With cDAQ chassis counters, the primary counter generates the specified pulse train and the embedded counter counts the pulses generated by the primary counter. When the embedded counter reaches the specified tick count, it generates a trigger that stops the primary counter generation.

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Chapter 5 Counters

Enablex

Source

Ctrx

Counter Armed

SOURCE

GATE

(Start Trigger)

OUT

5 3 5 3

Counter

Load Values

4 3 210210 43 210210

Figure 5-28. Finite Pulse Train Generation: Four Ticks Initial Delay, Four Pulses

Retriggerable Pulse or Pulse Train Generation

The counter can output a single pulse or multiple pulses in response to each pulse on a hardware Start Trigger signal. The generated pulses appear on the Counter n Internal Output signal of the counter.

You can route the Start Trigger signal to the Gate input of the counter. You can specify a delay from the Start Trigger to the beginning of each pulse. You also can specify the pulse width. The delay and pulse width are measured in terms of a number of active edges of the Source input. The initial delay can be applied to only the first trigger or to all triggers using the CO.EnableInitalDelayOnRetrigger property. The default for a single pulse is True, while the default for finite pulse trains is False.

The counter ignores the Gate input while a pulse generation is in progress. After the pulse generation is finished, the counter waits for another Start Trigger signal to begin another pulse generation. For retriggered pulse generation, pause triggers are not allowed since the pause trigger also uses the gate input.

Figure 5-29 shows a generation of two pulses with a pulse delay of five and a pulse width of three (using the rising edge of Source) with CO.EnableInitalDelayOnRetrigger set to the default True.

Figure 5-29. Retriggerable Single Pulse Generation with Initial Delay on Retrigger

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NI cDAQ-9181/9184/9188/9191 User Manual

SOURCE

OUT

Counter Armed

Figure 5-30 shows the same pulse train with CO.EnableInitalDelayOnRetrigger set to the default False.

Figure 5-30. Retriggerable Single Pulse Generation False

Counter

Load Values

GATE

(Start Trigger)

SOURCE

4 3 210210 43 210210

OUT

5 3 2 3

Note The minimum time between the trigger and the first active edge is two ticks

of the source.

For information about connecting counter signals, refer to the Default Counter/Timer Routing section.

Continuous Pulse Train Generation

This function generates a train of pulses with programmable frequency and duty cycle. The pulses appear on the Counter n Internal Output signal of the counter.

You can specify a delay from when the counter is armed to the beginning of the pulse train. The delay is measured in terms of a number of active edges of the Source input.

You specify the high and low pulse widths of the output signal. The pulse widths are also measured in terms of a number of active edges of the Source input. You also can specify the active edge of the Source input (rising or falling).

The counter can begin the pulse train generation as soon as the counter is armed, or in response to a hardware Start Trigger. You can route the Start Trigger to the Gate input of the counter.

You also can use the Gate input of the counter as a Pause Trigger (if it is not used as a Start Trigger). The counter pauses pulse generation when the Pause Trigger is active.

Figure 5-31 shows a continuous pulse train generation (using the rising edge of Source).

Figure 5-31. Continuous Pulse Train Generation

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Chapter 5 Counters

Continuous pulse train generation is sometimes called frequency division. If the high and low pulse widths of the output signal are M and N periods, then the frequency of the Counter n Internal Output signal is equal to the frequency of the Source input divided by M + N.

For information about connecting counter signals, refer to the Default Counter/Timer Routing section.

Buffered Pulse Train Generation

The cDAQ chassis counters can use the FIFO to perform a buffered pulse train generation. This pulse train can use implicit timing or sample clock timing. When using implicit timing, the pulse idle time and active time changes with each sample you write. With sample clocked timing, each sample you write updates the idle time and active time of your generation on each sample clock edge. Idle time and active time can also be defined in terms of frequency and duty cycle or idle ticks and active ticks.

Note On buffered implicit pulse trains the pulse specifications in the DAQmx

Create Counter Output Channel are ignored so that you generate the number of pulses defined in the multipoint write. On buffered sample clock pulse trains the pulse specifications in the DAQmx Create Counter Output Channel are generated after the counters starts and before the first sample clock so that you generate the number of updates defined in the multipoint write.

Finite Implicit Buffered Pulse Train Generation

This function generates a predetermined number of pulses with variable idle and active times. Each point you write generates a single pulse. The number of pairs of idle and active times (pulse specifications) you write determines the number of pulses generated. All points are generated back to back to create a user defined pulse train.

Table 5-6 and Figure 5-32 detail a finite implicit generation of three samples.

Table 5-6. Finite Implicit Buffered Pulse Train Generation

Sample Idle Ticks Active Ticks

1 2 2

2 3 4

3 2 2

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NI cDAQ-9181/9184/9188/9191 User Manual

SOURCE

OUT

Counter Armed

2 3 42

Figure 5-32. Finite Implicit Buffered Pulse Train Generation

Continuous Buffered Implicit Pulse Train Generation

This function generates a continuous train of pulses with variable idle and active times. Instead of generating a set number of data samples and stopping, a continuous generation continues until you stop the operation. Each point you write generates a single pulse. All points are generated back to back to create a user defined pulse train.

Finite Buffered Sample Clocked Pulse Train Generation

This function generates a predetermined number of pulse train updates. Each point you write defines pulse specifications that are updated with each sample clock. When a sample clock occurs, the current pulse (idle followed by active) finishes generation and the next pulse updates with the next sample specifications.

Note When the last sample is generated, the pulse train continues to generate with

these specifications until the task is stopped.

Table 5-7 and Figure 5-33 detail a finite sample clocked generation of three samples where the pulse specifications from the create channel are two ticks idle, two ticks active, and three ticks initial delay.

Table 5-7. Finite Buffered Sample Clocked Pulse Train Generation

Sample Idle Ticks Active Ticks

1 3 3

2 2 2

3 3 3

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Chapter 5 Counters

Figure 5-33. Finite Buffered Sample Clocked Pulse Train Generation

Counter Armed

Sample

Clock

Counter

Load Values

Source

21010101 2102100 21021010 02102110

Out

3 222 33332 332

There are several different methods of continuous generation that control what data is written. These methods are regeneration, FIFO regeneration, and non-regeneration modes.

Regeneration is the repetition of the data that is already in the buffer.

Standard regeneration is when data from the PC buffer is continually downloaded to the FIFO to be written out. New data can be written to the PC buffer at any time without disrupting the output. With FIFO regeneration, the entire buffer is downloaded to the FIFO and regenerated from there. Once the data is downloaded, new data cannot be written to the FIFO. To use FIFO regeneration, the entire buffer must fit within the FIFO size. The advantage of using FIFO regeneration is that it does not require communication with the main host memory once the operation is started, thereby preventing any problems that may occur due to excessive bus traffic.

With non-regeneration, old data is not repeated. New data must be continually written to the buffer. If the program does not write new data to the buffer at a fast enough rate to keep up with the generation, the buffer underflows and causes an error.

Continuous Buffered Sample Clocked Pulse Train Generation

This function generates a continuous train of pulses with variable idle and active times. Instead of generating a set number of data samples and stopping, a continuous generation continues until you stop the operation. Each point you write specifies pulse specifications that are updated with each sample clock. When a sample clock occurs, the current pulse finishes generation and the next pulse uses the next sample specifications.

Frequency Generation

You can generate a frequency by using a counter in pulse train generation mode or by using the frequency generator circuit, as described in the Using the Frequency Generator section.

Using the Frequency Generator

The frequency generator can output a square wave at many different frequencies. The frequency generator is independent of the four general-purpose 32-bit counter/timer modules on the cDAQ chassis.

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National Instruments NI cDAQ-9181, NI cDAQ-9188, NI cDAQ-9184, NI cDAQ-9191 User Manual

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Contents

Figure 1-1. cDAQ-9181/9191 Chassis

Figure 1-2. cDAQ-9184 Chassis

Figure 1-3. cDAQ-9188 Chassis

Safety Guidelines

Electromagnetic Compatibility Guidelines

Special Guidelines for Marine Applications

Hardware Symbol Definitions

Unpacking

Installing the cDAQ Chassis

Table 1-1. cDAQ Chassis NI-DAQmx Software Support

Figure 1-4. Ring Lug Attached to Chassis Ground Terminal

Figure 1-5. Connecting to a Wireless Network

Figure 1-6. Chassis Connected - Running on Ethernet and Wireless Networks

Figure 1-7. MAX Icons and States

Figure 1-8. Chassis Connected - Running on Wireless Network

Wiring Power to the cDAQ Chassis

Figure 1-9. Power Screw Terminal Connector Plug

Troubleshooting Chassis Connectivity

Figure 1-10. MAX Icons and States

Reserving the Chassis in MAX

QoS Priority

Table 1-2. QoS Priority

Mounting the cDAQ Chassis

Using the cDAQ Chassis on a Desktop

NI 9901 Desktop Kit for cDAQ-9184/9188 Chassis

Figure 1-11. NI 9901 Desktop Mounting Kit

Mounting the cDAQ Chassis on a Panel

cDAQ-9181/9191

Figure 1-12. Installing the cDAQ-9181/9191 Panel Mount Kit

Figure 1-13. NI 9903 Panel Mount Accessory Dimensions

Figure 1-14. Panel Mounting the cDAQ-9181/9191 without a Panel Mount Kit

cDAQ-9184/9188

Figure 1-15. cDAQ-9184/9188 Panel Mount Dimensions and Installation

Figure 1-16. Mounting the cDAQ Chassis Directly on a Flat Surface

Mounting the cDAQ Chassis on a DIN Rail

cDAQ-9181/9191

Figure 1-17. cDAQ-9181/9191 DIN Rail Clip Installation

Figure 1-18. DIN Rail Clip Parts Locator Diagram

cDAQ-9184/9188

Figure 1-19. cDAQ-9184/9188 DIN Rail Installation

cDAQ Chassis Features

Chassis Grounding Screw

LEDs

Table 1-3. LED State/Chassis Status

Table 1-4. Wireless Signal Strength LED State/Chassis Status

Ethernet Port

Ethernet LEDs

Table 1-5. Ethernet LED Indications

Ethernet Cabling

Table 1-6. Ethernet Cable Wiring Connections

Reset Button

Table 1-7. cDAQ Chassis Default Settings

Power Connector

PFI BNC Connectors

Antenna

Cables and Accessories

Table 1-8. cDAQ Chassis Cables and Accessories

Removing Modules from the cDAQ Chassis

Using the cDAQ Chassis

Figure 1-20. cDAQ Chassis Block Diagram

C Series Module