National Instruments NI 6602, NI660, NI 6601, NI 6608 User Manual

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NI 660x User Manual

NI 6601, NI 6602, and NI 6608 Devices

NI 660x User Manual

December 2009 372119B-01

Page 2

Support

Worldwide Technical Support and Product Information

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For further support information, refer to the Technical Support and Professional Services appendix. To comment on National Instruments documentation, refer to the National Instruments Web site at the info code

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Page 3

Important Information

Warranty

The NI 6601, NI 6602, and NI 6608 devices are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.

The media on which you receive National Instruments software are warranted not to fail to execute programming instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period. National Instruments does not warrant that the operation of the software shall be uninterrupted or error free.

A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work. National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty.

National Instruments believes that the information in this document is accurate. The document has been carefully reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition. The reader should consult National Instr Instruments be liable for any damages arising out of or related to this document or the information contained in it.

XCEPT AS SPECIFIED HEREIN, NATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR IMPLIED, AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF

MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. CUSTOMER’S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL

NSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER. NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING

FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS, OR INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY THEREOF. This limitation of

the liability of National Instruments will apply regardless of the form of action, whether in contract or tort, including negligence. Any action against National Instruments must be brought within one year after the cause of action accrues. National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control. The warranty provided herein does not cover damages, defects, malfunctions, or service failures caused by owner’s failure to follow the National Instruments installation, operation, or maintenance instructions; owner’s modification of the product; owner’s abuse, misuse, or negligent acts; and power failure or surges, fire, flood, accident, actions of third parties, or other events outside reasonable control.

uments if errors are suspected. In no event shall National

Copyright

Under the copyright laws, this publication may not be reproduced or transm itted in any form, electronic or mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, withou t the prior written consent of National Instruments Corporation.

National Instruments respects the intellectual property of others, and we ask our users to do the same. NI software is protected by copyright and other intellectual property laws. Where NI software may be used to reproduce software or other materials belonging to others, you may use NI software only to reproduce materials that you may reproduce in accordance with the terms of any applicable license or other legal restriction.

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National Instruments, NI, ni.com, and LabVIEW are trademarks of National Instruments Corporation. Refer to the Terms of Use section on

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Other product and company names mentioned herein are trademarks or trade names of their respective companies.

Members of the National Instruments Alliance Partner Program are business entities independent from National Instruments and have no agency, partnership, or joint-venture relationship with National Instruments.

Patents

For patents covering National Instruments products/technology, refer to the appropriate location: Help»Patents in your software, the patents.txt file on your media, or the National Instruments Patent Notice at ni.com/patents.

WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS

(1) NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL OF RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT INJURY TO A HUMAN.

(2) IN ANY APPLICATION, INCLUDING THE ABOVE, RELIABILITY OF OPERATION OF THE SOFTWARE PRODUCTS CAN BE IMPAIRED BY ADVERSE FACTORS, INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL POWER SUPPLY, COMPUTER HARDWARE MALFUNCTIONS, COMPUTER OPERATING SYSTEM SOFTWARE FITNESS, FITNESS OF COMPILERS AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION, INSTALLATION ERRORS, SOFTWARE AND HARDWARE COMPATIBILITY PROBLEMS, MALFUNCTIONS OR FAILURES OF ELECTRONIC MONITORING OR CONTROL DEVICES, TRANSIENT FAILURES OF ELECTRONIC SYSTEMS (HARDWARE AND/OR SOFTWARE), UNANTICIPATED USES OR MISUSES, OR ERRORS ON THE PART OF THE USER OR APPLICATIONS DESIGNER (ADVERSE FACTORS SUCH AS THESE ARE HEREAFTER COLLECTIVELY TERMED “SYSTEM FAILURES”). ANY APPLICATION WHERE A SYSTEM FAILURE WOULD CREATE A RISK OF HARM TO PROPERTY OR PERSONS (INCLUDING THE RISK OF BODILY INJURY AND DEATH) SHOULD NOT BE RELIANT SOLELY UPON ONE FORM OF ELECTRONIC SYSTEM DUE TO THE RISK OF SYSTEM FAILURE. TO AVOID DAMAGE, INJURY, OR DEATH, THE USER OR APPLICATION DESIGNER MUST TAKE REASONABLY PRUDENT STEPS TO PROTECT AGAINST SYSTEM FAILURES, INCLUDING BUT NOT LIMITED TO BACK-UP OR SHUT DOWN MECHANISMS. BECAUSE EACH END-USER SYSTEM IS CUSTOMIZED AND DIFFERS FROM NATIONAL INSTRUMENTS' TESTING PLATFORMS AND BECAUSE A USER OR APPLICATION DESIGNER MAY USE NATIONAL INSTRUMENTS PRODUCTS IN COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT EVALUATED OR CONTEMPLATED BY NATIONAL INSTRUMENTS, THE USER OR APPLICATION DESIGNER IS ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING THE SUITABILITY OF NATIONAL INSTRUMENTS PRODUCTS WHENEVER NATIONAL INSTRUMENTS PRODUCTS ARE INCORPORATED IN A SYSTEM OR APPLICATION, INCLUDING, WITHOUT LIMITATION, THE APPROPRIATE DESIGN, PROCESS AND SAFETY LEVEL OF SUCH SYSTEM OR APPLICATION.

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Compliance

Electromagnetic Compatibility Information

This hardware has been tested and found to comply with the applicable regulatory requirements and limits for electromagnetic compatibility (EMC) as indicated in the hardware’s Declaration of Conformity (DoC) designed to provide reasonable protection against harmful interference when the hardware is operated in the intended electromagnetic environment. In special cases, for example when either highly sensitive or noisy hardware is being used in close proximity, additional mitigation measures may have to be employed to minimize the potential for electromagnetic interference.

While this hardware is compliant with the applicable regulatory EMC requirements, there is no guarantee that interference will not occur in a particular installation. To minimize the potential for the hardware to cause interference to radio and television reception or to experience unacceptable performance degradation, install and use this hardware in strict accordance with the instructions in the hardware documentation and the DoC

If this hardware does cause interference with licensed radio communications services or other nearby electronics, which can be determined by turning the hardware off and on, you are encouraged to try to correct the interference by one or more of the following measures:

• Reorient the antenna of the receiver (the device suffering interference).

• Relocate the transmitter (the device generating interference) with respect to the receiver.

•Plug the transmitter into a different outlet so that the transmitter and the receiver are on different branch circuits.

Some hardware may require the use of a metal, shielded enclosure (windowless version) to meet the EMC requirements for special EMC environments such as, for marine use or in heavy industrial areas. Refer to the hardware’s user documentation and

for product installation requirements.

the DoC

When the hardware is connected to a test object or to test leads, the system may become more sensitive to disturbances or may cause interference in the local electromagnetic environment.

Operation of this hardware in a residential area is likely to cause harmful interference. Users are required to correct the interference at their own expense or cease operation of the hardware.

Changes or modifications not expressly approved by National Instruments could void the user’s right to operate the hardware under the local regulatory rules.

. These requirements and limits are

The Declaration of Conformity (DoC) contains important EMC compliance information and instructions for the user or installer. To obtain the DoC for this product, visit and click the appropriate link in the Certification column.

ni.com/certification, search by model number or product line,

Page 5

About This Manual

Conventions ...................................................................................................................vii

Related Documentation..................................................................................................viii

Chapter 1 Introduction

About NI 660x Devices..................................................................................................1-1

Using PXI with CompactPCI.........................................................................................1-1

Getting Started ...............................................................................................................1-2

Installing NI-DAQ Driver Software................................................................1-2

Installing Other Software ................................................................................1-2

Installing the Hardware ...................................................................................1-2

Accessories and Cables..................................................................................................1-3

Chapter 2 Device Overview

Digital I/O ......................................................................................................................2-1

Prescaling.......................................................................................................................2-1

Pad Synchronization ......................................................................................................2-2

Duplicate Count Prevention...........................................................................................2-4

Example Application That Works Correctly (No Duplicate Counting)..........2-5

Example Application That Works Incorrectly (Duplicate Counting) .............2-6

Example Application That Prevents Duplicate Counting ...............................2-6

Enabling Duplicate Count Prevention in NI-DAQmx.....................................2-7

When to Use Duplicate Count Prevention.......................................................2-7

When Not to Use Duplicate Count Prevention................................................2-7

Transfer Rates ................................................................................................................2-8

High Precision Clock (NI 6608) ....................................................................................2-9

Using the OCXO as the SOURCE Counter ....................................................2-9

Using the OCXO as the 10 MHz PXI Backplane Clock.................................2-9

Measuring OCXO Stable Frequency Deviation ..............................................2-11

Calibration .....................................................................................................................2-12

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Contents

Chapter 3 Signal Connections

Programmable Function Interfaces (PFIs)..................................................................... 3-1

Digital Filtering ............................................................................................................. 3-1

Power-On State.............................................................................................................. 3-3

Pin Assignments ............................................................................................................ 3-3

I/O Connector Pinout..................................................................................................... 3-5

Outputs ..........................................................................................................................3-8

Counters......................................................................................................................... 3-10

Counter n Source Signal ................................................................................. 3-10

Counter n Gate Signal ..................................................................................... 3-12

Counter n Auxiliary Signal ............................................................................. 3-13

Counter n Internal Output Signal.................................................................... 3-14

Hardware Arm Start Triggers ......................................................................... 3-14

Counter Pairs................................................................................................... 3-15

Counter Applications ...................................................................................... 3-15

Real-Time System Integration Bus ............................................................................... 3-16

RTSI Triggers ................................................................................................. 3-16

+5 V Power Source........................................................................................................ 3-17

I/O Signals .....................................................................................................................3-18

Field Wiring Considerations ........................................................................... 3-18

Noise ............................................................................................................... 3-18

Crosstalk..........................................................................................................3-19

Inductive Effects ............................................................................................. 3-20

Transmission Line Effects .............................................................................. 3-22

Counter Source to Counter Out Delay.............................................. 3-12

Appendix A Technical Support and Professional Services

Glossary

Index

NI 660x User Manual vi ni.com

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About This Manual

This manual describes the electrical and mechanical aspects of the National Instruments NI 6601, NI 6602, and NI 6608 devices, and contains information about device operation and programming. Unless otherwise noted, text applies to all NI 660x devices. The PCI and PXI implementations are the same in functionality; their primary difference is the bus interface.

Conventions

The following conventions appear in this manual:

<> Angle brackets that contain numbers separated by an ellipsis represent

a range of values associated with a bit or signal name—for example, AO <3. .0>.

» The » symbol leads you through nested menu items and dialog box options

to a final action. The sequence File»Page Setup»Options directs you to pull down the File menu, select the Page Setup item, and select Options from the last dialog box.

This icon denotes a note, which alerts you to important information.

This icon denotes a caution, which advises you of precautions to take to avoid injury, data loss, or a system crash. When this symbol is marked on a product, refer to the Read Me First: Safety and Electromagnetic Compatibility document for information about precautions to take.

bold Bold text denotes items that you must select or click in the software, such

as menu items and dialog box options. Bold text also denotes parameter names.

italic Italic text denotes variables, emphasis, a cross-reference, or an introduction

to a key concept. Italic text also denotes text that is a placeholder for a word or value that you must supply.

monospace Text in this font denotes text or characters that you should enter from the

keyboard, sections of code, programming examples, and syntax examples. This font is also used for the proper names of disk drives, paths, directories, programs, subprograms, subroutines, device names, functions, operations, variables, filenames, and extensions.

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About This Manual

About NI 660x Devices

The NI 660x devices are timing and digital I/O devices for use with the PCI bus in PC-compatible computers, PXI chassis, or CompactPCI chassis. The NI 6601 offers four 32-bit counter channels and up to 32 lines of individually configurable, TTL/CMOS-compatible digital I/O. The NI 6602 offers this capability and four additional 32-bit counter channels. The NI 6608 is a functional superset of the NI 6602 device with a high-stability clock called an oven-controlled crystal oscillator (OCXO).

The counter/timer channels have many measurement and generation modes, such as event counting, time measurement, frequency measurement, encoder position measurement, pulse generation, and square-wave generation.

The NI 660x devices contain the National Instruments MITE PCI interface. The MITE offers bus-master operation, PCI burst transfers, and high-speed DMA controller(s) for continuous, scatter-gather DMA without requiring DMA resources from your computer. Refer to the Using PXI with CompactPCI section for more information about your NI PXI-660x device.

Device specifications are available in the NI 660x Specifications docu ment, which is available for download from

ni.com/manuals.

Using PXI with CompactPCI

Using PXI-compatible products with CompactPCI products is an important feature provided by PXI Hardware Specification Revision 2.1. If you use a PXI-compatible plug-in module in a CompactPCI chassis, you cannot use PXI-specific functions, but you can still use the basic plug-in device functions. For example, the RTSI bus on a PXI TIO Series device is available in a PXI chassis, but not in a CompactPCI chassis.

Page 10

Chapter 1 Introduction

Caution Damage can result if these lines are driven by the sub-bus. NI is not liable for any

damage resulting from improper signal connections.

Getting Started

The specification permits vendors to develop sub-buses that coexist with the basic PCI interface on the bus. Compatible operation is not guaranteed between devices with different sub-buses nor between devices with sub-buses and PXI. The standard implementation for CompactPCI does not include these sub-buses. The PXI TIO Series device works in any CompactPCI chassis adhering to the PICMG 2.0 R3.0 core specification.

PXI-specific features are implemented on the J2 connector of the bus. The PXI device is compatible with any chassis with a sub-bus that does not drive the lines used by that device. Even if the sub-bus is capable of driving these lines, the PXI device is still compatible as long as those pins on the sub-bus are disabled by default and never enabled.

Before installing your DAQ device, you must install the software you plan to use with the device.

Installing NI-DAQ Driver Software

If you are using NI-DAQ 7.1 or later, refer to the DAQ Getting Started guides, which you can download at Started guides offer NI-DAQ users step-by-step instructions for installing software and hardware, configuring channels and tasks, and getting started developing an application.

ni.com/manuals. The DAQ Getting

Installing Other Software

If you are using other software, refer to the installation instructions that accompany your software.

Installing the Hardware

The DAQ Getting Started guides contain non-software-specific information about how to install PCI, PXI, PCMCIA, and USB/IEEE 1394 devices, as well as accessories and cables.

NI 660x User Manual 1-2 ni.com

Page 11

Accessories and Cables

Table 1-1 lists the accessories and cables available for use with NI 660x devices.

Accessory Description

SH68-68-D1 Shielded 68-conductor cable

R6868 cable 68-conductor flat ribbon cable

BNC-2121 BNC connector block with built-in test features

CA-1000 Configurable connector accessory

SCB-68 Shielded screw connector block

TB-2715 Front-mount terminal block for NI PXI-660x

TBX-68 DIN-rail connector block

CB-68LP Low-cost screw connector block

CB-68LPR Low-cost screw connector block

Chapter 1 Introduction

Table 1-1. Accessories and Cables

Page 12

Device Overview

This chapter provides information about NI 660x device functionality.

Digital I/O

The NI 660x devices have a 32-bit DIO port on PFI <0..31>. Digital I/O consists of asynchronous reads and writes to the digital port upon software command. You can individually configure each line for digital input or output. For output, you can individually configure PFI <8..31> for either counter-associated output or digital output. You must specify whether you are using the PFI line for counter I/O or digital I/O only if that line is being used as an output. For input, both counter I/O and digital I/O can share the lines on PFI <0..31>.

For more information about the signals that can be driven onto PFI lines, refer to the I/O Connector Pinout section of this document.

For information about how to implement specific digital I/O functions, refer to the application software documentation.

Prescaling

Prescaling allows the counter to count a signal that is faster than the maximum timebase of the counter. The counters on the NI 660x offer 8X and 2X prescaling on each counter (prescaling can be disabled). Each prescaler consists of a small, simple counter that counts to eight (or two) and rolls over. This counter is specifically designed for this application and can count signals that are faster than the general purpose counters. The CtrnSource signal on the general purpose counter will be the divided signal from the simple counter.

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Chapter 2 Device Overview

Figure 2-1 shows an example of prescaling.

External Signal

Prescaler Rollover

(Used as Source

by Counter)

Counter Value

Prescaling is intended for use with two counter period and frequency measurements where the measurement is made on a continuous, repetitive signal. The prescaling counter cannot be read, so you cannot determine how many edges have occurred since the previous roll-over. You can also use prescaling for counting edges if it is acceptable to have an error of up to seven when using 8X prescaling or one when using 2X prescaling.

Pad Synchronization

The NI 660x devices allow synchronization of their PFI lines and RTSI lines at the I/O pads. This is called pad synchronization in this document, and digital synchronization in the NI-DAQmx API. You cannot use digital filtering while enabling this feature.

Figure 2-1. Prescaling Example

Pad synchronization is useful when several counters are measuring or operating off the same external signal. For example, suppose counters 0 and 1 are configured for triggered pulse generation and each counter uses the same external trigger (this external signal is connected to PFI 38 on the I/O connector and both counters have PFI 38 selected as their GATE). After the trigger signal propagates through the I/O pad of the ASIC, the time for the signal to reach the GATE of each counter within the ASIC may differ by a few nanoseconds.

This signal is sampled at the counters’ GATEs using the selected SOURCE. Because of different propagation times for the paths to the two GATEs, it is possible for the counters to detect the trigger on different edges on SOURCE. Thus, one counter could see the trigger one SOURCE period after the other. If you want to allow the counters to see the changes in the signal at the same instance, you should use pad synchronization. During pad synchronization, the signal is offset by one clock cycle.

NI 660x User Manual 2-2 ni.com

Page 14

Chapter 2 Device Overview

Counter

Source

PFI 38

at CTR 0 GATE

PFI 38

at CTR 1 GATE

Sampled

GATE at Ctr0

Sampled

GATE at Ctr1

1/2 Cycles

1/4 Cycle

PFI 38

at Input To ASIC

This feature is useful in applications with two or more counters that are armed by an external start trigger, or that use the same PFI line as a counter control signal. Pad synchronization is only useful if the counters involved are using one of the internal timebases. A counter is using maximum timebase as its source if the synchronous counting mode is enabled for that counter.

Figures 2-2 and 2-3 illustrate how pad synchronization can be useful. These figures assume a 0.5 and a 0.75 SOURCE cycle delay between the PFI 38 input pin, and CTR 0 GATE and CTR 1 GATE, respectively. Figure 2-2 shows counter 0 at the gate edge on PFI 38 one source period before counter 1. Figure 2-3 shows both counters at the gate edge on PFI 38 at the same time.

Figure 2-2. Counter 0 at Gate Edge on PFI 38 One Source Period before Counter 1

Page 15

Chapter 2 Device Overview

Counter

Source

PFI 38

at CTR 0 GATE

PFI 38

at CTR 1 GATE

Sampled

GATE at Ctr0

Sampled

GATE at Ctr1

1/2 Cycles

1/4 Cycle

PFI 38

at Input To ASIC

PFI 38

Synchronized at Pad

Figure 2-3. Counters 0 and 1 at Gate Edge on PFI 38 at the Same Time

Duplicate Count Prevention

NI 660x User Manual 2-4 ni.com

Duplicate count prevention (or synchronous counting mode) ensures that a counter returns correct data in applications that are a slow or non-periodic external source. Duplicate count prevention applies only to buffered counter applications such as measuring frequency or period.

For such buffered applications, the counter should store the number of times an external source pulses between rising edges on the Gate signal.

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Chapter 2 Device Overview

Example Application That Works Correctly (No Duplicate Counting)

Figure 2-4 shows an external buffered signal as the period measurement Source.

Rising Edge of Gate

Counter detects rising edge of Gate on the next rising edge of Source.

Gate

Source

Counter Value

Buffer

67 12 1

2 7

Figure 2-4. Example Application That Works Correctly

On the first rising edge of the Gate, the current count of 7 is stored. On the next rising edge of the Gate, the counter stores a 2 because two Source pulses occurred after the previous rising edge of Gate.

The counter synchronizes or samples the Gate signal with the Source signal. So the counter does not detect a rising edge in the Gate until the next Source pulse. In this example, the counter stores the values in the buffer on the first rising Source edge after the rising edge of Gate.

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Chapter 2 Device Overview

Example Application That Works Incorrectly (Duplicate Counting)

In Figure 2-5, after the first rising edge of Gate, no Source pulses occur. So the counter does not write the correct data to the buffer.

No Source edge, so no value written to buffer.

Gate

Source

Counter Value

Buffer

67 1

Figure 2-5. Example Application That Works Incorrectly

Example Application That Prevents Duplicate Counting

With duplicate count prevention enabled, the counter synchronizes both the Source and Gate signals to the maximum onboard timebase. By synchronizing to the timebase, the counter detects edges on the Gate even if the Source does not pulse. This enables the correct current count to be stored in the buffer even if no Source edges occur between Gate signals. Figure 2-6 shows an example application that prevents duplicate counting.

Counter detects rising Gate edge.

Gate

Source

80 MHz Timebase

Counter value increments only one time for each Source pulse.

Counter Value

Buffer

670 1

0 7

Figure 2-6. Example Application That Prevents Duplicate Counting

NI 660x User Manual 2-6 ni.com

Page 18

Even if the Source pulses are long, the counter increments only once for each source pulse.

Normally, the counter and Counter n Internal Output signals change synchronously to the Source signal. With duplicate count prevention, the counter value and Counter n Internal Output signals change synchronously to the maximum onboard timebase.

Notice that duplicate count prevention should only be used if the frequency of the Source signal is one-fourth of the maximum onboard timebase.

Enabling Duplicate Count Prevention in NI-DAQmx

You can enable duplicate count prevention in NI-DAQmx by setting the Enable Duplicate Count Prevention attribute/property. For specific information on finding the Enable Duplicate Count Prevention attribute/property, refer to the help file for the API you are using. Refer to the NI-DAQmx Help for more information.

When to Use Duplicate Count Prevention

Use duplicate count prevention for buffered measurements that use an external CtrnSource signal and the frequency of the signal is less than or equal to one-fourth of the maximum onboard timebase. Use this mode if you are using a low frequency or you expect zero CtrnSource edges between successive edges of the CtrnGate signal.

Chapter 2 Device Overview

Yo u should use duplicate count prevention if the following conditions are true:

•You are making a buffered counter input measurement.

•You are using an external signal (such as PFI x) as the counter Source.

• The frequency of the external source is one-fourth of the maximum onboard timebase.

•You can have the counter value and outp with the maximum onboard timebase.

In all other cases, you should not enable duplicate count prevention.

ut to change synchronously

When Not to Use Duplicate Count Prevention

Use duplicate counter prevention only for buffered measurements with an external CtrnSource signal. Do not use it when the CtrnSource signal is greater than one-fourth of the maximum timebase.

Page 19

Chapter 2 Device Overview

Transfer Rates

Note The maximum sustainable transfer rate is always lower than the peak transfer rate.

DMA Interrupt

The maximum sustainable transfer rate a TIO device can achieve for a buffered acquisition depends on the following factors:

•Amount of available bus bandwidth

• Processor speed and operating system

• Application software

To re d uce the amount of bus activity, limit the number of devices generating bus cycles. Because direct-memory access (DMA) transfers are faster than interrupt-driven transfers, NI-DAQmx uses DMA by default for buffered acquisitions.

Table 2-1 lists the maximum transfer rates for TIO devices.

Table 2-1. Maximum Transfer Rates

.Finite Operation

Buffer Size (Samples) Rate (kS/s) Buffer Size (Samples) Rate (kS/s)

100 5,000 100 77

1,000 2,150 1,000 77

10,000 1,600 10,000 77

100,000 1,350 100,000 77

Continuous Operation

Buffer Size (Samples) Rate (kS/s) Buffer Size (Samples) Rate (kS/s)

100 44 100 7

1,000 202 1,000 46

10,000 212 10,000 75

100,000 245 100,000 76

default 212 default 75

NI 660x User Manual 2-8 ni.com

Page 20

Note Transfer rates may vary depending on your computer hardware, operating system

and system activity. This benchmark data was determined on an AMD Athlon XP 1800 computer with 128 MB of PC-2100 DDR RAM running Windows XP and LabVIEW using one counter of the TIO device. For continuous measurements, the transfer rate is the maximum sustained rate for 30 seconds on one counter.

High Precision Clock (NI 6608)

The accuracy of your time measurement and pulse generation is determined by the timing accuracy of your counter clock. The NI 6608 device has an oven-controlled crystal oscillator (OCXO) that provides a highly stable 10 MHz clock that you can use as a GATE or SOURCE of a counter. You can also use the OCXO as the PXI backplane clock. Modules phase locked to the PXI backplane clock will acquire the same clock stability as the NI 6608. For more information, refer to the KnowledgeBase at

support

Using the OCXO as the SOURCE Counter

Using the OCXO as the timebase source of the counter, you can route the 10 MHz clock to CtrnSource.

and search using keyword phase lock.

Chapter 2 Device Overview

ni.com/

Using the OCXO as the 10 MHz PXI Backplane Clock

Your PXI chassis has a built-in 10 MHz backplane clock that is independently routed to each peripheral slot. An independent buffer on the chassis drives the clock signal to each peripheral slot with a skew of less than 1 ns between slots. You can use this common reference clock signal to synchronize multiple modules in a measurement or control system.

Use the OCXO 10 MHz clock to drive the PXI backplane clock so the modules in the other slots can take advantage of the stable timebase.

Note On NI PXI-660x devices, the maximum timebase is phase locked to the PXI

backplane clock.

To use the OCXO 10 MHz clock as the PXI backplane clock, plug the NI PXI-6608 device into Slot 2, or the slot immediately to the right of the controller of the PXI chassis.

By default, NI-DAQ software drives the 10 MHz clock from the OCXO onto the PXI CLK10 in pin so that the OCXO is u sed as the PXI backplane clock. When the PXI chassis senses a clock on the PXI CLK10 in pin in

Page 21

Chapter 2 Device Overview

TIO(0)

NI PXI-6608 in Slot 2 of PXI Chassis

80 MHz Phase Locked to 10 MHz PXI Backplane Clock

TIO(1)

10 MHz

OCXO

10 MHz

Circuit toDrive 10MHz

PXI

Backplane

Clock

80 MHz

VCXO

Phase

Lock Loop

10 MHz PXI Backplane Clock

10 MHz from OCXO is Used as

10 MHz PXI Backplane Clock

PXI Backplane

PXI CLK10 in

(Driving 10 MHz

Supplied by

OCXO)

TIO(0)

NI PXI-6608 or NI PXI-6602 in Slot 3 of PXI Chassis

80 MHz Phase Locked to 10 MHz PXI Backplane Clock

TIO(1)

10 MHz

OCXO

80 MHz

VCXO

Phase

Lock Loop

10 MHz PXI Backplane Clock

PXI Star

(Not Used

for

Backplane

Clock)

Slot 2, the chassis disables its internal clock, then uses the OCXO clock instead, illustrated in Figure 2-7.

Note The PXI CLK10 in pin is used as the PXI Star pin in other slots. The PXI Star pin is

not used for the PXI backplane clock.

NI 660x User Manual 2-10 ni.com

Figure 2-7. OCXO as the 10 MHz PXI Backplane Clock

Page 22

Measuring OCXO Stable Frequency Deviation

When you power the NI 6608 device, the OCXO requires adequate warm-up time to reach stable frequency. Five minutes is adequate warm-up time for a power-off duration of less than one hour, with maximum deviation within 20 ppb, or parts per billion, while four hours of operation is adequate for a power-off duration of up to 90 days.

Note For best performance, minimize power-off periods for the OCXO.

The OCXO is calibrated to within 0.1 Hz of 10.000000 MHz prior to shipment. Table 2-2 shows additional change in stable frequency that occurs over time. A change in stable frequency of approximately 45 ppb occurs after the first year of normal use.

Table 2-2. Change in Stable Frequency over Time

Days of Operation

0–10 11.25

11–60 11.25

Chapter 2 Device Overview

Additional Change in

Stable Frequency (ppb)

61–200 11.25

201–365 11.25

366–375 5.63

376–425 5.63

426–565 5.63

566–730 5.63

731–740 2.82

741–790 2.82

For example, if the OCXO has a perfect stable frequency of 10 MHz after warm-up, after the first 10 days of operation, the stable frequency drifts

11.25 ppb. During the next 50 days of operation, this frequency will drift an additional 11.25 ppb, thus making the total drift caused by aging to be

22.5 ppb. After 365 days, drift will be 45 ppb. If you calibrate the OCXO after 365 days of operation to restore the stable frequency to a perfect 10 MHz, the drift during the first 10 days following calibration (days 366–375) will now be 5.63 ppb—the stable frequency in this case

Page 23

Chapter 2 Device Overview

will be 10 MHz ± 5.63 ppb after 375 days of operation. Calibration does not affect the drift in frequency; it only changes the stable frequency.

Calibration

When you are ready to calibrate your device to correct for drift in frequency, refer to the NI 6601/6602 Calibration Procedure or the NI 6608 Timing I/O Device Calibration Procedure available at

calibration

(Legacy) only.

. You can calibrate these devices in Traditional NI-DAQ

Register-Level Programming Information

Caution NI is not liable for any damage or injury that results from register-level

programming the TIO Series devices.

For information about programming the NI 660x devices at the register level, refer to the NI 660X Register-Level Programmer Manual, available from

ni.com/manuals.

ni.com/

The National Instruments Measurement Hardware DDK provides development tools and a register-level programming interface for NI data acquisition hardware. The NI Measurement Hardware DDK provides access to the full register map of each device and offers examples for completing common measurement and control functions. The Measurement Hardware DDK works with TIO Series digital I/O and counter/timer I/O devices. Refer to

NI 660x User Manual 2-12 ni.com

ni.com for more information.

Page 24

Signal Connections

This chapter describes how to make input and output signal connections to the NI 660x device by way of the device I/O connector and the RTSI connector.

Programmable Function Interfaces (PFIs)

The 40 PFI pins are connected to the signal routing multiplexer for each timing signal, and software can select a PFI as the external source for a given timing signal. Any PFI pin can be used as an input by any timing signal and multiple timing signals can simultaneously use the same PFI pin. This flexible routing scheme reduces the need to change physical connections to the I/O connector for different applications. You also can individually enable each PFI pin to output a specific internal timing signal.

Yo u can individually enable many of the PFI pins to output a specific internal timing signal. For example, if you need the Counter 0 Source signal as an output on the I/O connector, software can turn on the output driver for the PFI 39/CTR 0 SRC pin.

Caution Do not drive a PFI signal externally when it is configured as an output.

When using the PFI pin as an input, you can individually configure each PFI for edge or level detection and for polarity selection. You can use the polarity selection for any of the timing signals, but the edge or level detection depends upon the particular timing signal being controlled. The detection requirements for each timing signal are listed within the section that discusses that signal.

Digital Filtering

Use the digital filter option available on the NI 660x PFI lines to eliminate glitches on input data. The filter operates off a filter clock and a fast internal sampling clock. The filter circuit samples the signal on the PFI line on each rising edge of the sampling clock. However, a change in the signal is propagated only if the signal maintains its new state for at least two

Page 25

Chapter 3 Signal Connections

External Signal

on PFI Line

External Signal Sample by Maximum Timebase

LHL HH

Filtered PFI Line

Maximum Timebase

Filter Clock

HHH HH

consecutive rising edges of the filter clock. The frequency of the filter clock timebase determines whether a transition in the signal may propagate or not. The function of the internal sampling clock is to increase the sampling rate and prevent aliasing. Figure 3-1 demonstrates the function of this filter.

Figure 3-1. Digital Filtering

In period A, the filter blocks the glitches because the external signal does not remain steadily high from one rising edge of the filter clock to the next. In period B, the filter passes the transition because the external signal remains steadily high. Depending on when the transition occurs, the filter may require up to two filter clocks—one full filter interval—to pass a transition. The figure shows a rising (0 to 1) transition. The same filtering applies to falling (1 to 0) transitions.

NI 660x User Manual 3-2 ni.com

Note The effect of filtering is that the signal transition is shifted by a minimum of

one filter clock and a maximum of two filter clocks.

The filter is sensitive to the duration for which a digital signal transitions from one state to another. If a square wave is applied to the filter, its propagation will depend on its frequency and duty cycle.

There are four filter settings available in the TIO devices: 5 μs, 1 μs, 500 ns, and 100 ns. The 5 μs filter will pass all pulse widths (high and low) that are 5 μs or longer. It will block all pulse widths that are 2.5 μs (one-half of 5 μs) or shorter. Pulse widths between 2.5 μs and 5 μs may or may not pass, depending on the phase of the pulse with respect to the filter clock timebase. The same relationship extends to all other filter clocks.

In addition to these hard-wired filter clocks, you can use any PFI, RTSI, or internal signal as the source for the filter clock timebase. Use signals with a duty cycle as close to 50 percent as possible.

If the period of the filter clock timebase is t pass pulse widths that are 2*t

or longer and to block pulse widths that

fltrclk

, this filter guarantees to

fltrclk

Page 26

Chapter 3 Signal Connections

are t

or shorter. A pulse with a width between these two ranges may or

fltrclk

may not pass, depending on the phase of the pulse with respect to the filter clock timebase.

Table 3-1 s ummarizes the properties of the different filter settings.

Table 3-1. Filter Settings

Filter Setting Pulse Width Passed Pulse Width Blocked

5 μs 5 μs 2.5 μs

1 μs 1 μs 500 ns

500 ns 500 ns 250 ns

100 ns 100 ns 50 ns

Programmable setting with period of clock = t

fltrclk

2*t

fltrclk

Yo u individually configure the filter setting for each PFI line. The filters are useful to maintain signal integrity. They can prevent measurement errors caused by noise, crosstalk, or transmission line effects.

Note The digital filters on the NI 660x devices are not enabled by default.

For more information about using the digital filters on your device, refer to the NI-DAQmx Help.

Power-On State

The PFI lines are weakly pulled down within the NI-TIO ASIC, and the RTSI lines are weakly pulled high. Connections for pulling up the PFI lines or for stronger pull-down connections must be made external to the NI 660x. These connections affect the drive strength of the NI 660x when the lines pulled up or down are used as outputs.

Pin Assignments

Table 3-2 lists the pin assignments for the I/O connector on the NI 660x.

Note The NI 6601 uses counters <0..3> only.

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Chapter 3 Signal Connections

Table 3-2. NI 660x Connector Pin Assignments

Motion Signal Name

PFI 31 channel

D GND — — — 33 67 CTR 2

PFI 28 — P0.28 CTR 2

PFI 27 channel

D GND — — — 30 64 CTR 3

PFI 24 — P0.24 CTR 3

PFI 23 channel

D GND — — — 27 61 CTR 4

PFI 20 — P0.20 CTR 4

PFI 19 channel

D GND — — — 24 58 CTR 5

PFI 16 — P0.16 CTR 5

PFI 15 channel

PFI 14 index/z(6) P0.14 CTR 6

D GND — — — 20 54 CTR 6

RG — — — 19 53 CTR 6

D GND — — — 18 52 CTR 7

Encoder

Context

A(2)

A(3)

A(4)

A(5)

A(6)

DIO

Context

P0.31 CTR 2

P0.27 CTR 3

P0.23 CTR 4

P0.19 CTR 5

P0.15 CTR 6

Counter Context

(Default)

SRC

OUT

SRC

OUT

SRC

OUT

SRC

OUT

SRC

GATE

Counter

Number

34 68 — — — D GND

32 66 CTR 2

31 65 — — — D GND

29 63 CTR 3

28 62 — — — D GND

26 60 CTR 4

25 59 — — — D GND

23 57 CTR 5

22 56 — — — RG

21 55 — — — D GND

Number

Context

(Default)

GATE

AUX

GATE

AUX

GATE

AUX

GATE

AUX

OUT

SRC

Motion

DIO

Context

P0.30 index/z(2) PFI 30

P0.29 channel

P0.26 index/z(3) PFI 26

P0.25 channel

P0.22 index/z(4) PFI 22

P0.21 channel

P0.18 index/z(5) PFI 18

P0.17 channel

P0.13 channel

P0.12 — PFI 12

P0.11 channel

Encoder

Context

B(2)

B(3)

B(4)

B(5)

B(6)

A(7)

Signal Name

PFI 29

PFI 25

PFI 21

PFI 17

PFI 13

PFI 11

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Chapter 3 Signal Connections

Table 3-2. NI 660x Connector Pin Assignments (Continued)

Motion

Signal

Name

PFI 9 channel

PFI 8 — P0.8 CTR 7

PFI 7 — P0.7 — 15 49 — — — D GND

D GND — — — 14 48 — P0.6 — PFI 6

PFI 4 — P0.4 — 13 47 — P0.5 — PFI 5

PFI 3 — P0.3 — 12 46 — — — D GND

D GND — — — 11 45 — P0.2 — PFI 2

PFI 0 — P0.0 — 10 44 — P0.1 — PFI 1

PFI 32 — — CTR 1

PFI 34 index/z(1) — CTR 1

PFI 35 channel

PFI 33 channel

PFI 36 — — CTR 0

Reserved — — — 4 38 — — — Reserved

PFI 38 index/z(0) — CTR 0

PFI 39 channel

+5 V — — — 1 35 — — — RG

Encoder Context

B(7)

A(1)

B(1)

A(0)

DIO

Context

P0.9 CTR 7

— CTR 1

— CTR 0

Counter Context

(Default)

AUX

OUT

GATE

SRC

AUX

OUT

GATE

SRC

Counter

Number

17 51 CTR 7

16 50 — — — D GND

9 43 — — — RG

8 42 — — — D GND

7 41 — — — D GND

6 40 CTR 0

5 39 — — — D GND

3 37 — — — Reserved

2 36 — — — GND

Number

Context

(Default)

GATE

AUX

DIO

Context

P0.10 index/z(7) PFI 10

— channel

Motion

Encoder

Context

B(0)

Signal Name

PFI 37

I/O Connector Pinout

Figure 3-2 shows the pinout of the NI 6601. Figure 3-3 shows the pinout of the NI 6602/6608.

Note The NI 6601 uses counters <0..3> only.

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Chapter 3 Signal Connections

+5 V

PFI 39/CTR 0 SOURCE

PFI 38/CTR 0 GATE

RESERVED

PFI 36/CTR 0 OUT

PFI 33/CTR 1 AUX

PFI 35/CTR 1 SOURCE

PFI 34/CTR 1 GATE

PFI 32/CTR 1 OUT

PFI 0/P0.0

D GND

PFI 3/P0.3

PFI 4/P0.4

D GND

PFI 7/P0.7

PFI 8/P0.8

PFI 9/P0.9

D GND

R GND

D GND

PFI 14/P0.14

PFI 15/P0.15

PFI 16/P0.16

D GND

PFI 19/P0.19

PFI 20/P0.20

D GND

PFI 23/P0.23

PFI 24/P0.24/CTR 3 OUT

D GND

PFI 27/P0.27/CTR 3 SOURCE

PFI 28/P0.28/CTR 2 OUT

D GND

PFI 31/P0.31/CTR 2 SOURCE

R GND

RESERVED

PFI 37/CTR 0 AUX

D GND

R GND

D GND

PFI 1/P0.1

PFI 2/P0.2

D GND

PFI 5/P0.5

PFI 6/P0.6

D GND

PFI 10/P0.10

PFI 11/P0.11

PFI 12/P0.12

PFI 13/P0.13

D GND

R GND

PFI 17/P0.17

PFI 18/P0.18

D GND

PFI 21/P0.21

PFI 22/P0.22

D GND

PFI 25/P0.25/CTR 3 AUX

PFI 26/P0.26/CTR 3 GATE

D GND

PFI 29/P0.29/CTR 2 AUX

PFI 30/P0.30/CTR 2 GATE

D GND

RG: Reserved if using an SH68-68-D1 shielded

cable. Ground if using an R6868 ribbon cable.

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Figure 3-2. NI 6601 Pinout

Page 30

Chapter 3 Signal Connections

PFI 31/P0.31/CTR 2 SOURCE

D GND

PFI 28/P0.28/CTR 2 OUT

PFI 27/P0.27/CTR 3 SOURCE

D GND

PFI 24/P0.24/CTR 3 OUT

PFI 23/P0.23/CTR 4 SOURCE

D GND

CTR 4 OUT/PFI 20/P0.20

PFI 19/P0.19/CTR 5 SOURCE

D GND

CTR 5 OUT/PFI 16/P0.16

PFI 15/P0.15/CTR 6 SOURCE

PFI 14/P0.14/CTR 6 GATE

D GND

R GND

D GND

PFI 9/P0.9/CTR 7 AUX

CTR 7 OUT/PFI 8/P0.8

PFI 7/P0.7

D GND

PFI 4/P0.4

PFI 3/P0.3

D GND

PFI 0/P0.0

PFI 32/CTR 1 OUT

PFI 34/CTR 1 GATE

PFI 35/CTR 1 SOURCE

PFI 33/CTR 1 AUX

PFI 36/CTR 0 OUT

RESERVED

PFI 38/CTR 0 GATE

PFI 39/CTR 0 SOURCE

+5 V

34 68

33 67

32 66

31 65

30 64

29 63

28 62

27 61

26 60

25 59

24 58

23 57

22 56

21 55

20 54

19 53

18 52

17 51

16 50

15 49

14 48

13 47

12 46

11 45

10 44

943

842

741

640

539

438

337

236

135

D GND

PFI 30/P0.30/CTR 2 GATE

PFI 29/P0.29/CTR 2 AUX

D GND

PFI 26/P0.26/CTR 3 GATE

PFI 25/P0.25/CTR 3 AUX

D GND

PFI 22/P0.22/CTR 4 GATE

PFI 21/P0.21/CTR 4 AUX

D GND

PFI 18/P0.18/CTR 5 GATE

PFI 17/P0.17/CTR 5 AUX

R GND

D GND

PFI 13/P0.13/CTR 6 AUX

CTR 6 OUT/PFI 12/P0.12

PFI 11/P0.11/CTR 7 SOURCE

PFI 10/P0.10/CTR 7 GATE

D GND

PFI 6/P0.6

PFI 5/P0.5

D GND

PFI 2/P0.2

PFI 1/P0.1

R GND

D GND

PFI 37/CTR 0 AUX

D GND

RESERVED

D GND

R GND

RG: Reserved if using an SH68-68-D1 shielded cable. Ground if using an R6868 ribbon cable.

Figure 3-3. NI 6602/6608 Pinout

Page 31

Chapter 3 Signal Connections

Outputs

PFI <0..7> are used for DIO only. PFI <32..39> are used for counters and motion encoders only. You can use PFI <8..31> as either of the three choices. When used as an output, you can individually configure each PFI line as a DIO line or a counter line (you need not distinguish between counter/encoder or DIO applications when you use a PFI line as an input).

Furthermore, the PFI lines associated with gates and sources can be used as outputs associated with the counter. When used as such, these PFI lines drive the selected GATE or SOURCE associated with these lines. For example, if PFI 39 is configured as an output, it will drive the selected SOURCE of counter 0.

Table 3-3 s ummarizes what you can drive onto the different PFI lines when they are used as outputs.

Table 3-3. PFI Lines Used as Outputs

PFI Line Possible Signals

PFI 0 P0.0

PFI 1 P0.1

PFI 2 P0.2

PFI 3 P0.3

PFI 4 P0.4

PFI 5 P0.5

PFI 6 P0.6

PFI 7 P0.7

PFI 8 P0.8 or CTR 7 OUT

PFI 9 P0.9

PFI 10 P0.10 or CTR 7 GATE

PFI 11 P0.11 or CTR 7 SOURCE

PFI 12 P0.12 or CTR 6 OUT

PFI 13 P0.13

PFI 14 P0.14 or CTR 6 GATE

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Chapter 3 Signal Connections

Table 3-3. PFI Lines Used as Outputs (Continued)

PFI Line Possible Signals

PFI 15 P0.15 or CTR 6 SOURCE

PFI 16 P0.16 or CTR 5 OUT

PFI 17 P0.17

PFI 18 P0.18 or CTR 5 GATE

PFI 19 P0.19 or CTR 5 SOURCE

PFI 20 P0.20 or CTR 4 OUT

PFI 21 P0.21

PFI 22 P0.22 or CTR 4 GATE

PFI 23 P0.23 or CTR 4 SOURCE

PFI 24 P0.24 or CTR 3 OUT

PFI 25 P0.25

PFI 26 P0.26 or CTR 3 GATE

PFI 27 P0.27 or CTR 3 SOURCE

PFI 28 P0.28 or CTR 2 OUT

PFI 29 P0.29

PFI 30 P0.30 or CTR 2 GATE

PFI 31 P0.31 or CTR 2 SOURCE

PFI 32 CTR 1 OUT

PFI 33 Input only

PFI 34 CTR 1 GATE

PFI 35 CTR 1 SOURCE

PFI 36 CTR 0 OUT

PFI 37 Input only

PFI 38 CTR 0 GATE

PFI 39 CTR 0 SOURCE

Counters 4 through 7 are not available in NI 6601 devices.

Page 33

Chapter 3 Signal Connections

Note For NI 6602 devices, output frequency on any of the pins should not exceed 40 MHz.

The maximum frequency you can drive at the I/O connector is affected by the capacitive

load your cable presents. You can achieve 40 MHz output with a National Instruments 1 m

SH68-68-D1 shielded cable (capacitive load = 80 pF). At larger loads, your maximum

output frequency may be lower.

Counters

The counters on TIO devices are a superset of the DAQ system timing controller (DAQ-STC) general-purpose counters developed by National Instruments. These counters are backward compatible with the DAQ-STC in functionality and software programming. The same software API and functions are used to program the DAQ-STC general-purpose counters and the counters on TIO devices.

The counters on TIO devices have two internal timebases: 100 kHz and 20 MHz. The counters on the NI 6602 and NI 6608 also have an 80 MHz timebase. Each counter has a gate, auxiliary, and source input. Each of these inputs can be an internal or external signal that connects to the I/O connector. Each counter also has an output signal.

Counter n Source Signal

You can select any PFI as well as many other internal signals as the Counter n Source (CtrnSource) signal. The CtrnSource signal is configured in edge-detection mode on either the rising or falling edge. The selected edge of the CtrnSource signal increments and decrements the counter value depending on the application the counter is performing.

Yo u can export the CtrnSource signal to the I/O connector’s default PFI input for each CtrnSource. For example, you can export the Ctr0Source signal to the PFI 39/CTR 0 SRC pin, even if another PFI is inputting the Ctr0Source signal. This output is set to high-impedance at startup.

For most applications, unless you select an external source, the 80MHzTimebase signal (if available), 20MHzTimebase signal, or 100kHzTimebase signal generates the CtrnSource signal.

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Page 34

Chapter 3 Signal Connections

CtrnSource

Tsrcpw

Tgatepw

Tsrcper

Figure 3-4 shows the timing requirements for the CtrnSource signal.

Figure 3-4. Timing Requirements for CtrnSource Signal

Figure 3-4 shows the minimum pulse width and period that you must use for the CtrnSource signal. This signal must satisfy both minimum criteria. If the high phase of the CtrnSource signal is Tsrcpw ns, the low phase must be Tsrcper – Tsrcpw.

Table 3-4. Minimum Pulse Width and Period for CtrnSource Internal Signals

Parameter

Tsrcpw (without prescaling)

Tsrcpw (with prescaling)

Tsrcper (without prescaling)

Tsrcper (with prescaling)

Minimum

Minimum with

RTSI Connector

DescriptionNI 6601 NI 6602

5 ns 5 ns 5 ns CtrnSource minimum pulse

width (without prescaling)

3.5 ns 3.5 ns 3.5 ns CtrnSource minimum pulse width (with prescaling)

50 ns 12.5 ns 50 ns CtrnSource minimum period

(without prescaling)

16.67 ns 8 ns 16.67 ns CtrnSource minimum period (with prescaling)

Page 35

Chapter 3 Signal Connections

CtrnInternalOutput

Tso Tso

CtrnSource

Counter Source to Counter Out Delay

Figure 3-5 shows the CtrnSource to CtrnInternalOutput delay.

Figure 3-5. CtrnSource to CtrnInternalOutput Delay

Figure 3-5 shows the delay between the active edge of the CtrnSource signal and the active edge of the CtrnInternalOutput signal. In the figure, the CtrnSource and CtrnInternalOutput signals are active high. If you use the pulse output mode for the CtrnInternalOutput signal, you will see the TC pulse one CtrnSource period before the CtrnInternalOutput toggles under the toggle output mode.

The output delay listed in Table 3-5 is for internal signals. The corresponding delay values at a connector block are larger due to cable delays.

Table 3-5. Output Delay for Internal Signals

Parameter Typic al Maximum Description

Tso 16 ns 26 ns CtrnSource to CtrnInternalOutput delay

Note When using duplicate count prevention mode, the minimum period of signal used as

the source of the counter must be greater than or equal to four times the period of the maximum timebase. For more information, refer to the Duplicate Count Prevention section of this document.

Counter n Gate Signal

You can select any PFI or RTSI, as well as many other internal signals like the Counter n Gate (CtrnGate) signal. The CtrnGate signal is configured in edge-detection or level-detection mode depending on the application performed by the counter. The gate signal can perform many different operations including starting and stopping the counter, generating interrupts, and saving the counter contents.

NI 660x User Manual 3-12 ni.com

Page 36

Yo u can export the CtrnGate signal to the I/O connector’s default PFI input for each CtrnGate. For example, you can export the gate signal connected to counter 0 to the PFI 38/CTR 0 GATE pin, even if another PFI is inputting the Ctr0Gate signal. This output is set to high-impedance at startup.

Figure 3-6 shows the timing requirements for the CtrnGate signal.

Table 3-6 shows the minimum pulse width required for the internal signals.

Table 3-6. Minimum Pulse Width for CtrnGate Internal Signals

Parameter Minimum

Chapter 3 Signal Connections

Tgatepw

CtrnGate

Tgatepw

Figure 3-6. Timing Requirements for CtrnGate Signal

Minimum with

RTSI Connector

Description

Tgatepw 5 ns 5 ns CtrnGate minimum pulse width

Note For buffered measurements, the minimum period required for the CtrnGate signal is

determined by how fast the system can transfer data from your device to computer memory.

Counter n Auxiliary Signal

You can select any PFI or RTSI, as well as many other internal signals as the Counter n Auxiliary (CtrnAux) signal. Much like this CtrnGate signal, the CtrnAux signal is configured in edge-detection or level-detection mode depending on the application performed by the counter. The aux signal can perform many different operations including starting and stopping the counter, generating interrupts, and saving the counter contents. You can also use this signal to control the counting direction in edge-counting applications.

Page 37

Chapter 3 Signal Connections

Figure 3-7 shows the timing requirements for the CtrnAux signal.

Tauxpw

CtrnAux

Tauxpw

Figure 3-7. Timing Requirements for the CtrnAux Signal

Table 3-7. Minimum Pulse Width for CtrnAux Internal Signals

Minimum

with RTSI

Parameter Minimum

Connector

Description

Tauxpw 5 ns 5 ns CtrnAux minimum pulse width

Counter n Internal Output Signal

The Counter n Internal Output (CtrnInternalOutput) signal is available only as an output on the CTR n OUT pin, where n is the number of your counter. For example, the Ctr0InternalOutput signal is available as an output on the PFI 36/CTR 0 OUT pin. You can also route the CtrnInternalOutput signal to other locations on the board, such as RTSI.

The CtrnInternalOutput signal reflects the terminal counter (TC) of counter n. The counter generates a terminal count when its count value rolls over. The two software-selectable output options are pulse on TC and toggle output polarity on TC. The output polarity is software-selectable for both options. This output is set to high-impedance at startup.

Hardware Arm Start Triggers

You can arm each counter using a software command or by using the Arm Start Trigger. The Arm Start Trigger may be an internal or an external signal. By using the Arm Start Trigger, you can start more than one counter simultaneously by configuring each counter to use the same Arm Start Trigger signal.

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Page 38

Counter Pairs

Note Ctr <4..7> are not available on the NI 6601.

Chapter 3 Signal Connections

Each counter on the TIO is paired with another counter. This pairing allows some counter signals to connect to signals on the other counter. The counters are paired as shown in Table 3-8.

Table 3-8. Counter Pairs

ctr0 ctr1

ctr2 ctr3

ctr4 ctr5

ctr6 ctr7

Ctr0InternalOutput, which you can connect to Ctr1Gate, is an example of two signals that you can connect between the ctr0/ctr1 pair. Conversely, to connect Ctr0InternalOutput to Ctr2Gate, you must use other circuitry on the TIO device (such as RTSI Triggers).

Counter Applications

You can use the TIO device in the following counter-based applications:

•Counting Edges

•Frequency Measurement

•Period Measurement

• Position Measurement with Linear and Angular Encoders

•Pulse Width Measurement

• Semi-Period Measurement

• Two-Edge Separation Measurement

•Pulse Generation

Yo u can perform these measurements through programmed I/O, interrupt, or DMA data transfer mechanisms. The measurements can be finite or continuous in duration. Some of the applications also use start triggers, pause triggers, and hardware arm triggers.

Note For more information about programming counter applications and triggers in

software, refer to the NI-DAQmx Help, and/or use the examples that are available with NI-DAQmx.

Page 39

Chapter 3 Signal Connections

Real-Time System Integration Bus

TIO devices use the National Instruments Real-Time System Integration (RTSI) bus to easily synchronize several measurement fu nctions to a common trigger or timing event. In a PCI system, the RTSI bus consists of the RTSI bus interface and a ribbon cable. The bus can route timing and trigger signals between several functions on as many as five DAQ devices in the computer. In a PXI system, the RTSI bus consists of the RTSI bus interface and the PXI trigger signals on the PXI backplane. This bus can route timing and trigger signals between several functions on as many as seven DAQ devices in the system. For a RTSI connector pinout, go to

ni.com/info and enter rtsipin.

RTSI Triggers

TIO devices require a frequency timebase for its operation. This frequency timebase must come from the onboard crystal oscillator and is required even if the device is receiving a MasterTimebase signal from the RTSI trigger bus. Any TIO device can drive its 20MHzTimebase signal onto the RTSI Trigger 7 pin. Although some TIO devices have a 80MHzTimebase (such as the NI 6602), the RTSI bus cannot carry the 80MHzTimebase signal for bandwidth reasons. By default, TIO devices do not drive the RTSI Trigger 7 bus clock line.

Figure 3-8 shows the RTSI signal connection scheme for PCI TIO devices.

CtrnSource

Trigger <0..6>

RTSI SwitchRTSI Switch

RTSI Bus Connector

RTSI Trigger 7

Figure 3-8. RTSI Signal Connection Scheme for PCI

NI 660x User Manual 3-16 ni.com

CtrnGate

CtrnAux

CtrnInternalOutput

20 MHz Timebase

Master Timebase

Page 40

Chapter 3 Signal Connections

PXI Star 6

CtrnSource

CtrnGate

CtrnAux

CtrnInternalOutput

20 MHz Timebase

Master Timebase

PXI Trigger 7

RTSI Bus Connector

RTSI SwitchRTSI Switch

PXI Trigger

<0..5>

PXI TIO devices use PXI trigger line 7 as their RTSI clock line. The maximum timebase provided by the PXI TIO device is phase locked to the 10 MHz PXI backplane clock. By using other PXI modules that phase lock their board clocks to the 10 MHz PXI backplane clock, you can better synchronize operation in a multi-module PXI system. The phase locking is enabled by default and can be disabled by way of software. If the module is used in a compact PCI chassis that does not have the 10 MHz PXI backplane clock, the phase locking is automatically disabled. Additionally, PXI trigger line 6 corresponds to PXI star trigger on PXI TIO devices.

Figure 3-9 shows the RTSI signal connection scheme for PXI TIO devices.

+5 V Power Source

Figure 3-9. RTSI Signal Connection for PXI

The +5 V pin on the I/O connector supplies power from the computer power supply through a self-resetting fuse. The fuse resets automatically within a few seconds after removal of an overcurrent condition. The power pin is referenced to the D GND pins and can supply power to external digital circuitry. The power rating for this +5 V pin on the NI 660x is +4.65 to +5.25 VDC at 1 A.

Page 41

Chapter 3 Signal Connections

Caution Do not connect the +5 V power pin directly to D GND, RG, or any pin configured

for output on the NI 660x device, or any voltage source or output pin on another device. Doing so can damage the device and the computer. National Instruments is not liable for damages resulting from such a connection.

I/O Signals

Field Wiring Considerations

To prevent incorrect results caused by environmental noise and crosstalk, make sure the NI 660x and the peripheral device share a common ground reference. Connect one or more NI 660x device D GND lines to the ground reference of your peripheral device.

Yo u can also use the digital filters available on each PFI line to reduce errors that these problems might cause.

Noise

For noise immunity, take the following precautions:

•When routing signals to the TIO device, keep cabling away from noise sources.

• Separate the TIO device signal lines from high-current or high-voltage lines. High-current or high-voltage lines that run in parallel paths at a close distance can induce currents in or voltages on the TIO device signal lines. To reduce the coupling between lines, separate parallel lines by a reasonable distance or run the lines at right angles to one another.

• Do not run signal lines through conduits that also contain power lines.

• Protect signal lines from magnetic and electric fields caused by monitors, electric motors, welding equipment, breakers, transformers, or other devices by running them through special metal conduits.

• Use appropriate digital filtering to remove noise.

NI 660x User Manual 3-18 ni.com

Page 42

Crosstalk

Chapter 3 Signal Connections

Crosstalk mainly occurs when the capacitance between lines in a cable induces a smaller transition on another line. Figure 3-10 shows an example of crosstalk.

PFI 10

PFI 11

Cable

Capacitance

Figure 3-10. Crosstalk Example

PFI 11

PFI 10

In Figure 3-10, PFI 10 and PFI 11 are configured as inputs. V0 drives PFI 10 and V

drives PFI 11. When PFI 10 (the offending line) transitions from

one state to another, it induces a small transition in PFI 11 (the victim line). The magnitude of the transition (or crosstalk) induced in PFI 11 is proportional to the following:

• The speed of the transition on the offending line (PFI 10 in the previous example)

• The length of the cable and the proximity of the victim to the offending line

•The source impedance of the victim line (V and the level of the offending line (V

in the previous example)

)

Crosstalk is most likely to cause measurement errors when the victim line is at a low voltage. If this crosstalk is 0.5 V or greater, you may get errors in measurement.

Yo u should not experience crosstalk if the source impedance of the voltage source driving the victim line is less than 100 Ω. If this source impedance is larger than 100 Ω and you see crosstalk problems, you should use NI-TIO filters or a voltage follower with a low output impedance to drive the victim line.

Page 43

Chapter 3 Signal Connections

PFI 39 Pin 2

GND Pin 36

GND

Output of External DeviceSCB-68

Inductive Effects

For high-speed signals, inductive effects can degrade signal integrity and cause ringing. To minimize inductive effects, you must minimize ground loops and allow a return path for currents. Twist your signal with a ground wire when you connect it to the 68-pin connector block you are using. Connect the signal wire to the PFI pin you are using and connect the ground wire to the adjacent D GND line with which the PFI line is twisted.

Figure 3-11 shows an example of wiring that minimizes inductive effects.

Figure 3-11. Example of Wiring That Minimizes Inductive Effects

The SH68-68-D1 cable is designed to help minimize inductive effects. Each signal line is twisted with a ground wire connected to a nearby pin. Each ground wire is shared by two signal lines.

NI 660x User Manual 3-20 ni.com

Table 3-9 lists the signals and the D GND pin number on the 68-pin connector block.

Table 3-9. Signals and D GND Pin Number on 68-Pin Connector Block

PFI Number Pin Number for D GND

PFI 0 11

PFI 1 11

PFI 2 46

PFI 3 46

PFI 4 14

PFI 5 14

PFI 6 49

PFI 7 49

PFI 8 50

PFI 9 50

Page 44

Chapter 3 Signal Connections

Table 3-9. Signals and D GND Pin Number on 68-Pin Connector Block (Continued)

PFI Number Pin Number for D GND

PFI 10 18

PFI 11 18

PFI 12 20

PFI 13 20

PFI 14 55

PFI 15 55

PFI 16 24

PFI 17 24

PFI 18 59

PFI 19 59

PFI 20 27

PFI 21 17

PFI 22 62

PFI 23 62

PFI 24 30

PFI 25 30

PFI 26 65

PFI 27 65

PFI 28 33

PFI 29 33

PFI 30 68

PFI 31 68

PFI 32 42

PFI 33 39

PFI 34 42

PFI 35 41

Page 45

Chapter 3 Signal Connections

Table 3-9. Signals and D GND Pin Number on 68-Pin Connector Block (Continued)

PFI 36 39

PFI 37 41

PFI 38 36

PFI 39 36

Transmission Line Effects

Transmission line effects can degrade the signal and cause measurement errors. Use twisted-pair wires to connect external signals to the device to improve impedance matching and signal integrity. The NI 660x provide onboard series termination to reduce signal reflections when it drives an output.

For reflection problems that occur when the device drives the signal, use parallel AC termination at the destination. When using a National Instruments SH68-68-D1 cable, the recommended values for R 68 Ω and 150 pF, respectively.

PFI Number Pin Number for D GND

and CP are

For reflection problems that occur when the NI 660x receives the signal, use series termination at the device driving the signal. The sum of R

and the

output impedance of the source is approximately 80 Ω. Typically, this condition results in a value of approximately 50 Ω for R

. To use serial

termination when the source impedance is larger than 80 Ω, use a voltage follower with low output impedance, and connect R

at the output of the

voltage follower.

Note Before using a voltage follower or series termination, use digital filtering to

eliminate measurement errors.

NI 660x User Manual 3-22 ni.com

Page 46

Figure 3-12 shows an example of parallel and series termination.

Driving Signal Driving SignalReceiving SignalReceiving Signal

660x

Parallel Termination Series Termination

Other

Device

Figure 3-12. Parallel and Series Termination Example

660x

Chapter 3 Signal Connections

Other

Device

Page 47

Technical Support and Professional Services

Visit the following sections of the award-winning National Instruments Web site at

• Support—Technical support at

• Training and Certification—Visit

• System Integration—If you have time constraints, limited in-house

ni.com for technical support and professional services:

following resources:

– Self-Help Technical Resources—For answers and solutions,

visit

ni.com/support for software drivers and updates,

a searchable KnowledgeBase, product manuals, step-by-step troubleshooting wizards, thousands of example programs, tutorials, application notes, instrument drivers, and so on. Registered users also receive access to the NI Discussion Forums at

ni.com/forums. NI Applications Engineers make sure every

question submitted online receives an answer.

– Standard Service Program Membership—This program

entitles members to direct access to NI Applications Engineers via phone and email for one-to-one technical support as well as exclusive access to on demand training modules via the Services Resource Center. NI offers complementary membership for a full year after purchase, after which you may renew to continue your benefits.

For information about other technical support options in your area, visit

ni.com/contact.

self-paced training, eLearning virtual classrooms, interactive CDs, and Certification program information. You also can register for instructor-led, hands-on courses at locations around the world.

technical resources, or other project challenges, National Instruments Alliance Partner members can help. To learn more, call your local NI office or visit

ni.com/services, or contact your local office at

ni.com/alliance.

ni.com/support includes the

ni.com/training for

Page 48

Appendix A Technical Support and Professional Services

• Declaration of Conformity (DoC)—A DoC is our claim of

compliance with the Council of the European Communities using the manufacturer’s declaration of conformity. This system affords the user protection for electromagnetic compatibility (EMC) and product safety. You can obtain the DoC for your product by visiting

ni.com/certification.

• Calibration Certificate—If your product supports calibration,

you can obtain the calibration certificate for your product at

ni.com/calibration.

If you searched

ni.com and could not find the answers you need, contact

your local office or NI corporate headquarters. Phone numbers for our worldwide offices are listed at the front of this manual. You also can visit the Worldwide Offices section of

ni.com/niglobal to access the branch

office Web sites, which provide up-to-date contact information, support phone numbers, email addresses, and current events.

NI 660x User Manual A-2 ni.com

Page 49

Glossary

Symbol Prefix Value

c centi 10

m milli 10

μ micro 10

nnano10

k kilo 10

Mmega10

Symbols

°degree

– negative of, or minus

/per

–2

–3

–6

–9

% percent

±plus or minus

+ positive of, or plus

A amperes

ANSI American National Standards Institute

API application programming interface

arm To enable a counter to start an operation. If the application requires a

trigger, an armed counter waits for the trigger to begin the operation.

ASIC application specific integrated circuit

Page 50

Glossary

asynchronous A property of an event that occurs at an arbitrary time, without

synchronization to a reference clock.

b bit—one binary digit, either 0 or 1.

B byte—eight related bits of data, an eight-bit binary number. Also used to

denote the amount of memory required to store one byte of data.

base address A memory address that serves as the starting address for programmable

registers. All other addresses are located by adding to the base address.

buffer A block of memory used to store measurement results.

buffered A type of measurement in which multiple measurements are made

consecutively and measurement results are stored in a buffer.

bus The group of conductors that interconnect individual circuitry in a

computer. Typically, a bus is the expansion vehicle to which I/O or other devices are connected. Examples of PC buses are the AT, EISA, and PCI bus.

CCelsius

clock Hardware component that provides timing for various device operations.

cm centimeters

CMOS complementary metal-oxide semiconductor

CompactPCI An electrical superset of the PCI bus architecture with a mechanical form

factor suited for industrial applications.

crosstalk An unwanted signal on one channel due to activity on a different channel.

current drive capability

NI 660x User Manual G-2 ni.com

The amount of current a digital or analog output channel is capable of sourcing or sinking while still operating within voltage range specifications.

Page 51

Glossary

current sinking The ability of a DAQ board to dissipate current for analog or digital output

signals.

current sourcing The ability of a DAQ board to supply current for analog or digital output

signals.

DAQ data acqu isition

Collecting and measuring electrical signals from sensors, transducers, and test probes or fixtures and inputting them to a computer for processing.

Collecting and measuring the same kinds of electrical signals with A/D and/or DIO boards plugged into a computer, and possibly generating control signals with D/A and/or DIO boards in the same computer.

DAQ-STC A custom ASIC developed by National Instruments that provides timing

information and general-purpose counter/timers on National Instruments E Series boards.

DC direct current

decode Used in the context of motion encoders. The two channels of a motion

encoder indicate information about movement and direction of movement of an external device. Decoding refers to extracting this information from the signals on these channels.

device A plug-in data acquisition board, card, or pad that can contain multiple

channels and conversion devices. Plug-in boards, PCMCIA cards, and DAQ devices that connect to your computer parallel port, are all examples of DAQ devices.

DIO digital input/output

DLL dynamic link library—a software module in Microsoft Windows

containing executable code and data that can be called or used by Windows applications or other DLLs. Functions and data in a DLL are loaded and linked at run time when they are referenced by a Windows application or other DLLs.

Page 52

Glossary

DMA direct memory access—a method by which data can be transferred to/from

computer memory from/to a device or memory on the bus while the processor does something else. DMA is the fastest method of transferring data to/from computer memory.

driver Software that controls a specific hardware device such as a DAQ board.

EEPROM electrically erasable programmable read-only memory—ROM that can be

erased with an electrical signal and reprogrammed.

EISA extended industry standard architecture

encode Used in the context of motion encoders. Motion encoders provide

information about movement and direction of movement of an external device. The process of producing the pulses that contain this information is called encoding.

ETS equivalent time sampling

FSK frequency shift keying

GATE The signal that controls the operation of a counter. This signal may start or

stop the operation of a counter, reload the counter, or save the results of a counter.

glitch A brief, unwanted change, or disturbance, in a signal level.

GND ground

hardware The physical components of a computer system, such as the circuit boards,

plug-in boards, chassis, enclosures, peripherals, cables, and so on.

HW hardware

NI 660x User Manual G-4 ni.com

Page 53

Glossary

HW Save Register A register inside the NI-TIO ASIC that stores the result of a measurement.

Hz hertz—a unit of frequency. One hertz corresponds to one cycle or event per

second.

I/O input/output—the transfer of data to/from a computer system involving

communications channels, operator interface devices, and/or data acquisition and control interfaces.

in. inches

interrupt A computer signal indicating that the CPU should suspend its current task

to service a designated activity.

interrupt level The relative priority at which a device can interrupt.

IOH current, output high

IOL current, output low

IRQ interrupt request signal

ISA industry standard architecture

LabVIEW Laboratory Virtual Instrument Engineering Workbench, a National

Instruments graphical programming application.

m meters

max maximum

maximum timebase The fastest internal timebase available on a device. For NI 6601 devices,

the maximum timebase is 20 MHz. For NI 6602 devices, the maximum timebase is 80 MHz.

min minimum

Page 54

Glossary

MITE A custom ASIC designed by National Instruments that implements the

PCI bus interface. The MITE supports bus mastering for high speed data transfers over the PCI bus.

motion encoders Transducers that generate pulses to indicate the physical motion of a

device. The most common type of motion encoders are quadrature encoders. Two-pulse encoders (also referred to as up/down encoders) are another example.

NI-DAQ NI driver software for DAQ hardware.

NI-TIO A custom ASIC developed by National Instruments that provides counter

and digital I/O functionality.

noise An undesirable electrical signal—noise comes from external sources such

as the AC power line, motors, generators, transformers, fluorescent lights, soldering irons, CRT displays, computers, electrical storms, welders, radio transmitters, and internal sources such as semiconductors, resistors, and capacitors. Noise corrupts signals you are trying to send or receive.

OCXO oven-controlled crystal oscillator

operating system Base-level software that controls a computer, runs programs, interacts with

users, and communicates with installed hardware or peripheral devices.

PCI peripheral component interconnect—a high-performance expansion bus

architecture originally developed by Intel to replace ISA and EISA. It is achieving widespread acceptance as a standard for PCs and work-stations; it offers a theoretical maximum transfer rate of 132 Mbytes/s.

PFI programmable function input

port A communications connection on a computer or a remote controller.

A digital port, consisting of lines of digital input and/or output.

NI 660x User Manual G-6 ni.com

Page 55

Glossary

ppb parts per billion

prescaling The division of frequency of an input signal that is to be used as SOURCE

of a counter.

programmed I/O A data transfer method in which the CPU reads or writes data as prompted

by software.

PXI Modular instrumentation standard based on CompactPCI developed by

National Instruments with enhancements for instrumentation.

reflection A high-speed signal transition behaves like a wave and is reflected like a

wave at an inadequately terminated endpoint. This phenomenon is referred to as reflection.

RG reserved ground. Pins that are marked RG on the I/O connector are

no-connects if you use the SH100-100-S2 shielded cable, while they are ground pins if you use the R100100 unshielded ribbon cable.

ribbon cable A flat cable in which the conductors are side by side.

ringing The oscillation of a signal about a high-voltage or low-voltage state

immediately following a transition to that state.

RTS I Bus real-time system integration bus—the National Instruments timing bus that

connects DAQ boards directly, by means of connectors on top of the boards, for precise synchronization of functions.

s seconds

(HW) Save register A register inside the NI-TIO ASIC that stores the result of a measurement.

source In the counter context, source refers to the signal that causes the counter to

increment or decrement. In the context of signals, source refers to the device that drives a signal.

SOURCE The signal that causes the counter to increment or decrement.

Page 56

Glossary

start trigger A TTL level signal having two discrete levels, a high and a low level, that

starts an operation.

synchronous A property of an event that is synchronized to a reference clock.

TC terminal count—a strobe that occurs when a counter reaches zero from

either direction.

termination Matching of impedances at the end of a signal path to minimize reflections.

timebase Another term used for the SOURCE of a counter. Usually indicates an

internal SOURCE provided by or derived from an onboard oscillator.

trigger Any event that causes, starts, or stops some form of data capture.

tri-state A third output state, other than high or low, in which the output is undriven.

TTL transistor-transistor logic

two-pulse encoder A motion encoder that has two channels: channels A and B. Pulses on

channel A indicate movement in one direction while pulses on channel B indicate movement in the opposite direction. This type of encoder is also referred to as up down encoder.

unstrobed digital I/O A type of digital input or output in which software reads or writes the

digital line or port states directly, without using any handshaking or hardware-controlled timing functions. Also called immediate, nonhandshaking, or unlatched digital I/O.

UP_DOWN The signal that determines whether a counter increments or decrements.

VDC volts direct current

NI 660x User Manual G-8 ni.com

volts

Page 57

Glossary

Vin vol t s in

VI Virtual Instrument. A LabVIEW program; so-called because it models the

appearance and function of a physical instrument.

wire Data path between nodes.

Page 58

Index

accessories, 1-3 ASIC

pad synchronization, 2-4 power-on state, 3-3

backplane clock

OCXO, 2-9 phase locking, 3-17

cables, 1-3 calibration, 2-11, 2-12 calibration certificate (NI resources), A-2 CompactPCI, 1-1 connector pinout, 3-5 conventions used in the manual, vii counters

counter applications, 3-15 Counter n Auxiliary signal, 3-13 Counter n Gate signal, 3-12 Counter n Internal Output signal, 3-14 Counter n Source signal, 3-10 counter pairs, 3-15

crosstalk, 3-3, 3-18, 3-19

digital filter

description, 3-1 example (figure), 3-2 pad synchronization, 2-2

settings (table), 3-3 digital I/O, 2-1 digital synchronization, 2-2 DMA, 1-1

counter applications, 3-15

transfer rates, 2-8

transfer rates (table), 2-8 documentation

conventions used in the manual, vii

NI resources, A-1

related documentation, viii drivers (NI resources), A-1 duplicate count prevention, 2-4

application that prevents (example), 2-7

application that works correctly

(example), 2-5

application that works incorrectly

(example), 2-6 when not to use, 2-7 when to use, 2-7

examples (NI resources), A-1

data transfer

counter applications, 3-15 DMA channels, 2-8

transfer rates, 2-8 Declaration of Conformity (NI resources), A-2 diagnostic tools (NI resources), A-1

field wiring considerations, 3-18 filter, digital

description, 3-1 example (figure), 3-2 pad synchronization, 2-2 settings (table), 3-3

Page 59

Index

ground loops, 3-20

hardware arm start triggers, 3-14 help, technical support, A-1

I/O connector pinout, 3-5 inductive effects

description, 3-20 minimizing (example), 3-20

installation

hardware, 1-2

software, 1-2 instrument drivers (NI resources), A-1 interrupts

counter applications, 3-15

Counter n Auxiliary signal, 3-13

Counter n Gate signal, 3-12

transfer rates, 2-8

KnowledgeBase, A-1

MITE, 1-1

National Instruments support and services,

A-1

noise, 3-3, 3-18

OCXO

about, 1-1, 2-9 calibration, 2-11 stable frequency deviation, 2-11 using as the 10 MHz PXI backplane

clock, 2-9

using as the SOURCE counter, 2-9 outputs, 3-8 oven-controlled crystal oscillator

about, 1-1, 2-9

calibration, 2-11

stable frequency deviation, 2-11

using as the 10 MHz PXI backplane

clock, 2-9

using as the SOURCE counter, 2-9

pad synchronization, 2-2 parallel termination, 3-22 PFIs, 3-1 phase lock, 2-9, 3-17 pin assignments, 3-3 pinout, 3-5 power source, 3-17 power-on state, 3-3 prescaling, 2-1 programmable function interfaces, 3-1 programming

examples (NI resources), A-1

digital filtering, 3-2

table, 3-3 minimum, 3-11, 3-13 minimum for internal signals (table), 3-13

PXI backplane clock

OCXO, 2-9 phase locking, 3-17

NI 660x User Manual I-2 ni.com

Page 60

Index

real-time system integration bus. See RTSI register-level programming, 2-12 related documentation, viii RTS I

connector, 3-1 counter n auxiliary signal, 3-13 counter n auxiliary signal (table), 3-14 counter n gate signal, 3-12 counter n gate signal (table), 3-13 counter n internal output signal, 3-14 counter n source signal (table), 3-11 description, 3-16 digital filtering, 3-2 MAX, viii pad synchronization, 2-2 power-on state, 3-3 PXI-compatible products, 1-1 signal connection for PCI, 3-16 signal connection for PXI, 3-17 triggers, 3-15, 3-16

technical support, A-1 TIO ASIC

pad synchronization, 2-2, 2-4

power-on state, 3-3 training and certification (NI resources), A-1 transfer rates, 2-8 transfer rates, maximum (table), 2-8 transmission line effects, 3-3, 3-22 troubleshooting (NI resources), A-1

Web reso urces, A-1

signals

Counter n Auxiliary signal, 3-13 Counter n Gate, 3-12 Counter n Internal Output, 3-14 Counter n Source, 3-10

software

counter applications, 3-15 NI resources, A-1

change in, 2-11 start triggers, 3-14 support, technical, A-1

National Instruments NI 6602, NI660, NI 6601, NI 6608 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

NI 660x User Manual

Support

Worldwide Technical Support and Product Information

National Instruments Corporate Headquarters

Worldwide Offices

Important Information

Warranty

Copyright

Trademarks

Patents

WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS

Compliance

Contents

About This Manual

Conventions

Related Documentation

About NI 660x Devices

Using PXI with CompactPCI

Getting Started

Installing NI-DAQ Driver Software

Installing Other Software

Installing the Hardware

Accessories and Cables

Table 1-1. Accessories and Cables

Digital I/O

Prescaling

Pad Synchronization

Figure 2-1. Prescaling Example

Figure 2-2. Counter 0 at Gate Edge on PFI 38 One Source Period before Counter 1

Figure 2-3. Counters 0 and 1 at Gate Edge on PFI 38 at the Same Time

Duplicate Count Prevention

Example Application That Works Correctly (No Duplicate Counting)

Figure 2-4. Example Application That Works Correctly

Example Application That Works Incorrectly (Duplicate Counting)

Figure 2-5. Example Application That Works Incorrectly

Example Application That Prevents Duplicate Counting

Figure 2-6. Example Application That Prevents Duplicate Counting

Enabling Duplicate Count Prevention in NI-DAQmx

When to Use Duplicate Count Prevention

When Not to Use Duplicate Count Prevention

Transfer Rates

Table 2-1. Maximum Transfer Rates

High Precision Clock (NI 6608)

Using the OCXO as the SOURCE Counter

Using the OCXO as the 10 MHz PXI Backplane Clock

Figure 2-7. OCXO as the 10 MHz PXI Backplane Clock

Measuring OCXO Stable Frequency Deviation

Table 2-2. Change in Stable Frequency over Time

Calibration

Register-Level Programming Information

Programmable Function Interfaces (PFIs)

Digital Filtering

Figure 3-1. Digital Filtering

Table 3-1. Filter Settings

Power-On State

Pin Assignments

Table 3-2. NI 660x Connector Pin Assignments

I/O Connector Pinout

Figure 3-2. NI 6601 Pinout

Figure 3-3. NI 6602/6608 Pinout

Outputs

Table 3-3. PFI Lines Used as Outputs

Counters

Counter n Source Signal

Figure 3-4. Timing Requirements for CtrnSource Signal

Table 3-4. Minimum Pulse Width and Period for CtrnSource Internal Signals

Counter Source to Counter Out Delay

Figure 3-5. CtrnSource to CtrnInternalOutput Delay

Table 3-5. Output Delay for Internal Signals

Counter n Gate Signal

Table 3-6. Minimum Pulse Width for CtrnGate Internal Signals

Figure 3-6. Timing Requirements for CtrnGate Signal

Counter n Auxiliary Signal

Figure 3-7. Timing Requirements for the CtrnAux Signal

Table 3-7. Minimum Pulse Width for CtrnAux Internal Signals

Counter n Internal Output Signal