National Instruments NI 6238, NI 6239 User Manual

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DAQ M Series

NI 6238/6239 User Manual

Isolated Current Input/Current Output Devices

NI 6238/6239 User Manual

July 2006 371913A-01

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The NI 6238/6239 is warranted against defects in materials and workmanship for a period of three years from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.

The media on which you receive National Instruments software are warranted not to fail to execute programming instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do not execute programming instruc tions if National Instruments receives notice of such defects during the warranty period. National Instruments does not warrant that the operation of the software shall be uninterrupted or error free.

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About This Manual

Conventions ...................................................................................................................xiii

Related Documentation.................................................................................................. xiv

NI-DAQ........................................................................................................... xiv

NI-DAQmx for Linux...................................................................................... xiv

NI-DAQmx Base.............................................................................................xv

LabVIEW ........................................................................................................xv

LabWindows™/CVI™....................................................................................xvi

Measurement Studio........................................................................................xvi

ANSI C without NI Application Software ......................................................xvi

.NET Languages without NI Application Software ........................................xvii

Device Documentation and Specifications......................................................xvii

Training Courses .............................................................................................xvii

Technical Support on the Web ........................................................................xvii

Chapter 1 Getting Started

Installing NI-DAQmx ....................................................................................................1-1

Installing Other Software...............................................................................................1-1

Installing the Hardware..................................................................................................1-1

Device Pinouts ...............................................................................................................1-1

Device Specifications ....................................................................................................1-2

Device Accessories and Cables .....................................................................................1-2

Chapter 2 DAQ System Overview

DAQ Hardware ..............................................................................................................2-1

DAQ-STC2......................................................................................................2-2

Calibration Circuitry........................................................................................2-3

Sensors and Transducers................................................................................................ 2-3

Cables and Accessories.................................................................................................. 2-4

Custom Cabling...............................................................................................2-4

Programming Devices in Software................................................................................2-5

Chapter 3 Connector Information

I/O Connector Signal Descriptions................................................................................3-1

RTSI Connector Pinout.................................................................................................. 3-3

Contents

Chapter 4 Analog Input

Analog Input Circuitry .................................................................................................. 4-1

Analog Input Range....................................................................................................... 4-2

Connecting Analog Current Input Signals .................................................................... 4-3

Analog Input Ground-Reference Settings ..................................................................... 4-5

Multichannel Scanning Considerations......................................................................... 4-8

Analog Input Data Acquisition Methods....................................................................... 4-10

Analog Input Triggering................................................................................................ 4-11

Field Wiring Considerations.......................................................................................... 4-11

Analog Input Timing Signals ........................................................................................ 4-12

Method 1 ......................................................................................................... 4-3

Method 2 ......................................................................................................... 4-4

Configuring AI Ground-Reference Settings in Software ................. 4-7

Use Short High-Quality Cabling..................................................................... 4-8

Minimize Current Step between Adjacent Channels ...................................... 4-8

Avoid Scanning Faster Than Necessary ......................................................... 4-9

Example 1 ......................................................................................... 4-9

Example 2 ......................................................................................... 4-9

Software-Timed Acquisitions ......................................................................... 4-10

Hardware-Timed Acquisitions........................................................................ 4-10

Buffered ............................................................................................ 4-10

Non-Buffered.................................................................................... 4-11

AI Sample Clock Signal.................................................................................. 4-15

Using an Internal Source .................................................................. 4-16

Using an External Source ................................................................. 4-16

Routing AI Sample Clock Signal to an Output Terminal................. 4-16

Other Timing Requirements ............................................................. 4-17

AI Sample Clock Timebase Signal ................................................................. 4-17

AI Convert Clock Signal................................................................................. 4-18

Using an Internal Source .................................................................. 4-18

Using an External Source ................................................................. 4-19

Routing AI Convert Clock Signal to an Output Terminal ................ 4-19

Using a Delay from Sample Clock to Convert Clock ...................... 4-19

Other Timing Requirements ............................................................. 4-20

AI Convert Clock Timebase Signal ................................................................ 4-21

AI Hold Complete Event Signal ..................................................................... 4-21

AI Start Trigger Signal.................................................................................... 4-22

Using a Digital Source...................................................................... 4-22

Routing AI Start Trigger to an Output Terminal.............................. 4-22

AI Reference Trigger Signal........................................................................... 4-23

Using a Digital Source...................................................................... 4-24

Routing AI Reference Trigger Signal to an Output Terminal .......... 4-24

NI 6238/6239 User Manual vi ni.com

AI Pause Trigger Signal ..................................................................................4-24

Getting Started with AI Applications in Software......................................................... 4-25

Chapter 5 Analog Output

Analog Output Circuitry ................................................................................................5-1

Analog Output Data Generation Methods .....................................................................5-2

Software-Timed Generations...........................................................................5-2

Hardware-Timed Generations .........................................................................5-2

Analog Output Triggering .............................................................................................5-4

Connecting Analog Current Output Signals..................................................................5-4

Analog Output Timing Signals ......................................................................................5-5

AO Start Trigger Signal...................................................................................5-5

AO Pause Trigger Signal.................................................................................5-6

AO Sample Clock Signal................................................................................. 5-8

AO Sample Clock Timebase Signal................................................................5-9

Getting Started with AO Applications in Software .......................................................5-10

Contents

Using a Digital Source ......................................................................4-24

Routing AI Pause Trigger Signal to an Output Terminal .................4-25

Non-Buffered ....................................................................................5-3

Buffered ............................................................................................5-3

Using a Digital Source ......................................................................5-6

Routing AO Start Trigger Signal to an Output Terminal..................5-6

Using a Digital Source ......................................................................5-7

Routing AO Pause Trigger Signal to an Output Terminal................5-8

Using an Internal Source...................................................................5-8

Using an External Source..................................................................5-8

Routing AO Sample Clock Signal to an Output Terminal................ 5-8

Other Timing Requirements..............................................................5-9

Chapter 6 Digital Input and Output

I/O Protection................................................................................................................. 6-1

Programmable Power-Up States....................................................................................6-1

Connecting Digital I/O Signals......................................................................................6-2

Logic Conventions.........................................................................................................6-3

Getting Started with DIO Applications in Software......................................................6-4

Contents

Chapter 7 Counters

Counter Input Applications ........................................................................................... 7-3

Counter Output Applications......................................................................................... 7-21

Counting Edges............................................................................................... 7-3

Single Point (On-Demand) Edge Counting...................................... 7-3

Buffered (Sample Clock) Edge Counting......................................... 7-4

Non-Cumulative Buffered Edge Counting....................................... 7-5

Controlling the Direction of Counting.............................................. 7-5

Pulse-Width Measurement.............................................................................. 7-6

Single Pulse-Width Measurement .................................................... 7-6

Buffered Pulse-Width Measurement ................................................ 7-6

Period Measurement ....................................................................................... 7-7

Single Period Measurement.............................................................. 7-8

Buffered Period Measurement.......................................................... 7-8

Semi-Period Measurement.............................................................................. 7-9

Single Semi-Period Measurement .................................................... 7-9

Buffered Semi-Period Measurement ................................................ 7-10

Frequency Measurement................................................................................. 7-10

Method 1—Measure Low Frequency with One Counter................. 7-10

Method 1b—Measure Low Frequency with One Counter

(Averaged) ..................................................................................... 7-11

Method 2—Measure High Frequency with Two Counters .............. 7-12

Method 3—Measure Large Range of Frequencies Using Two

Counters......................................................................................... 7-13

Choosing a Method for Measuring Frequency................................. 7-14

Position Measurement..................................................................................... 7-16

Measurements Using Quadrature Encoders...................................... 7-16

Measurements Using Two Pulse Encoders ...................................... 7-18

Two-Signal Edge-Separation Measurement ................................................... 7-19

Single Two-Signal Edge-Separation Measurement.......................... 7-19

Buffered Two-Signal Edge-Separation Measurement...................... 7-20

Simple Pulse Generation................................................................................. 7-21

Single Pulse Generation.................................................................... 7-21

Single Pulse Generation with Start Trigger...................................... 7-21

Retriggerable Single Pulse Generation............................................. 7-22

Pulse Train Generation.................................................................................... 7-23

Continuous Pulse Train Generation.................................................. 7-23

Frequency Generation..................................................................................... 7-24

Using the Frequency Generator........................................................ 7-24

Frequency Division......................................................................................... 7-25

Pulse Generation for ETS ............................................................................... 7-25

NI 6238/6239 User Manual viii ni.com

Contents

Counter Timing Signals .................................................................................................7-26

Counter n Source Signal..................................................................................7-26

Routing a Signal to Counter n Source...............................................7-27

Routing Counter n Source to an Output Terminal ............................7-27

Counter n Gate Signal .....................................................................................7-28

Routing a Signal to Counter n Gate ..................................................7-28

Routing Counter n Gate to an Output Terminal................................7-28

Counter n Aux Signal ......................................................................................7-28

Routing a Signal to Counter n Aux...................................................7-28

Counter n A, Counter n B, and Counter n Z Signals .......................................7-29

Routing Signals to A, B, and Z Counter Inputs ................................7-29

Routing Counter n Z Signal to an Output Terminal..........................7-29

Counter n Up_Down Signal ............................................................................7-29

Counter n HW Arm Signal..............................................................................7-29

Routing Signals to Counter n HW Arm Input...................................7-30

Counter n Internal Output and Counter n TC Signals .....................................7-30

Routing Counter n Internal Output to an Output Terminal...............7-30

Frequency Output Signal.................................................................................7-30

Routing Frequency Output to a Terminal .........................................7-31

Default Counter Terminals ............................................................................................7-31

Counter Triggering ........................................................................................................7-32

Arm Start Trigger ............................................................................................7-32

Start Trigger.....................................................................................................7-32

Pause Trigger...................................................................................................7-32

Other Counter Features.................................................................................................. 7-33

Cascading Counters.........................................................................................7-33

Counter Filters.................................................................................................7-33

Prescaling ........................................................................................................7-34

Duplicate Count Prevention ............................................................................ 7-35

Example Application That Works Correctly

(No Duplicate Counting)................................................................ 7-35

Example Application That Works Incorrectly

(Duplicate Counting)......................................................................7-36

Example Application That Prevents Duplicate Count......................7-37

When To Use Duplicate Count Prevention.......................................7-38

Enabling Duplicate Count Prevention in NI-DAQmx......................7-38

Synchronization Modes...................................................................................7-38

80 MHz Source Mode.......................................................................7-39

Other Internal Source Mode..............................................................7-39

External Source Mode.......................................................................7-40

Contents

Chapter 8 PFI

Using PFI Terminals as Timing Input Signals .............................................................. 8-2

Exporting Timing Output Signals Using PFI Terminals............................................... 8-3

Using PFI Terminals as Static Digital Inputs and Outputs............................................ 8-3

Connecting PFI Input Signals........................................................................................ 8-3

PFI Filters ...................................................................................................................... 8-4

I/O Protection ................................................................................................................ 8-5

Programmable Power-Up States.................................................................................... 8-6

Connecting Digital I/O Signals ..................................................................................... 8-6

Chapter 9 Isolation and Digital Isolators

Digital Isolation............................................................................................................. 9-2

Benefits of an Isolated DAQ Device............................................................................. 9-2

Reducing Common-Mode Noise................................................................................... 9-3

Chapter 10 Digital Routing and Clock Generation

Clock Routing................................................................................................................ 10-1

80 MHz Timebase........................................................................................... 10-2

20 MHz Timebase........................................................................................... 10-2

100 kHz Timebase .......................................................................................... 10-2

External Reference Clock ............................................................................... 10-2

10 MHz Reference Clock................................................................................ 10-3

Synchronizing Multiple Devices ................................................................................... 10-3

Real-Time System Integration Bus (RTSI)................................................................... 10-3

RTSI Connector Pinout................................................................................... 10-4

Using RTSI as Outputs ................................................................................... 10-5

Using RTSI Terminals as Timing Input Signals............................................. 10-6

RTSI Filters..................................................................................................... 10-6

PXI Clock and Trigger Signals...................................................................................... 10-7

PXI_CLK10 .................................................................................................... 10-8

PXI Triggers.................................................................................................... 10-8

PXI_STAR Trigger ......................................................................................... 10-8

PXI_STAR Filters........................................................................................... 10-8

NI 6238/6239 User Manual x ni.com

Chapter 11 Bus Interface

DMA Controllers ...........................................................................................................11-1

PXI Considerations ........................................................................................................11-2

PXI Clock and Trigger Signals........................................................................ 11-2

PXI and PXI Express.......................................................................................11-2

Using PXI with CompactPCI ..........................................................................11-3

Data Transfer Methods ..................................................................................................11-3

Direct Memory Access (DMA).......................................................................11-3

Interrupt Request (IRQ)...................................................................................11-4

Programmed I/O ..............................................................................................11-4

Changing Data Transfer Methods between DMA and IRQ ............................11-4

Chapter 12 Triggering

Triggering with a Digital Source ...................................................................................12-1

Appendix A Device-Specific Information

NI 6238 ..........................................................................................................................A-1

NI 6239 ..........................................................................................................................A-4

Contents

Appendix B Troubleshooting

Analog Input ..................................................................................................................B-1

Analog Output................................................................................................................B-2

Counters ......................................................................................................................... B-3

Appendix C Technical Support and Professional Services

Glossary

Index

Figures

Figure A-1. NI 6238 Pinout ......................................................................................A-2

Figure A-2. NI 6239 Pinout ......................................................................................A-5

About This Manual

The NI 6238/6239 User Manual contains information about using the NI 6238 and NI 6239 M Series data acquisition (DAQ) devices with NI-DAQmx 8.1 and later. National Instruments 6238/6239 devices feature up to eight differential analog input (AI) channels, two analog output (AO) channels, two counters, six lines of digital input (DI), and four lines of digital output (DO).

Conventions

The following conventions are used in this manual:

<> Angle brackets that contain numbers separated by an ellipsis represent

a range of values associated with a bit or signal name—for example, AO <3..0>.

» The » symbol leads you through nested menu items and dialog box options

to a final action. The sequence File»Page Setup»Options directs you to pull down the File menu, select the Page Setup item, and select Options from the last dialog box.

This icon denotes a tip, which alerts you to advisory information.

This icon denotes a note, which alerts you to important information.

This icon denotes a caution, which advises you of precautions to take to avoid injury, data loss, or a system crash. When this symbol is marked on a product, refer to the NI 6238/6239 Specifcations for information about precautions to take.

When symbol is marked on a product, it denotes a warning advising you to take precautions to avoid electrical shock.

When symbol is marked on a product, it denotes a component that may be hot. Touching this component may result in bodily injury.

bold Bold text denotes items that you must select or click in the software, such

as menu items and dialog box options. Bold text also denotes parameter names.

About This Manual

italic Italic text denotes variables, emphasis, a cross-reference, or an introduction

to a key concept. Italic text also denotes text that is a placeholder for a word or value that you must supply.

monospace Text in this font denotes text or characters that you should enter from the

keyboard, sections of code, programming examples, and syntax examples. This font is also used for the proper names of disk drives, paths, directories, programs, subprograms, subroutines, device names, functions, operations, variables, filenames, and extensions.

Installing NI-DAQmx

The DAQ Getting Started Guide, which you can download at

ni.com/manuals, offers NI-DAQmx users step-by-step instructions for

installing software and hardware, configuring channels and tasks, and getting started developing an application.

ni.com/manuals.

Installing Other Software

If you are using other software, refer to the installation instructions that accompany your software.

Installing the Hardware

The DAQ Getting Started Guide contains non-software-specific information on how to install PCI and PXI devices, as well as accessories and cables.

Device Pinouts

Refer to Appendix A, Device-Specific Information, for NI 6238/6239 device pinouts.

Chapter 1 Getting Started

Device Specifications

Refer to the NI 6238/6239 Specifications, available on the NI-DAQ Device Document Browser or on NI 6238/6239 devices.

ni.com/manuals, for more detailed information

Device Accessories and Cables

NI offers a variety of accessories and cables to use with your DAQ device. Refer to Appendix A, Device-Specific Information, or information.

ni.com for more

NI 6238/6239 User Manual 1-2 ni.com

DAQ System Overview

Figure 2-1 shows a typical DAQ system, which includes sensors, transducers, cables that connect the various devices to the accessories, the M Series device, programming software, and PC. The following sections cover the components of a typical DAQ system.

Sensors and

Transducers

DAQ Hardware

Cables and

Accessories

DAQ hardware digitizes input signals, performs D/A conversions to generate analog output signals, and measures and controls digital I/O signals. Figure 2-2 features the components of the NI 6238/6239 devices.

DAQ

Hardware

Figure 2-1. Components of a Typical DAQ System

DAQ

Software

Personal

Computer

Chapter 2 DAQ System Overview

Analog Input

Analog Output

I/O Connector

Counters

PFI/Static DI

AI GND

AO GND

P0.GND

Isolation

Barrier

Digital

Isolators

Routing

and Clock

Generation

RTSI

Bus

Interface

Bus

DAQ-STC2

PFI/Static DO

P1.GND

Figure 2-2. General NI 6238/6239 Block Diagram

The DAQ-STC2 implements a high-performance digital engine for NI 6238/6239 data acquisition hardware. Some key features of this engine include the following:

• Flexible AI and AO sample and convert timing

• Many triggering modes

• Independent AI and AO FIFOs

• Generation and routing of RTSI signals for multi-device synchronization

• Generation and routing of internal and external timing signals

• Two flexible 32-bit counter/timer modules with hardware gating

• Static DIO signals

• PLL for clock synchronization

• PCI/PXI interface

• Independent scatter-gather DMA controllers for all acquisition and generation functions

NI 6238/6239 User Manual 2-2 ni.com

Calibration Circuitry

The M Series analog inputs and outputs can self calibrate to correct gain and offset errors. You can calibrate the device to minimize AI and AO errors caused by time and temperature drift at run time. No external circuitry is necessary; an internal reference ensures high accuracy and stability over time and temperature changes.

Factory-calibration constants are permanently stored in an onboard EEPROM and cannot be modified. When you self-calibrate the device, software stores new constants in a user-modifiable section of the EEPROM. To return a device to its initial factory calibration settings, software can copy the factory-calibration constants to the user-modifiable section of the EEPROM. Refer to the NI-DAQmx Help or the LabVIEW 8.x Help for more information on using calibration constants.

Sensors and Transducers

Sensors can generate electrical signals to measure physical phenomena, such as temperature, force, sound, or light. Some commonly used sensors are strain gauges, thermocouples, thermistors, angular encoders, linear encoders, and resistance temperature detectors (RTDs).

Chapter 2 DAQ System Overview

Note Current input measurement devices can only interface with sensors that output a current.

To measure signals from these various transducers, you must convert them into a form that a DAQ device can accept. For example, the output voltage of most thermocouples is very small and susceptible to noise. Therefore, you may need to amplify or filter the thermocouple output before digitizing it, or use the smallest measurement range available within the DAQ device.

For more information about sensors, refer to the following:

• For general information about sensors, visit

• If you are using LabVIEW, refer to the LabVIEW Help by selecting

Help»Search the LabVIEW Help in LabVIEW, and then navigate to the Taking Measurements book on the Contents tab.

• If you are using other application software, refer to Common Sensors in the NI-DAQmx Help, which can be accessed from Start»All Programs»National Instruments»NI-DAQ»NI-DAQmx Help.

ni.com/sensors.

Chapter 2 DAQ System Overview

Cables and Accessories

NI offers a variety of products to use with NI 6238/6239 devices, including cables, connector blocks, and other accessories, as follows:

• Cables and cable assemblies

– Shielded

– Unshielded ribbon

• Screw terminal connector blocks, shielded and unshielded

• RTSI bus cables

Custom Cabling

For more specific information about these products, refer to

Refer to the Custom Cabling section of this chapter, the Field Wiring

Considerations section of Chapter 4, Analog Input, and Appendix A, Device-Specific Information, for information on how to select accessories

for your M Series device.

NI offers cables and accessories for many applications. However, if you want to develop your own cable, the following kits can assist you:

• TB-37F-37SC—37-pin solder cup terminals, shell with strain relief

• TB-37F-37CP—37-pin crimp & poke terminals, shell with strain

relief

Also, adhere to the following guidelines for best results:

• For AI signals, use shielded, twisted-pair wires for each AI pair of differential inputs. Connect the shield for each signal pair to the ground reference at the source.

• Route the analog lines separately from the digital lines.

• When using a cable shield, use separate shields for the analog and digital sections of the cable. Failure to do so results in noise coupling into the analog signals from transient digital signals.

ni.com.

For more information on the connectors used for DAQ devices, refer to the KnowledgeBase document, Specifications and Manufacturers for Board Mating Connectors, by going to

rdspmb.

NI 6238/6239 User Manual 2-4 ni.com

ni.com/info and entering the info code

Programming Devices in Software

National Instruments measurement devices are packaged with NI-DAQ driver software, an extensive library of functions and VIs you can call from your application software, such as LabVIEW or LabWindows/CVI, to program all the features of your NI measurement devices. Driver software has an application programming interface (API), which is a library of VIs, functions, classes, attributes, and properties for creating applications for your device.

NI-DAQ includes two NI-DAQ drivers, Traditional NI-DAQ (Legacy) and NI-DAQmx. M Series devices use the NI-DAQmx driver. Each driver has its own API, hardware configuration, and software configuration. Refer to the DAQ Getting Started Guide for more information about the two drivers.

NI-DAQmx includes a collection of programming examples to help you get started developing an application. You can modify example code and save it in an application. You can use examples to develop a new application or add example code to an existing application.

To locate LabVIEW and LabWindows/CVI examples, open the National Instruments Example Finder.

• In LabVIEW, select Help»Find Examples.

• In LabWindows/CVI, select Help»NI Example Finder.

Chapter 2 DAQ System Overview

Measurement Studio, Visual Basic, and ANSI C examples are located in the following directories:

• NI-DAQmx examples for Measurement Studio-supported languages are in the following directories:

–

MeasurementStudio\VCNET\Examples\NIDaq

– MeasurementStudio\DotNET\Examples\NIDaq

• NI-DAQmx examples for ANSI C are in the

NI-DAQ\Examples\DAQmx ANSI C Dev directory

For additional examples, refer to

zone.ni.com.

Connector Information

The I/O Connector Signal Descriptions and RTSI Connector Pinout sections contain information on M Series connectors. Refer to Appendix A, Device-Specific Information, for device I/O connector pinouts.

I/O Connector Signal Descriptions

Table 3-1 describes the signals found on the I/O connectors. Not all signals are available on all devices.

Table 3-1. I/O Connector Signals

Signal Name Reference Direction Description

AI GND — — Analog Input Ground—These terminals are the input bias

current return point. AI GND and AO GND are connected on the device.

Note: AI GND and AO GND are isolated from earth ground, chassis ground, P0.GND, and P1.GND.

AI <0..7>± AI GND Input Analog Input Channels 0 to 7±—AI 0+ and AI 0– are the

positive and negative inputs of differential analog input channel 0. Similarly, the following signal pairs also form differential input channels:

Also refer to the Analog Input Ground-Reference Settings section of Chapter 4, Analog Input.

Note: AI <0..7>± are isolated from earth ground and chassis ground.

AO <0..1> AO GND Output Analog Output Channels 0 to 1—These terminals supply the

current output of AO channels 0 to 1.

Note: AO <0..1> are isolated from earth ground and chassis ground.

Chapter 3 Connector Information

Table 3-1. I/O Connector Signals (Continued)

Signal Name Reference Direction Description

AO GND — — Analog Output Ground—AO GND is the reference for

AO <0..1>. AI GND and AO GND are connected on the device.

Note: AI GND and AO GND are isolated from earth ground, chassis ground, P0.GND, and P1.GND.

PFI <0..5>/P0.<0..5> P0.GND Input Programmable Function Interface or Static Digital Input

Channels 0 to 5—Each of these terminals can be individually configured as an input directional PFI terminal or a digital input terminal.

As an input, each input PFI terminal can be used to supply an external source for AI or AO timing signals or counter/timer inputs.

Note: PFI <0..5>/P0.<0..5> are isolated from earth ground, chassis ground, AI GND, AO GND, and P1.GND.

PFI <6..9>/P1.<0..3> P1.GND Output Programmable Function Interface or Static Digital

Output Channels 6 to 9—Each of these terminals can be individually configured as an output directional PFI terminal or a digital output terminal.

As a PFI output, you can route many different internal AI or AO timing signals to each PFI terminal. You also can route the counter/timer outputs to each PFI terminal.

Note: PFI <6..9>/P1.<0..3> are isolated from earth ground, chassis ground, AI GND, AO GND, and P0.GND.

NC — — No connect—Do not connect signals to these terminals.

P0.GND — — Digital Ground—P0.GND supplies the reference for input

PFI <0..5>/P0.<0..5>.

Note: P0.GND is isolated from earth ground, chassis ground, AI GND, AO GND, and P1.GND.

P1.GND — — Digital Ground—P1.GND supplies the reference for output

P1.VCC — — Digital Output Power—P1.VCC supplies the power for

AO POWER SUPPLY — — Analog Output Power Supply—AO POWER SUPPLY

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PFI <6..9>/P1.<0..3>.

Note: P1.GND is isolated from earth ground, chassis ground, AI GND, AO GND, and P0.GND.

digital output lines. The actual power consumed depends on the load connected between the digital output and P1.GND.

supplies power to the analog current output terminals.

Chapter 3 Connector Information

Table 3-1. I/O Connector Signals (Continued)

Signal Name Reference Direction Description

CAL+ — — External Calibration Positive Reference—CAL+ supplies

the positive reference during external calibration of the NI 6238/6239.

CAL– — — External Calibration Negative Reference—CAL– supplies

the negative reference during external calibration of the NI 6238/6239.

RTSI Connector Pinout

Refer to the RTSI Connector Pinout section of Chapter 10, Digital Routing

and Clock Generation, for information on the RTSI connector.

Analog Input

Figure 4-1 shows the analog input circuitry of NI 6238 and NI 6239 devices.

AI <0..7>+

Mux

AI Terminal

AI <0..7>–

I/O Connector

AI GND

Analog Input Circuitry

Configuration

Selection

Isolation

Barrier

NI-PGIA

Input Range

Selection

Figure 4-1. NI 6238/6239 Analog Input Circuitry

ADC

Digital

Isolators

AI FIFO

AI Data

I/O Connector

You can connect analog input signals to the M Series device through the I/O connector. The proper way to connect analog input signals is outlined in the

Connecting Analog Current Input Signals section. Also refer to

Appendix A, Device-Specific Information, for device I/O connector pinouts.

MUX

Each M Series device has one analog-to-digital converter (ADC). The multiplexers (MUX) route one AI channel at a time to the ADC through the NI-PGIA.

Instrumentation Amplifier (NI-PGIA)

The NI programmable gain instrumentation amplifier (PGIA) is a measurement and instrument class amplifier that minimizes settling times

Chapter 4 Analog Input

for all input ranges. The NI-PGIA can amplify or attenuate an AI signal to ensure that you use the maximum resolution of the ADC.

M Series devices use the NI-PGIA to deliver high accuracy even when sampling multiple channels with small input ranges at fast rates. M Series devices can sample channels in any order at the maximum conversion rate, and you can individually program each channel in a sample with a different input range.

A/D Converter

The analog-to-digital converter (ADC) digitizes the AI signal by converting the analog voltage into a digital number.

Isolation Barrier and Digital Isolators

The digital isolators across the isolation barrier provide a ground break between the isolated analog front end and the earth/chassis/building ground.

AI FIFO

M Series devices can perform both single and multiple A/D conversions of a fixed or infinite number of samples. A large first-in-first-out (FIFO) buffer holds data during AI acquisitions to ensure that no data is lost. M Series devices can handle multiple A/D conversion operations with DMA, interrupts, or programmed I/O.

Analog Input Range

Input range refers to the set of input voltages or currents that an analog input channel can digitize with the specified accuracy. The NI-PGIA amplifies or attenuates the AI signal depending on the input range. You can individually program the input range of each AI channel on your M Series device.

The input range affects the resolution of the M Series device for an AI channel. Resolution refers to the voltage or current of one ADC code.

For example, a 16-bit ADC converts analog current inputs into one of 65,536 (= 2 values are spread fairly evenly across the input range. So, for an input range of ±20 mA, the current of each code of a 16-bit ADC is:

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) codes—that is, one of 65,536 possible digital values. These

Chapter 4 Analog Input

(20 mA – (–20 mA))

M Series devices use a calibration method that requires some codes (typically about 5% of the codes) to lie outside of the specified range. This calibration method improves absolute accuracy, but it increases the nominal resolution of input ranges by about 5% over what the formulas shown above would indicate.

Choose an input range that matches the expected input range of your signal. A large input range can accommodate a large signal variation, but reduces the measurement resolution. Choosing a smaller input range improves the measurement resolution, but may result in the input signal going out of range.

For more information on programming these settings, refer to the NI-DAQmx Help or the LabVIEW 8.x Help.

Table 4-1 shows the input ranges and resolutions supported by the NI 6238 and NI 6239 devices.

Table 4-1. Input Ranges for NI 6238/6239

Input Range

= 610 nA

Nominal Resolution Assuming

5% Over Range

20 mA 640 nA

Connecting Analog Current Input Signals

When making signal connections, caution must be taken with the voltage level of the signal going into the device. There are two types of connections that can be made.

Method 1

Method 1, shown in Figure 4-2, connects AI + and AI – inputs at a voltage level with respect to AI GND. Verify that the voltage levels on the AI + and AI – side do not exceed the common-mode input range of ±10 V. Common-mode input range is the voltage input range with respect to AI GND (AI + versus AI GND, AI – versus AI GND, or AI + versus AI –).

Chapter 4 Analog Input

AI +

Isolation

Barrier

Method 2

AI –

–

AI GND

–

AI GND

Figure 4-2. Analog Current Input Connection Method 1

Method 2, shown in Figure 4-3, ties the AI – input to AI GND. When measuring current up to 20 mA, this type of connection ensures that the voltage level on both the positive and negative side are within the common-mode input range for NI 6238/6239 devices.

Isolation

Barrier

AI +

AI –

AI GND

–

Figure 4-3. Analog Current Input Connection Method 2

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Chapter 4 Analog Input

Note that AI GND must always be connected to some voltage level. AI GND is the reference that NI 6238/6239 devices measure against.

The NI 6238 and NI 6239 are isolated devices with isolation ratings up to 60 VDC/30 Vrms. This allows for current measurement at high voltage levels provided that the common-mode input range requirement is satisfied. For example, in Figure 4-4, the node connected to AI GND can be at 50 V above the earth ground.

Isolation

Barrier

AI +

Vcm = 50 V

AI –

AI GND

–

Figure 4-4. Current Measurement at High Voltage Levels

Analog Input Ground-Reference Settings

The NI 6238/6239 device measures the voltage generated across the current input sense resistor during current input measurement. This voltage difference is then routed into the instrumentation amplifier (PGIA) differentially, as shown in Figure 4-5.

Chapter 4 Analog Input

in+

Current

Sense

Resistor

in–

Instrumentation

Amplifier

PGIA

Measured

Voltage

AI Ground-Reference

Settings

DIFF AI <0..7>+ AI <0..7>–

AI GND

Vm = Iin • R × Gain

–

Figure 4-5. NI 6238/6239 PGIA

Analog input ground-reference setting refers to the reference that the PGIA measures against. Differential is the only ground-reference setting for NI 6238/6239 analog input signals, which means that the PGIA always measures the voltages between AI + and AI – generated across the input sense resistor, regardless of which analog input connection method is used. Refer to the Connecting Analog Current Input Signals section for allowable input connection methods.

When measuring voltages internal to the device, such as the onboard reference, the signal is measured against AI GND. This measurement method is called referenced single-ended (RSE). The name is derived from the fact that one end of the measurement, the positive input of the PGIA, is connected to a signal, and the negative input of the PGIA is connected to the AI GND reference.

Table 4-2 shows how signals are routed to the NI-PGIA.

Table 4-2. Signals Routed to the NI-PGIA

Signals Routed to the Positive

Input of the NI-PGIA (V

in+

Signals Routed to the Negative

)

Input of the NI-PGIA (V

in–

)

RSE Internal Channels AI GND

Note On devices that allow multiple ground-reference settings, the settings are programmed on a per-channel basis.

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Chapter 4 Analog Input

Caution The maximum input voltages rating of AI signals with respect to AI GND (and for differential signals with respect to each other) and earth/chassis ground are listed in the Maximum Working Voltage section of the NI 6238/6239 Specifications. Exceeding the maximum input voltage or maximum working voltage of AI signals distorts the measurement results. Exceeding the maximum input voltage or maximum working voltage rating also can damage the device and the computer. Exceeding the maximum input voltage can cause injury and harm the user. NI is not liable for any damage or injuries resulting from such signal connections.

AI ground-reference setting is sometimes referred to as AI terminal configuration.

Configuring AI Ground-Reference Settings in Software

You can program channels on an M Series device to acquire with different ground references.

To enable multimode scanning in LabVIEW, use

Virtual Channel.vi

each channel or group of channels configured in a different input mode. In Figure 4-6, channel 0 is configured in differential mode and aignd_vs_aignd reads the internal analog input ground-reference of the device.

Figure 4-6. Enabling Multimode Scanning in LabVIEW

To configure the input mode of your current measurement using the DAQ Assistant, use the Terminal Configuration drop-down list. Refer to the DAQ Assistant Help for more information on the DAQ Assistant.

To configure the input mode of your current measurement using the NI-DAQmx C API, set the terminalConfig property. Refer to the NI-DAQmx C Reference Help for more information.

of the NI-DAQmx API. You must use a new VI for

NI-DAQmx Create

Chapter 4 Analog Input

Multichannel Scanning Considerations

M Series devices can scan multiple channels at high rates and digitize the signals accurately. However, you should consider several issues when designing your measurement system to ensure the high accuracy of your measurements.

In multichannel scanning applications, accuracy is affected by settling time. When your M Series device switches from one AI channel to another AI channel, the device configures the NI-PGIA with the input range of the new channel. The NI-PGIA then amplifies the input signal with the gain for the new input range. Settling time refers to the time it takes the NI-PGIA to amplify the input signal to the desired accuracy before it is sampled by the ADC. The NI 6238/6239 Specifications shows the device settling time.

M Series devices are designed to have fast settling times. However, several factors can increase the settling time which decreases the accuracy of your measurements. To ensure fast settling times, you should do the following (in order of importance):

• Use short high-quality cabling

• Minimize current step between adjacent channels

• Avoid scanning faster than necessary

Refer to the following sections for more information on these factors.

Use Short High-Quality Cabling

Using short high-quality cables can minimize several effects that degrade accuracy including crosstalk, transmission line effects, and noise. The capacitance of the cable also can increase the settling time.

National Instruments recommends using individually shielded, twisted-pair wires that are 2 m or less to connect AI signals to the device. Refer to the Connecting Analog Current Input Signals section for more information.

Minimize Current Step between Adjacent Channels

When scanning between channels that have the same input range, the settling time increases with the current step between the channels. If you know the expected input range of your signals, you can group signals with similar expected ranges together in your scan list.

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For example, suppose all channels in a system use a –20 to 20 mA input range. The signals on channels 0, 2, and 4 vary between 18 and 19 mA. The signals on channels 1, 3, and 5 vary between –18 and 0 mA. Scanning channels in the order 0, 2, 4, 1, 3, 5 will produce more accurate results than scanning channels in the order 0, 1, 2, 3, 4, 5.

Avoid Scanning Faster Than Necessary

Designing your system to scan at slower speeds gives the PGIA more time to settle to a more accurate level. Here are two examples to consider.

Example 1

Averaging many AI samples can increase the accuracy of the reading by decreasing noise effects. In general, the more points you average, the more accurate the final result will be. However, you may choose to decrease the number of points you average and slow down the scanning rate.

Suppose you want to sample 10 channels over a period of 40 ms and average the results. You could acquire 500 points from each channel at a scan rate of 125 kS/s. Another method would be to acquire 1,000 points from each channel at a scan rate of 250 kS/s. Both methods take the same amount of time. Doubling the number of samples averaged (from 500 to 1,000) decreases the effect of noise by a factor of 1.4 (the square root of 2). However, doubling the number of samples (in this example) decreases the time the PGIA has to settle from 8 µs to 4 µs. In some cases, the slower scan rate system returns more accurate results.

Chapter 4 Analog Input

Example 2

If the time relationship between channels is not critical, you can sample from the same channel multiple times and scan less frequently. For example, suppose an application requires averaging 100 points from channel 0 and averaging 100 points from channel 1. You could alternate reading between channels—that is, read one point from channel 0, then one point from channel 1, and so on. You also could read all 100 points from channel 0 then read 100 points from channel 1. The second method switches between channels much less often and is affected much less by settling time.

Chapter 4 Analog Input

Analog Input Data Acquisition Methods

When performing analog input measurements, you either can perform software-timed or hardware-timed acquisitions. Hardware-timed acquisitions can be buffered or non-buffered.

Software-Timed Acquisitions

With a software-timed acquisition, software controls the rate of the acquisition. Software sends a separate command to the hardware to initiate each ADC conversion. In NI-DAQmx, software-timed acquisitions are referred to as having on-demand timing. Software-timed acquisitions are also referred to as immediate or static acquisitions and are typically used for reading a single sample of data.

Hardware-Timed Acquisitions

With hardware-timed acquisitions, a digital hardware signal (ai/SampleClock) controls the rate of the acquisition. This signal can be generated internally on your device or provided externally.

Hardware-timed acquisitions have several advantages over software-timed acquisitions.

• The time between samples can be much shorter.

• The timing between samples is deterministic.

• Hardware-timed acquisitions can use hardware triggering.

Hardware-timed operations can be buffered or non-buffered. A buffer is a temporary storage in computer memory for to-be-generated samples.

Buffered

In a buffered acquisition, data is moved from the DAQ device’s onboard FIFO memory to a PC buffer using DMA or interrupts before it is transferred to application memory. Buffered acquisitions typically allow for much faster transfer rates than non-buffered acquisitions because data is moved in large blocks, rather than one point at a time.

One property of buffered I/O operations is the sample mode. The sample mode can be either finite or continuous.

Finite sample mode acquisition refers to the acquisition of a specific, predetermined number of data samples. After the specified number of

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Chapter 4 Analog Input

samples has been written out, the generation stops. If you use a reference trigger, you must use finite sample mode.

Continuous acquisition refers to the acquisition of an unspecified number of samples. Instead of acquiring a set number of data samples and stopping, a continuous acquisition continues until you stop the operation. Continuous acquisition is also referred to as double-buffered or circular-buffered acquisition.

If data cannot be transferred across the bus fast enough, the FIFO will become full. New acquisitions will overwrite data in the FIFO before it can be transferred to host memory. The device generates an error in this case. With continuous operations, if the user program does not read data out of the PC buffer fast enough to keep up with the data transfer, the buffer could reach an overflow condition, causing an error to be generated.

Non-Buffered

In non-buffered acquisitions, data is read directly from the FIFO on the device. Typically, hardware-timed, non-buffered operations are used to read single samples with known time increments between them and good latency.

Analog Input Triggering

Analog input supports three different triggering actions:

• Start trigger

• Reference trigger

• Pause trigger

Refer to the AI Start Trigger Signal, AI Reference Trigger Signal, and AI

Pause Trigger Signal sections for information on these triggers.

A digital trigger can initiate these actions. NI 6238/6239 devices support digital triggering, but do not support analog triggering.

Field Wiring Considerations

Environmental noise can seriously affect the measurement accuracy of the device if you do not take proper care when running signal wires between signal sources and the device. The following recommendations apply

Chapter 4 Analog Input

mainly to AI signal routing to the device, although they also apply to signal routing in general.

Minimize noise pickup and maximize measurement accuracy by using individually shielded, twisted-pair wires to connect AI signals to the device. With this type of wire, the signals attached to the positive and negative input channels are twisted together and then covered with a shield. You then connect this shield only at one point to the signal source ground. This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference.

Refer to the NI Developer Zone document, Field Wiring and Noise Considerations for Analog Signals, for more information. To access this document, go to

ni.com/info and enter the info code rdfwn3.

Analog Input Timing Signals

In order to provide all of the timing functionality described throughout this section, NI 6238/6239 devices have a flexible timing engine. Figure 4-7 summarizes all of the timing options provided by the analog input timing engine. Also refer to the Clock Routing section of Chapter 10, Digital

Routing and Clock Generation.

PFI, RTSI

PXI_STAR

20 MHz Timebase

100 kHz Timebase

PXI_CLK10

ai/Sample

Clock

Timebase

ai/Convert

Clock

Timebase

Ctr

Programmable

Clock

Divider

Ctr

Programmable

Clock

Divider

PXI_STAR

Internal Output

SW Pulse

PFI, RTSI

PXI_STAR

Internal Output

ai/Sample

Clock

ai/Convert

Clock

Figure 4-7. Analog Input Timing Options

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Chapter 4 Analog Input

M Series devices use ai/SampleClock and ai/ConvertClock to perform interval sampling. As Figure 4-8 shows, ai/SampleClock controls the sample period, which is determined by the following equation:

1/Sample Period = Sample Rate

Channel 0

Channel 1

Convert Period

Sample Period

Figure 4-8. Interval Sampling

ai/ConvertClock controls the Convert Period, which is determined by the following equation:

1/Convert Period = Convert Rate

By default, the NI-DAQmx driver chooses the fastest Channel Clock rate possible while still allowing extra time for adequate amplifier settling time. At slower scan rates, 10 μs of delay is added to the fastest possible channel conversion rate of the device, which is the same as the maximum scan rate, to derive the Channel Clock.

As the scan rate increases, there eventually will not be enough time to have a full 10 μs of additional delay time between channel conversions and to finish acquiring all channels before the next edge of the Scan Clock. At this point, NI-DAQmx uses round robin channel sampling, evenly dividing the time between scans by the number of channels being acquired to obtain the interchannel delay. In this case, you can calculate the Channel Clock by multiplying the scan rate by the number of channels being acquired.

For example, the NI 623x M Series device has a maximum sampling rate of 250 kS/s. At a slower acquisition rate, such as 10 kHz with 2 channels, the Convert Clock would be set to 71428.6 Hz. This rate is determined by taking the fastest channel conversion rate for the device and adding 10 μs, 4 μs (1/250000) + 10 μs, which results in 14 μs or 71428.6 Hz.

Chapter 4 Analog Input

Note The sampling rate is the fastest you can acquire data on the device and still achieve accurate results. For example, if an M Series device has a sampling rate of 250 kS/s, this sampling rate is aggregate—one channel at 250 kS/s or two channels at 125 kS/s per channel illustrates the relationship.

When this calculation results in the sampling rate exceeding 35 kHz, there is not enough time between samples to acquire both channels and still add a 10 μs delay per channel, so the Convert Clock rate becomes the sampling rate multiplied by the number of channels being acquired. For example, on the PCI-6220 M Series device, a sampling rate of 40 kHz for two channels would result in a Convert Clock rate of 80 kHz.

Maximum settling time for the amplifier is also very important. For example, to ensure accuracy to within ± 1 LSB on an NI 623x M Series device, the device requires a minimum amplifier settling time of 6 μs even though the maximum channel conversion rate is 4 μs. Higher source impedance also increases amplifier settling time.

Posttriggered data acquisition allows you to view only data that is acquired after a trigger event is received. A typical posttriggered DAQ sequence is shown in Figure 4-9. In this example, the DAQ device reads two channels five times. The sample counter is loaded with the specified number of posttrigger samples, in this example, five. The value decrements with each pulse on ai/SampleClock, until the value reaches zero and all desired samples have been acquired.

ai/StartTrigger

ai/SampleClock

ai/ConvertClock

Sample Counter

Figure 4-9. Posttriggered Data Acquisition Example

13042

Pretriggered data acquisition allows you to view data that is acquired before the trigger of interest, in addition to data acquired after the trigger. Figure 4-10 shows a typical pretriggered DAQ sequence. ai/StartTrigger can be either a hardware or software signal. If ai/StartTrigger is set up to be a software start trigger, an output pulse appears on the ai/StartTrigger line when the acquisition begins. When the ai/StartTrigger pulse occurs, the sample counter is loaded with the number of pretriggered samples, in this

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Chapter 4 Analog Input

example, four. The value decrements with each pulse on ai/SampleClock, until the value reaches zero. The sample counter is then loaded with the number of posttriggered samples, in this example, three.

ai/StartTrigger

ai/ReferenceTrigger

ai/SampleClock

ai/ConvertClock

Scan Counter

Figure 4-10. Pretriggered Data Acquisition Example

n/a

0123 10222

If an ai/ReferenceTrigger pulse occurs before the specified number of pretrigger samples are acquired, the trigger pulse is ignored. Otherwise, when the ai/ReferenceTrigger pulse occurs, the sample counter value decrements until the specified number of posttrigger samples have been acquired.

NI 6238/6239 devices feature the following analog input timing signals.

• AI Sample Clock Signal

• AI Sample Clock Timebase Signal

• AI Convert Clock Signal

• AI Convert Clock Timebase Signal

• AI Hold Complete Event Signal

• AI Start Trigger Signal

• AI Reference Trigger Signal

• AI Pause Trigger Signal

AI Sample Clock Signal

Use the AI Sample Clock (ai/SampleClock) signal to initiate a set of measurements. Your M Series device samples the AI signals of every channel in the task once for every ai/SampleClock. A measurement acquisition consists of one or more samples.

Chapter 4 Analog Input

You can specify an internal or external source for ai/SampleClock. You also can specify whether the measurement sample begins on the rising edge or falling edge of ai/SampleClock.

Using an Internal Source

One of the following internal signals can drive ai/SampleClock.

• Counter n Internal Output

• AI Sample Clock Timebase (divided down)

• A pulse initiated by host software

A programmable internal counter divides down the sample clock timebase.

Several other internal signals can be routed to ai/SampleClock through RTS I . Refer t o Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

Using an External Source

Use one of the following external signals as the source of ai/SampleClock:

• Input PFI <0..5>

•RTSI <0..7>

•PXI_STAR

Note Refer to the NI 6238/6239 Specifications for the minimum allowable pulse width and the propagation delay of PFI <0..5>.

Routing AI Sample Clock Signal to an Output Terminal

You can route ai/SampleClock out to any output PFI <6..9> or RTSI <0..7> terminal. This pulse is always active high.

You can specify the output to have one of two behaviors. With the pulse behavior, your DAQ device briefly pulses the PFI terminal once for every occurrence of ai/SampleClock.

With level behavior, your DAQ device drives the PFI terminal high during the entire sample.

PFI <0..5> terminals are fixed inputs. PFI <6..9> terminals are fixed outputs.

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Chapter 4 Analog Input

Other Timing Requirements

Your DAQ device only acquires data during an acquisition. The device ignores ai/SampleClock when a measurement acquisition is not in progress. During a measurement acquisition, you can cause your DAQ device to ignore ai/SampleClock using the ai/PauseTrigger signal.

A counter on your device internally generates ai/SampleClock unless you select some external source. ai/StartTrigger starts this counter and either software or hardware can stop it after a finite acquisition completes. When using an internally generated ai/SampleClock, you also can specify a configurable delay from ai/StartTrigger to the first ai/SampleClock pulse. By default, this delay is set to two ticks of the ai/SampleClockTimebase signal. When using an externally generated ai/SampleClock, you must ensure the clock signal is consistent with respect to the timing requirements of ai/ConvertClock. Failure to do so may result in ai/SampleClock pulses that are masked off and acquisitions with erratic sampling intervals. Refer to the AI Convert Clock Signal section for more information on the timing requirements between ai/ConvertClock and ai/SampleClock.

Figure 4-11 shows the relationship of ai/SampleClock to ai/StartTrigger.

ai/SampleClockTimebase

ai/StartTrigger

ai/SampleClock

Delay

From

Start

Trigger

Figure 4-11. ai/SampleClock and ai/StartTrigger

AI Sample Clock Timebase Signal

You can route any of the following signals to be the AI Sample Clock Timebase (ai/SampleClockTimebase) signal:

• 20 MHz Timebase

• 100 kHz Timebase

•PXI_CLK10

Chapter 4 Analog Input

•RTSI <0..7>

• Input PFI <0..5>

•PXI_STAR

ai/SampleClockTimebase is not available as an output on the I/O connector. ai/SampleClockTimebase is divided down to provide one of the possible sources for ai/SampleClock. You can configure the polarity selection for ai/SampleClockTimebase as either rising or falling edge.

AI Convert Clock Signal

Caution Setting the conversion rate higher than the maximum rate specified for your

device will result in errors.

Use the AI Convert Clock (ai/ConvertClock) signal to initiate a single A/D conversion on a single channel. A sample, controlled by the AI Sample Clock, consists of one or more conversions.

You can specify either an internal or external signal as the source of ai/ConvertClock. You also can specify whether the measurement sample begins on the rising edge or falling edge of ai/ConvertClock.

With NI-DAQmx, the driver will choose the fastest conversion rate possible based on the speed of the A/D converter and add 10 µs of padding between each channel to allow for adequate settling time. This scheme enables the channels to approximate simultaneous sampling and still allow for adequate settling time. If the AI Sample Clock rate is too fast to allow for this 10 µs of padding, NI-DAQmx will choose the conversion rate so that the AI Convert Clock pulses are evenly spaced throughout the sample.

To explicitly specify the conversion rate, use the AI Convert Clock Rate DAQmx Timing property node or function.

Using an Internal Source

One of the following internal signals can drive ai/ConvertClock:

• AI Convert Clock Timebase (divided down)

• Counter n Internal Output

A programmable internal counter divides down the AI Convert Clock Timebase to generate ai/ConvertClock. The counter is started by ai/SampleClock and continues to count down to zero, produces an ai/ConvertClock, reloads itself, and repeats the process until the sample is

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Chapter 4 Analog Input

finished. It then reloads itself in preparation for the next ai/SampleClock pulse.

Using an External Source

Use one of the following external signals as the source of ai/ConvertClock:

• Input PFI <0..5>

•RTSI <0..7>

•PXI_STAR

Note Refer to the NI 6238/6239 Specifications for the minimum allowable pulse width and the propagation delay of PFI <0..5>.

Routing AI Convert Clock Signal to an Output Terminal

You can route ai/ConvertClock (as an active low signal) out to any output PFI <6..9> or RTSI <0..7> terminal.

PFI <0..5> terminals are fixed inputs. PFI <6..9> terminals are fixed outputs.

Using a Delay from Sample Clock to Convert Clock

When using an internally generated ai/ConvertClock, you also can specify a configurable delay from ai/SampleClock to the first ai/ConvertClock pulse within the sample. By default, this delay is three ticks of ai/ConvertClockTimebase.

Figure 4-12 shows the relationship of ai/SampleClock to ai/ConvertClock.

Chapter 4 Analog Input

ai/ConvertClockTimebase

ai/SampleClock

ai/ConvertClock

Delay From

Sample

Clock

Convert

Perio d

Figure 4-12. ai/SampleClock and ai/ConvertClock

Other Timing Requirements

The sample and conversion level timing of M Series devices work such that clock signals are gated off unless the proper timing requirements are met. For example, the device ignores both ai/SampleClock and ai/ConvertClock until it receives a valid ai/StartTrigger signal. When the device recognizes an ai/SampleClock pulse, it ignores subsequent ai/SampleClock pulses until it receives the correct number of ai/ConvertClock pulses.

Similarly, the device ignores all ai/ConvertClock pulses until it recognizes an ai/SampleClock pulse. After the device receives the correct number of ai/ConvertClock pulses, it ignores subsequent ai/ConvertClock pulses until it receives another ai/SampleClock. Figure 4-13 shows timing sequences for a four-channel acquisition (using AI channels 0, 1, 2, and 3) and demonstrates proper and improper sequencing of ai/SampleClock and ai/ConvertClock.

It is also possible to use a single external signal to drive both ai/SampleClock and ai/ConvertClock at the same time. In this mode, each tick of the external clock will cause a conversion on the ADC. Figure 4-13 shows this timing relationship.

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ai/SampleClock

ai/ConvertClock

Channel Measured

Figure 4-13. Single External Signal Driving ai/SampleClock and ai/ConvertClock

AI Convert Clock Timebase Signal

The AI Convert Clock Timebase (ai/ConvertClockTimebase) signal is divided down to provide on of the possible sources for ai/ConvertClock. Use one of the following signals as the source of ai/ConvertClockTimebase:

• ai/SampleClockTimebase

• 20 MHz Timebase

Chapter 4 Analog Input

1230

Sample #1 Sample #2 Sample #3

• One External Signal Driving Both Clocks

Simultaneously

12301…0

ai/ConvertClockTimebase is not available as an output on the I/O connector.

AI Hold Complete Event Signal

The AI Hold Complete Event (ai/HoldCompleteEvent) signal generates a pulse after each A/D conversion begins. You can route ai/HoldCompleteEvent out to any output PFI <6..9> or RTSI <0..7> terminal.

The polarity of ai/HoldCompleteEvent is software-selectable, but is typically configured so that a low-to-high leading edge can clock external AI multiplexers indicating when the input signal has been sampled and can be removed.

Chapter 4 Analog Input

AI Start Trigger Signal

Use the AI Start Trigger (ai/StartTrigger) signal to begin a measurement acquisition. A measurement acquisition consists of one or more samples. If you do not use triggers, begin a measurement with a software command. After the acquisition begins, configure the acquisition to stop under the following conditions:

• When a certain number of points are sampled (in finite mode)

• After a hardware reference trigger (in finite mode)

• With a software command (in continuous mode)

An acquisition that uses a start trigger (but not a reference trigger) is sometimes referred to as a posttriggered acquisition.

Using a Digital Source

To use ai/StartTrigger with a digital source, specify a source and an edge. The source can be any of the following signals:

• Input PFI <0..5>

•RTSI <0..7>

• Counter n Internal Output

•PXI_STAR

Note Refer to the NI 6238/6239 Specifications for the minimum allowable pulse width and the propagation delay of PFI <0..5>.

The source also can be one of several other internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

You also can specify whether the measurement acquisition begins on the rising edge or falling edge of ai/StartTrigger.

Routing AI Start Trigger to an Output Terminal

You can route ai/StartTrigger out to any output PFI <6..9> or RTSI <0..7> terminal.

The output is an active high pulse.

The device also uses ai/StartTrigger to initiate pretriggered DAQ operations. In most pretriggered applications, a software trigger generates ai/StartTrigger. Refer to the AI Reference Trigger Signal section for a

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complete description of the use of ai/StartTrigger and ai/ReferenceTrigger in a pretriggered DAQ operation.

AI Reference Trigger Signal

Use a reference trigger (ai/ReferenceTrigger) signal to stop a measurement acquisition. To use a reference trigger, specify a buffer of finite size and a number of pretrigger samples (samples that occur before the reference trigger). The number of posttrigger samples (samples that occur after the reference trigger) desired is the buffer size minus the number of pretrigger samples.

After the acquisition begins, the DAQ device writes samples to the buffer. After the DAQ device captures the specified number of pretrigger samples, the DAQ device begins to look for the reference trigger condition. If the reference trigger condition occurs before the DAQ device captures the specified number of pretrigger samples, the DAQ device ignores the condition.

If the buffer becomes full, the DAQ device continuously discards the oldest samples in the buffer to make space for the next sample. This data can be accessed (with some limitations) before the DAQ device discards it. Refer to the KnowledgeBase document, Can a Pretriggered Acquisition be Continuous?, for more information. To access this KnowledgeBase, go to

ni.com/info and enter the info code rdcanq.

Chapter 4 Analog Input

When the reference trigger occurs, the DAQ device continues to write samples to the buffer until the buffer contains the number of posttrigger samples desired. Figure 4-14 shows the final buffer.

Reference Trigger

Pretrigger Samples

Complete Buffer

Figure 4-14. Reference Trigger Final Buffer

Posttrigger Samples

Chapter 4 Analog Input

Using a Digital Source

To use ai/ReferenceTrigger with a digital source, specify a source and an edge. The source can be any of the following signals:

• Input PFI <0..5>

•RTSI <0..7>

•PXI_STAR

The source also can be one of several internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

You also can specify whether the measurement acquisition stops on the rising edge or falling edge of ai/ReferenceTrigger.

Routing AI Reference Trigger Signal to an Output Terminal

You can route ai/ReferenceTrigger out to any output PFI <6..9> or RTSI <0..7> terminal.

AI Pause Trigger Signal

You can use the AI Pause Trigger (ai/PauseTrigger) signal to pause and resume a measurement acquisition. The internal sample clock pauses while the external trigger signal is active and resumes when the signal is inactive. You can program the active level of the pause trigger to be high or low.

Using a Digital Source

To use ai/SampleClock, specify a source and a polarity. The source can be any of the following signals:

• Input PFI <0..5>

•RTSI <0..7>

•PXI_STAR

Note Refer to the NI 6238/6239 Specifications for the minimum allowable pulse width and the propagation delay of PFI <0..5>.

The source also can be one of several other internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

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Chapter 4 Analog Input

Routing AI Pause Trigger Signal to an Output Terminal

You can route ai/PauseTrigger out to RTSI <0..7>.

Note Pause triggers are only sensitive to the level of the source, not the edge.

Getting Started with AI Applications in Software

You can use the M Series device in the following analog input applications.

• Single-point analog input

• Finite analog input

• Continuous analog input

You can perform these applications through DMA, interrupt, or programmed I/O data transfer mechanisms. Some of the applications also use start, reference, and pause triggers.

Note For more information about programming analog input applications and triggers in software, refer to the NI-DAQmx Help or the LabVIEW 8.x Help.

Analog Output

NI 6238/6239 devices have two AO channels controlled by a single clock and capable of waveform generation. Figure 5-1 shows the analog current output circuitry of NI 6238 and NI 6239 devices.

V-I Converter

AO POWER SUPPLY

AO 0

V-I Converter

AO 1

AO GND

Figure 5-1. NI 6238/6239 Analog Current Output Circuitry

Analog Output Circuitry

DACs

Digital-to-analog converters (DACs) convert digital codes to analog voltages.

DAC0

DAC1

Isolation

Barrier

Digital

Isolators

AO FIFO

AO Sample Cloc

V-I Converter

The V-I converter converts voltage (V) into current (I).

AO FIFO

The AO FIFO enables analog output waveform generation. It is a first-in-first-out (FIFO) memory buffer between the computer and the

Chapter 5 Analog Output

DACs. It allows you to download the points of a waveform to your M Series device without host computer interaction.

AO Sample Clock

The AO Sample Clock signal reads a sample from the DAC FIFO and generates the AO voltage.

Isolation Barrier and Digital Isolators

The digital isolators across the isolation barrier provide a ground break between the isolated analog front end and the earth/chassis/building ground.

Analog Output Data Generation Methods

When performing an analog output operation, you either can perform software-timed or hardware-timed generations. Hardware-timed generations can be non-buffered or buffered.

Software-Timed Generations

With a software-timed generation, software controls the rate at which data is generated. Software sends a separate command to the hardware to initiate each DAC conversion. In NI-DAQmx, software-timed generations are referred to as on-demand timing. Software-timed generations are also referred to as immediate or static operations. They are typically used for writing a single value out, such as a constant DC current.

Hardware-Timed Generations

With a hardware-timed generation, a digital hardware signal controls the rate of the generation. This signal can be generated internally on your device or provided externally.

Hardware-timed generations have several advantages over software-timed acquisitions:

• The time between samples can be much shorter.

• The timing between samples can be deterministic.

• Hardware-timed acquisitions can use hardware triggering.

Hardware-timed operations can be buffered or non-buffered. A buffer is a temporary storage in computer memory for to-be-generated samples.

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Chapter 5 Analog Output

Non-Buffered

In non-buffered acquisitions, data is written directly to the DACs on the device. Typically, hardware-timed, non-buffered operations are used to write single samples with good latency and known time increments between them.

Buffered

In a buffered acquisition, data is moved from a PC buffer to the DAQ device’s onboard FIFO using DMA or interrupts before it is written to the DACs one sample at a time. Buffered acquisitions typically allow for much faster transfer rates than non-buffered acquisitions because data is moved in large blocks, rather than one point at a time.

One property of buffered I/O operations is the sample mode. The sample mode can be either finite or continuous.

Finite sample mode generation refers to the generation of a specific, predetermined number of data samples. After the specified number of samples has been written out, the generation stops.

Continuous generation refers to the generation of an unspecified number of samples. Instead of generating a set number of data samples and stopping, a continuous generation continues until you stop the operation. There are several different methods of continuous generation that control what data is written. These methods are regeneration, FIFO regeneration, and non-regeneration modes.

Regeneration is the repetition of the data that is already in the buffer. Standard regeneration is when data from the PC buffer is continually downloaded to the FIFO to be written out. New data can be written to the PC buffer at any time without disrupting the output.

With FIFO regeneration, the entire buffer is downloaded to the FIFO and regenerated from there. After the data is downloaded, new data cannot be written to the FIFO. To use FIFO regeneration, the entire buffer must fit within the FIFO size. The advantage of using FIFO regeneration is that it does not require communication with the main host memory after the operation is started, thereby preventing any problems that may occur due to excessive bus traffic.

With non-regeneration, old data will not be repeated. New data must be continually written to the buffer. If the program does not write new data to

Chapter 5 Analog Output

the buffer at a fast enough rate to keep up with the generation, the buffer will underflow and cause an error.

Analog Output Triggering

Analog output supports two different triggering actions:

• Start trigger

• Pause trigger

A digital trigger can initiate these actions. NI 6238/6239 devices support digital triggering, but do not support analog triggering. Refer to the AO

Start Trigger Signal and AO Pause Trigger Signal sections for more

information on these triggering actions.

Connecting Analog Current Output Signals

AO <0..1> are the current output signals for AO channels 0 and 1. AO GND is the ground reference for AO <0..1>.

Figure 5-2 shows how to make analog current output connections to the device.

User-

Provided

Powe r

Supply

AO Power Supply Pin

Internal

–

AO GND

Figure 5-2. Analog Current Output Connections

Voltage

Drop

UserProvided Load

User-Provided AO GND

NI 6238/6239

DAC

Tip Internal voltage drop for the NI 6238/6239 devices is a maximum of 3 V relative to the externally supplied voltage.

Caution The maximum output voltages rating of AO signals and input voltage ratings for AO power supply with respect to AO GND and earth/chassis ground are listed in the

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Maximum Working Voltage section of the NI 6238/6239 Specifications. Exceeding the maximum input supply voltage or maximum working voltage of AO signals distorts the measurement results. Exceeding the maximum input supply voltage or maximum working voltage rating also can damage the device and the computer. Exceeding the maximum output voltage can cause injury and harm the user. NI is not liable for any damage or injuries resulting from such signal connections.

Analog Output Timing Signals

Figure 5-3 summarizes all of the timing options provided by the analog output timing engine.

Chapter 5 Analog Output

PFI, RTSI

PXI_STAR

20 MHz Timebase

100 kHz Timebase

PXI_CLK10

NI 6238/6239 devices feature the following AO (waveform generation) timing signals.

• AO Start Trigger Signal

• AO Pause Trigger Signal

• AO Sample Clock Signal

• AO Sample Clock Timebase Signal

AO Start Trigger Signal

Use the AO Start Trigger (ao/StartTrigger) signal to initiate a waveform generation. If you do not use triggers, you can begin a generation with a software command.

ao/Sample

Clock

Timebase

PXI_STAR

Internal Output

Ctr

Programmable

Clock

Divider

Figure 5-3. Analog Output Timing Options

ao/Sample

Clock

Chapter 5 Analog Output

Note Refer to the NI 6238/6239 Specifications for the minimum allowable pulse width and the propagation delay of PFI <0..5>.

Using a Digital Source

To use ao/StartTrigger, specify a source and an edge. The source can be one of the following signals:

• A pulse initiated by host software

• Input PFI <0..5>

•RTSI<0..7>

• ai/ReferenceTrigger

• ai/StartTrigger

•PXI_STAR

The source also can be one of several internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

You also can specify whether the waveform generation begins on the rising edge or falling edge of ao/StartTrigger.

Routing AO Start Trigger Signal to an Output Terminal

You can route ao/StartTrigger out to any output PFI <6..9> or RTSI <0..7> terminal.

The output is an active high pulse.

PFI <0..5> terminals are fixed inputs. PFI <6..9> terminals are fixed outputs.

AO Pause Trigger Signal

Use the AO Pause Trigger signal (ao/PauseTrigger) to mask off samples in a DAQ sequence. That is, when ao/PauseTrigger is active, no samples occur.

ao/PauseTrigger does not stop a sample that is in progress. The pause does not take effect until the beginning of the next sample.

When you generate analog output signals, the generation pauses as soon as the pause trigger is asserted. If the source of your sample clock is the

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Chapter 5 Analog Output

onboard clock, the generation resumes as soon as the pause trigger is deasserted, as shown in Figure 5-4.

Pause Trigger

Sample Clock

Figure 5-4. ao/PauseTrigger with the Onboard Clock Source

If you are using any signal other than the onboard clock as the source of your sample clock, the generation resumes as soon as the pause trigger is deasserted and another edge of the sample clock is received, as shown in Figure 5-5.

Pause Trigger

Sample Clock

Figure 5-5. ao/PauseTrigger with Other Signal Source

Using a Digital Source

To use ao/PauseTrigger, specify a source and a polarity. The source can be one of the following signals:

• Input PFI <0..5>

•RTSI<0..7>

•PXI_STAR

Note Refer to the NI 6238/6239 Specifications for the minimum allowable pulse width and the propagation delay of PFI <0..5>.

The source also can be one of several other internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

Chapter 5 Analog Output

You also can specify whether the samples are paused when ao/PauseTrigger is at a logic high or low level.

Routing AO Pause Trigger Signal to an Output Terminal

You can route ao/PauseTrigger out to RTSI <0..7>.

AO Sample Clock Signal

Use the AO Sample Clock (ao/SampleClock) signal to initiate AO samples. Each sample updates the outputs of all of the DACs. You can specify an internal or external source for ao/SampleClock. You also can specify whether the DAC update begins on the rising edge or falling edge of ao/SampleClock.

Using an Internal Source

One of the following internal signals can drive ao/SampleClock.

• AO Sample Clock Timebase (divided down)

• Counter n Internal Output

A programmable internal counter divides down the AO Sample Clock Timebase signal.

Using an External Source

Use one of the following external signals as the source of ao/SampleClock:

• Input PFI <0..5>

•RTSI<0..7>

•PXI_STAR

Note Refer to the NI 6238/6239 Specifications for the minimum allowable pulse width and the propagation delay of PFI <0..5>.

Routing AO Sample Clock Signal to an Output Terminal

You can route ao/SampleClock (as an active low signal) out to any output PFI <6..9> or RTSI <0..7> terminal.

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Chapter 5 Analog Output

Other Timing Requirements

A counter on your device internally generates ao/SampleClock unless you select some external source. ao/StartTrigger starts the counter and either the software or hardware can stop it after a finite generation completes. When using an internally generated ao/SampleClock, you also can specify a configurable delay from ao/StartTrigger to the first ao/SampleClock pulse. By default, this delay is two ticks of ao/SampleClockTimebase.

Figure 5-6 shows the relationship of ao/SampleClock to ao/StartTrigger.

ao/SampleClockTimebase

ao/StartTrigger

ao/SampleClock

Delay

From

Start

Trigger

Figure 5-6. ao/SampleClock and ao/StartTrigger

AO Sample Clock Timebase Signal

The AO Sample Clock Timebase (ao/SampleClockTimebase) signal is divided down to provide a source for ao/SampleClock.

You can route any of the following signals to be the AO Sample Clock Timebase (ao/SampleClockTimebase) signal:

•20MHzTimebase

• 100 kHz Timebase

•PXI_CLK10

• Input PFI <0..5>

•RTSI<0..7>

•PXI_STAR

Note Refer to the NI 6238/6239 Specifications for the minimum allowable pulse width and the propagation delay of PFI <0..5>.

Chapter 5 Analog Output

ao/SampleClockTimebase is not available as an output on the I/O connector.

You might use ao/SampleClockTimebase if you want to use an external sample clock signal, but need to divide the signal down. If you want to use an external sample clock signal but do not need to divide the signal, then you should use ao/SampleClock rather than ao/SampleClockTimebase.

Getting Started with AO Applications in Software

You can use an M Series device in the following analog output applications.

• Single-point (on-demand) generation

• Finite generation

• Continuous generation

• Waveform generation

You can perform these generations through programmed I/O, interrupt, or DMA data transfer mechanisms. Some of the applications also use start triggers and pause triggers.

Note For more information about programming analog output applications and triggers in software, refer to the NI-DAQmx Help or the LabVIEW 8.x Help.

NI 6238/6239 User Manual 5-10 ni.com

Digital Input and Output

NI 6238/6239 devices have six static digital input lines, P0.<0..5>. These lines also can be used as PFI inputs.

In addition, the NI 6238/6239 devices have four static digital output lines, P1.<0..3>. These lines also can be used as PFI output.

The voltage input and output levels and the current drive level of the DI and DO lines are listed in the NI 6238/6239 Specifications. Refer to Chapter 8,

PFI, for more information on PFI inputs and outputs.

I/O Protection

Each DI, DO, and PFI signal is protected against overvoltage and undervoltage conditions as well as ESD events on NI 6238/6239 devices. Consult the device specifications for details. However, you should avoid these fault conditions by following these guidelines.

•Do not connect any digital output line to any external signal source, ground signal, or power supply.

• Understand the current requirements of the load connected to the digital output lines. Do not exceed the specified current output limits of the digital outputs. NI has several signal conditioning solutions for digital applications requiring high current drive.

•Do not drive the digital input lines with voltages or current outside of its normal operating range.

• Treat the DAQ device as you would treat any static sensitive device. Always properly ground yourself and the equipment when handling the DAQ device or connecting to it.

Programmable Power-Up States

By default, the digital output lines (P1.<0..3>/PFI <6..9>) are set to 0. They can be programmed to power up as 0 or 1.

Refer to the NI-DAQmx Help or the LabVIEW 8.x Help for more information about setting power-up states in NI-DAQmx or MAX.

Chapter 6 Digital Input and Output

Connecting Digital I/O Signals

The DI signals P0.<0..5> are referenced to P0.GND and DO signals P1.<0..3> are referenced to P1.GND.

Figures 6-1 and 6-2 show P0.<0..5> and P1.<0..3> on the NI 6238 and the NI 6239 device, respectively. Digital input and output signals can range from 0 to 30 V. Refer to the NI 6238/6239 Specifications for more information.

P1.VCC

P1.0

P1.<0..3>

P1.1

P1.GND

Digital

Isolators

P1.GND

P0.0

P0.GND

Figure 6-1. NI 6238 Digital I/O Connections (DO Source)

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P1.VCC

Chapter 6 Digital Input and Output

P1.0

P1.GND

P1.1

P1.GND

P0.0

P0.GND

Buffer

P1.<0..3>

Digital

Isolators

P1.GND

P0.GND

Figure 6-2. NI 6239 Digital I/O Connections (DO Sink)

Caution Exceeding the maximum input voltage or maximum working voltage ratings,

which are listed in the NI 6238/6239 Specifications, can damage the DAQ device and the computer. NI is not liable for any damage resulting from such signal connections.

Logic Conventions

With NI 6238/6239 devices, logic “0” means that the Darlington output switch is open, while logic “1” means closed. Table 6-1 summarizes the expected behavior.

Chapter 6 Digital Input and Output

Table 6-1. NI 6238/6239 Logic Conventions

Logic

Device

NI 6238 (Source) P1.GND P1.VCC

NI 6239 (Sink) P1.VCC P1.GND

0 1

Getting Started with DIO Applications in Software

You can use NI 6238/6239 devices in the following digital I/O applications:

• Static digital input

• Static digital output

Note For more information about programming digital I/O applications and triggers in software, refer to the NI-DAQmx Help or the LabVIEW 8.x Help.

NI 6238/6239 User Manual 6-4 ni.com

Counters

Caution When making measurements, take into account the minimum pulse width and

time delay of the digital input and output lines. Refer to the NI 6238/6239 Specifications for more information.

NI 6238/6239 devices have two general-purpose 32-bit counter/timers and one frequency generator, as shown in Figure 7-1. The general-purpose counter/timers can be used for many measurement and pulse generation applications.

Chapter 7 Counters

Input Selection Muxes

Counter 0

Counter 0 Source (Counter 0 Timebase)

Counter 0 Gate

Counter 0 Aux

Counter 0 HW Arm

Counter 0 A

Counter 0 B (Counter 0 Up_Down)

Counter 0 Z

Counter 1 Source (Counter 1 Timebase)

Counter 1 Gate

Counter 1 Aux

Counter 1 HW Arm

Counter 1 A

Counter 1 B (Counter 1 Up_Down)

Counter 1 Z

Counter 0 Internal Output

Counter 0 TC

Counter 1

Counter 0 Internal Output

Counter 0 TC

Input Selection Muxes

Frequency Output Timebase Freq Out

Frequency Generator

Figure 7-1. M Series Counters

The counters have seven input signals, although in most applications only a few inputs are used.

For information on connecting counter signals, refer to the Default Counter

Terminals section.

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Counter Input Applications

Counting Edges

In edge counting applications, the counter counts edges on its Source after the counter is armed. You can configure the counter to count rising or falling edges on its Source input. You also can control the direction of counting (up or down).

The counter values can be read on demand or with a sample clock.

Single Point (On-Demand) Edge Counting

With single point (on-demand) edge counting, the counter counts the number of edges on the Source input after the counter is armed. On-demand refers to the fact that software can read the counter contents at any time without disturbing the counting process. Figure 7-2 shows an example of single point edge counting.

Chapter 7 Counters

Counter Armed

SOURCE

Counter Value 105432

Figure 7-2. Single Point (On-Demand) Edge Counting

You also can use a pause trigger to pause (or gate) the counter. When the pause trigger is active, the counter ignores edges on its Source input. When the pause trigger is inactive, the counter counts edges normally.

You can route the pause trigger to the Gate input of the counter. You can configure the counter to pause counting when the pause trigger is high or when it is low. Figure 7-3 shows an example of on-demand edge counting with a pause trigger.

Chapter 7 Counters

Counter Armed

Pause Trigger

(Pause When Low)

SOURCE

Counter Value

100 5432

Figure 7-3. Single Point (On-Demand) Edge Counting with Pause Trigger

Buffered (Sample Clock) Edge Counting

With buffered edge counting (edge counting using a sample clock), the counter counts the number of edges on the Source input after the counter is armed. The value of the counter is sampled on each active edge of a sample clock. A DMA controller transfers the sampled values to host memory.

The count values returned are the cumulative counts since the counter armed event. That is, the sample clock does not reset the counter.

You can route the counter sample clock to the Gate input of the counter. You can configure the counter to sample on the rising or falling edge of the sample clock.

Figure 7-4 shows an example of buffered edge counting. Notice that counting begins when the counter is armed, which occurs before the first active edge on Gate.

Counter Armed

(Sample on Rising Edge)

Sample Clock

SOURCE

Counter Value

Buffer

10763452

3 6

Figure 7-4. Buffered (Sample Clock) Edge Counting

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Non-Cumulative Buffered Edge Counting

Non-cumulative edge counting is similar to buffered (sample clock) edge counting. However, the counter resets after each active edge of the Sample Clock. You can route the Sample Clock to the Gate input of the counter.

Figure 7-5 shows an example of non-cumulative buffered edge counting.

Sample Clock

(Sample on Rising Edge)

SOURCE

Chapter 7 Counters

Counter

Armed

Counter Value

Buffer

Figure 7-5. Non-Cumulative Buffered Edge Counting

1101331222

2232

3 3

Notice that the first count interval begins when the counter is armed, which occurs before the first active edge on Gate.

Notice that if you are using an external signal as the Source, at least one Source pulse should occur between each active edge of the Gate signal. This condition ensures that correct values are returned by the counter. If this condition is not met, consider using duplicate count prevention.

Controlling the Direction of Counting

In edge counting applications, the counter can count up or down. You can configure the counter to do the following.

• Always count up

• Always count down

• Count up when the Counter n B input is high; count down when it is low

For information on connecting counter signals, refer to the Default Counter

Terminals section.

Chapter 7 Counters

Pulse-Width Measurement

In pulse-width measurements, the counter measures the width of a pulse on its Gate input signal. You can configure the counter to measure the width of high pulses or low pulses on the Gate signal.

You can route an internal or external periodic clock signal (with a known period) to the Source input of the counter. The counter counts the number of rising (or falling) edges on the Source signal while the pulse on the Gate signal is active.

You can calculate the pulse width by multiplying the period of the Source signal by the number of edges returned by the counter.

A pulse-width measurement will be accurate even if the counter is armed while a pulse train is in progress. If a counter is armed while the pulse is in the active state, it will wait for the next transition to the active state to begin the measurement.

Single Pulse-Width Measurement

With single pulse-width measurement, the counter counts the number of edges on the Source input while the Gate input remains active. When the Gate input goes inactive, the counter stores the count in a hardware save register and ignores other edges on the Gate and Source inputs. Software then can read the stored count.

Figure 7-6 shows an example of a single pulse-width measurement.

GATE

SOURCE

Counter Value

HW Save Register

Figure 7-6. Single Pulse-Width Measurement

Buffered Pulse-Width Measurement

Buffered pulse-width measurement is similar to single pulse-width measurement, but buffered pulse-width measurement takes measurements over multiple pulses.

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GATE

SOURCE

Chapter 7 Counters

The counter counts the number of edges on the Source input while the Gate input remains active. On each trailing edge of the Gate signal, the counter stores the count in a hardware save register. A DMA controller transfers the stored values to host memory.

Figure 7-7 shows an example of a buffered pulse-width measurement.

Counter Value

Buffer

Note that if you are using an external signal as the Source, at least one Source pulse should occur between each active edge of the Gate signal. This condition ensures that correct values are returned by the counter. If this condition is not met, consider using duplicate count prevention.

For information on connecting counter signals, refer to the Default Counter

Terminals section.

Period Measurement

In period measurements, the counter measures a period on its Gate input signal after the counter is armed. You can configure the counter to measure the period between two rising edges or two falling edges of the Gate input signal.

You can route an internal or external periodic clock signal (with a known period) to the Source input of the counter. The counter counts the number of rising (or falling) edges occurring on the Source input between the two active edges of the Gate signal.

103

Figure 7-7. Buffered Pulse-Width Measurement

212

You can calculate the period of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter.

Chapter 7 Counters

Single Period Measurement

With single period measurement, the counter counts the number of rising (or falling) edges on the Source input occurring between two active edges of the Gate input. On the second active edge of the Gate input, the counter stores the count in a hardware save register and ignores other edges on the Gate and Source inputs. Software then can read the stored count.

Figure 7-8 shows an example of a single period measurement.

GATE

SOURCE

Counter Value

HW Save Register

103

Figure 7-8. Single Period Measurement

Buffered Period Measurement

Buffered period measurement is similar to single period measurement, but buffered period measurement measures multiple periods.

The counter counts the number of rising (or falling) edges on the Source input between each pair of active edges on the Gate input. At the end of each period on the Gate signal, the counter stores the count in a hardware save register. A DMA controller transfers the stored values to host memory.

The counter begins when it is armed. The arm usually occurs in the middle of a period of the Gate input. So the first value stored in the hardware save register does not reflect a full period of the Gate input. In most applications, this first point should be discarded.

Figure 7-9 shows an example of a buffered period measurement.

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GATE

SOURCE

Counter Value

Buffer

Chapter 7 Counters

Counter Armed

112 3

(Discard) (Discard) (Discard)

Figure 7-9. Buffered Period Measurement

2 3

311

2 3 3

For information on connecting counter signals, refer to the Default Counter

Terminals section.

Semi-Period Measurement

In semi-period measurements, the counter measures a semi-period on its Gate input signal after the counter is armed. A semi-period is the time between any two consecutive edges on the Gate input.

You can calculate the semi-period of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter.

Single Semi-Period Measurement

Single semi-period measurement is equivalent to single pulse-width measurement.

Chapter 7 Counters

Buffered Semi-Period Measurement

In buffered semi-period measurement, on each edge of the Gate signal, the counter stores the count in a hardware save register. A DMA controller transfers the stored values to host memory.

The counter begins counting when it is armed. The arm usually occurs between edges on the Gate input. So the first value stored in the hardware save register does not reflect a full semi-period of the Gate input. In most applications, this first point should be discarded.

Figure 7-10 shows an example of a buffered semi-period measurement.

Counter Armed

GATE

SOURCE

For information on connecting counter signals, refer to the Default Counter

Terminals section.

Frequency Measurement

You can use the counters to measure frequency in several different ways. You can choose one of the following methods depending on your application.

Method 1—Measure Low Frequency with One Counter

In this method, you measure one period of your signal using a known timebase. This method is good for low frequency signals.

Counter Value

Buffer

Figure 7-10. Buffered Semi-Period Measurement

12102

2 3

132

3 1

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Chapter 7 Counters

You can route the signal to measure (F1) to the Gate of a counter. You can route a known timebase (Ft) to the Source of the counter. The known timebase can be 80MHzTimebase. For signals that might be slower than

0.02 Hz, use a slower known timebase.

You can configure the counter to measure one period of the gate signal. The frequency of F1 is the inverse of the period. Figure 7-11 illustrates this method.

Interval Measured

Gate

Source

Single Period Measurement

Method 1b—Measure Low Frequency with One Counter (Averaged)

In this method, you measure several periods of your signal using a known timebase. This method is good for low to medium frequency signals.

0.02 Hz, use a slower known timebase.

You can configure the counter to make K + 1 buffered period measurements. Recall that the first period measurement in the buffer should be discarded.

123…

Period of F1 =

Frequency of F1 =

Figure 7-11. Method 1

…

Average the remaining K period measurements to determine the average period of F1. The frequency of F1 is the inverse of the average period. Figure 7-12 illustrates this method.

Chapter 7 Counters

Intervals Measured

…T

Gate

Source

Buffered Period

Measurement

2 ...

1... ...

Average Period of F1 =

Frequency of F1 =

… 1... ...

K × Ft

+ …

Figure 7-12. Method 1b

Method 2—Measure High Frequency with Two Counters

In this method, you measure one pulse of a known width using your signal and derive the frequency of your signal from the result. This method is good for high frequency signals.

In this method, you route a pulse of known duration (T) to the Gate of a counter. You can generate the pulse using a second counter. You also can generate the pulse externally and connect it to a PFI or RTSI terminal. You only need to use one counter if you generate the pulse externally.

Route the signal to measure (F1) to the Source of the counter. Configure the counter for a single pulse-width measurement. Suppose you measure the width of pulse T to be N periods of F1. Then the frequency of F1 is N/T.

Figure 7-13 illustrates this method. Another option would be to measure the width of a known period instead of a known pulse.

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Width of Pulse (T)

Chapter 7 Counters

Pulse

Gate

Source

Pulse-Width

Measurement

12…

Width of

Pulse

Frequency of F1 =

T =

Figure 7-13. Method 2

Method 3—Measure Large Range of Frequencies Using Two Counters

By using two counters, you can accurately measure a signal that might be high or low frequency. This technique is called reciprocal frequency measurement. In this method, you generate a long pulse using the signal to measure. You then measure the long pulse with a known timebase. The M Series device can measure this long pulse more accurately than the faster input signal.

You can route the signal to measure to the Source input of Counter 0, as shown in Figure 7-14. Assume this signal to measure has frequency F1. Configure Counter 0 to generate a single pulse that is the width of N periods of the source input signal.

Chapter 7 Counters

Signal to

Measure (F1)

Signal of Known

Frequency (F2)

CTR_0_SOURCE

(Signal to Measure)

CTR_0_OUT

(CTR_1_GATE)

CTR_1_SOURCE

SOURCE OUT

COUNTER 0

SOURCE

COUNTER 1

GATE

0123…

Interval

to Measure

Figure 7-14. Method 3

OUT

Then route the Counter 0 Internal Output signal to the Gate input of Counter 1. You can route a signal of known frequency (F2) to the Counter 1 Source input. F2 can be 80MHzTimebase. For signals that might be slower than 0.02 Hz, use a slower known timebase. Configure Counter 1 to perform a single pulse-width measurement. Suppose the result is that the pulse width is J periods of the F2 clock.

From Counter 0, the length of the pulse is N/F1. From Counter 1, the length of the same pulse is J/F2. Therefore, the frequency of F1 is given by F1 = F2 * (N/J).

Choosing a Method for Measuring Frequency

The best method to measure frequency depends on several factors including the expected frequency of the signal to measure, the desired accuracy, how many counters are available, and how long the measurement can take.

• Method 1 uses only one counter. It is a good method for many applications. However, the accuracy of the measurement decreases as the frequency increases.

Consider a frequency measurement on a 50 kHz signal using an 80 MHz Timebase. This frequency corresponds to 1600 cycles of the

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Chapter 7 Counters

80 MHz Timebase. Your measurement may return 1600 ±1 cycles depending on the phase of the signal with respect to the timebase. As your frequency becomes larger, this error of ±1 cycle becomes more significant; Table 7-1 illustrates this point.

Table 7-1. Frequency Measurement Method 1

Tas k Equation Example 1 Example 2

Actual Frequency to Measure F1 50 kHz 5MHz

Timebase Frequency Ft 80 MHz 80 MHz

Actual Number of Timebase

Ft/F1 1600 16

Periods

Worst Case Measured Number of

(Ft/F1) – 1 1599 15

Timebase Periods

Measured Frequency Ft F1/(Ft – F1) 50.125 kHz 5.33 MHz

Error [Ft F1/(Ft – F1)] – F1 125 kHz 333 kHz

Error % [Ft/(Ft – F1)] – 1 0.06% 6.67%

• Method 1b (measuring K periods of F1) improves the accuracy of the measurement. A disadvantage of Method 1b is that you have to take K + 1 measurements. These measurements take more time and consume some of the available PCI or PXI bandwidth.

• Method 2 is accurate for high frequency signals. However, the accuracy decreases as the frequency of the signal to measure decreases. At very low frequencies, Method 2 may be too inaccurate for your application. Another disadvantage of Method 2 is that it requires two counters (if you cannot provide an external signal of known width). An advantage of Method 2 is that the measurement completes in a known amount of time.

• Method 3 measures high and low frequency signals accurately. However, it requires two counters.

Table 7-2 summarizes some of the differences in methods of measuring frequency.

Chapter 7 Counters

Table 7-2. Frequency Measurement Method Comparison

Number of

Method

1 1 1 Poor Good

1b 1 Many Fair Good

2 1 or 2 1 Good Poor

3 2 1 Good Good

Counters Used

For information on connecting counter signals, refer to the Default Counter

Terminals section.

Position Measurement

You can use the counters to perform position measurements with quadrature encoders or two-pulse encoders. You can measure angular position with X1, X2, and X4 angular encoders. Linear position can be measured with two-pulse encoders. You can choose to do either a single point (on-demand) position measurement or a buffered (sample clock) position measurement. You must arm a counter to begin position measurements.

Number of

Measurements

Returned

Measures High

Frequency

Signals

Accurately

Measures Low

Frequency

Signals

Accurately

Measurements Using Quadrature Encoders

The counters can perform measurements of quadrature encoders that use X1, X2, or X4 encoding.

A quadrature encoder can have up to three channels—channels A, B, and Z.

X1 Encoding

When channel A leads channel B in a quadrature cycle, the counter increments. When channel B leads channel A in a quadrature cycle, the counter decrements. The amount of increments and decrements per cycle depends on the type of encoding—X1, X2, or X4.

Figure 7-15 shows a quadrature cycle and the resulting increments and decrements for X1 encoding. When channel A leads channel B, the increment occurs on the rising edge of channel A. When channel B leads channel A, the decrement occurs on the falling edge of channel A.

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Ch A Ch B

Chapter 7 Counters

Counter Value

Figure 7-15. X1 Encoding

X2 Encoding

The same behavior holds for X2 encoding except the counter increments or decrements on each edge of channel A, depending on which channel leads the other. Each cycle results in two increments or decrements, as shown in Figure 7-16.

Ch A Ch B

Counter Value

56 8

Figure 7-16. X2 Encoding

X4 Encoding

Similarly, the counter increments or decrements on each edge of channels A and B for X4 encoding. Whether the counter increments or decrements depends on which channel leads the other. Each cycle results in four increments or decrements, as shown in Figure 7-17.

Ch A

Ch B

Counter Value 5 6 8 9 10 1011 1112 1213 137

56879

Figure 7-17. X4 Encoding

Channel Z Behavior

Some quadrature encoders have a third channel, channel Z, which is also referred to as the index channel. A high level on channel Z causes the counter to be reloaded with a specified value in a specified phase of the quadrature cycle. You can program this reload to occur in any one of the four phases in a quadrature cycle.

Chapter 7 Counters

Channel Z behavior—when it goes high and how long it stays high—differs with quadrature encoder designs. You must refer to the documentation for your quadrature encoder to obtain timing of channel Z with respect to channels A and B. You must then ensure that channel Z is high during at least a portion of the phase you specify for reload. For instance, in Figure 7-18, channel Z is never high when channel A is high and channel B is low. Thus, the reload must occur in some other phase.

In Figure 7-18, the reload phase is when both channel A and channel B are low. The reload occurs when this phase is true and channel Z is high. Incrementing and decrementing takes priority over reloading. Thus, when the channel B goes low to enter the reload phase, the increment occurs first. The reload occurs within one maximum timebase period after the reload phase becomes true. After the reload occurs, the counter continues to count as before. Figure 7-18 channel Z reload with X4 decoding.

Ch A Ch B Ch Z

Max Timebase

Counter Value

Figure 7-18. Channel Z Reload with X4 Decoding

890 21743

A = 0 B = 0 Z = 1

Measurements Using Two Pulse Encoders

The counter supports two pulse encoders that have two channels—channels A and B.

The counter increments on each rising edge of channel A. The counter decrements on each rising edge of channel B, as shown in Figure 7-19.

Ch A

Ch B

Counter Value 2 3 54344

Figure 7-19. Measurements Using Two Pulse Encoders

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For information on connecting counter signals, refer to the Default Counter

Terminals section.

Two-Signal Edge-Separation Measurement

Two-signal edge-separation measurement is similar to pulse-width measurement, except that there are two measurement signals—Aux and Gate. An active edge on the Aux input starts the counting and an active edge on the Gate input stops the counting. You must arm a counter to begin a two edge separation measurement.

After the counter has been armed and an active edge occurs on the Aux input, the counter counts the number of rising (or falling) edges on the Source. The counter ignores additional edges on the Aux input.

The counter stops counting upon receiving an active edge on the Gate input. The counter stores the count in a hardware save register.

You can configure the rising or falling edge of the Aux input to be the active edge. You can configure the rising or falling edge of the Gate input to be the active edge.

Use this type of measurement to count events or measure the time that occurs between edges on two signals. This type of measurement is sometimes referred to as start/stop trigger measurement, second gate measurement, or A-to-B measurement.

Chapter 7 Counters

Single Two-Signal Edge-Separation Measurement

With single two-signal edge-separation measurement, the counter counts the number of rising (or falling) edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal. The counter then stores the count in a hardware save register and ignores other edges on its inputs. Software then can read the stored count.

Figure 7-20 shows an example of a single two-signal edge-separation measurement.

Chapter 7 Counters

Counter

AUX

GATE

SOURCE

Counter Value

HW Save Register

Armed

0000123456788 8

Measured Interval

Figure 7-20. Single Two-Signal Edge-Separation Measurement

Buffered Two-Signal Edge-Separation Measurement

Buffered and single two-signal edge-separation measurements are similar, but buffered measurement measures multiple intervals.

The counter counts the number of rising (or falling) edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal. The counter then stores the count in a hardware save register. On the next active edge of the Gate signal, the counter begins another measurement. A DMA controller transfers the stored values to host memory.

Figure 7-21 shows an example of a buffered two-signal edge-separation measurement.

AUX

GATE

SOURCE

Counter Value

Buffer

123 123 123

3333

3 3

Figure 7-21. Buffered Two-Signal Edge-Separation Measurement

For information on connecting counter signals, refer to the Default Counter

Terminals section.

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Counter Output Applications

Simple Pulse Generation

Single Pulse Generation

The counter can output a single pulse. The pulse appears on the Counter n Internal Output signal of the counter.

You can specify a delay from when the counter is armed to the beginning of the pulse. The delay is measured in terms of a number of active edges of the Source input.

You can specify a pulse width. The pulse width is also measured in terms of a number of active edges of the Source input. You also can specify the active edge of the Source input (rising or falling).

Figure 7-22 shows a generation of a pulse with a pulse delay of four and a pulse width of three (using the rising edge of Source).

Counter Armed

Chapter 7 Counters

SOURCE

OUT

Figure 7-22. Single Pulse Generation

Single Pulse Generation with Start Trigger

The counter can output a single pulse in response to one pulse on a hardware Start Trigger signal. The pulse appears on the Counter n Internal Output signal of the counter.

You can route the Start Trigger signal to the Gate input of the counter. You can specify a delay from the Start Trigger to the beginning of the pulse. You also can specify the pulse width. The delay and pulse width are measured in terms of a number of active edges of the Source input.

After the Start Trigger signal pulses once, the counter ignores the Gate input.

Figure 7-23 shows a generation of a pulse with a pulse delay of four and a pulse width of three (using the rising edge of Source).

Chapter 7 Counters

GATE

(Start Trigger)

SOURCE

OUT

Figure 7-23. Single Pulse Generation with Start Trigger

Retriggerable Single Pulse Generation

The counter can output a single pulse in response to each pulse on a hardware Start Trigger signal. The pulses appear on the Counter n Internal Output signal of the counter.

You can route the Start Trigger signal to the Gate input of the counter. You can specify a delay from the Start Trigger to the beginning of each pulse. You also can specify the pulse width. The delay and pulse width are measured in terms of a number of active edges of the Source input.

The counter ignores the Gate input while a pulse generation is in progress. After the pulse generation is finished, the counter waits for another Start Trigger signal to begin another pulse generation.

Figure 7-24 shows a generation of two pulses with a pulse delay of five and a pulse width of three (using the rising edge of Source).

GATE

(Start Trigger)

SOURCE

OUT

Figure 7-24. Retriggerable Single Pulse Generation

For information on connecting counter signals, refer to the Default Counter

Terminals section.

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Pulse Train Generation

Continuous Pulse Train Generation

This function generates a train of pulses with programmable frequency and duty cycle. The pulses appear on the Counter n Internal Output signal of the counter.

You can specify a delay from when the counter is armed to the beginning of the pulse train. The delay is measured in terms of a number of active edges of the Source input.

You specify the high and low pulse widths of the output signal. The pulse widths are also measured in terms of a number of active edges of the Source input. You also can specify the active edge of the Source input (rising or falling).

The counter can begin the pulse train generation as soon as the counter is armed, or in response to a hardware Start Trigger. You can route the Start Trigger to the Gate input of the counter.

You also can use the Gate input of the counter as a Pause Trigger (if it is not used as a Start Trigger). The counter pauses pulse generation when the Pause Trigger is active.

Chapter 7 Counters

Figure 7-25 shows a continuous pulse train generation (using the rising edge of Source).

SOURCE

OUT

Counter Armed

Figure 7-25. Continuous Pulse Train Generation

Continuous pulse train generation is sometimes called frequency division. If the high and low pulse widths of the output signal are M and N periods, then the frequency of the Counter n Internal Output signal is equal to the frequency of the Source input divided by M + N.

For information on connecting counter signals, refer to the Default Counter

Terminals section.

Chapter 7 Counters

Frequency Generation

You can generate a frequency by using a counter in pulse train generation mode or by using the frequency generator circuit.

Using the Frequency Generator

The frequency generator can output a square wave at many different frequencies. The frequency generator is independent of the two general-purpose 32-bit counter/timer modules on M Series devices.

Figure 7-26 shows a block diagram of the frequency generator.

20 MHz Timebase

100 kHz Timebase

÷ 2

Frequency

Output

Timebase

Frequency Generator

Divisor

(1–16)

Figure 7-26. Frequency Generator Block Diagram

Freq Out

The frequency generator generates the Frequency Output signal. The Frequency Output signal is the Frequency Output Timebase divided by a number you select from 1 to 16. The Frequency Output Timebase can be either the 20 MHz Timebase divided by 2 or the 100 kHz Timebase.

The duty cycle of Frequency Output is 50% if the divider is either 1 or an even number. For an odd divider, suppose the divider is set to D. In this case, Frequency Output is low for (D + 1)/2 cycles and high for (D – 1)/2 cycles of the Frequency Output Timebase.

Figure 7-27 shows the output waveform of the frequency generator when the divider is set to 5.

Frequency Output Timebase

Freq Out (Divisor = 5)

Figure 7-27. Frequency Generator Output Waveform

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Frequency Output can be routed out to any output PFI <6..9> or RTSI <0..7> terminal. All PFI terminals are set to high-impedance at startup.

In software, program the frequency generator as you would program one of the counters for pulse train generation.

For information on connecting counter signals, refer to the Default Counter

Terminals section.

Frequency Division

The counters can generate a signal with a frequency that is a fraction of an input signal. This function is equivalent to continuous pulse train generation.

For information on connecting counter signals, refer to the Default Counter

Terminals section.

Pulse Generation for ETS

In this application, the counter produces a pulse on the output a specified delay after an active edge on Gate. After each active edge on Gate, the counter cumulatively increments the delay between the Gate and the pulse on the output by a specified amount. Thus, the delay between the Gate and the pulse produced successively increases.

Chapter 7 Counters

Note ETS = Equivalent Time Sampling.

The increase in the delay value can be between 0 and 255. For instance, if you specify the increment to be 10, the delay between the active Gate edge and the pulse on the output will increase by 10 every time a new pulse is generated.

Suppose you program your counter to generate pulses with a delay of 100 and pulse width of 200 each time it receives a trigger. Furthermore, suppose you specify the delay increment to be 10. On the first trigger, your pulse delay will be 100, on the second it will be 110, on the third it will be 120; the process will repeat in this manner until the counter is disarmed. The counter ignores any Gate edge that is received while the pulse triggered by the previous Gate edge is in progress.

The waveform thus produced at the counter’s output can be used to provide timing for undersampling applications where a digitizing system can sample repetitive waveforms that are higher in frequency than the Nyquist

Chapter 7 Counters

frequency of the system. Figure 7-28 shows an example of pulse generation for ETS; the delay from the trigger to the pulse increases after each subsequent Gate active edge.

GATE

OUT

For information on connecting counter signals, refer to the Default Counter

Terminals section.

Counter Timing Signals

M Series devices feature the following counter timing signals.

• Counter n Source

• Counter n Gate

• Counter n Aux

• Counter n A

• Counter n B

• Counter n Z

• Counter n Up_Down

• Counter n HW Arm

• Counter n Internal Output

• Counter n TC

•Frequency Output

D1 D2 = D1 + ΔDD3 = D1 + 2ΔD

Figure 7-28. Pulse Generation for ETS

In this section, n refers to either Counter 0 or 1. For example, Counter n Source refers to two signals—Counter 0 Source (the source input to Counter 0) and Counter 1 Source (the source input to Counter 1).

Counter n Source Signal

The selected edge of the Counter n Source signal increments and decrements the counter value depending on the application the counter is

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Chapter 7 Counters

performing. Table 7-3 lists how this terminal is used in various applications.

Table 7-3. Counter Applications and Counter n Source

Application Purpose of Source Terminal

Pulse Generation Counter Timebase

One Counter Time Measurements Counter Timebase

Two Counter Time Measurements Input Terminal

Non-Buffered Edge Counting Input Terminal

Buffered Edge Counting Input Terminal

Two-Edge Separation Counter Timebase

Routing a Signal to Counter n Source

Each counter has independent input selectors for the Counter n Source signal. Any of the following signals can be routed to the Counter n Source input.

•80MHz Timebase

•20MHz Timebase

• 100 kHz Timebase

•RTSI<0..7>

• Input PFI <0..5>

•PXI_CLK10

•PXI_STAR

In addition, Counter 1 TC or Counter 1 Gate can be routed to Counter 0 Source. Counter 0 TC or Counter 0 Gate can be routed to Counter 1 Source.

Some of these options may not be available in some driver software.

Routing Counter n Source to an Output Terminal

You can route Counter n Source out to any output PFI <6..9> or RTSI <0..7> terminal. All PFIs are set to high-impedance at startup.

Chapter 7 Counters

Counter n Gate Signal

The Counter n Gate signal can perform many different operations depending on the application including starting and stopping the counter, and saving the counter contents.

Routing a Signal to Counter n Gate

Each counter has independent input selectors for the Counter n Gate signal. Any of the following signals can be routed to the Counter n Gate input.

•RTSI<0..7>

• Input PFI <0..5>

• ai/ReferenceTrigger

• ai/StartTrigger

• ai/SampleClock

• ai/ConvertClock

• ao/SampleClock

•PXI_STAR

In addition, Counter 1 Internal Output or Counter 1 Source can be routed to Counter 0 Gate. Counter 0 Internal Output or Counter 0 Source can be routed to Counter 1 Gate.

Some of these options may not be available in some driver software.

Routing Counter n Gate to an Output Terminal

You can route Counter n Gate out to any output PFI <6..9> or RTSI <0..7> terminal. All PFIs are set to high-impedance at startup.

Counter n Aux Signal

The Counter n Aux signal indicates the first edge in a two-signal edge-separation measurement.

Routing a Signal to Counter n Aux

Each counter has independent input selectors for the Counter n Aux signal. Any of the following signals can be routed to the Counter n Aux input.

•RTSI<0..7>

• Input PFI <0..5>

• ai/ReferenceTrigger

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• ai/StartTrigger

•PXI_STAR

In addition, Counter 1 Internal Output, Counter 1 Gate, Counter 1 Source, or Counter 0 Gate can be routed to Counter 0 Aux. Counter 0 Internal Output, Counter 0 Gate, Counter 0 Source, or Counter 1 Gate can be routed to Counter 1 Aux.

Some of these options may not be available in some driver software.

Counter n A, Counter n B, and Counter n Z Signals

Counter n B can control the direction of counting in edge counting applications.

Use the A, B, and Z inputs to each counter when measuring quadrature encoders or measuring two pulse encoders.

Routing Signals to A, B, and Z Counter Inputs

Each counter has independent input selectors for each of the A, B, and Z inputs. Any of the following signals can be routed to each input.

•RTSI<0..7>

• Input PFI <0..5>

•PXI_STAR

Chapter 7 Counters

Routing Counter n Z Signal to an Output Terminal

You can route Counter n Z out to RTSI <0..7>.

Counter n Up_Down Signal

Counter n Up_Down is another name for the Counter n B signal.

Counter n HW Arm Signal

The Counter n HW Arm signal enables a counter to begin an input or output function.

To begin any counter input or output function, you must first enable, or arm, the counter. In some applications, such as buffered semi-period measurement, the counter begins counting when it is armed. In other applications, such as single pulse-width measurement, the counter begins

Chapter 7 Counters

waiting for the Gate signal when it is armed. Counter output operations can use the arm signal in addition to a start trigger.

Software can arm a counter or configure counters to be armed on a hardware signal. Software calls this hardware signal the Arm Start Trigger. Internally, software routes the Arm Start Trigger to the Counter n HW Arm input of the counter.

Routing Signals to Counter n HW Arm Input

Any of the following signals can be routed to the Counter n HW Arm input.

•RTSI<0..7>

• Input PFI <0..5>

• ai/ReferenceTrigger

• ai/StartTrigger

•PXI_STAR

Counter 1 Internal Output can be routed to Counter 0 HW Arm. Counter 0 Internal Output can be routed to Counter 1 HW Arm.

Some of these options may not be available in some driver software.

Counter n Internal Output and Counter n TC Signals

Counter n TC is an internal signal that asserts when the counter value is 0.

The Counter n Internal Output signal changes in response to Counter n TC. The two software-selectable output options are pulse on TC and toggle output polarity on TC. The output polarity is software-selectable for both options.

Routing Counter n Internal Output to an Output Terminal

You can route Counter n Internal Output to any output PFI <6..9> or RTSI <0..7> terminal. All output PFIs are set to high-impedance at startup.

Frequency Output Signal

The Frequency Output (FREQ OUT) signal is the output of the frequency output generator.

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Routing Frequency Output to a Terminal

You can route Frequency Output to any output PFI <6..9> terminal. All PFIs are set to high-impedance at startup.

Default Counter Terminals

By default, NI-DAQmx routes the counter/timer inputs and outputs to the PFI pins, shown in Table 7-4.

Table 7-4. NI 6238/6239 Device Default NI-DAQmx Counter/Timer Pins

Counter/Timer Signal Default Pin Number (Name) Port

CTR 0 SRC 13 (PFI 0) P0.0

CTR 0 GATE 32 (PFI 1) P0.1

CTR 0 AUX 33 (PFI 2) P0.2

CTR 0 OUT 17 (PFI 6) P1.0

CTR 0 A 13 (PFI 0) P0.0

CTR 0 Z 32 (PFI 1) P0.1

CTR 0 B 33 (PFI 2) P0.2

Chapter 7 Counters

CTR 1 SRC 15 (PFI 3) P0.3

CTR 1 GATE 34 (PFI 4) P0.4

CTR 1 AUX 16 (PFI 5) P0.5

CTR 1 OUT 36 (PFI 7) P1.1

CTR 1 A 15 (PFI 3) P0.3

CTR 1 Z 34 (PFI 4) P0.4

CTR 1 B 16 (PFI 5) P0.5

You can use these defaults or select other sources and destinations for the counter/timer signals in NI-DAQmx. Refer to Connecting Counter Signals in the NI-DAQmx Help or the LabVIEW 8.x Help for more information on how to connect your signals for common counter measurements and generations. M Series default PFI lines for counter functions are listed in Physical Channels in the NI-DAQmx Help or the LabVIEW 8.x Help.

Chapter 7 Counters

Counter Triggering

Counters support three different triggering actions—arm start, start, and pause.

Arm Start Trigger

To begin any counter input or output function, you must first enable, or arm, the counter. Software can arm a counter or configure counters to be armed on a hardware signal. Software calls this hardware signal the Arm Start Trigger. Internally, software routes the Arm Start Trigger to the Counter n HW Arm input of the counter.

For counter output operations, you can use it in addition to the start and pause triggers. For counter input operations, you can use the arm start trigger to have start trigger-like behavior. The arm start trigger can be used for synchronizing multiple counter input and output tasks.

Start Trigger

For counter output operations, a start trigger can be configured to begin a finite or continuous pulse generation. After a continuous generation has triggered, the pulses continue to generate until you stop the operation in software. For finite generations, the specified number of pulses is generated and the generation stops unless you use the retriggerable attribute. When you use this attribute, subsequent start triggers cause the generation to restart.

When using a start trigger, the start trigger source is routed to the Counter n Gate signal input of the counter.

Counter input operations can use the arm start trigger to have start trigger-like behavior.

Pause Trigger

You can use pause triggers in edge counting and continuous pulse generation applications. For edge counting acquisitions, the counter stops counting edges while the external trigger signal is low and resumes when the signal goes high or vice versa. For continuous pulse generations, the counter stops generating pulses while the external trigger signal is low and resumes when the signal goes high or vice versa.

When using a pause trigger, the pause trigger source is routed to the Counter n Gate signal input of the counter.

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Other Counter Features

Cascading Counters

You can internally route the Counter n Internal Output and Counter n TC signal of each counter to the Gate inputs of the other counter. By cascading two counters together, you can effectively create a 64-bit counter. By cascading counters, you also can enable other applications. For example, to improve the accuracy of frequency measurements, use reciprocal frequency measurement, as described in the Method 3—Measure Large Range of

Frequencies Using Two Counters section.

Counter Filters

You can enable a programmable debouncing filter on each PFI, RTSI, or PXI_STAR signal. When the filters are enabled, your device samples the input on each rising edge of a filter clock. M Series devices use an onboard oscillator to generate the filter clock with a 40 MHz frequency.

Note NI-DAQmx only supports filters on counter inputs.

Chapter 7 Counters

The following is an example of low-to-high transitions of the input signal. High-to-low transitions work similarly.

Assume that an input terminal has been low for a long time. The input terminal then changes from low-to-high, but glitches several times. When the filter clock has sampled the signal high on N consecutive edges, the low-to-high transition is propagated to the rest of the circuit. The value of N depends on the filter setting; refer to Table 7-5.

Table 7-5. Filters

N (Filter

Clocks Needed

Filter Setting

125 ns 5 125 ns 100 ns

6.425 µs 257 6.425 µs 6.400 µs

2.55 ms ~101,800 2.55 ms 2.54 ms

Disabled — — —

to Pass Signal)

Pulse Width

Guaranteed to

Pass Filter

Pulse Width Guaranteed to Not Pass Filter

Chapter 7 Counters

The filter setting for each input can be configured independently. On power up, the filters are disabled. Figure 7-29 shows an example of a low-to-high transition on an input that has its filter set to 125 ns (N = 5).

RTSI, PFI, or

PXI_STAR Terminal

Filter Clock

(40 MHz)

Filtered Input

Prescaling

Filtered input goes high

1231 4 12345

Figure 7-29. Filter Example

when terminal is sampled high on five consecutive filter clocks.

Enabling filters introduces jitter on the input signal. For the 125 ns and

6.425 µs filter settings, the jitter is up to 25 ns. On the 2.55 ms setting, the jitter is up to 10.025 µs.

When a PFI input is routed directly to RTSI, or a RTSI input is routed directly to PFI, the M Series device does not use the filtered version of the input signal.

Refer to the KnowledgeBase document, Digital Filtering with M Seriesand CompactDAQ, for more information about digital filters and counters. To access this KnowledgeBase, go to

rddfms.

ni.com/info and enter the info code

Prescaling allows the counter to count a signal that is faster than the maximum timebase of the counter. M Series devices offer 8X and 2X prescaling on each counter (prescaling can be disabled). Each prescaler consists of a small, simple counter that counts to eight (or two) and rolls over. This counter can run faster than the larger counters, which simply count the rollovers of this smaller counter. Thus, the prescaler acts as a frequency divider on the Source and puts out a frequency that is one-eighth (or one-half) of what it is accepting.

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External Signal

Prescaler Rollover

(Used as Source

Prescaling is intended to be used for frequency measurement where the measurement is made on a continuous, repetitive signal. The prescaling counter cannot be read; therefore, you cannot determine how many edges have occurred since the previous rollover. Prescaling can be used for event counting provided it is acceptable to have an error of up to seven (or one). Prescaling can be used when the counter Source is an external signal. Prescaling is not available if the counter Source is one of the internal timebases (80MHzTimebase, 20MHzTimebase, or 100kHzTimebase).

Duplicate Count Prevention

Duplicate count prevention (or synchronous counting mode) ensures that a counter returns correct data in applications that use a slow or non-periodic external source. Duplicate count prevention applies only to buffered counter applications such as measuring frequency or period. In such buffered applications, the counter should store the number of times an external Source pulses between rising edges on the Gate signal.

by Counter)

Counter Value

Chapter 7 Counters

Figure 7-30. Prescaling

Example Application That Works Correctly (No Duplicate Counting)

Figure 7-31 shows an external buffered signal as the period measurement Source.

National Instruments NI 6238, NI 6239 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

NI 6238/6239 User Manual

Support

Worldwide Technical Support and Product Information

National Instruments Corporate Headquarters

Worldwide Offices

Important Information

Warranty

Copyright

Trademarks

Patents

WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS

Contents

About This Manual

Conventions

Related Documentation

NI-DAQ

NI-DAQmx for Linux

NI-DAQmx Base

LabVIEW

Measurement Studio

ANSI C without NI Application Software

.NET Languages without NI Application Software

Device Documentation and Specifications

Training Courses

Technical Support on the Web

Installing NI-DAQmx

Installing Other Software

Installing the Hardware

Device Pinouts

Device Specifications

Device Accessories and Cables

DAQ Hardware

Figure 2-1. Components of a Typical DAQ System

DAQ-STC2

Figure 2-2. General NI 6238/6239 Block Diagram

Calibration Circuitry

Sensors and Transducers

Cables and Accessories

Custom Cabling

Programming Devices in Software

I/O Connector Signal Descriptions

Table 3-1. I/O Connector Signals

RTSI Connector Pinout

Analog Input Circuitry

Figure 4-1. NI 6238/6239 Analog Input Circuitry

Analog Input Range

Table 4-1. Input Ranges for NI 6238/6239

Connecting Analog Current Input Signals

Method 1

Method 2

Figure 4-2. Analog Current Input Connection Method 1

Figure 4-3. Analog Current Input Connection Method 2

Figure 4-4. Current Measurement at High Voltage Levels

Analog Input Ground-Reference Settings

Figure 4-5. NI 6238/6239 PGIA

Table 4-2. Signals Routed to the NI-PGIA

Configuring AI Ground-Reference Settings in Software

Figure 4-6. Enabling Multimode Scanning in LabVIEW

Multichannel Scanning Considerations

Use Short High-Quality Cabling

Minimize Current Step between Adjacent Channels

Avoid Scanning Faster Than Necessary

Example 1

Example 2

Analog Input Data Acquisition Methods

Software-Timed Acquisitions

Hardware-Timed Acquisitions

Buffered

Non-Buffered

Analog Input Triggering

Field Wiring Considerations

Analog Input Timing Signals

Figure 4-7. Analog Input Timing Options

Figure 4-8. Interval Sampling

Figure 4-9. Posttriggered Data Acquisition Example

Figure 4-10. Pretriggered Data Acquisition Example