National Instruments NI 6232, NI 6233 User Manual

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DAQ M Series

NI 6232/6233 User Manual

July 2006 371995A-01

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The NI 6232/6233 is warranted against defects in materials and workmanship for a period of three years from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.

The media on which you receive National Instruments software are warranted not to fail to execute programming instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do not execute programming instruc tions if National Instruments receives notice of such defects during the warranty period. National Instruments does not warrant that the operation of the software shall be uninterrupted or error free.

A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work. National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty.

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Compliance

Compliance with FCC/Canada Radio Frequency Interference Regulations

Determining FCC Class

The Federal Communications Commission (FCC) has rules to protect wireless communications from interference. The FCC places digital electronics into two classes. These classes are known as Class A (for use in industrial-commercial locations only) or Class B (for use in residential or commercial locations). All National Instruments (NI) products are FCC Class A products.

Depending on where it is operated, this Class A product could be subject to restrictions in the FCC rules. (In Canada, the Department of Communications (DOC), of Industry Canada, regulates wireless interference in much the same way.) Digital electronics emit weak signals during normal operation that can affect radio, television, or other wireless products.

All Class A products display a simple warning statement of one paragraph in length regarding interference and undesired operation. The FCC rules have restrictions regarding the locations where FCC Class A products can be operated.

Consult the FCC Web site at

FCC/DOC Warnings

This equipment generates and uses radio frequency energy and, if not installed and used in strict accordance with the instructions in this manual and the CE marking Declaration of Conformity*, may cause interference to radio and television reception. Classification requirements are the same for the Federal Communications Commission (FCC) and the Canadian Department of Communications (DOC).

Changes or modifications not expressly approved by NI could void the user’s authority to operate the equipment under the FCC Rules.

Class A

Federal Communications Commission

This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user is required to correct the interference at their own expense.

www.fcc.gov for more information.

Canadian Department of Communications

This Class A digital apparatus meets all requirements of the Canadian Interference-Causing Equipment Regulations. Cet appareil numérique de la classe A respecte toutes les exigences du Règlement sur le matériel brouilleur du Canada.

Compliance with EU Directives

Users in the European Union (EU) should refer to the Declaration of Conformity (DoC) for information* pertaining to the CE marking. Refer to the Declaration of Conformity (DoC) for this product for any additional regulatory compliance information. To obtain the DoC for this product, visit and click the appropriate link in the Certification column.

* The CE marking Declaration of Conformity contains important supplementary information and instructions for the user or

installer.

ni.com/certification, search by model number or product line,

About This Manual

Conventions ...................................................................................................................xv

Related Documentation..................................................................................................xvi

NI-DAQ........................................................................................................... xvi

NI-DAQmx for Linux......................................................................................xvii

NI-DAQmx Base.............................................................................................xvii

LabVIEW ........................................................................................................xvii

LabWindows™/CVI™....................................................................................xviii

Measurement Studio........................................................................................xviii

ANSI C without NI Application Software ......................................................xix

.NET Languages without NI Application Software ........................................xix

Device Documentation and Specifications...................................................... xix

Training Courses ............................................................................................. xix

Technical Support on the Web ........................................................................xix

Chapter 1 Getting Started

Installing NI-DAQmx ....................................................................................................1-1

Installing Other Software...............................................................................................1-1

Installing the Hardware..................................................................................................1-1

Device Pinouts ...............................................................................................................1-1

Device Specifications .................................................................................................... 1-2

Device Accessories and Cables .....................................................................................1-2

Chapter 2 DAQ System Overview

DAQ Hardware ..............................................................................................................2-1

DAQ-STC2......................................................................................................2-2

Calibration Circuitry........................................................................................2-3

Sensors and Transducers................................................................................................2-3

Cables and Accessories..................................................................................................2-4

Custom Cabling ...............................................................................................2-4

Programming Devices in Software ................................................................................2-5

Contents

Chapter 3 Connector Information

I/O Connector Signal Descriptions................................................................................ 3-1

RTSI Connector Pinout ................................................................................................. 3-3

Chapter 4 Analog Input

Analog Input Circuitry .................................................................................................. 4-1

Analog Input Range....................................................................................................... 4-2

Analog Input Ground-Reference Settings ..................................................................... 4-3

Configuring AI Ground-Reference Settings in Software .................4-5

Multichannel Scanning Considerations ......................................................................... 4-6

Use Low Impedance Sources.......................................................................... 4-6

Use Short High-Quality Cabling..................................................................... 4-7

Carefully Choose the Channel Scanning Order ..............................................4-7

Avoid Switching from a Large to a Small Input Range ................... 4-7

Insert Grounded Channel between Signal Channels ........................ 4-8

Minimize Voltage Step between Adjacent Channels ....................... 4-8

Avoid Scanning Faster Than Necessary ......................................................... 4-9

Example 1 ......................................................................................... 4-9

Example 2 ......................................................................................... 4-9

Analog Input Data Acquisition Methods....................................................................... 4-9

Software-Timed Acquisitions ......................................................................... 4-9

Hardware-Timed Acquisitions........................................................................ 4-10

Buffered ............................................................................................ 4-10

Non-Buffered.................................................................................... 4-11

Analog Input Triggering................................................................................................ 4-11

Connecting Analog Voltage Input Signals .................................................................... 4-11

Types of Signal Sources ................................................................................................ 4-12

Floating Signal Sources .................................................................................. 4-13

Ground-Referenced Signal Sources ................................................................ 4-13

Differential Connection Considerations.......................................................... 4-13

Differential Connections for Ground-Referenced Signal Sources.................. 4-14

Differential Input Biasing................................................................. 4-15

Differential Connections for Non-Referenced or Floating Signal Sources .... 4-15

Single-Ended Connection Considerations ...................................................... 4-16

Single-Ended Connections for Floating or

Grounded Signal Sources............................................................... 4-17

Field Wiring Considerations.......................................................................................... 4-18

Analog Input Timing Signals ........................................................................................ 4-19

AI Sample Clock Signal.................................................................................. 4-22

Using an Internal Source .................................................................. 4-23

NI 6232/6233 User Manual viii ni.com

Contents

Using an External Source..................................................................4-23

Routing AI Sample Clock Signal to an Output Terminal.................4-23

Other Timing Requirements..............................................................4-23

AI Sample Clock Timebase Signal..................................................................4-24

AI Convert Clock Signal .................................................................................4-25

Using an Internal Source...................................................................4-25

Using an External Source..................................................................4-26

Routing AI Convert Clock Signal to an Output Terminal ................4-26

Using a Delay from Sample Clock to Convert Clock.......................4-26

Other Timing Requirements..............................................................4-27

AI Convert Clock Timebase Signal.................................................................4-27

AI Hold Complete Event Signal...................................................................... 4-28

AI Start Trigger Signal .................................................................................... 4-28

Using a Digital Source ......................................................................4-28

Routing AI Start Trigger to an Output Terminal .............................. 4-29

AI Reference Trigger Signal ...........................................................................4-29

Using a Digital Source ......................................................................4-30

Routing AI Reference Trigger Signal to an Output Terminal ..........4-30

AI Pause Trigger Signal ..................................................................................4-30

Using a Digital Source ......................................................................4-31

Routing AI Pause Trigger Signal to an Output Terminal .................4-31

Getting Started with AI Applications in Software......................................................... 4-31

Chapter 5 Analog Output

Analog Output Circuitry ................................................................................................ 5-1

Minimizing Glitches on the Output Signal ....................................................................5-2

Analog Output Data Generation Methods .....................................................................5-2

Software-Timed Generations...........................................................................5-2

Hardware-Timed Generations .........................................................................5-3

Non-Buffered ....................................................................................5-3

Buffered ............................................................................................ 5-3

Analog Output Triggering ............................................................................................. 5-4

Connecting Analog Voltage Output Signals.................................................................. 5-4

Analog Output Timing Signals ......................................................................................5-5

AO Start Trigger Signal...................................................................................5-6

Using a Digital Source ......................................................................5-6

Routing AO Start Trigger Signal to an Output Terminal..................5-7

AO Pause Trigger Signal.................................................................................5-7

Using a Digital Source ......................................................................5-8

Routing AO Pause Trigger Signal to an Output Terminal................5-8

Contents

AO Sample Clock Signal ................................................................................ 5-8

Using an Internal Source .................................................................. 5-9

Using an External Source ................................................................. 5-9

Routing AO Sample Clock Signal to an Output Terminal ............... 5-9

Other Timing Requirements ............................................................. 5-9

AO Sample Clock Timebase Signal................................................................ 5-10

Getting Started with AO Applications in Software....................................................... 5-10

Chapter 6 Digital Input and Output

I/O Protection ................................................................................................................ 6-1

Programmable Power-Up States.................................................................................... 6-1

Connecting Digital I/O Signals ..................................................................................... 6-2

Logic Conventions......................................................................................................... 6-3

Getting Started with DIO Applications in Software...................................................... 6-4

Chapter 7 Counters

Counter Input Applications ........................................................................................... 7-3

Counting Edges ............................................................................................... 7-3

Single Point (On-Demand) Edge Counting ...................................... 7-3

Buffered (Sample Clock) Edge Counting......................................... 7-4

Non-Cumulative Buffered Edge Counting ....................................... 7-5

Controlling the Direction of Counting.............................................. 7-5

Pulse-Width Measurement.............................................................................. 7-6

Single Pulse-Width Measurement .................................................... 7-6

Buffered Pulse-Width Measurement ................................................ 7-7

Period Measurement ....................................................................................... 7-7

Single Period Measurement.............................................................. 7-8

Buffered Period Measurement.......................................................... 7-8

Semi-Period Measurement.............................................................................. 7-9

Single Semi-Period Measurement .................................................... 7-9

Buffered Semi-Period Measurement ................................................ 7-10

Frequency Measurement ................................................................................. 7-10

Method 1—Measure Low Frequency with One Counter ................. 7-10

Method 1b—Measure Low Frequency with

One Counter (Averaged)................................................................ 7-11

Method 2—Measure High Frequency with Two Counters .............. 7-12

Method 3—Measure Large Range of Frequencies Using

Two Counters................................................................................. 7-13

Choosing a Method for Measuring Frequency ................................. 7-14

NI 6232/6233 User Manual x ni.com

Contents

Position Measurement ..................................................................................... 7-16

Measurements Using Quadrature Encoders......................................7-16

Measurements Using Two Pulse Encoders.......................................7-18

Two-Signal Edge-Separation Measurement....................................................7-19

Single Two-Signal Edge-Separation Measurement ..........................7-19

Buffered Two-Signal Edge-Separation Measurement ......................7-20

Counter Output Applications ......................................................................................... 7-21

Simple Pulse Generation .................................................................................7-21

Single Pulse Generation .................................................................... 7-21

Single Pulse Generation with Start Trigger ......................................7-21

Retriggerable Single Pulse Generation .............................................7-22

Pulse Train Generation ....................................................................................7-23

Continuous Pulse Train Generation ..................................................7-23

Frequency Generation .....................................................................................7-24

Using the Frequency Generator ........................................................7-24

Frequency Division ......................................................................................... 7-25

Pulse Generation for ETS................................................................................7-25

Counter Timing Signals.................................................................................................7-26

Counter n Source Signal..................................................................................7-27

Routing a Signal to Counter n Source...............................................7-27

Routing Counter n Source to an Output Terminal ............................ 7-28

Counter n Gate Signal ..................................................................................... 7-28

Routing a Signal to Counter n Gate ..................................................7-28

Routing Counter n Gate to an Output Terminal................................ 7-28

Counter n Aux Signal ......................................................................................7-28

Routing a Signal to Counter n Aux................................................... 7-29

Counter n A, Counter n B, and Counter n Z Signals.......................................7-29

Routing Signals to A, B, and Z Counter Inputs ................................ 7-29

Routing Counter n Z Signal to an Output Terminal.......................... 7-29

Counter n Up_Down Signal ............................................................................7-29

Counter n HW Arm Signal ..............................................................................7-30

Routing Signals to Counter n HW Arm Input...................................7-30

Counter n Internal Output and Counter n TC Signals .....................................7-30

Routing Counter n Internal Output to an Output Terminal...............7-31

Frequency Output Signal.................................................................................7-31

Routing Frequency Output to a Terminal .........................................7-31

Default Counter Terminals ............................................................................................7-31

Counter Triggering ........................................................................................................ 7-32

Arm Start Trigger ............................................................................................7-32

Start Trigger..................................................................................................... 7-32

Pause Trigger...................................................................................................7-33

Other Counter Features..................................................................................................7-33

Cascading Counters .........................................................................................7-33

Counter Filters .................................................................................................7-33

Contents

Chapter 8 PFI

Using PFI Terminals as Timing Input Signals .............................................................. 8-2

Exporting Timing Output Signals Using PFI Terminals............................................... 8-3

Using PFI Terminals as Static Digital Inputs and Outputs............................................ 8-3

Connecting PFI Input Signals........................................................................................ 8-3

PFI Filters ...................................................................................................................... 8-4

I/O Protection ................................................................................................................ 8-5

Programmable Power-Up States.................................................................................... 8-6

Connecting Digital I/O Signals ..................................................................................... 8-6

Prescaling ........................................................................................................ 7-34

Duplicate Count Prevention ............................................................................ 7-35

Duplicate Count Prevention Example .............................................. 7-35

Duplicate Count Example.................................................................7-36

Example Application That Prevents Duplicate Count...................... 7-37

When To Use Duplicate Count Prevention ...................................... 7-38

Enabling Duplicate Count Prevention in NI-DAQmx...................... 7-38

Synchronization Modes................................................................................... 7-38

80 MHz Source Mode....................................................................... 7-39

Other Internal Source Mode ............................................................. 7-40

External Source Mode ...................................................................... 7-40

Chapter 9 Isolation and Digital Isolators

Digital Isolation............................................................................................................. 9-2

Benefits of an Isolated DAQ Device ............................................................................. 9-2

Chapter 10 Digital Routing and Clock Generation

Clock Routing................................................................................................................ 10-1

80 MHz Timebase........................................................................................... 10-2

20 MHz Timebase........................................................................................... 10-2

100 kHz Timebase .......................................................................................... 10-2

External Reference Clock ...............................................................................10-2

10 MHz Reference Clock................................................................................ 10-3

Synchronizing Multiple Devices ................................................................................... 10-3

Real-Time System Integration Bus (RTSI) ................................................................... 10-3

RTSI Connector Pinout................................................................................... 10-4

Using RTSI as Outputs ................................................................................... 10-5

NI 6232/6233 User Manual xii ni.com

PXI Clock and Trigger Signals......................................................................................10-8

Chapter 11 Bus Interface

DMA Controllers ...........................................................................................................11-1

PXI Considerations ........................................................................................................11-2

Data Transfer Methods ..................................................................................................11-3

Contents

Using RTSI Terminals as Timing Input Signals .............................................10-6

RTSI Filters ..................................................................................................... 10-6

PXI_CLK10.....................................................................................................10-8

PXI Triggers ....................................................................................................10-8

PXI_STAR Trigger ......................................................................................... 10-8

PXI_STAR Filters ...........................................................................................10-9

PXI Clock and Trigger Signals........................................................................11-2

PXI and PXI Express.......................................................................................11-2

Using PXI with CompactPCI ..........................................................................11-3

Direct Memory Access (DMA) .......................................................................11-3

Interrupt Request (IRQ)...................................................................................11-4

Programmed I/O .............................................................................................. 11-4

Changing Data Transfer Methods between DMA and IRQ ............................11-4

Chapter 12 Triggering

Triggering with a Digital Source ...................................................................................12-1

Appendix A Device-Specific Information

Appendix B Troubleshooting

Appendix C Technical Support and Professional Services

Glossary

Index

About This Manual

The NI 6232/6233 User Manual contains information about using the National Instruments 6232/6233 M Series data acquisition (DAQ) devices with NI-DAQmx 8.0 and later. NI 6232/6233 devices feature eight analog input (AI) channels, four analog output (AO) channels, two counters, six lines of digital input (DI), and four lines of digital output (DO).

Conventions

The following conventions are used in this manual:

<> Angle brackets that contain numbers separated by an ellipsis represent

a range of values associated with a bit or signal name—for example, AO <3..0>.

[ ] Square brackets enclose optional items—for example, [

» The » symbol leads you through nested menu items and dialog box options

to a final action. The sequence File»Page Setup»Options directs you to pull down the File menu, select the Page Setup item, and select Options from the last dialog box.

This icon denotes a note, which alerts you to important information.

This icon denotes a caution, which advises you of precautions to take to avoid injury, data loss, or a system crash. When this symbol is marked on a product, refer to the NI 6232/6233 Specifcations for information about precautions to take.

When symbol is marked on a product, it denotes a warning advising you to take precautions to avoid electrical shock.

When symbol is marked on a product, it denotes a component that may be hot. Touching this component may result in bodily injury.

bold Bold text denotes items that you must select or click in the software, such

as menu items and dialog box options. Bold text also denotes parameter names.

italic Italic text denotes variables, emphasis, a cross-reference, or an introduction

to a key concept. Italic text also denotes text that is a placeholder for a word or value that you must supply.

response].

About This Manual

monospace Text in this font denotes text or characters that you should enter from the

keyboard, sections of code, programming examples, and syntax examples. This font is also used for the proper names of disk drives, paths, directories, programs, subprograms, subroutines, device names, functions, operations, variables, filenames, and extensions.

Installing NI-DAQmx

The DAQ Getting Started Guide, which you can download at

ni.com/manuals, offers NI-DAQmx users step-by-step instructions for

installing software and hardware, configuring channels and tasks, and getting started developing an application.

Installing Other Software

If you are using other software, refer to the installation instructions that accompany your software.

Installing the Hardware

The DAQ Getting Started Guide contains non-software-specific information on how to install PCI and PXI devices, as well as accessories and cables.

Device Pinouts

Refer to Appendix A, Device-Specific Information, for the NI 6232/6233 device pinout.

Chapter 1 Getting Started

Device Specifications

Refer to the NI 6232/6233 Specifications, available on the NI-DAQ Device Document Browser or on the NI 6232/6233 device.

ni.com/manuals, for more detailed information

Device Accessories and Cables

NI offers a variety of accessories and cables to use with your DAQ device. Refer to Appendix A, Device-Specific Information, or information.

ni.com for more

NI 6232/6233 User Manual 1-2 ni.com

DAQ System Overview

Figure 2-1 shows a typical DAQ system, which includes sensors, transducers, cables that connect the various devices to the accessories, the M Series device, programming software, and a PC. The following sections cover the components of a typical DAQ system.

Sensors and

Transducers

DAQ Hardware

Cables and

Accessories

DAQ hardware digitizes signals, performs D/A conversions to generate analog output signals, and measures and controls digital I/O signals. Figure 2-2 features the components of the NI 6232/6233 device.

DAQ

Hardware

Figure 2-1. Components of a Typical DAQ System

DAQ

Software

Personal

Computer

Chapter 2 DAQ System Overview

Analog Input

Analog Output

I/O Connector

Counters

PFI/Static DI

AI GND

AO GND

P0.GND

Isolation

Barrier

Digital

Isolators

Routing

and Clock

Generation

RTSI

Bus

Interface

Bus

DAQ-STC2

PFI/Static DO

P1.GND

Figure 2-2. General NI 6232/6233 Block Diagram

The DAQ-STC2 implements a high-performance digital engine for NI 6232/6233 data acquisition hardware. Some key features of this engine include the following:

• Flexible AI and AO sample and convert timing

• Many triggering modes

• Independent AI and AO FIFOs

• Generation and routing of RTSI signals for multi-device synchronization

• Generation and routing of internal and external timing signals

• Two flexible 32-bit counter/timer modules with hardware gating

• Static DIO signals

• PLL for clock synchronization

• PCI/PXI interface

• Independent scatter-gather DMA controllers for all acquisition and generation functions

NI 6232/6233 User Manual 2-2 ni.com

Calibration Circuitry

The M Series analog inputs and outputs have calibration circuitry to correct gain and offset errors. You can calibrate the device to minimize AI and AO errors caused by time and temperature drift at run time. No external circuitry is necessary; an internal reference ensures high accuracy and stability over time and temperature changes.

Factory-calibration constants are permanently stored in an onboard EEPROM and cannot be modified. When you self-calibrate the device, software stores new constants in a user-modifiable section of the EEPROM. To return a device to its initial factory calibration settings, software can copy the factory-calibration constants to the user-modifiable section of the EEPROM. Refer to the NI-DAQmx Help or the LabVIEW 8.x Help for more information on using calibration constants.

Sensors and Transducers

Sensors can generate electrical signals to measure physical phenomena, such as temperature, force, sound, or light. Some commonly used sensors are strain gauges, thermocouples, thermistors, angular encoders, linear encoders, and resistance temperature detectors (RTDs).

Chapter 2 DAQ System Overview

To measure signals from these various transducers, you must convert them into a form that a DAQ device can accept. For example, the output voltage of most thermocouples is very small and susceptible to noise. Therefore, you may need to amplify or filter the thermocouple output before digitizing it, or use the smallest measurement range available within the DAQ device.

For more information about sensors, refer to the following documents.

• For general information about sensors, visit

• If you are using LabVIEW, refer to the LabVIEW Help by selecting

Help»Search the LabVIEW Help in LabVIEW, and then navigate to the Taking Measurements book on the Contents tab.

• If you are using other application software, refer to Common Sensors in the NI-DAQmx Help, which can be accessed from Start»All Programs»National Instruments»NI-DAQ»NI-DAQmx Help.

ni.com/sensors.

Chapter 2 DAQ System Overview

Cables and Accessories

NI offers a variety of products to use with NI 6232/6233 devices, including cables, connector blocks, and other accessories, as follows:

• Cables and cable assemblies

– Shielded

– Unshielded ribbon

• Screw terminal connector blocks, shielded and unshielded

• RTSI bus cables

Custom Cabling

For more specific information about these products, refer to

Refer to the Custom Cabling section of this chapter, the Field Wiring

Considerations section of Chapter 4, Analog Input, and Appendix A, Device-Specific Information, for information on how to select accessories

for your M Series device.

NI offers cables and accessories for many applications. However, if you want to develop your own cable, the following kits can assist you:

• TB-37F-37SC—37-pin solder cup terminals, shell with strain relief

• TB-37F-37CP—37-pin crimp & poke terminals, shell with strain

relief

Also, adhere to the following guidelines for best results:

• For AI signals, use shielded, twisted-pair wires for each AI pair of differential inputs. Connect the shield for each signal pair to the ground reference at the source.

• Route the analog lines separately from the digital lines.

• When using a cable shield, use separate shields for the analog and digital sections of the cable. Failure to do so results in noise coupling into the analog signals from transient digital signals.

ni.com.

For more information on the connectors used for DAQ devices, refer to the KnowledgeBase document, Specifications and Manufacturers for Board Mating Connectors, by going to

rdspmb.

NI 6232/6233 User Manual 2-4 ni.com

ni.com/info and entering the info code

Programming Devices in Software

National Instruments measurement devices are packaged with NI-DAQ driver software, an extensive library of functions and VIs you can call from your application software, such as LabVIEW or LabWindows/CVI, to program all the features of your NI measurement devices. Driver software has an application programming interface (API), which is a library of VIs, functions, classes, attributes, and properties for creating applications for your device.

NI-DAQ includes two NI-DAQ drivers, Traditional NI-DAQ (Legacy) and NI-DAQmx. M Series devices use the NI-DAQmx driver. Each driver has its own API, hardware configuration, and software configuration. Refer to the DAQ Getting Started Guide for more information about the two drivers.

NI-DAQmx includes a collection of programming examples to help you get started developing an application. You can modify example code and save it in an application. You can use examples to develop a new application or add example code to an existing application.

To locate LabVIEW and LabWindows/CVI examples, open the National Instruments Example Finder.

• In LabVIEW, select Help»Find Examples.

• In LabWindows/CVI, select Help»NI Example Finder.

Chapter 2 DAQ System Overview

Measurement Studio, Visual Basic, and ANSI C examples are located in the following directories:

• NI-DAQmx examples for Measurement Studio-supported languages are in the following directories:

–

MeasurementStudio\VCNET\Examples\NIDaq

– MeasurementStudio\DotNET\Examples\NIDaq

• NI-DAQmx examples for ANSI C are in the

NI-DAQ\Examples\DAQmx ANSI C Dev directory

For additional examples, refer to

zone.ni.com.

Connector Information

The I/O Connector Signal Descriptions and RTSI Connector Pinout sections contain information on M Series connectors. Refer to Appendix A, Device-Specific Information, for device I/O connector pinouts.

I/O Connector Signal Descriptions

Table 3-1 describes the signals found on the I/O connectors. Not all signals are available on all devices.

Table 3-1. I/O Connector Signals

Signal Name Reference Direction Description

AI GND — — Analog Input Ground—These terminals are the input bias

current return point. AI GND and AO GND are connected on the device.

Note: AI GND and AO GND are isolated from earth ground, chassis ground, P0.GND, and P1.GND.

AI <0..15> AI GND Input Analog Input Channels 0 to 15—For single-ended

measurements, each signal is an analog input voltage channel. In RSE mode, AI GND is the reference for these signals.

For differential measurements, AI 0 and AI 8 are the positive and negative inputs of differential analog input channel 0. Similarly, the following signal pairs also form differential input channels:

<AI1,AI9>, <AI2,AI10>, <AI3,AI11>, <AI4,AI12>, <AI5,AI13>, <AI6,AI14>, <AI7,AI15>

Also refer to the Analog Input Ground-Reference Settings section of Chapter 4, Analog Input.

Note: AI <0..15> are isolated from earth ground and chassis ground.

AO <0..1> AO GND Output Analog Output Channels 0 to 1—These terminals supply the

voltage output of AO channels 0 to 1.

Note: AO <0..1> are isolated from earth ground and chassis ground.

Chapter 3 Connector Information

Table 3-1. I/O Connector Signals (Continued)

Signal Name Reference Direction Description

AO GND — — Analog Output Ground—AO GND is the reference for

AO <0..1>. AI GND and AO GND are connected on the device.

Note: AI GND and AO GND are isolated from earth ground, chassis ground, P0.GND, and P1.GND.

PFI <0..5>/P0.<0..5> P0.GND Input Programmable Function Interface or Static Digital Input

Channels 0 to 5—Each of these terminals can be individually configured as an input directional PFI terminal or a digital input terminal.

As an input, each input PFI terminal can be used to supply an external source for AI or AO timing signals or counter/timer inputs.

Note: PFI <0..5>/P0.<0..5> are isolated from earth ground, chassis ground, AI GND, AO GND, and P1.GND.

PFI <6..9>/P1.<0..3> P1.GND Output Programmable Function Interface or Static Digital

Output Channels 6 to 9—Each of these terminals can be individually configured as an output directional PFI terminal or a digital output terminal.

As a PFI output, you can route many different internal AI or AO timing signals to each PFI terminal. You also can route the counter/timer outputs to each PFI terminal.

Note: PFI <6..9>/P1.<0..3> are isolated from earth ground, chassis ground, AI GND, AO GND, and P0.GND.

NC — — No connect—Do not connect signals to these terminals.

P0.GND — — Digital Input Ground—P0.GND supplies the reference for

input PFI <0..5>/P0.<0..5>.

Note: P0.GND is isolated from earth ground, chassis ground, AI GND, AO GND, and P1.GND.

P1.GND — — Digital Output Ground—P1.GND supplies the reference for

P1.VCC — — Digital Output Power—P1.VCC supplies the power for

NI 6232/6233 User Manual 3-2 ni.com

output PFI <6..9>/P1.<0..3>.

Note: P1.GND is isolated from earth ground, chassis ground, AI GND, AO GND, and P0.GND.

digital output lines. The actual power consumed depends on the load connected between the digital output and P1.GND.

RTSI Connector Pinout

Refer to the RTSI Connector Pinout section of Chapter 10, Digital Routing

and Clock Generation, for information on the RTSI connector.

Chapter 3 Connector Information

Analog Input

Figure 4-1 shows the analog input circuitry of NI 6232/6233 devices.

Isolation

Barrier

AI <0..n>

I/O Connector

AI GND

Mux

DIFF,

RSE,

or NRSE

AI Terminal

Configuration

Selection

NI-PGIA

Input Range

Selection

Analog Input Circuitry

I/O Connector

You can connect analog input signals to the M Series device through the I/O connector. The proper way to connect analog input signals depends on the analog input ground-reference settings, described in the Analog Input

Ground-Reference Settings section. Also refer to Appendix A, Device-Specific Information, for device I/O connector pinouts.

MUX

Each M Series device has one analog-to-digital converter (ADC). The multiplexers (MUX) route one AI channel at a time to the ADC through the NI-PGIA.

ADC

Figure 4-1. NI 6232/6233 Analog Input Circuitry

Digital

Isolators

AI FIFO

AI Data

Chapter 4 Analog Input

Ground-Reference Settings

The analog input ground-reference settings circuitry selects between differential and referenced single-ended modes. Each AI channel can use a different mode.

Instrumentation Amplifier (NI-PGIA)

The NI programmable gain instrumentation amplifier (PGIA) is a measurement and instrument class amplifier that minimizes settling times for all input ranges. The NI-PGIA can amplify or attenuate an AI signal to ensure that you use the maximum resolution of the ADC.

M Series devices use the NI-PGIA to deliver high accuracy even when sampling multiple channels with small input ranges at fast rates. M Series devices can sample channels in any order at the maximum conversion rate, and you can individually program each channel in a sample with a different input range.

A/D Converter

The analog-to-digital converter (ADC) digitizes the AI signal by converting the analog voltage into a digital number.

Isolation Barrier and Digital Isolators

The digital isolators across the isolation barrier provide a ground break between the isolated analog front end and the earth/chassis/building ground.

AI FIFO

M Series devices can perform both single and multiple A/D conversions of a fixed or infinite number of samples. A large first-in-first-out (FIFO) buffer holds data during AI acquisitions to ensure that no data is lost. M Series devices can handle multiple A/D conversion operations with DMA, interrupts, or programmed I/O.

Analog Input Range

Input range refers to the set of input voltages that an analog input channel can digitize with the specified accuracy. The NI-PGIA amplifies or attenuates the AI signal depending on the input range. You can individually program the input range of each AI channel on your M Series device.

The input range affects the resolution of the M Series device for an AI channel. Resolution refers to the voltage of one ADC code. For example, a

NI 6232/6233 User Manual 4-2 ni.com

Chapter 4 Analog Input

16-bit ADC converts analog inputs into one of 65,536 (= 216) codes—that is, one of 65,536 possible digital values. These values are spread fairly evenly across the input range. So, for an input range of –10 V to 10 V, the voltage of each code of a 16-bit ADC is:

(10 V – (–10 V))

M Series devices use a calibration method that requires some codes (typically about 5% of the codes) to lie outside of the specified range. This calibration method improves absolute accuracy, but it increases the nominal resolution of input ranges by about 5% over what the formula shown above would indicate.

Choose an input range that matches the expected input range of your signal. A large input range can accommodate a large signal variation, but reduces the voltage resolution. Choosing a smaller input range improves the voltage resolution, but may result in the input signal going out of range.

For more information on programming these settings, refer to the NI-DAQmx Help or the LabVIEW 8.x Help.

Table 4-1 shows the input ranges and resolutions supported by the NI 6232/6233 device.

Table 4-1. Input Ranges for NI 6232/6233

Input Range

–10 V to 10 V 320 μV

= 305 mV

Nominal Resolution Assuming

5% Over Range

–5 V to 5 V 160 μV

–1 V to 1 V 32 μV

–200 mV to 200 mV 6.4 μV

Analog Input Ground-Reference Settings

NI 6232/6233 devices support the analog input ground-reference settings shown in Table 4-2.

Chapter 4 Analog Input

AI Ground-Reference

Settings

DIFF In differential (DIFF) mode, the NI 6232/6233 device measures the

RSE In referenced single-ended (RSE) mode, the NI 6232/6233 device

NRSE Non-referenced single-ended (NRSE) mode is identical to RSE mode

Table 4-2. Analog Input Ground-Reference Settings

Description

difference in voltage between two AI signals. AI GND is the bias current return point for DIFF mode.

measures the voltage of an AI signal relative to AI GND, which is isolated from earth/chassis ground. The ground reference point is provided by the user through AI GND.

on NI 6232/6233 devices.

The AI ground-reference setting determines how you should connect your AI signals to the NI 6232/6233 device. Refer to the Connecting Analog

Voltage Input Signals section for more information.

Ground-reference settings are programmed on a per-channel basis. For example, you might configure the device to scan five channels—two differentially-configured channels and three single-ended channels.

NI 6232/6233 devices implement the different analog input ground-reference settings by routing different signals to the PGIA. The PGIA is a differential amplifier. That is, the PGIA amplifies (or attenuates) the difference in voltage between its two inputs. The PGIA drives the ADC with this amplified voltage. The amount of amplification (the gain), is determined by the analog input range, as shown in Figure 4-2.

Instrumentation

Amplifier

in+

] × Gain

Measured

Voltage

–

PGIA

in–

Vm = [V

in+

– V

in–

Figure 4-2. PGIA

NI 6232/6233 User Manual 4-4 ni.com

Chapter 4 Analog Input

Table 4-3 shows how signals are routed to the NI-PGIA.

Table 4-3. Signals Routed to the NI-PGIA

AI Ground-Reference

Settings

Signals Routed to the Positive

Input of the NI-PGIA (V

in+

)

Signals Routed to the Negative

Input of the NI-PGIA (V

RSE and NRSE AI <0..15> AI GND

DIFF AI <0..7> AI <8..15>

For differential measurements, AI 0 and AI 8 are the positive and negative inputs of differential analog input channel 0. For a complete list of signal pairs that form differential input channels, refer to the I/O Connector Signal

Descriptions section of Chapter 3, Connector Information.

Caution The maximum input voltages rating of AI signals with respect to AI GND (and for differential signals with respect to each other) and earth/chassis ground are listed in the Maximum Working Voltage section of the NI 6232/6233 Specifications. Exceeding the maximum input voltage or maximum working voltage of AI signals distorts the measurement results. Exceeding the maximum input voltage or maximum working voltage rating also can damage the device and the computer. Exceeding the maximum input voltage can cause injury and harm the user. NI is not liable for any damage or injuries resulting from such signal connections.

AI ground-reference setting is sometimes referred to as AI terminal configuration.

in–

)

Configuring AI Ground-Reference Settings in Software

You can program channels on an M Series device to acquire with different ground references.

To enable multimode scanning in LabVIEW, use

Virtual Channel.vi

of the NI-DAQmx API. You must use a new VI for each channel or group of channels configured in a different input mode. In Figure 4-3, channel 0 is configured in differential mode, and channel 1 is configured in RSE mode.

NI-DAQmx Create

Chapter 4 Analog Input

Figure 4-3. Enabling Multimode Scanning in LabVIEW

Multichannel Scanning Considerations

M Series devices can scan multiple channels at high rates and digitize the signals accurately. However, you should consider several issues when designing your measurement system to ensure the high accuracy of your measurements.

In multichannel scanning applications, accuracy is affected by settling time. When your M Series device switches from one AI channel to another AI channel, the device configures the NI-PGIA with the input range of the new channel. The NI-PGIA then amplifies the input signal with the gain for the new input range. Settling time refers to the time it takes the NI-PGIA to amplify the input signal to the desired accuracy before it is sampled by the ADC. The NI 6232/6233 Specifications shows the device settling time.

M Series devices are designed to have fast settling times. However several factors can increase the settling time which decreases the accuracy of your measurements. To ensure fast settling times, you should do the following (in order of importance):

• Use low impedance sources

• Use short high-quality cabling

• Carefully choose the channel scanning order

• Avoid scanning faster than necessary

Refer to the following sections for more information on these factors.

Use Low Impedance Sources

To ensure fast settling times, your signal sources should have an impedance of <1 kΩ. Large source impedances increase the settling time of the PGIA, and so decrease the accuracy at fast scanning rates.

NI 6232/6233 User Manual 4-6 ni.com

Settling times increase when scanning high-impedance signals due to a phenomenon called charge injection. Multiplexers contain switches, usually made of switched capacitors. When one of the channels, for example channel 0, is selected in a multiplexer, those capacitors accumulate charge. When the next channel, for example channel 1, is selected, the accumulated charge leaks backward through channel 1. If the output impedance of the source connected to channel 1 is high enough, the resulting reading of channel 1 can be partially affected by the voltage on channel 0. This effect is referred to as ghosting.

If your source impedance is high, you can decrease the scan rate to allow the PGIA more time to settle. Another option is to use a voltage follower circuit external to your DAQ device to decrease the impedance seen by the DAQ device. Refer to the KnowledgeBase document, How Do I Create a Buffer to Decrease the Source Impedance of My Analog Input Signal?, by going to

ni.com/info and entering the info code rdbbis.

Use Short High-Quality Cabling

Using short high-quality cables can minimize several effects that degrade accuracy including crosstalk, transmission line effects, and noise. The capacitance of the cable also can increase the settling time.

Chapter 4 Analog Input

National Instruments recommends using individually shielded, twisted-pair wires that are 2 m or less to connect AI signals to the device. Refer to the Connecting Analog Voltage Input Signals section for more information.

Carefully Choose the Channel Scanning Order

Avoid Switching from a Large to a Small Input Range

Switching from a channel with a large input range to a channel with a small input range can greatly increase the settling time.

Suppose a 4 V signal is connected to channel 0 and a 1 mV signal is connected to channel 1. The input range for channel 0 is –10 V to 10 V and the input range of channel 1 is –200 mV to 200 mV.

When the multiplexer switches from channel 0 to channel 1, the input to the PGIA switches from 4 V to 1 mV. The approximately 4 V step from 4 V to 1 mV is 1,000% of the new full-scale range. For a 16-bit device to settle within 0.0015% (15 ppm or 1 LSB) of the ±200 mV full-scale range on channel 1, the input circuitry must settle to within 0.000031% (0.31 ppm or

Chapter 4 Analog Input

1/50 LSB) of the ±10 V range. Some devices can take many microseconds for the circuitry to settle this much.

To avoid this effect, you should arrange your channel scanning order so that transitions from large to small input ranges are infrequent.

In general, you do not need this extra settling time when the PGIA is switching from a small input range to a larger input range.

Insert Grounded Channel between Signal Channels

Another technique to improve settling time is to connect an input channel to ground. Then insert this channel in the scan list between two of your signal channels. The input range of the grounded channel should match the input range of the signal after the grounded channel in the scan list.

Consider again the example above where a 4 V signal is connected to channel 0 and a 1 mV signal is connected to channel 1. Suppose the input range for channel 0 is –10 V to 10 V and the input range of channel 1 is –200mV to 200mV.

You can connect channel 2 to AI GND (or you can use the internal ground signal; refer to Internal Channels in the NI-DAQmx Help or the LabVIEW 8.x Help). Set the input range of channel 2 to –200 mV to 200 mV to match channel 1. Then scan channels in the order: 0, 2, 1.

Inserting a grounded channel between signal channels improves settling time because the NI-PGIA adjusts to the new input range setting faster when the input is grounded.

Minimize Voltage Step between Adjacent Channels

When scanning between channels that have the same input range, the settling time increases with the voltage step between the channels. If you know the expected input range of your signals, you can group signals with similar expected ranges together in your scan list.

For example, suppose all channels in a system use a –5 to 5 V input range. The signals on channels 0, 2, and 4 vary between 4.3 V and 5 V. The signals on channels 1, 3, and 5 vary between –4 V and 0 V. Scanning channels in the order 0, 2, 4, 1, 3, 5 will produce more accurate results than scanning channels in the order 0, 1, 2, 3, 4, 5.

NI 6232/6233 User Manual 4-8 ni.com

Avoid Scanning Faster Than Necessary

Designing your system to scan at slower speeds gives the PGIA more time to settle to a more accurate level. Here are two examples to consider.

Example 1

Averaging many AI samples can increase the accuracy of the reading by decreasing noise effects. In general, the more points you average, the more accurate the final result will be. However, you may choose to decrease the number of points you average and slow down the scanning rate.

Suppose you want to sample 10 channels over a period of 20 ms and average the results. You could acquire 500 points from each channel at a scan rate of 250 kS/s. Another method would be to acquire 1,000 points from each channel at a scan rate of 500 kS/s. Both methods take the same amount of time. Doubling the number of samples averaged (from 500 to 1,000) decreases the effect of noise by a factor of 1.4 (the square root of 2). However, doubling the number of samples (in this example) decreases the time the PGIA has to settle from 4 µs to 2 µs. In some cases, the slower scan rate system returns more accurate results.

Chapter 4 Analog Input

Example 2

If the time relationship between channels is not critical, you can sample from the same channel multiple times and scan less frequently. For example, suppose an application requires averaging 100 points from channel 0 and averaging 100 points from channel 1. You could alternate reading between channels—that is, read one point from channel 0, and then one point from channel 1, and so on. You also could read all 100 points from channel 0 then read 100 points from channel 1. The second method switches between channels much less often and is affected much less by settling time.

Analog Input Data Acquisition Methods

When performing analog input measurements, you either can perform software-timed or hardware-timed acquisitions. Hardware-timed acquisitions can be buffered or non-buffered.

Software-Timed Acquisitions

With a software-timed acquisition, software controls the rate of the acquisition. Software sends a separate command to the hardware to initiate

Chapter 4 Analog Input

each ADC conversion. In NI-DAQmx, software-timed acquisitions are referred to as having on-demand timing. Software-timed acquisitions are also referred to as immediate or static acquisitions and are typically used for reading a single sample of data.

Hardware-Timed Acquisitions

With hardware-timed acquisitions, a digital hardware signal (ai/SampleClock) controls the rate of the acquisition. This signal can be generated internally on your device or provided externally.

Hardware-timed acquisitions have several advantages over software-timed acquisitions.

• The time between samples can be much shorter.

• The timing between samples is deterministic.

• Hardware-timed acquisitions can use hardware triggering.

Hardware-timed operations can be buffered or non-buffered. A buffer is a temporary storage in computer memory for to-be-generated samples.

Buffered

In a buffered acquisition, data is moved from the onboard FIFO memory of a DAQ device to a PC buffer using DMA or interrupts before it is transferred to application memory. Buffered acquisitions typically allow for much faster transfer rates than non-buffered acquisitions because data is moved in large blocks, rather than one point at a time.

One property of buffered I/O operations is the sample mode. The sample mode can be either finite or continuous.

Finite sample mode acquisition refers to the acquisition of a specific, predetermined number of data samples. When the specified number of samples has been written out, the generation stops. If you use a reference trigger, you must use finite sample mode.

Continuous acquisition refers to the acquisition of an unspecified number of samples. Instead of acquiring a set number of data samples and stopping, a continuous acquisition continues until you stop the operation. Continuous acquisition is also referred to as double-buffered or circular-buffered acquisition.

If data cannot be transferred across the bus fast enough, the FIFO will become full. New acquisitions will overwrite data in the FIFO before it can

NI 6232/6233 User Manual 4-10 ni.com

be transferred to host memory. The device generates an error in this case. With continuous operations, if the user program does not read data out of the PC buffer fast enough to keep up with the data transfer, the buffer could reach an overflow condition, causing an error to be generated.

Non-Buffered

In non-buffered acquisitions, data is read directly from the FIFO on the device. Typically, hardware-timed, non-buffered operations are used to read single samples with known time increments between them and good latency.

Analog Input Triggering

Analog input supports three different triggering actions:

• Start trigger

• Reference trigger

• Pause trigger

Refer to the AI Start Trigger Signal, AI Reference Trigger Signal, and AI

Pause Trigger Signal sections for information on these triggers.

Chapter 4 Analog Input

A digital trigger can initiate these actions. NI 6232/6233 devices support digital triggering, but do not support analog triggering.

Connecting Analog Voltage Input Signals

Table 4-4 summarizes the recommended input configuration for both types of signal sources.

Chapter 4 Analog Input

Table 4-4. Analog Input Configuration

Floating Signal Sources (Not

Connected to Building Ground)

Ground-Referenced Signal Sources

Input

Differential (DIFF)

Referenced Single-Ended (RSE)

Examples:

• Ungrounded thermocouples

• Signal conditioning with isolated outputs

• Battery devices

Isolation

AI +

AI –

AI +

AI GND

–

AI GND

–

+ –

Barrier

Isolation

Barrier

Example:

• Plug-in instruments with non-isolated outputs

Isolation

AI +

AI –

AI GND

–

AI GND

–

+ –

Barrier

Isolation

Barrier

Refer to the Analog Input Ground-Reference Settings section for descriptions of DIFF and RSE modes.

Types of Signal Sources

When configuring the input channels and making signal connections, first determine whether the signal sources are floating or ground-referenced. For isolated measurement products, the front ends are isolated from the building ground system, breaking any electrical connection between the

NI 6232/6233 User Manual 4-12 ni.com

two reference planes. Isolated front ends require a ground-reference point to the signal that is being measured.

Floating Signal Sources

A floating signal source is not connected to the building ground system (earth or chassis ground), but has an isolated ground-reference point. Some examples of floating signal sources are outputs of transformers, thermocouples, battery-powered devices, optical isolators, and isolation amplifiers. An instrument or device that has an isolated output is a floating signal source. You must connect the ground reference of a floating signal to the AI ground of the device to establish a local or onboard reference for the signal. Otherwise, the measured input signal varies as the source floats outside the common-mode input range.

Ground-Referenced Signal Sources

A ground-referenced signal source is connected to the building system ground (earth or chassis ground), so you must connect the ground-reference to AI GND to establish a local or onboard reference to the signal. Non-isolated outputs of instruments and devices that plug into the building power system fall into this category.

Chapter 4 Analog Input

The difference in ground potential between an instrument and your PC connected to the same building power system is typically between 1 and 100 mV, but the difference can be much higher if power distribution circuits are improperly connected. If a grounded signal source is incorrectly measured, this difference can appear as measurement error. The NI 6232/6233 isolates the ground of the instrument from the PC to help eliminate this error.

Differential Connection Considerations

A DIFF connection is one in which the AI signal has its own reference signal or signal return path. These connections are available when the selected channel is configured in DIFF input mode. The input signal is connected to the positive input of the PGIA, and its reference signal, or return, is connected to the negative input of the PGIA.

When you configure a channel for DIFF input, each signal uses two multiplexer inputs—one for the signal and one for its reference signal.

Chapter 4 Analog Input

Use DIFF input connections for any channel that meets any of the following conditions:

• The input signal is low level (less than 1 V).

• The leads connecting the signal to the device are greater than 3 m (10 ft).

• The input signal requires a separate ground-reference point or return signal.

• The signal leads travel through noisy environments.

DIFF signal connections reduce noise pickup and increase common-mode noise rejection. DIFF signal connections also allow input signals to float within the common-mode limits of the PGIA.

Differential Connections for Ground-Referenced Signal Sources

Figure 4-4 shows how to connect a ground-referenced signal source to a channel on the device configured in DIFF mode.

AI +

Isolation

Ground-

Referenced

Signal

Source

Common-

Mode

Noise and

Ground

Potential

I/O Connector

–

AI –

–

Input Multiplexers

AI GND

M Series Isolated Device Configured in DIFF Mode

Instrumentation

Amplifier

PGIA

–

Measured

Voltage

–

Barrier

Digital

Isolators

Figure 4-4. Differential Connections for Ground-Referenced Signal Sources

NI 6232/6233 User Manual 4-14 ni.com

Chapter 4 Analog Input

With this type of connection, the PGIA rejects both the common-mode noise in the signal and the ground potential difference between the signal source and the device ground, shown as V NI 6232/6233 Specifications for the usable range of V

in the figure. Refer to the

Common-Mode Signal Rejection Considerations

For signal sources that are already referenced to some ground point with respect to the device, the PGIA can reject any voltage caused by ground potential differences between the signal source and the device. In addition, with DIFF input connections, the PGIA can reject common-mode noise pickup in the leads connecting the signal sources to the device. The PGIA can reject common-mode signals as long as AI+ and AI– (input signals) are both within ±11 V of AI GND.

Differential Input Biasing

Figure 4-4 shows AI GND connected to the negative lead of the signal source. If you do not connect AI GND, the source is not likely to remain within the common-mode signal range of the PGIA due to the floating source or the isolation barrier. The PGIA then saturates, causing erroneous readings.

You must reference the source to AI GND. The easiest way to make this reference is to connect the positive side of the signal to the positive input of the PGIA and connect the negative side of the signal to AI GND as well as to the negative input of the PGIA, without using resistors.

Differential Connections for Non-Referenced or Floating Signal Sources

Figure 4-5 shows how to connect a floating signal source to a channel configured in DIFF mode.

Chapter 4 Analog Input

Floating

Signal

Source

–

AI +

AI –

Input Multiplexers

AI GND

Instrumentation

Amplifier

PGIA

–

Measured

Voltage

–

Isolation

Barrier

Digital

Isolators

I/O Connector

M Series Isolated Device Configured in DIFF Mode

Figure 4-5. Differential Connections for Floating Signal Sources

This figure shows AI GND connected to the ground reference point for the floating signal source. If you do not connect AI GND, the source is not likely to remain within the common-mode signal range of the PGIA due to the floating source or the isolation barrier. The PGIA then saturates, causing erroneous readings.

Single-Ended Connection Considerations

A single-ended connection is one in which the device AI signal is referenced to a ground that it can share with other input signals. The input

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Chapter 4 Analog Input

signal connects to the positive input of the PGIA, and the ground connects to the negative input of the PGIA.

You should only use single-ended input connections if the input signal meets the following conditions.

• The input signal is high-level (greater than 1 V).

• The leads connecting the signal to the device are less than 3 m (10 ft).

• The input signal can share a common reference point with other signals.

DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions.

For single-ended measurements, there is one ground-reference point for all analog input signals, but the reference ground plane is floating, requiring the user to provide a reference ground. An isolated device protects users against ground loops in their measurement, as well as allowing the user to provide a reference ground that is not electrically connected to earth, system, or building ground.

In the single-ended modes, more electrostatic and magnetic noise couples into the signal connections than in DIFF configurations. The coupling is the result of differences in the signal path. Magnetic coupling is proportional to the area between the two signal conductors. Electrical coupling is a function of how much the electric field differs between the two conductors.

Single-Ended Connections for Floating or Grounded Signal Sources

Figure 4-6 shows how to connect a floating or grounded signal source to a channel configured for RSE mode.

Chapter 4 Analog Input

Floating or

Grounded

Signal

Source

–

I/O Connector

Selected Channel in RSE or NRSE Configuration

Isolation

AI <0..

Input Multiplexers

AI GND

Programmable Gain

Instrumentation

Amplifier

–

PGIA

Measured

Voltage

–

Barrier

Digital

Isolators

Figure 4-6. Single-Ended Connections for Floating Signal Sources (RSE

Configuration)

Refer to the NI 6232/6233 Specifications for the usable range of Vcm.

Common-Mode Signal Rejection Considerations

Field Wiring Considerations

Environmental noise can seriously affect the measurement accuracy of the device if you do not take proper care when running signal wires between signal sources and the device. The following recommendations apply mainly to AI signal routing to the device, although they also apply to signal routing in general.

Minimize noise pickup and maximize measurement accuracy by taking the following precautions:

• Use DIFF AI connections to reject common-mode noise.

NI 6232/6233 User Manual 4-18 ni.com

• Use individually shielded, twisted-pair wires to connect AI signals to the device. With this type of wire, the signals attached to the positive and negative input channels are twisted together and then covered with a shield. You then connect this shield only at one point to the signal source ground. This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference.

Refer to the NI Developer Zone document, Field Wiring and Noise Considerations for Analog Signals, for more information. To access this document, go to

ni.com/info and enter the info code rdfwn3.

Analog Input Timing Signals

In order to provide all of the timing functionality described throughout this section, NI 6232/6233 devices have a flexible timing engine. Figure 4-7 summarizes all of the timing options provided by the analog input timing engine. Also refer to the Clock Routing section of Chapter 10, Digital

Routing and Clock Generation.

Chapter 4 Analog Input

PFI, RTSI

PXI_STAR

20 MHz Timebase

100 kHz Timebase

PXI_CLK10

PFI, RTSI

PXI_STAR

ai/Sample

Clock

Timebase

ai/Convert

Clock

Timebase

Ctr

Programmable

Clock

Divider

Ctr

Programmable

Clock

Divider

Internal Output

SW Pulse

PFI, RTSI

PXI_STAR

Internal Output

ai/Sample

Clock

ai/Convert

Clock

Figure 4-7. Analog Input Timing Options

M Series devices use ai/SampleClock and ai/ConvertClock to perform interval sampling. As Figure 4-8 shows, ai/SampleClock controls the sample period, which is determined by the following equation:

Chapter 4 Analog Input

1/Sample Period = Sample Rate

Channel 0

Channel 1

Convert Period

Sample Period

Figure 4-8. Interval Sampling

ai/ConvertClock controls the Convert Period, which is determined by the following equation:

1/Convert Period = Convert Rate

By default, the NI-DAQmx driver chooses the fastest Channel Clock rate possible while still allowing extra time for adequate amplifier settling time. At slower scan rates, 10 μs of delay is added to the fastest possible channel conversion rate of the device, which is the same as the maximum scan rate, to derive the Channel Clock.

As the scan rate increases, there eventually will not be enough time to have a full 10 μs of additional delay time between channel conversions and to finish acquiring all channels before the next edge of the Scan Clock. At this point, NI-DAQmx uses round robin channel sampling, evenly dividing the time between scans by the number of channels being acquired to obtain the interchannel delay. In this case, you can calculate the Channel Clock by multiplying the scan rate by the number of channels being acquired.

For example, the NI 623x M Series device has a maximum sampling rate of 250 kS/s. At a slower acquisition rate, such as 10 kHz with 2 channels, the Convert Clock would be set to 71428.6 Hz. This rate is determined by taking the fastest channel conversion rate for the device and adding 10 μs, 4 μs (1/250000) + 10 μs, which results in 14 μs or 71428.6 Hz.

When this calculation results in the sampling rate exceeding 35 kHz, there is not enough time between samples to acquire both channels and still add a 10 μs delay per channel, so the Convert Clock rate becomes the sampling rate multiplied by the number of channels being acquired. For example, on

NI 6232/6233 User Manual 4-20 ni.com

Chapter 4 Analog Input

the PCI-6220 M Series device, a sampling rate of 40 kHz for two channels would result in a Convert Clock rate of 80 kHz.

Maximum settling time for the amplifier is also very important. For example, to ensure accuracy to within ± 1 LSB on an NI 623x M Series device, the device requires a minimum amplifier settling time of 6 μs even though the maximum channel conversion rate is 4 μs. Higher source impedance also increases amplifier settling time.

Note The sampling rate is the fastest you can acquire data on the device and still achieve accurate results. For example, if an M Series device has a sampling rate of 250 kS/s, this sampling rate is aggregate—one channel at 250 kS/s or two channels at 125 kS/s per channel illustrates the relationship.

Posttriggered data acquisition allows you to view only data that is acquired after a trigger event is received. A typical posttriggered DAQ sequence is shown in Figure 4-9. In this example, the DAQ device reads two channels five times. The sample counter is loaded with the specified number of posttrigger samples, in this example, five. The value decrements with each pulse on ai/SampleClock, until the value reaches zero and all desired samples have been acquired.

ai/StartTrigger

ai/SampleClock

ai/ConvertClock

Sample Counter

Figure 4-9. Posttriggered Data Acquisition Example

13042

Pretriggered data acquisition allows you to view data that is acquired before the trigger of interest, in addition to data acquired after the trigger. Figure 4-10 shows a typical pretriggered DAQ sequence. ai/StartTrigger can be either a hardware or software signal. If ai/StartTrigger is set up to be a software start trigger, an output pulse appears on the ai/StartTrigger line when the acquisition begins. When the ai/StartTrigger pulse occurs, the sample counter is loaded with the number of pretriggered samples, in this example, four. The value decrements with each pulse on ai/SampleClock, until the value reaches zero. The sample counter is then loaded with the number of posttriggered samples, in this example, three.

Chapter 4 Analog Input

ai/StartTrigger

ai/ReferenceTrigger

ai/SampleClock

ai/ConvertClock

Scan Counter

Figure 4-10. Pretriggered Data Acquisition Example

n/a

0123 10222

If an ai/ReferenceTrigger pulse occurs before the specified number of pretrigger samples are acquired, the trigger pulse is ignored. Otherwise, when the ai/ReferenceTrigger pulse occurs, the sample counter value decrements until the specified number of posttrigger samples have been acquired.

NI 6232/6233 devices feature the following analog input timing signals.

• AI Sample Clock Signal

• AI Sample Clock Timebase Signal

• AI Convert Clock Signal

• AI Convert Clock Timebase Signal

• AI Hold Complete Event Signal

• AI Start Trigger Signal

• AI Reference Trigger Signal

• AI Pause Trigger Signal

AI Sample Clock Signal

Use the AI Sample Clock (ai/SampleClock) signal to initiate a set of measurements. Your M Series device samples the AI signals of every channel in the task once for every ai/SampleClock. A measurement acquisition consists of one or more samples.

You can specify an internal or external source for ai/SampleClock. You also can specify whether the measurement sample begins on the rising edge or falling edge of ai/SampleClock.

NI 6232/6233 User Manual 4-22 ni.com

Chapter 4 Analog Input

Using an Internal Source

One of the following internal signals can drive ai/SampleClock.

• Counter n Internal Output

• AI Sample Clock Timebase (divided down)

•A software pulse

A programmable internal counter divides down the sample clock timebase.

Several other internal signals can be routed to ai/SampleClock through RTS I . Refer t o Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

Using an External Source

Use one of the following external signals as the source of ai/SampleClock:

• Input PFI <0..5>

•RTSI <0..7>

•PXI_STAR

Routing AI Sample Clock Signal to an Output Terminal

You can route ai/SampleClock out to any output PFI <6..9> or RTSI <0..7> terminal. This pulse is always active high.

You can specify the output to have one of two behaviors. With the pulse behavior, your DAQ device briefly pulses the PFI terminal once for every occurrence of ai/SampleClock.

With level behavior, your DAQ device drives the PFI terminal high during the entire sample.

PFI <0..5> terminals are fixed inputs. PFI <6..9> terminals are fixed outputs.

Other Timing Requirements

Your DAQ device only acquires data during an acquisition. The device ignores ai/SampleClock when a measurement acquisition is not in progress. During a measurement acquisition, you can cause your DAQ device to ignore ai/SampleClock using the ai/PauseTrigger signal.

Chapter 4 Analog Input

A counter on your device internally generates ai/SampleClock unless you select some external source. ai/StartTrigger starts this counter and either software or hardware can stop it when a finite acquisition completes. When using an internally generated ai/SampleClock, you also can specify a configurable delay from ai/StartTrigger to the first ai/SampleClock pulse. By default, this delay is set to two ticks of the ai/SampleClockTimebase signal. When using an externally generated ai/SampleClock, you must ensure the clock signal is consistent with respect to the timing requirements of ai/ConvertClock. Failure to do so may result in ai/SampleClock pulses that are masked off and acquisitions with erratic sampling intervals. Refer to the AI Convert Clock Signal section for more information on the timing requirements between ai/ConvertClock and ai/SampleClock.

Figure 4-11 shows the relationship of ai/SampleClock to ai/StartTrigger.

ai/SampleClockTimebase

ai/StartTrigger

ai/SampleClock

Delay

From

Start

Trigger

Figure 4-11. ai/SampleClock and ai/StartTrigger

AI Sample Clock Timebase Signal

You can route any of the following signals to be the AI Sample Clock Timebase (ai/SampleClockTimebase) signal:

• 20 MHz Timebase

• 100 kHz Timebase

•PXI_CLK10

•RTSI <0..7>

• Input PFI <0..5>

•PXI_STAR

ai/SampleClockTimebase is not available as an output on the I/O connector. ai/SampleClockTimebase is divided down to provide one of the possible

NI 6232/6233 User Manual 4-24 ni.com

sources for ai/SampleClock. You can configure the polarity selection for ai/SampleClockTimebase as either rising or falling edge.

AI Convert Clock Signal

Use the AI Convert Clock (ai/ConvertClock) signal to initiate a single A/D conversion on a single channel. A sample, controlled by the AI Sample Clock, consists of one or more conversions.

You can specify either an internal or external signal as the source of ai/ConvertClock. You also can specify whether the measurement sample begins on the rising edge or falling edge of ai/ConvertClock.

With NI-DAQmx, the driver will choose the fastest conversion rate possible based on the speed of the A/D converter and add 10 µs of padding between each channel to allow for adequate settling time. This scheme enables the channels to approximate simultaneous sampling and still allow for adequate settling time. If the AI Sample Clock rate is too fast to allow for this 10 µs of padding, NI-DAQmx will choose the conversion rate so that the AI Convert Clock pulses are evenly spaced throughout the sample.

To explicitly specify the conversion rate, use the AI Convert Clock Rate DAQmx Timing property node or function.

Chapter 4 Analog Input

Caution Setting the conversion rate higher than the maximum rate specified for your device will result in errors.

Using an Internal Source

One of the following internal signals can drive ai/ConvertClock:

• AI Convert Clock Timebase (divided down)

• Counter n Internal Output

A programmable internal counter divides down the AI Convert Clock Timebase to generate ai/ConvertClock. The counter is started by ai/SampleClock and continues to count down to zero, produces an ai/ConvertClock, reloads itself, and repeats the process until the sample is finished. It then reloads itself in preparation for the next ai/SampleClock pulse.

Chapter 4 Analog Input

Using an External Source

Use one of the following external signals as the source of ai/ConvertClock:

• Input PFI <0..5>

•RTSI <0..7>

•PXI_STAR

Routing AI Convert Clock Signal to an Output Terminal

You can route ai/ConvertClock (as an active low signal) out to any output PFI <6..9> or RTSI <0..7> terminal.

PFI <0..5> terminals are fixed inputs. PFI <6..9> terminals are fixed outputs.

Using a Delay from Sample Clock to Convert Clock

When using an internally generated ai/ConvertClock, you also can specify a configurable delay from ai/SampleClock to the first ai/ConvertClock pulse within the sample. By default, this delay is three ticks of ai/ConvertClockTimebase.

Figure 4-12 shows the relationship of ai/SampleClock to ai/ConvertClock.

ai/ConvertClockTimebase

ai/SampleClock

ai/ConvertClock

Delay

From

Sample

Clock

NI 6232/6233 User Manual 4-26 ni.com

Convert

Perio d

Figure 4-12. ai/SampleClock and ai/ConvertClock

Chapter 4 Analog Input

Other Timing Requirements

The sample and conversion level timing of M Series devices work such that clock signals are gated off unless the proper timing requirements are met. For example, the device ignores both ai/SampleClock and ai/ConvertClock until it receives a valid ai/StartTrigger signal. When the device recognizes an ai/SampleClock pulse, it ignores subsequent ai/SampleClock pulses until it receives the correct number of ai/ConvertClock pulses.

Similarly, the device ignores all ai/ConvertClock pulses until it recognizes an ai/SampleClock pulse. When the device receives the correct number of ai/ConvertClock pulses, it ignores subsequent ai/ConvertClock pulses until it receives another ai/SampleClock. Figure 4-13 shows timing sequences for a four-channel acquisition (using AI channels 0, 1, 2, and 3) and demonstrates proper and improper sequencing of ai/SampleClock and ai/ConvertClock.

It is also possible to use a single external signal to drive both ai/SampleClock and ai/ConvertClock at the same time. In this mode, each tick of the external clock will cause a conversion on the ADC. Figure 4-13 shows this timing relationship.

ai/SampleClock

ai/ConvertClock

Channel Measured

One External Signal Driving Both Clocks

Figure 4-13. Single External Signal Driving ai/SampleClock and ai/ConvertClock

1 2 3 0

Sample #1 Sample #2 Sample #3

Simultaneously

1 2 3 0 1 … 0

AI Convert Clock Timebase Signal

The AI Convert Clock Timebase (ai/ConvertClockTimebase) signal is divided down to provide on of the possible sources for ai/ConvertClock. Use one of the following signals as the source of ai/ConvertClockTimebase:

• ai/SampleClockTimebase

• 20 MHz Timebase

Chapter 4 Analog Input

ai/ConvertClockTimebase is not available as an output on the I/O connector.

AI Hold Complete Event Signal

The AI Hold Complete Event (ai/HoldCompleteEvent) signal generates a pulse after each A/D conversion begins. You can route ai/HoldCompleteEvent out to any output PFI <6..9> or RTSI <0..7> terminal.

The polarity of ai/HoldCompleteEvent is software-selectable, but is typically configured so that a low-to-high leading edge can clock external AI multiplexers indicating when the input signal has been sampled and can be removed.

AI Start Trigger Signal

Use the AI Start Trigger (ai/StartTrigger) signal to begin a measurement acquisition. A measurement acquisition consists of one or more samples. If you do not use triggers, begin a measurement with a software command. When the acquisition begins, configure the acquisition to stop under the following conditions:

• When a certain number of points are sampled (in finite mode)

• After a hardware reference trigger (in finite mode)

• With a software command (in continuous mode)

An acquisition that uses a start trigger (but not a reference trigger) is sometimes referred to as a posttriggered acquisition.

Using a Digital Source

To use ai/StartTrigger with a digital source, specify a source and an edge. The source can be any of the following signals:

• Input PFI <0..5>

•RTSI <0..7>

• Counter n Internal Output

•PXI_STAR

The source also can be one of several other internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

NI 6232/6233 User Manual 4-28 ni.com

You also can specify whether the measurement acquisition begins on the rising edge or falling edge of ai/StartTrigger.

Routing AI Start Trigger to an Output Terminal

You can route ai/StartTrigger out to any output PFI <6..9> or RTSI <0..7> terminal.

The output is an active high pulse.

The device also uses ai/StartTrigger to initiate pretriggered DAQ operations. In most pretriggered applications, a software trigger generates ai/StartTrigger. Refer to the AI Reference Trigger Signal section for a complete description of the use of ai/StartTrigger and ai/ReferenceTrigger in a pretriggered DAQ operation.

AI Reference Trigger Signal

Use a reference trigger (ai/ReferenceTrigger) signal to stop a measurement acquisition. To use a reference trigger, specify a buffer of finite size and a number of pretrigger samples (samples that occur before the reference trigger). The number of posttrigger samples (samples that occur after the reference trigger) desired is the buffer size minus the number of pretrigger samples.

Chapter 4 Analog Input

When the acquisition begins, the DAQ device writes samples to the buffer. After the DAQ device captures the specified number of pretrigger samples, the DAQ device begins to look for the reference trigger condition. If the reference trigger condition occurs before the DAQ device captures the specified number of pretrigger samples, the DAQ device ignores the condition.

If the buffer becomes full, the DAQ device continuously discards the oldest samples in the buffer to make space for the next sample. This data can be accessed (with some limitations) before the DAQ device discards it. Refer to the KnowledgeBase document, Can a Pretriggered Acquisition be Continuous?, for more information. To access this KnowledgeBase, go to

ni.com/info and enter the info code rdcanq.

When the reference trigger occurs, the DAQ device continues to write samples to the buffer until the buffer contains the number of posttrigger samples desired. Figure 4-14 shows the final buffer.

Chapter 4 Analog Input

Reference Trigger

Pretrigger Samples

Complete Buffer

Figure 4-14. Reference Trigger Final Buffer

Posttrigger Samples

Using a Digital Source

To use ai/ReferenceTrigger with a digital source, specify a source and an edge. The source can be any of the following signals:

• Input PFI <0..5>

•RTSI <0..7>

•PXI_STAR

The source also can be one of several internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

You also can specify whether the measurement acquisition stops on the rising edge or falling edge of ai/ReferenceTrigger.

Routing AI Reference Trigger Signal to an Output Terminal

You can route ai/ReferenceTrigger out to any output PFI <6..9> or RTSI <0..7> terminal.

AI Pause Trigger Signal

You can use the AI Pause Trigger (ai/PauseTrigger) signal to pause and resume a measurement acquisition. The internal sample clock pauses while the external trigger signal is active and resumes when the signal is inactive. You can program the active level of the pause trigger to be high or low.

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Chapter 4 Analog Input

Using a Digital Source

To use ai/SampleClock, specify a source and a polarity. The source can be any of the following signals:

• Input PFI <0..5>

•RTSI <0..7>

•PXI_STAR

The source also can be one of several other internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

Routing AI Pause Trigger Signal to an Output Terminal

You can route ai/PauseTrigger out to RTSI <0..7>.

Note Pause triggers are only sensitive to the level of the source, not the edge.

Getting Started with AI Applications in Software

You can use the M Series device in the following analog input applications.

• Single-point analog input

• Finite analog input

• Continuous analog input

You can perform these applications through DMA, interrupt, or programmed I/O data transfer mechanisms. Some of the applications also use start, reference, and pause triggers.

Note For more information about programming analog input applications and triggers in software, refer to the NI-DAQmx Help or the LabVIEW 8.x Help.

Analog Output

NI 6232/6233 devices have two AO channels that are controlled by a single clock and are capable of waveform generation.

Figure 5-1 shows the analog output circuitry of NI 6232/6233 devices.

Isolation

Barrier

AO 0

AO 1

DAC0

DAC1

Analog Output Circuitry

DACs

Digital-to-analog converters (DACs) convert digital codes to analog voltages.

AO FIFO

The AO FIFO enables analog output waveform generation. It is a first-in-first-out (FIFO) memory buffer between the computer and the

Digital

Isolators

Figure 5-1. NI 6232/6233 Analog Output Circuitry

AO FIFO

AO Data

AO Sample Clock

Chapter 5 Analog Output

DACs. It allows you to download the points of a waveform to your M Series device without host computer interaction.

AO Sample Clock

The AO Sample Clock signal reads a sample from the DAC FIFO and generates the AO voltage.

Isolation Barrier and Digital Isolators

The digital isolators across the isolation barrier provide a ground break between the isolated analog front end and the earth/chassis/building ground.

Minimizing Glitches on the Output Signal

When you use a DAC to generate a waveform, you may observe glitches on the output signal. These glitches are normal; when a DAC switches from one voltage to another, it produces glitches due to released charges (usually worst at mid-scale transitions). The largest glitches occur when the most significant bit of the DAC code changes. You can build a lowpass deglitching filter to remove some of these glitches, depending on the frequency and nature of the output signal. Visit information on minimizing glitches.

ni.com/support for more

Analog Output Data Generation Methods

When performing an analog output operation, you either can perform software-timed or hardware-timed generations. Hardware-timed generations can be non-buffered or buffered.

Software-Timed Generations

With a software-timed generation, software controls the rate at which data is generated. Software sends a separate command to the hardware to initiate each DAC conversion. In NI-DAQmx, software-timed generations are referred to as on-demand timing. Software-timed generations are also referred to as immediate or static operations. They are typically used for writing a single value out, such as a constant DC voltage.

NI 6232/6233 User Manual 5-2 ni.com

Hardware-Timed Generations

With a hardware-timed generation, a digital hardware signal controls the rate of the generation. This signal can be generated internally on your device or provided externally.

Hardware-timed generations have several advantages over software-timed acquisitions:

• The time between samples can be much shorter.

• The timing between samples can be deterministic.

• Hardware-timed acquisitions can use hardware triggering.

Hardware-timed operations can be buffered or non-buffered. A buffer is a temporary storage in computer memory for to-be-generated samples.

Non-Buffered

In non-buffered acquisitions, data is written directly to the DACs on the device. Typically, hardware-timed, non-buffered operations are used to write single samples with known time increments between them and good latency.

Chapter 5 Analog Output

Buffered

In a buffered acquisition, data is moved from a PC buffer to the onboard FIFO of the DAQ device using DMA or interrupts before it is written to the DACs one sample at a time. Buffered acquisitions typically allow for much faster transfer rates than non-buffered acquisitions because data is moved in large blocks, rather than one point at a time.

One property of buffered I/O operations is the sample mode. The sample mode can be either finite or continuous.

Finite sample mode generation refers to the generation of a specific, predetermined number of data samples. When the specified number of samples has been written out, the generation stops.

Continuous generation refers to the generation of an unspecified number of samples. Instead of generating a set number of data samples and stopping, a continuous generation continues until you stop the operation. There are several different methods of continuous generation that control what data is written. These methods are regeneration, FIFO regeneration, and non-regeneration modes.

Chapter 5 Analog Output

Regeneration is the repetition of the data that is already in the buffer. Standard regeneration is when data from the PC buffer is continually downloaded to the FIFO to be written out. New data can be written to the PC buffer at any time without disrupting the output.

With FIFO regeneration, the entire buffer is downloaded to the FIFO and regenerated from there. When the data is downloaded, new data cannot be written to the FIFO. To use FIFO regeneration, the entire buffer must fit within the FIFO size. The advantage of using FIFO regeneration is that it does not require communication with the main host memory when the operation is started, thereby preventing any problems that may occur due to excessive bus traffic.

With non-regeneration, old data will not be repeated. New data must be continually written to the buffer. If the program does not write new data to the buffer at a fast enough rate to keep up with the generation, the buffer will underflow and cause an error.

Analog Output Triggering

Analog output supports two different triggering actions:

• Start trigger

• Pause trigger

A digital trigger can initiate these actions. NI 6232/6233 devices support digital triggering, but do not support analog triggering. Refer to the AO

Start Trigger Signal and AO Pause Trigger Signal sections for more

information on these triggering actions.

Connecting Analog Voltage Output Signals

AO <0..3> are the voltage output signals for AO channels 0, 1, 2, and 3. AO GND is the ground reference for AO <0..3>.

Figure 5-2 shows how to make AO connections to the device.

NI 6232/6233 User Manual 5-4 ni.com

Chapter 5 Analog Output

Load

I/O Connector

V OUT

–

AO 0

AO 1

AO GND

Channel 0

Channel 1

Digital

Isolators

Isolation

Barrier

Figure 5-2. Analog Output Connections

Analog Output Timing Signals

Figure 5-3 summarizes all of the timing options provided by the analog output timing engine.

Chapter 5 Analog Output

PFI, RTSI

PXI_STAR

20 MHz Timebase

100 kHz Timebase

PXI_CLK10

NI 6232/6233 devices feature the following AO (waveform generation) timing signals.

• AO Start Trigger Signal

• AO Pause Trigger Signal

• AO Sample Clock Signal

• AO Sample Clock Timebase Signal

AO Start Trigger Signal

Use the AO Start Trigger (ao/StartTrigger) signal to initiate a waveform generation. If you do not use triggers, you can begin a generation with a software command.

ao/Sample

Clock

Timebase

PXI_STAR

Internal Output

Ctr

Programmable

Clock

Divider

Figure 5-3. Analog Output Timing Options

ao/Sample

Clock

Using a Digital Source

To use ao/StartTrigger, specify a source and an edge. The source can be one of the following signals:

•A software pulse

• Input PFI <0..5>

•RTSI<0..7>

• ai/ReferenceTrigger

• ai/StartTrigger

•PXI_STAR

NI 6232/6233 User Manual 5-6 ni.com

The source also can be one of several internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

You also can specify whether the waveform generation begins on the rising edge or falling edge of ao/StartTrigger.

Routing AO Start Trigger Signal to an Output Terminal

You can route ao/StartTrigger out to any output PFI <6..9> or RTSI <0..7> terminal.

The output is an active high pulse.

PFI <0..5> terminals are fixed inputs. PFI <6..9> terminals are fixed outputs.

AO Pause Trigger Signal

Use the AO Pause Trigger signal (ao/PauseTrigger) to mask off samples in a DAQ sequence. That is, when ao/PauseTrigger is active, no samples occur.

Chapter 5 Analog Output

ao/PauseTrigger does not stop a sample that is in progress. The pause does not take effect until the beginning of the next sample.

When you generate analog output signals, the generation pauses as soon as the pause trigger is asserted. If the source of your sample clock is the onboard clock, the generation resumes as soon as the pause trigger is deasserted, as shown in Figure 5-4.

Pause Trigger

Sample Clock

Figure 5-4. ao/PauseTrigger with the Onboard Clock Source

If you are using any signal other than the onboard clock as the source of your sample clock, the generation resumes as soon as the pause trigger is

Chapter 5 Analog Output

deasserted and another edge of the sample clock is received, as shown in Figure 5-5.

Pause Trigger

Sample Clock

Figure 5-5. ao/PauseTrigger with Other Signal Source

Using a Digital Source

To use ao/PauseTrigger, specify a source and a polarity. The source can be one of the following signals:

• Input PFI <0..5>

•RTSI<0..7>

•PXI_STAR

The source also can be one of several other internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

You also can specify whether the samples are paused when ao/PauseTrigger is at a logic high or low level.

Routing AO Pause Trigger Signal to an Output Terminal

You can route ao/PauseTrigger out to RTSI <0..7>.

AO Sample Clock Signal

Use the AO Sample Clock (ao/SampleClock) signal to initiate AO samples. Each sample updates the outputs of all of the DACs. You can specify an internal or external source for ao/SampleClock. You also can specify whether the DAC update begins on the rising edge or falling edge of ao/SampleClock.

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Chapter 5 Analog Output

Using an Internal Source

One of the following internal signals can drive ao/SampleClock.

• AO Sample Clock Timebase (divided down)

• Counter n Internal Output

A programmable internal counter divides down the AO Sample Clock Timebase signal.

Using an External Source

Use one of the following external signals as the source of ao/SampleClock:

• Input PFI <0..5>

•RTSI<0..7>

•PXI_STAR

Routing AO Sample Clock Signal to an Output Terminal

You can route ao/SampleClock (as an active low signal) out to any output PFI <6..9> or RTSI <0..7> terminal.

Other Timing Requirements

A counter on your device internally generates ao/SampleClock unless you select some external source. ao/StartTrigger starts the counter and either the software or hardware can stop it when a finite generation completes. When using an internally generated ao/SampleClock, you also can specify a configurable delay from ao/StartTrigger to the first ao/SampleClock pulse. By default, this delay is two ticks of ao/SampleClockTimebase.

Figure 5-6 shows the relationship of ao/SampleClock to ao/StartTrigger.

Chapter 5 Analog Output

ao/SampleClockTimebase

ao/SampleClock

Figure 5-6. ao/SampleClock and ao/StartTrigger

AO Sample Clock Timebase Signal

The AO Sample Clock Timebase (ao/SampleClockTimebase) signal is divided down to provide a source for ao/SampleClock.

You can route any of the following signals to be the AO Sample Clock Timebase (ao/SampleClockTimebase) signal:

•20MHzTimebase

• 100 kHz Timebase

•PXI_CLK10

• Input PFI <0..5>

•RTSI<0..7>

•PXI_STAR

ao/StartTrigger

Delay

From

Start

Trigger

ao/SampleClockTimebase is not available as an output on the I/O connector.

You might use ao/SampleClockTimebase if you want to use an external sample clock signal, but need to divide the signal down. If you want to use an external sample clock signal but do not need to divide the signal, then you should use ao/SampleClock rather than ao/SampleClockTimebase.

Getting Started with AO Applications in Software

You can use an M Series device in the following analog output applications.

• Single-point (on-demand) generation

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Chapter 5 Analog Output

• Finite generation

• Continuous generation

• Waveform generation

You can perform these generations through programmed I/O, interrupt, or DMA data transfer mechanisms. Some of the applications also use start triggers and pause triggers.

Note For more information about programming analog output applications and triggers in software, refer to the NI-DAQmx Help or the LabVIEW 8.x Help.

Digital Input and Output

NI 6232/6233 devices have six static digital input lines, P0.<0..5>. These lines also can be used as PFI inputs.

The voltage input and output levels and the current drive level of the DI and DO lines are listed in the NI 6232/6233 Specifications. Refer to Chapter 8,

PFI, for more information on PFI inputs and outputs.

I/O Protection

Each DI, DO, and PFI signal is protected against ESD events on NI 6232/6233 devices. Consult the device specifications for details. However, you should avoid these fault conditions by following these guidelines.

•Do not connect any digital output line to any external signal source, ground signal, or power supply.

• Understand the current requirements of the load connected to the digital output lines. Do not exceed the specified current output limits of the digital outputs. NI has several signal conditioning solutions for digital applications requiring high current drive.

•Do not drive the digital input lines with voltages or current outside of its normal operating range.

• Treat the DAQ device as you would treat any static sensitive device. Always properly ground yourself and the equipment when handling the DAQ device or connecting to it.

Programmable Power-Up States

By default, the digital output lines (P1.<0..3>/PFI <6..9>) are set to 0. They can be programmed to power up as 0 or 1.

Refer to the NI-DAQmx Help or the LabVIEW 8.x Help for more information about setting power-up states in NI-DAQmx or MAX.

Chapter 6 Digital Input and Output

Connecting Digital I/O Signals

The DI signals P0.<0..5> are referenced to P0.GND and DO signals P1.<0..3> are referenced to P1.GND.

Figures 6-1 and 6-2 show P0.<0..5> and P1.<0..3> on the NI 6232 and the NI 6233 device, respectively. Digital input and output signals can range from 0 to 30 V. Refer to the NI 6232/6233 Specifications for more information.

P1.VCC

P1.0

P1.<0..3>

P1.1

P1.GND

Digital

Isolators

P1.GND

P0.0

P0.GND

Figure 6-1. NI 6232 Digital I/O Connections (DO Source)

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P1.VCC

Chapter 6 Digital Input and Output

P1.0

P1.GND

P1.1

P1.GND

P0.0

P0.GND

Buffer

P1.<0..3>

Digital

Isolators

P1.GND

P0.GND

Figure 6-2. NI 6233 Digital I/O Connections (DO Sink)

Caution Exceeding the maximum input voltage or maximum working voltage ratings,

which are listed in the NI 6232/6233 Specifications, can damage the DAQ device and the computer. NI is not liable for any damage resulting from such signal connections.

Logic Conventions

With NI 6232/6233 devices, logic “0” means that the Darlington output switch is open, while logic “1” means closed. Table 6-1 summarizes the expected behavior.

Chapter 6 Digital Input and Output

Table 6-1. NI 6232/6233 Logic Conventions

Device Logic

0 1

NI 6232 (Source) DO P1.GND P1.VCC

NI 6233 (Sink) DO P1.VCC P1.GND

Getting Started with DIO Applications in Software

You can use NI 6232/6233 devices in the following digital I/O applications:

• Static digital input

• Static digital output

Note For more information about programming digital I/O applications and triggers in software, refer to the NI-DAQmx Help or the LabVIEW 8.x Help.

NI 6232/6233 User Manual 6-4 ni.com

Counters

Caution When making measurements, take into account the minimum pulse width and

time delay of the digital input and output lines. Refer to the NI 6238/6239 Specifications for more information.

NI 6232/6233 devices have two general-purpose 32-bit counter/timers and one frequency generator, as shown in Figure 7-1. The general-purpose counter/timers can be used for many measurement and pulse generation applications.

Chapter 7 Counters

Input Selection Muxes

Counter 0

Counter 0 Source (Counter 0 Timebase)

Counter 0 Gate

Counter 0 Aux

Counter 0 HW Arm

Counter 0 A

Counter 0 B (Counter 0 Up_Down)

Counter 0 Z

Counter 1 Source (Counter 1 Timebase)

Counter 1 Gate

Counter 1 Aux

Counter 1 HW Arm

Counter 1 A

Counter 1 B (Counter 1 Up_Down)

Counter 1 Z

Counter 0 Internal Output

Counter 1

Counter 0 Internal Output

Counter 0 TC

Input Selection Muxes

Frequency Output Timebase Freq Out

Frequency Generator

Figure 7-1. M Series Counters

The counters have seven input signals, although in most applications only a few inputs are used.

For information on connecting counter signals, refer to the Default Counter

Terminals section.

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Counter Input Applications

Counting Edges

In edge counting applications, the counter counts edges on its Source after the counter is armed. You can configure the counter to count rising or falling edges on its Source input. You also can control the direction of counting (up or down).

The counter values can be read on demand or with a sample clock.

Single Point (On-Demand) Edge Counting

With single point (on-demand) edge counting, the counter counts the number of edges on the Source input after the counter is armed. On-demand refers to the fact that software can read the counter contents at any time without disturbing the counting process. Figure 7-2 shows an example of single point edge counting.

Chapter 7 Counters

Counter Armed

SOURCE

Counter Value 105432

Figure 7-2. Single Point (On-Demand) Edge Counting

You also can use a pause trigger to pause (or gate) the counter. When the pause trigger is active, the counter ignores edges on its Source input. When the pause trigger is inactive, the counter counts edges normally.

You can route the pause trigger to the Gate input of the counter. You can configure the counter to pause counting when the pause trigger is high or when it is low. Figure 7-3 shows an example of on-demand edge counting with a pause trigger.

Chapter 7 Counters

Counter Armed

Pause Trigger

(Pause When Low)

SOURCE

Counter Value

100 5432

Figure 7-3. Single Point (On-Demand) Edge Counting with Pause Trigger

Buffered (Sample Clock) Edge Counting

With buffered edge counting (edge counting using a sample clock), the counter counts the number of edges on the Source input after the counter is armed. The value of the counter is sampled on each active edge of a sample clock. A DMA controller transfers the sampled values to host memory.

The count values returned are the cumulative counts since the counter armed event. That is, the sample clock does not reset the counter.

You can route the counter sample clock to the Gate input of the counter. You can configure the counter to sample on the rising or falling edge of the sample clock.

Figure 7-4 shows an example of buffered edge counting. Notice that counting begins when the counter is armed, which occurs before the first active edge on Gate.

Counter Armed

(Sample on Rising Edge)

Sample Clock

SOURCE

Counter Value

Buffer

10763452

3 6

Figure 7-4. Buffered (Sample Clock) Edge Counting

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Non-Cumulative Buffered Edge Counting

Non-cumulative edge counting is similar to buffered (sample clock) edge counting. However, the counter resets after each active edge of the Sample Clock. You can route the Sample Clock to the Gate input of the counter.

Figure 7-5 shows an example of non-cumulative buffered edge counting.

Sample Clock

(Sample on Rising Edge)

SOURCE

Chapter 7 Counters

Counter

Armed

Counter Value

Buffer

Figure 7-5. Non-Cumulative Buffered Edge Counting

1101331222

2232

3 3

Notice that the first count interval begins when the counter is armed, which occurs before the first active edge on Gate.

Notice that if you are using an external signal as the Source, at least one Source pulse should occur between each active edge of the Gate signal. This condition ensures that correct values are returned by the counter. If this condition is not met, consider using duplicate count prevention.

Controlling the Direction of Counting

In edge counting applications, the counter can count up or down. You can configure the counter to do the following.

• Always count up

• Always count down

• Count up when the Counter n B input is high; count down when it is low

For information on connecting counter signals, refer to the Default Counter

Terminals section.

Chapter 7 Counters

Pulse-Width Measurement

In pulse-width measurements, the counter measures the width of a pulse on its Gate input signal. You can configure the counter to measure the width of high pulses or low pulses on the Gate signal.

You can route an internal or external periodic clock signal (with a known period) to the Source input of the counter. The counter counts the number of rising (or falling) edges on the Source signal while the pulse on the Gate signal is active.

You can calculate the pulse width by multiplying the period of the Source signal by the number of edges returned by the counter.

A pulse-width measurement will be accurate even if the counter is armed while a pulse train is in progress. If a counter is armed while the pulse is in the active state, it will wait for the next transition to the active state to begin the measurement.

Single Pulse-Width Measurement

With single pulse-width measurement, the counter counts the number of edges on the Source input while the Gate input remains active. When the Gate input goes inactive, the counter stores the count in a hardware save register and ignores other edges on the Gate and Source inputs. Software then can read the stored count.

Figure 7-6 shows an example of a single pulse-width measurement.

GATE

SOURCE

Counter Value

HW Save Register

Figure 7-6. Single Pulse-Width Measurement

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GATE

SOURCE

Chapter 7 Counters

Buffered Pulse-Width Measurement

Buffered pulse-width measurement is similar to single pulse-width measurement, but buffered pulse-width measurement takes measurements over multiple pulses.

The counter counts the number of edges on the Source input while the Gate input remains active. On each trailing edge of the Gate signal, the counter stores the count in a hardware save register. A DMA controller transfers the stored values to host memory.

Figure 7-7 shows an example of a buffered pulse-width measurement.

Counter Value

Buffer

Note that if you are using an external signal as the Source, at least one Source pulse should occur between each active edge of the Gate signal. This condition ensures that correct values are returned by the counter. If this condition is not met, consider using duplicate count prevention.

For information on connecting counter signals, refer to the Default Counter

Terminals section.

Period Measurement

In period measurements, the counter measures a period on its Gate input signal after the counter is armed. You can configure the counter to measure the period between two rising edges or two falling edges of the Gate input signal.

You can route an internal or external periodic clock signal (with a known period) to the Source input of the counter. The counter counts the number

103

Figure 7-7. Buffered Pulse-Width Measurement

212

Chapter 7 Counters

of rising (or falling) edges occurring on the Source input between the two active edges of the Gate signal.

You can calculate the period of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter.

Single Period Measurement

With single period measurement, the counter counts the number of rising (or falling) edges on the Source input occurring between two active edges of the Gate input. On the second active edge of the Gate input, the counter stores the count in a hardware save register and ignores other edges on the Gate and Source inputs. Software then can read the stored count.

Figure 7-8 shows an example of a single period measurement.

GATE

SOURCE

Counter Value

HW Save Register

103

Figure 7-8. Single Period Measurement

Buffered Period Measurement

Buffered period measurement is similar to single period measurement, but buffered period measurement measures multiple periods.

The counter counts the number of rising (or falling) edges on the Source input between each pair of active edges on the Gate input. At the end of each period on the Gate signal, the counter stores the count in a hardware save register. A DMA controller transfers the stored values to host memory.

The counter begins when it is armed. The arm usually occurs in the middle of a period of the Gate input. So the first value stored in the hardware save register does not reflect a full period of the Gate input. In most applications, this first point should be discarded.

Figure 7-9 shows an example of a buffered period measurement.

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GATE

SOURCE

Counter Value

Buffer

Chapter 7 Counters

Counter Armed

112 3

(Discard) (Discard) (Discard)

Figure 7-9. Buffered Period Measurement

2 3

311

2 3 3

For information on connecting counter signals, refer to the Default Counter

Terminals section.

Semi-Period Measurement

In semi-period measurements, the counter measures a semi-period on its Gate input signal after the counter is armed. A semi-period is the time between any two consecutive edges on the Gate input.

You can route an internal or external periodic clock signal (with a known period) to the Source input of the counter. The counter counts the number of rising (or falling) edges occurring on the Source input between two edges of the Gate signal.

You can calculate the semi-period of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter.

Single Semi-Period Measurement

Single semi-period measurement is equivalent to single pulse-width measurement.

Chapter 7 Counters

Buffered Semi-Period Measurement

In buffered semi-period measurement, on each edge of the Gate signal, the counter stores the count in a hardware save register. A DMA controller transfers the stored values to host memory.

The counter begins counting when it is armed. The arm usually occurs between edges on the Gate input. So the first value stored in the hardware save register does not reflect a full semi-period of the Gate input. In most applications, this first point should be discarded.

Figure 7-10 shows an example of a buffered semi-period measurement.

Counter Armed

GATE

SOURCE

For information on connecting counter signals, refer to the Default Counter

Terminals section.

Frequency Measurement

You can use the counters to measure frequency in several different ways. You can choose one of the following methods depending on your application.

Method 1—Measure Low Frequency with One Counter

In this method, you measure one period of your signal using a known timebase. This method is good for low frequency signals.

Counter Value

Buffer

Figure 7-10. Buffered Semi-Period Measurement

12102

2 3

132

3 1

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Chapter 7 Counters

You can route the signal to measure (F1) to the Gate of a counter. You can route a known timebase (Ft) to the Source of the counter. The known timebase can be 80MHzTimebase. For signals that might be slower than

0.02 Hz, use a slower known timebase.

You can configure the counter to measure one period of the gate signal. The frequency of F1 is the inverse of the period. Figure 7-11 illustrates this method.

Interval Measured

Gate

Source

Single Period Measurement

Method 1b—Measure Low Frequency with One Counter (Averaged)

In this method, you measure several periods of your signal using a known timebase. This method is good for low to medium frequency signals.

0.02 Hz, use a slower known timebase.

You can configure the counter to make K + 1 buffered period measurements. Recall that the first period measurement in the buffer should be discarded.

123…

Period of F1 =

Frequency of F1 =

Figure 7-11. Method 1

…

Average the remaining K period measurements to determine the average period of F1. The frequency of F1 is the inverse of the average period. Figure 7-12 illustrates this method.

Chapter 7 Counters

Intervals Measured

…T

Gate

Source

Buffered Period

Measurement

2 ...

1... ...

Average Period of F1 =

Frequency of F1 =

… 1... ...

K × Ft

+ …

Figure 7-12. Method 1b

Method 2—Measure High Frequency with Two Counters

In this method, you measure one pulse of a known width using your signal and derive the frequency of your signal from the result. This method is good for high frequency signals.

In this method, you route a pulse of known duration (T) to the Gate of a counter. You can generate the pulse using a second counter. You also can generate the pulse externally and connect it to a PFI or RTSI terminal. You only need to use one counter if you generate the pulse externally.

Route the signal to measure (F1) to the Source of the counter. Configure the counter for a single pulse-width measurement. Suppose you measure the width of pulse T to be N periods of F1. Then the frequency of F1 is N/T.

Figure 7-13 illustrates this method. Another option would be to measure the width of a known period instead of a known pulse.

NI 6232/6233 User Manual 7-12 ni.com

Width of Pulse (T)

Chapter 7 Counters

Pulse

Gate

Source

Pulse-Width

Measurement

12…

Width of

Frequency of F1 =

Pulse

T =

Figure 7-13. Method 2

Method 3—Measure Large Range of Frequencies Using Two Counters

By using two counters, you can accurately measure a signal that might be high or low frequency. This technique is called reciprocal frequency measurement. In this method, you generate a long pulse using the signal to measure. You then measure the long pulse with a known timebase. The M Series device can measure this long pulse more accurately than the faster input signal.

You can route the signal to measure to the Source input of Counter 0, as shown in Figure 7-14. Assume this signal to measure has frequency F1. Configure Counter 0 to generate a single pulse that is the width of N periods of the source input signal.

Chapter 7 Counters

Signal to

Measure (F1)

Signal of Known

Frequency (F2)

CTR_0_SOURCE

(Signal to Measure)

CTR_0_OUT

(CTR_1_GATE)

CTR_1_SOURCE

SOURCE OUT

COUNTER 0

SOURCE

COUNTER 1

GATE

0123…

Interval

to Measure

OUT

Figure 7-14. Method 3

Then route the Counter 0 Internal Output signal to the Gate input of Counter 1. You can route a signal of known frequency (F2) to the Counter 1 Source input. F2 can be 80MHzTimebase. For signals that might be slower than 0.02 Hz, use a slower known timebase. Configure Counter 1 to perform a single pulse-width measurement. Suppose the result is that the pulse width is J periods of the F2 clock.

From Counter 0, the length of the pulse is N/F1. From Counter 1, the length of the same pulse is J/F2. Therefore, the frequency of F1 is given by F1 = F2 * (N/J).

Choosing a Method for Measuring Frequency

The best method to measure frequency depends on several factors including the expected frequency of the signal to measure, the desired accuracy, how many counters are available, and how long the measurement can take.

• Method 1 uses only one counter. It is a good method for many applications. However, the accuracy of the measurement decreases as the frequency increases.

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Chapter 7 Counters

Consider a frequency measurement on a 50 kHz signal using an 80 MHz Timebase. This frequency corresponds to 1600 cycles of the 80 MHz Timebase. Your measurement may return 1600 ±1 cycles depending on the phase of the signal with respect to the timebase. As your frequency becomes larger, this error of ±1 cycle becomes more significant. Table 7-1 illustrates this point.

Table 7-1. Frequency Measurement Method 1

Tas k Equation Example 1 Example 2

Actual Frequency to Measure F1 50 kHz 5MHz

Timebase Frequency Ft 80 MHz 80 MHz

Actual Number of Timebase

Ft/F1 1600 16

Periods

Worst Case Measured Number of

(Ft/F1) – 1 1599 15

Timebase Periods

Measured Frequency Ft F1/(Ft – F1) 50.125 kHz 5.33 MHz

Error [Ft F1/(Ft – F1)] – F1 125 kHz 333 kHz

Error % [Ft/(Ft – F1)] – 1 0.06% 6.67%

• Method 1b (measuring K periods of F1) improves the accuracy of the measurement. A disadvantage of Method 1b is that you have to take K + 1 measurements. These measurements take more time and consume some of the available PCI or PXI bandwidth.

• Method 2 is accurate for high frequency signals. However, the accuracy decreases as the frequency of the signal to measure decreases. At very low frequencies, Method 2 may be too inaccurate for your application. Another disadvantage of Method 2 is that it requires two counters (if you cannot provide an external signal of known width). An advantage of Method 2 is that the measurement completes in a known amount of time.

• Method 3 measures high and low frequency signals accurately. However, it requires two counters.

Table 7-2 summarizes some of the differences in methods of measuring frequency.

Chapter 7 Counters

Table 7-2. Frequency Measurement Method Comparison

Number of

Method

1 1 1 Poor Good

1b 1 Many Fair Good

2 1 or 2 1 Good Poor

3 2 1 Good Good

Counters Used

For information on connecting counter signals, refer to the Default Counter

Terminals section.

Position Measurement

You can use the counters to perform position measurements with quadrature encoders or two-pulse encoders. You can measure angular position with X1, X2, and X4 angular encoders. Linear position can be measured with two-pulse encoders. You can choose to do either a single point (on-demand) position measurement or a buffered (sample clock) position measurement. You must arm a counter to begin position measurements.

Number of

Measurements

Returned

Measures High

Frequency

Signals

Accurately

Measures Low

Frequency

Signals

Accurately

Measurements Using Quadrature Encoders

The counters can perform measurements of quadrature encoders that use X1, X2, or X4 encoding.

A quadrature encoder can have up to three channels—channels A, B, and Z.

X1 Encoding

When channel A leads channel B in a quadrature cycle, the counter increments. When channel B leads channel A in a quadrature cycle, the counter decrements. The amount of increments and decrements per cycle depends on the type of encoding—X1, X2, or X4.

Figure 7-15 shows a quadrature cycle and the resulting increments and decrements for X1 encoding. When channel A leads channel B, the increment occurs on the rising edge of channel A. When channel B leads channel A, the decrement occurs on the falling edge of channel A.

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Ch A Ch B

Chapter 7 Counters

Counter Value

Figure 7-15. X1 Encoding

X2 Encoding

The same behavior holds for X2 encoding except the counter increments or decrements on each edge of channel A, depending on which channel leads the other. Each cycle results in two increments or decrements, as shown in Figure 7-16.

Ch A Ch B

Counter Value

56 8

Figure 7-16. X2 Encoding

X4 Encoding

Similarly, the counter increments or decrements on each edge of channels A and B for X4 encoding. Whether the counter increments or decrements depends on which channel leads the other. Each cycle results in four increments or decrements, as shown in Figure 7-17.

Ch A

Ch B

Counter Value 5 6 8 9 10 1011 1112 1213 137

56879

Figure 7-17. X4 Encoding

Channel Z Behavior

Some quadrature encoders have a third channel, channel Z, which is also referred to as the index channel. A high level on channel Z causes the counter to be reloaded with a specified value in a specified phase of the quadrature cycle. You can program this reload to occur in any one of the four phases in a quadrature cycle.

Chapter 7 Counters

Channel Z behavior—when it goes high and how long it stays high—differs with quadrature encoder designs. You must refer to the documentation for your quadrature encoder to obtain timing of channel Z with respect to channels A and B. You must then ensure that channel Z is high during at least a portion of the phase you specify for reload. For instance, in Figure 7-18, channel Z is never high when channel A is high and channel B is low. Thus, the reload must occur in some other phase.

In Figure 7-18, the reload phase is when both channel A and channel B are low. The reload occurs when this phase is true and channel Z is high. Incrementing and decrementing takes priority over reloading. Thus, when the channel B goes low to enter the reload phase, the increment occurs first. The reload occurs within one maximum timebase period after the reload phase becomes true. After the reload occurs, the counter continues to count as before. Figure 7-18 illustrates channel Z reload with X4 decoding.

Ch A Ch B

Ch Z

Max Timebase

Counter Value

Figure 7-18. Channel Z Reload with X4 Decoding

890 21743

A = 0 B = 0 Z = 1

Measurements Using Two Pulse Encoders

The counter supports two pulse encoders that have two channels—channels A and B.

The counter increments on each rising edge of channel A. The counter decrements on each rising edge of channel B, as shown in Figure 7-19.

Ch A

Ch B

Counter Value 2 3 54344

Figure 7-19. Measurements Using Two Pulse Encoders

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For information on connecting counter signals, refer to the Default Counter

Terminals section.

Two-Signal Edge-Separation Measurement

Two-signal edge-separation measurement is similar to pulse-width measurement, except that there are two measurement signals—Aux and Gate. An active edge on the Aux input starts the counting and an active edge on the Gate input stops the counting. You must arm a counter to begin a two edge separation measurement.

After the counter has been armed and an active edge occurs on the Aux input, the counter counts the number of rising (or falling) edges on the Source. The counter ignores additional edges on the Aux input.

The counter stops counting upon receiving an active edge on the Gate input. The counter stores the count in a hardware save register.

You can configure the rising or falling edge of the Aux input to be the active edge. You can configure the rising or falling edge of the Gate input to be the active edge.

Use this type of measurement to count events or measure the time that occurs between edges on two signals. This type of measurement is sometimes referred to as start/stop trigger measurement, second gate measurement, or A-to-B measurement.

Chapter 7 Counters

Single Two-Signal Edge-Separation Measurement

With single two-signal edge-separation measurement, the counter counts the number of rising (or falling) edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal. The counter then stores the count in a hardware save register and ignores other edges on its inputs. Software then can read the stored count.

Figure 7-20 shows an example of a single two-signal edge-separation measurement.

Chapter 7 Counters

Counter

AUX

GATE

SOURCE

Counter Value

HW Save Register

Armed

0000123456788 8

Measured Interval

Figure 7-20. Single Two-Signal Edge-Separation Measurement

Buffered Two-Signal Edge-Separation Measurement

Buffered and single two-signal edge-separation measurements are similar, but buffered measurement measures multiple intervals.

The counter counts the number of rising (or falling) edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal. The counter then stores the count in a hardware save register. On the next active edge of the Gate signal, the counter begins another measurement. A DMA controller transfers the stored values to host memory.

Figure 7-21 shows an example of a buffered two-signal edge-separation measurement.

AUX

GATE

SOURCE

Counter Value

Buffer

123 123 123

3333

3 3

Figure 7-21. Buffered Two-Signal Edge-Separation Measurement

For information on connecting counter signals, refer to the Default Counter

Terminals section.

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Counter Output Applications

Simple Pulse Generation

Single Pulse Generation

The counter can output a single pulse. The pulse appears on the Counter n Internal Output signal of the counter.

You can specify a delay from when the counter is armed to the beginning of the pulse. The delay is measured in terms of a number of active edges of the Source input.

You can specify a pulse width. The pulse width is also measured in terms of a number of active edges of the Source input. You also can specify the active edge of the Source input (rising or falling).

Figure 7-22 shows a generation of a pulse with a pulse delay of four and a pulse width of three (using the rising edge of Source).

Counter Armed

Chapter 7 Counters

SOURCE

OUT

Figure 7-22. Single Pulse Generation

Single Pulse Generation with Start Trigger

The counter can output a single pulse in response to one pulse on a hardware Start Trigger signal. The pulse appears on the Counter n Internal Output signal of the counter.

You can route the Start Trigger signal to the Gate input of the counter. You can specify a delay from the Start Trigger to the beginning of the pulse. You also can specify the pulse width. The delay and pulse width are measured in terms of a number of active edges of the Source input.

After the Start Trigger signal pulses once, the counter ignores the Gate input.

Figure 7-23 shows a generation of a pulse with a pulse delay of four and a pulse width of three (using the rising edge of Source).

Chapter 7 Counters

GATE

(Start Trigger)

SOURCE

OUT

Figure 7-23. Single Pulse Generation with Start Trigger

Retriggerable Single Pulse Generation

The counter can output a single pulse in response to each pulse on a hardware Start Trigger signal. The pulses appear on the Counter n Internal Output signal of the counter.

You can route the Start Trigger signal to the Gate input of the counter. You can specify a delay from the Start Trigger to the beginning of each pulse. You also can specify the pulse width. The delay and pulse width are measured in terms of a number of active edges of the Source input.

The counter ignores the Gate input while a pulse generation is in progress. After the pulse generation is finished, the counter waits for another Start Trigger signal to begin another pulse generation.

Figure 7-24 shows a generation of two pulses with a pulse delay of five and a pulse width of three (using the rising edge of Source).

GATE

(Start Trigger)

SOURCE

OUT

Figure 7-24. Retriggerable Single Pulse Generation

For information on connecting counter signals, refer to the Default Counter

Terminals section.

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Pulse Train Generation

Continuous Pulse Train Generation

This function generates a train of pulses with programmable frequency and duty cycle. The pulses appear on the Counter n Internal Output signal of the counter.

You can specify a delay from when the counter is armed to the beginning of the pulse train. The delay is measured in terms of a number of active edges of the Source input.

You specify the high and low pulse widths of the output signal. The pulse widths are also measured in terms of a number of active edges of the Source input. You also can specify the active edge of the Source input (rising or falling).

The counter can begin the pulse train generation as soon as the counter is armed, or in response to a hardware Start Trigger. You can route the Start Trigger to the Gate input of the counter.

You also can use the Gate input of the counter as a Pause Trigger (if it is not used as a Start Trigger). The counter pauses pulse generation when the Pause Trigger is active.

Chapter 7 Counters

Figure 7-25 shows a continuous pulse train generation (using the rising edge of Source).

SOURCE

OUT

Counter Armed

Figure 7-25. Continuous Pulse Train Generation

Continuous pulse train generation is sometimes called frequency division. If the high and low pulse widths of the output signal are M and N periods, then the frequency of the Counter n Internal Output signal is equal to the frequency of the Source input divided by M + N.

For information on connecting counter signals, refer to the Default Counter

Terminals section.

Chapter 7 Counters

Frequency Generation

You can generate a frequency by using a counter in pulse train generation mode or by using the frequency generator circuit.

Using the Frequency Generator

The frequency generator can output a square wave at many different frequencies. The frequency generator is independent of the two general-purpose 32-bit counter/timer modules on M Series devices.

Figure 7-26 shows a block diagram of the frequency generator.

20 MHz Timebase

100 kHz Timebase

÷ 2

Frequency

Output

Timebase

Frequency Generator

Divisor

(1–16)

Figure 7-26. Frequency Generator Block Diagram

Freq Out

The frequency generator generates the Frequency Output signal. The Frequency Output signal is the Frequency Output Timebase divided by a number you select from 1 to 16. The Frequency Output Timebase can be either the 20 MHz Timebase divided by 2 or the 100 kHz Timebase.

The duty cycle of Frequency Output is 50% if the divider is either 1 or an even number. For an odd divider, suppose the divider is set to D. In this case, Frequency Output is low for (D + 1)/2 cycles and high for (D – 1)/2 cycles of the Frequency Output Timebase.

Figure 7-27 shows the output waveform of the frequency generator when the divider is set to 5.

Frequency Output Timebase

Freq Out (Divisor = 5)

Figure 7-27. Frequency Generator Output Waveform

NI 6232/6233 User Manual 7-24 ni.com

Frequency Output can be routed out to any output PFI <6..9> or RTSI <0..7> terminal. All PFI terminals are set to high-impedance at startup.

In software, program the frequency generator as you would program one of the counters for pulse train generation.

For information on connecting counter signals, refer to the Default Counter

Terminals section.

Frequency Division

The counters can generate a signal with a frequency that is a fraction of an input signal. This function is equivalent to continuous pulse train generation.

For information on connecting counter signals, refer to the Default Counter

Terminals section.

Pulse Generation for ETS

In this application, the counter produces a pulse on the output a specified delay after an active edge on Gate. After each active edge on Gate, the counter cumulatively increments the delay between the Gate and the pulse on the output by a specified amount. Thus, the delay between the Gate and the pulse produced successively increases.

Chapter 7 Counters

Note ETS = Equivalent Time Sampling.

The increase in the delay value can be between 0 and 255. For instance, if you specify the increment to be 10, the delay between the active Gate edge and the pulse on the output will increase by 10 every time a new pulse is generated.

Suppose you program your counter to generate pulses with a delay of 100 and pulse width of 200 each time it receives a trigger. Furthermore, suppose you specify the delay increment to be 10. On the first trigger, your pulse delay will be 100, on the second it will be 110, on the third it will be 120; the process will repeat in this manner until the counter is disarmed. The counter ignores any Gate edge that is received while the pulse triggered by the previous Gate edge is in progress.

The waveform thus produced at the output of the counter can be used to provide timing for undersampling applications where a digitizing system can sample repetitive waveforms that are higher in frequency than the

Chapter 7 Counters

Nyquist frequency of the system. Figure 7-28 shows an example of pulse generation for ETS; the delay from the trigger to the pulse increases after each subsequent Gate active edge.

GATE

OUT

For information on connecting counter signals, refer to the Default Counter

Terminals section.

Counter Timing Signals

M Series devices feature the following counter timing signals.

• Counter n Source

• Counter n Gate

• Counter n Aux

• Counter n A

• Counter n B

• Counter n Z

• Counter n Up_Down

• Counter n HW Arm

• Counter n Internal Output

• Counter n TC

•Frequency Output

D1 D2 = D1 + ΔDD3 = D1 + 2ΔD

Figure 7-28. Pulse Generation for ETS

In this section, n refers to either Counter 0 or 1. For example, Counter n Source refers to two signals—Counter 0 Source (the source input to Counter 0) and Counter 1 Source (the source input to Counter 1).

NI 6232/6233 User Manual 7-26 ni.com

Counter n Source Signal

The selected edge of the Counter n Source signal increments and decrements the counter value depending on the application the counter is performing. Table 7-3 lists how this terminal is used in various applications.

Pulse Generation Counter Timebase

One Counter Time Measurements Counter Timebase

Two Counter Time Measurements Input Terminal

Non-Buffered Edge Counting Input Terminal

Buffered Edge Counting Input Terminal

Two-Edge Separation Counter Timebase

Routing a Signal to Counter n Source

Each counter has independent input selectors for the Counter n Source signal. Any of the following signals can be routed to the Counter n Source input.

•80MHz Timebase

•20MHz Timebase

• 100 kHz Timebase

•RTSI<0..7>

• Input PFI <0..5>

•PXI_CLK10

•PXI_STAR

Chapter 7 Counters

Table 7-3. Counter Applications and Counter n Source

Application Purpose of Source Terminal

In addition, Counter 1 TC or Counter 1 Gate can be routed to Counter 0 Source. Counter 0 TC or Counter 0 Gate can be routed to Counter 1 Source.

Some of these options may not be available in some driver software.

National Instruments NI 6232, NI 6233 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

NI 6232/6233 User Manual

Support

Worldwide Technical Support and Product Information

National Instruments Corporate Headquarters

Worldwide Offices

Important Information

Warranty

Copyright

Trademarks

Patents

WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS

Compliance

Contents

About This Manual

Conventions

Related Documentation

NI-DAQ

NI-DAQmx for Linux

NI-DAQmx Base

LabVIEW

Measurement Studio

ANSI C without NI Application Software

.NET Languages without NI Application Software

Device Documentation and Specifications

Training Courses

Technical Support on the Web

Installing NI-DAQmx

Installing Other Software

Installing the Hardware

Device Pinouts

Device Specifications

Device Accessories and Cables

DAQ Hardware

Figure 2-1. Components of a Typical DAQ System

DAQ-STC2

Figure 2-2. General NI 6232/6233 Block Diagram

Calibration Circuitry

Sensors and Transducers

Cables and Accessories

Custom Cabling

Programming Devices in Software

I/O Connector Signal Descriptions

Table 3-1. I/O Connector Signals

RTSI Connector Pinout

Analog Input Circuitry

Figure 4-1. NI 6232/6233 Analog Input Circuitry

Analog Input Range

Table 4-1. Input Ranges for NI 6232/6233

Analog Input Ground-Reference Settings

Table 4-2. Analog Input Ground-Reference Settings

Figure 4-2. PGIA

Table 4-3. Signals Routed to the NI-PGIA

Configuring AI Ground-Reference Settings in Software

Figure 4-3. Enabling Multimode Scanning in LabVIEW

Multichannel Scanning Considerations

Use Low Impedance Sources

Use Short High-Quality Cabling

Carefully Choose the Channel Scanning Order

Avoid Switching from a Large to a Small Input Range

Insert Grounded Channel between Signal Channels

Minimize Voltage Step between Adjacent Channels

Avoid Scanning Faster Than Necessary

Example 1

Example 2

Analog Input Data Acquisition Methods

Software-Timed Acquisitions

Hardware-Timed Acquisitions

Buffered

Non-Buffered

Analog Input Triggering

Connecting Analog Voltage Input Signals

Table 4-4. Analog Input Configuration

Types of Signal Sources

Floating Signal Sources

Ground-Referenced Signal Sources

Differential Connection Considerations