National Instruments NI 5791R, 5791R Specifications
USER MANUAL AND SPECIFICATIONS
NI 5791R
RF Transceiver Adapter Module
The NI 5791 is an RF transceiver adapter module designed to work in conjunction with your
NI FlexRIO™ FPGA module. The NI 5791 features the following connectors and chips:
• 2-channel, 130 MS/s analog-to-digital converter (ADC) with 14-bit accuracy
• 2-channel, 130 MS/s (520 MS/s after interpolation) digital-to-analog converter (DAC)
with 16-bit accuracy
• LO input and LO output connectors to support LO sharing for multiple-channel
applications
• Timing chip with clocking options from the backplane and the front panel
• Programmable attenuators
• Selectable receive and transmit filters
• The following front panel connectors:
– RX IN
– LO OUT
– CLK IN
– CLK OUT
– LO IN
– TX OUT
The NI 5791 can upconvert and downconvert RF signals ranging from 200 MHz to 4.4 GHz.
This document contains signal information and lists the specifications of the NI 5791R, which
is composed of the NI FlexRIO FPGA module and the NI 5791. This document also contains
tutorial sections that demonstrate how to acquire data using a LabVIEW FPGA Example VI
and how to create and run your own LabVIEW project with the NI 5791R.
Note NI 5791R refers to the combination of your NI 5791 adapter module and
your NI FlexRIO FPGA module. NI 5791 refers to your NI 5791 adapter module
only.
Note The NI 5791 is only compatible with the NI PXIe-796xR FPGA modules.
Note Before configuring your NI 5791, you must install the appropriate software
and hardware. Refer to the NI FlexRIO FPGA Module Installation Guide and
Specifications for installation instructions.
Note For EMC compliance, operate this device according to the documentation.
The following figure shows an example of a properly connected NI FlexRIO device.
Figure 1. NI FlexRIO Device
NI FlexRIO
Adapter Module
+ =
NI FlexRIO Device
NI FlexRIO
FPGA Module
Related Information
NI 5791 Specifications on page 21
Contents
Electromagnetic Compatibility Guidelines...............................................................................3
Connecting Cables....................................................................................................................4
How to Use Your NI FlexRIO Documentation Set..................................................................4
Key Features.............................................................................................................................6
Configuration............................................................................................................................6
Front Panel and Connector Pinouts...........................................................................................6
AUX I/O Connector..........................................................................................................8
Block Diagram..........................................................................................................................9
NI 5791 Component-Level Intellectual Property (CLIP).......................................................11
5791 CLIP.......................................................................................................................12
Programmable Chips.......................................................................................................13
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NI 5791R User Manual and Specifications | ni.com
Using Your NI 5791R with a LabVIEW FPGA Example VI.................................................13
Using the Included Streaming Example..........................................................................14
Creating a LabVIEW Project..........................................................................................14
NI-579x Configuration Design Library..................................................................................16
FPGA VI Requirements..................................................................................................17
Host VI Requirements.....................................................................................................17
Synchronization Overview......................................................................................................17
Synchronization Versions...............................................................................................18
Synchronization Example...............................................................................................19
How Synchronization Works..........................................................................................19
Synchronization Checklist..............................................................................................20
Clocking..................................................................................................................................21
579x Sample Projects..............................................................................................................21
NI 5791 Specifications............................................................................................................21
RX IN..............................................................................................................................22
LO OUT Front Panel Connector.....................................................................................27
CLK IN Front Panel Connector......................................................................................28
CLK OUT Front Panel Connector..................................................................................28
LO IN Front Panel Connector.........................................................................................29
TX OUT Front Panel Connector.....................................................................................29
TX OUT Spurious Responses.........................................................................................31
RX IN and TX OUT Frequency Characteristics.............................................................33
Baseband Characteristics................................................................................................35
AUX I/O (Port 0 DIO <0..3>, Port 1 DIO <0..3>, and PFI <0..3>)...............................35
Compliance and Certifications........................................................................................36
Environment....................................................................................................................37
Installing PXI EMC Filler Panels...................................................................................38
Where to Go for Support.................................................................................................39
Electromagnetic Compatibility Guidelines
This product was tested and complies with the regulatory requirements and limits for
electromagnetic compatibility (EMC) stated in the product specifications. These requirements
and limits are designed to provide reasonable protection against harmful interference when the
product is operated in the intended operational electromagnetic environment.
This product is intended for use in industrial locations. However, harmful interference may
occur in some installations, when the product is connected to a peripheral device or test object,
or if the product is used in residential or commercial areas. To minimize interference with
radio and television reception and prevent unacceptable performance degradation, install and
use this product in strict accordance with the instructions in the product documentation.
NI 5791R User Manual and Specifications
| © National Instruments | 3
Furthermore, any modifications to the product not expressly approved by National Instruments
could void your authority to operate it under your local regulatory rules.
Caution To ensure the specified EMC performance, operate this product only with
shielded cables and accessories.
Caution To ensure the specified EMC performance, the length of all I/O cables
must be no longer than 3 m (10 ft).
Caution To ensure the specified EMC performance, you must install PXI EMC
Filler Panels (National Instruments part number 778700-1) in adjacent chassis slots.
Related Information
Installing PXI EMC Filler Panels on page 38
Connecting Cables
1. Use any shielded 50 Ω SMA cable to connect signals to the connectors on the front panel
of your device.
2. Use the SHH19-H19-AUX cable (NI part number: 152629-01 or 152629-02) to connect
to the digital I/O (DIO) and programmable function interface (PFI) signals on the
AUX I/O connector. NI recommends using the SCB-19 connector block to access the
DIO and PFI signals.
Related Information
NI 5791 Specifications on page 21
How to Use Your NI FlexRIO
Documentation Set
Refer to Figure 2 and Table 1 to learn how to use your FlexRIO documentation set.
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NI 5791R User Manual and Specifications | ni.com
Figure 2. How to Use Your NI FlexRIO Documentation Set.
LabVIEW FPGA
Module Help
NI FlexRIO
Help
LabVIEW
Examples
INSTALL Hardware
and Software
CONNECT Signals
and Learn About
Your Adapter
Module
LEARN About
LabVIEW FPGA
Module
PROGRAM Your
NI FlexRIO System
in LabVIEW FPGA
Module
NI FlexRIO FPGA Module
Installation Guide and Specifications
NI FlexRIO Adapter Module
User Guide and Specifications
Are
You New to
LabVIEW FPGA
Module?
Yes No
No
Table 1. NI FlexRIO Documentation Locations and Descriptions
Document Location Description
NI FlexRIO FPGA
Module Installation
Guide and Specifications
Available from the Start
menu and at ni.com/
manuals.
Contains installation instructions for
your NI FlexRIO system and
specifications for your FPGA module.
NI 5791R User Manual
and Specifications (this
document)
Available from the Start
menu and at ni.com/
manuals.
Contains signal information,
examples, CLIP details, and
specifications for your adapter
module.
LabVIEW FPGA Module
Help
Embedded in LabVIEW
Help and at ni.com/
manuals.
Contains information about the basic
functionality of the LabVIEW FPGA
Module.
NI FlexRIO Help Available from the Start
menu and at ni.com/
manuals.
Contains FPGA Module, adapter
module, and CLIP configuration
information.
LabVIEW Examples Available in NI Example
Finder.
Contains examples of how to run
FPGA VIs and Host VIs on your
device.
NI 5791R User Manual and Specifications | © National Instruments | 5
Table 1. NI FlexRIO Documentation Locations and Descriptions (Continued)
Document Location Description
IPNet ni.com/ipnet Contains LabVIEW FPGA functions
and intellectual property to share.
NI FlexRIO product
page
ni.com/flexrio Contains product information and
data sheets for NI FlexRIO devices.
Key Features
The NI 5791 includes the following key features:
............................................................................RF frequency range 200 MHz to 4.4 GHz
............................................................................Instantaneous bandwidth 100 MHz
............................................................................ADC 14-bit dual channel at 130 MS/s
............................................................................DAC 16-bit dual channel at 130 MS/s, interpolated
to 520 MS/s
............................................................................Phase noise <94 dBc/Hz, 10 kHz offset, 2.4 GHz carrier
............................................................................Dynamic range >105 dB
............................................................................Noise figure <8 dB at 2 GHz
............................................................................EVM <1.5% (RMS)
............................................................................Receive (RX) IP
3
+1 dBm at 2 GHz
............................................................................Transmit (TX) IP
3
+17 dBm at 2 GHz
Configuration
You can configure the NI 5791 as follows:
• Instantaneous bandwidth up to 100 MHz
• 1 transmitter channel, 16-bit, 520 MS/s (4× interpolation) (I and Q)
• 1 receiver channel, 14-bit, 130 MS/s (I and Q)
Front Panel and Connector Pinouts
Table 2 shows the front panel connector and signal descriptions for the NI 5791.
Caution To avoid permanent damage to the NI 5791, disconnect all signals
connected to the NI 5791 before powering down the module, and connect signals
6 | NI 5791R User Manual and Specifications | ni.com
only after the adapter module has been powered on by the NI FlexRIO FPGA
module.
Caution Connections that exceed any of the maximum ratings of any connector on
the NI 5791R can damage the device and the chassis. NI is not liable for any damage
resulting from such connections.
Table 2. NI 5791 Front Panel Connectors
Device Front Panel Connector Signal Description
AUX
I/O
NI 5791
200MHz - 4.4 GHz
RF Transceiver
RX IN
LO OUT
CLK OUT
LO IN
TX OUT
CLK IN
INSTRUMENTS
NATIONAL
RX IN Receive channel input, +20 dBm maximum
LO OUT Local oscillator output, +12 dBm maximum, +0 dBm
nominal
CLK IN Reference Clock input, 50 Ω single-ended, +20 dBm
maximum
CLK OUT Exported clock output, DC-coupled, 0 V to 2 V
LO IN Local oscillator input, +20 dBm maximum
TX OUT Transmit channel output, +20 dBm maximum
AUX I/O Refer to Table 3 for the signal list and descriptions.
Related Information
NI 5791 Specifications on page 21
NI 5791R User Manual and Specifications
| © National Instruments | 7
AUX I/O Connector
Table 3. NI 5791 AUX I/O Connector Pin Assignments
AUX I/O Connector Pin Signal Signal Description
18
16
14
12
10
8
6
4
2
19
17
1
3
5
7
9
11
13
15
1 DIO Port 0 (0) Bidirectional single-ended (SE) digital I/O (DIO)
data channel.
2 GND Ground reference for signals.
3 DIO Port 0 (1) Bidirectional SE DIO data channel.
4 DIO Port 0 (2) Bidirectional SE DIO data channel.
5 GND Ground reference for signals.
6 DIO Port 0 (3) Bidirectional SE DIO data channel.
7 DIO Port 1 (0) Bidirectional SE DIO data channel.
8 GND Ground reference for signals.
9 DIO Port 1 (1) Bidirectional SE DIO data channel.
10 DIO Port 1 (2) Bidirectional SE DIO data channel.
11 GND Ground reference for signals.
12 DIO Port 1 (3) Bidirectional SE DIO data channel.
13 PFI 0 Bidirectional SE DIO data channel.
14 NC No connect.
15 PFI 1 Bidirectional SE DIO data channel.
16 PFI 2 Bidirectional SE DIO data channel.
17 GND Ground reference for signals.
18 +5 V +5 V power (10 mA maximum).
19 PFI 3 Bidirectional SE DIO data channel.
Caution The AUX I/O connector accepts a standard, third-party HDMI cable, but
the AUX I/O port is not an HDMI interface. Do not connect the AUX I/O port on the
NI 5791 to the HDMI port of another device. NI is not liable for any damage
resulting from such signal connections.
8 | NI 5791R User Manual and Specifications | ni.com
Block Diagram
The following figure shows the NI 5791 block diagram.
Figure 3. NI 5791 Block Diagram
ADC
14 bit
TI ADS4246
Noise Reject
LPF
4.4 GHz
LPF
4.4 GHz
LPF
TX RF Filter
Bank
44 MHz
HPF
Noise Reject
LPF
52 MHz
LPF
204 MHz
LPF
204 MHz
LPF
52 MHz
LPF
TX LO Filter
Bank
ADC
14 bit
TI ADS4246
DAC
16 bit
TI DAC3482
DAC
16 bit
TI DAC3482
31.75 dB Maximum
0.25 dB Step
31.75 dB Maximum
0.25 dB Step
ADI ADF4351
Synthesizer LO
RX RF Filter
Bank
RX LO Filter
Bank
RX IN
TX OUT
LO OUT
LO IN
31.75 dB Maximum
0.25 dB Step
12 dB
0
90
12 dB
0
90
The following figure shows the connections between the NI 5791 and the LabVIEW FPGA
CLIP.
NI 5791R User Manual and Specifications | © National Instruments | 9
Figure 4. NI 5791 Connector Signals and CLIP Signal Block Diagram
NI 5791 Adapter Module
From RF
Mixer
To RF Mixer
DIO Port 0 (0)
From RF LO
RF Filters
RF LO
and Attenuators
SPI
DIO Port 0 (1)
DIO Port 0 (2)
DIO Port 0 (3)
DIO Port 1 (0)
DIO Port 1 (1)
DIO Port 1 (2)
DIO Port 1 (3)
PFI 0
PFI 1
PFI 2
PFI 3
AUX I/O
ADC Clock
ADC Data
DAC
DAC3482
LabVIEW FPGA CLIP
DAC Clock
DAC Data
DAC
Interface
ADC
Interface
Rx I
Tx I
14
Register Bus Write
Register Write Data
Register Bus Read
Register Bus Read Data
Register Bus Address
Register Bus Idle
16
14
DIO Port 0 WE
DIO Port 0 Rd Data (0)
DIO Port 0 Wr Data (0)
DIO Port 0 Rd Data (1)
DIO Port 0 Wr Data (1)
DIO Port 0 Rd Data (2)
DIO Port 0 Wr Data (2)
DIO Port 0 Rd Data (3)
DIO Port 0 Wr Data (3)
DIO Port 1 Rd Data (0)
DIO Port 1 Wr Data (0)
DIO Port 1 Rd Data (1)
DIO Port 1 Wr Data (1)
DIO Port 1 Rd Data (2)
DIO Port 1 Wr Data (2)
DIO Port 1 Rd Data (3)
DIO Port 1 Wr Data (3)
LO Locked
DIO Port 1 WE
PFI 3 Wr Data
PFI <0..3> WE
PFI 3 Rd Data
PFI 1 Rd Data
PFI 1 Wr Data
PFI 2 Rd Data
PFI 2 Wr Data
PFI 0 Rd Data
PFI 0 Wr Data
4
User Data 1
User Command
User Command Commit
User Command Status
User Return
Initialization Done
User Error
User Command Idle
User Data 0
From RF
Mixer
To RF Mixer
PLL Locked
Sync Clock
Sample Clock 2x
Sample Clock
Sample Clock
Synchronize DAC
CLK IN
CLK OUT
SPI
Engine
PLL
Register
Bus
Calibration
EEPROM
Clock
DAC SPI
ADC SPI
DAC SPI
DAC
OUT3
OUT2
CP
OUT1
CLK1
REF IN
AD9511
CLK2
OUT 4
SPI
VCXO
Gain
PLL Loop
Filter
Enable VCXO
Enable PLL
External Sample CLK
External Ref CLK
AI Gain Control
RF Filter Control
Microcontroller
Rx Q
Tx Q
16
16
14
ADC
ADS4246
The following figure shows the NI 5791 low-pass filter bank.
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NI 5791R User Manual and Specifications | ni.com
Figure 5. Low-Pass Filter (LPF) Bank
3600 MHz LPF
2400 MHz LPF
1600 MHz LPF
1066 MHz LPF
711 MHz LPF
474 MHz LPF
316 MHz LPF
4400 MHz LPF
NI 5791 Component-Level Intellectual Property
(CLIP)
The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL
IP integration. NI FlexRIO devices support two types of CLIP: user-defined and socketed.
• User-defined CLIP allows you to insert HDL IP into an FPGA target, enabling VHDL
code to communicate directly with an FPGA VI.
• Socketed CLIP provides the same IP integration of the user-defined CLIP, but also allows
the CLIP to communicate directly with circuitry external to the FPGA. Adapter module
socketed CLIP allows your IP to communicate directly with both the FPGA VI and the
external adapter module connector interface.
The following figure shows the relationship between an FPGA VI and the CLIP.
NI 5791R User Manual and Specifications
| © National Instruments | 11
Figure 6. CLIP and FPGA VI Relationship
Adapter Module
CLIP Socket
LabVIEW
FPGA VI
User-Defined
CLIP
NI FlexRIO FPGA Module
FPGA
External
I/O Connector
Adapter
Module
Socketed
CLIP
User-Defined
CLIP
Fixed I/O
DRAM 0
CLIP Socket
Socketed
CLIP
DRAM 1
CLIP Socket
Socketed
CLIP
Fixed I/O
Fixed I/O
DRAM 0 DRAM 1
The NI 5791 ships with socketed CLIP items that add module I/O to the LabVIEW project.
5791 CLIP
The 5791 CLIP provides access to I and Q data for one receive channel and one transmit
channel. The CLIP also provides a User Command interface for common configurations of the
baseband clocking, programmable attenuators, receive amplifier, receive and transmit filters,
LO filters, and RF path. You can also import and export the LO.
Configure the baseband clocking using one of the following settings:
• Internal Sample Clock
• Internal Sample Clock locked to an external Reference Clock though the CLK IN
connector
• External Sample Clock through the CLK IN connector
• Internal Sample Clock locked to an external Reference Clock through the Sync Clock
This CLIP also contains a FAM Registers Bus interface, which is a low-level bus interface that
directly programs registers on all programmable devices, such as the analog-to-digital
converter (ADC) and the digital-to-analog converter (DAC). Programming registers on these
devices allows for more advanced configuration.
Note You cannot configure the LO using the User Command interface. Use the
FAM Registers Bus interface to program the LO synthesizer, then use the User
Command interface to configure the LO filters.
Refer to the NI FlexRIO Help for more information about NI FlexRIO CLIP items,
configuring the NI 5791 with a socketed CLIP, and a list of available socketed CLIP signals.
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