National Instruments NI 5782R, 5782R Specifications

NI 5782R User Manual and Specifications

The NI 5782 is an analog dual-input, dual-ouput, intermediate-frequency (IF) transceiver adapter module designed to work with your NI FlexRIO™ FPGA module. The NI 5782 features two analog input (AI) channels with 14-bit sample rates of up to 250 MS/s. The NI 5782 also has two analog output (AO) channels with 16-bit sample rates of up to 500 MS/s when using both AO channels, or up to 1 GS/s when using only one AO channel.

This document contains signal information and specifications for the NI 5782R, which is composed of an NI FlexRIO FPGA module and the NI 5782 adapter module. This document also contains tutorial sections that demonstrate how to acquire data using a LabVIEW FPGA example VI and how to create and run your own LabVIEW project with the NI 5782R.

Note NI 5782R refers to the combination of your NI 5782 adapter module and your

NI FlexRIO FPGA module. NI 5782 refers to your NI 5782 adapter module only.

Caution The protection provided by the NI 5782R can be impaired if it is used in

a manner not described in this document.

Contents

Electromagnetic Compatibility Guidelines .............................................................................. 2

How to Use Your NI FlexRIO Documentation Set.................................................................. 3

Front Panel and Connector Pinouts .......................................................................................... 4

Block Diagram.......................................................................................................................... 7

NI 5782 Component-Level Intellectual Property (CLIP)......................................................... 8

Connecting Cables .................................................................................................................... 10

Clocking.................................................................................................................................... 10

Using Your NI 5782R with a LabVIEW FPGA Example VI .................................................. 11

Creating a LabVIEW Project and Running a VI on an FPGA Target...................................... 13

Appendix A: Specifications......................................................................................................16

Appendix B: Installing EMI Controls ...................................................................................... 34

Where to Go for Support .......................................................................................................... 36

Figure 1. NI FlexRIO Device

NI FlexRIO

Adapter Module

Note Before configuring your NI 5782R, you must install the appropriate software

NI FlexRIO

+ = NI FlexRIO Device

FPGA Module

and hardware. Refer to the NI FlexRIO FPGA Module Installation Guide and Specifications for installation instructions. Figure 1 shows an example of a properly

connected NI FlexRIO device.

Electromagnetic Compatibility Guidelines

This product was tested and complies with the regulatory requirements and limits for electromagnetic compatibility (EMC) as stated in the product specifications. These requirements and limits are designed to provide reasonable protection against harmful interference when the product is operated in its intended operational electromagnetic environment.

This product is intended for use in industrial locations. There is no guarantee that harmful interference will not occur in a particular installation, when the product is connected to a test object, or if the product is used in residential areas. To minimize the potential for the product to cause interference to radio and television reception or to experience unacceptable performance degradation, install and use this product in strict accordance with instructions in the product documentation.

Furthermore, any changes or modifications to the product not expressly approved by National Instruments could void your authority to operate it under your local regulatory rules.

Caution To ensure the specified EMC performance, you must install PXI EMC

Filler Panels (National Instruments part number 778700-01) in adjacent chassis slots. For more information about installing PXI EMC filler panels in your system, refer to the Appendix B: Installing EMI Controls section of this document.

Caution To ensure the specified EMC performance, operate this product only with

shielded cables and accessories.

Caution This product is sensitive to electrostatic discharge (ESD). To ensure the

specified EMC performance, follow the programming instructions listed at the end of the Using Your NI 5782R with a LabVIEW FPGA Example VI and Creating a

LabVIEW Project and Running a VI on an FPGA Target sections of this document.

2 | ni.com | NI 5782R User Manual and Specifications

Caution To ensure the specified EMC performance, the length of all I/O cables

LabVIEW FPGA

Module Help

NI FlexRIO

Help

LabVIEW

Examples

INSTALL Hardware

and Software

CONNECT Signals

and Learn About

Your Adapter

Module

LEARN About

LabVIEW FPGA

Module

PROGRAM Your

NI FlexRIO System

in LabVIEW FPGA

Module

NI FlexRIO FPGA Module

Installation Guide and Specifications

NI FlexRIO Adapter Module

User Guide and Specifications

Are

You New to

LabVIEW FPGA

Module?

Yes No

must be no longer than 30 m (100 ft).

How to Use Your NI FlexRIO Documentation Set

Refer to Figure 2 and Table 1 for information about how to use your NI FlexRIO documentation set.

Figure 2. How to Use Your NI FlexRIO Documentation Set

NI 5782R User Manual and Specifications | © National Instruments | 3

Table 1. NI FlexRIO Documentation Locations and Descriptions

Document Location Description

NI FlexRIO FPGA Module Installation Guide and Specifications

NI 5782R User Manual and Specifications

(this document)

LabVIEW FPGA Module Help

NI FlexRIO Help Available from the Start menu

LabVIEW Examples Available in NI Example

IPNet ni.com/ipnet

NI FlexRIO product page

Available in your FPGA module hardware kit, from the Start Menu, and at

manuals.

Available from the Start Menu

ni.com/manuals.

and at

Embedded in LabVIEW Help

ni.com/manuals.

and at

ni.com/manuals.

and at

Finder.

ni.com/flexrio

ni.com/

Contains installation instructions for your NI FlexRIO system and specifications for your FPGA module.

Contains signal information, examples, CLIP details, and specifications for your adapter module.

Contains information about the basic functionality of the LabVIEW FPGA module.

Contains FPGA module, adapter module, and CLIP configuration information.

Contains examples of how to run FPGA VIs and Host VIs on your device.

Contains LabVIEW FPGA functions and intellectual property to share.

Contains product information and data sheets for NI FlexRIO devices.

Front Panel and Connector Pinouts

Table 2 shows the front panel connector and signal descriptions for the NI 5782. Refer to

Appendix A: Specifications for additional signal information.

Caution To avoid permanent damage to the NI 5782, disconnect all signals

connected to the NI 5782 before powering down the module, and connect signals only after the adapter module has been powered on by the NI FlexRIO FPGA module.

Caution Connections that exceed any of the maximum ratings of any connector on

the NI 5782R can damage the device and the chassis. NI is not liable for any damage resulting from such signal connections. For the maximum input and output ratings for each signal, refer to Appendix A: Specifications.

4 | ni.com | NI 5782R User Manual and Specifications

Device Front

Panel

NI 5782

AUX

I/O

Table 2. NI 5782 Front Panel Connectors

Connector Signal Description

AUX I/O Refer to Table 3 for the signal list and

descriptions.

CLK IN 50 Ω single-ended (SE) external Reference or

Sample Clock input.

TRIG Trigger input channel.

CLK IN

TRIG

AI 0

AI 1

AO 0

AO 1

14-Bit AI

16-Bit AO

Analog I/O

AI 0 50 Ω SE analog input (AI) channel 0.

AI 1 50 Ω SE AI channel 1.

AO 0 50 Ω SE analog output (AO) channel 0.

AO 1 50 Ω SE AO channel 1.

NI 5782R User Manual and Specifications | © National Instruments | 5

AUX I/O Connector

Table 3. NI 5782 AUX I/O Connector Pin Assignments

AUX I/O Connector Pin Signal Signal Description

1 DIO Port 0 (Bit 0) Bidirectional single-ended (SE)

digital I/O (DIO) data channel.

2 GND Ground reference for signals.

3 DIO Port 0 (Bit 1) Bidirectional SE DIO data channel.

4 DIO Port 0 (Bit 2) Bidirectional SE DIO data channel.

5 GND Ground reference for signals.

6 DIO Port 0 (Bit 3) Bidirectional SE DIO data channel.

7 DIO Port 1 (Bit 0) Bidirectional SE DIO data channel.

8 GND Ground reference for signals.

9 DIO Port 1 (Bit 1) Bidirectional SE DIO data channel.

10 DIO Port 1 (Bit 2) Bidirectional SE DIO data channel.

11 GND Ground reference for signals.

12 DIO Port 1 (Bit 3) Bidirectional SE DIO data channel.

13 PFI 0 Bidirectional SE DIO data channel.

14 NC No connect.

15 PFI 1 Bidirectional SE DIO data channel.

16 PFI 2 Bidirectional SE DIO data channel.

17 GND Ground reference for signals.

18 +5V +5 V power (10 mA maximum).

19 PFI 3 Bidirectional SE DIO data channel.

Caution The AUX I/O connector accepts a standard, third-party HDMI cable, but

the AUX I/O port is not an HDMI interface. Do not connect the AUX I/O port on the NI 5782 into the HDMI port of another device. NI is not liable for any damage resulting from such signal connections.

6 | ni.com | NI 5782R User Manual and Specifications

Block Diagram

Figure 3 shows the NI 5782 block diagram and signal flow to and from the NI 5782 component-level intellectual property (CLIP) by way of the adapter module and the corresponding NI 5782 Multiple Sample CLIP in LabVIEW FPGA.

Figure 3. NI 5782 Connector Signals and NI 5782 CLIP Signal Block Diagram

AUX I/O

CLK IN

TRIG

Bus

Tr anslator

Bus

Tr ansceiv

Internal

Reference

Clock

SwitchSwitch

Clock

Synthesizer

Switch

AD9512

LabVIEW FPGA CLIPNI 5782 Adapter Module

Clock Buffer

Sample

Clock

SPI Engine

Interfacing

Switches

Analog front

end (FE)

with:

AD9512

ADCs DACs

DIO Port 0 Rd Data <0..3>, DIO Port 1 Rd Data <0..3> DIO Port 0 Wr Data <0..3>,

DIO Port 1 Wr Data <0..3> PFI <0..3> Rd Data

PFI <0..3> Wr Data

DIO Port <0..1> Write Enable

PFI <0..3> Write Enable

Trigger Input

SPI Read SPI Write SPI Address SPI Write Data SPI Read Data SPI Device Select SPI Idle

Initialization Done Reinitialize Configuration Error

Sample Clock Select Sample Clock Commit Synthesizer Locked

Data Clock

AI 0

AI 1

AO 0

AO 1

Analog

Front End

Analog

Front End

Analog

Front End

Analog

Front End

ADC

DAC

Data

Clock

Data

Clock

ADC

Interface

DAC

Interface

AI 0 Data N

AI 0 Data N–1

AI 1 Data N

AI 1 Data N–1

AO 0 Data N AO 0 Data N–1 AO 0 Data N– AO 0 Data N–3 AO 1 Data N AO 1 Data N–1 AO 1 Data N–2 AO 1 Data N–3

IOModSyncClock

NI 5782R User Manual and Specifications | © National Instruments | 7

NI 5782 Component-Level Intellectual Property (CLIP)

The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL IP integration. NI FlexRIO devices support two types of CLIP: user-defined and socketed.

• User-defined CLIP allows you to insert HDL IP into an FPGA target, enabling VHDL code to communicate directly with an FPGA VI.

• Socketed CLIP provides the same IP integration functionality of the user-defined CLIP, but also allows the CLIP to communicate directly with circuitry external to the FPGA. Adapter module socketed CLIP allows your IP to communicate directly with both the FPGA VI and the external adapter module connector interface.

The following figure shows the relationship between an FPGA VI and CLIP.

Figure 4. CLIP and FPGA VI Relationship

NI FlexRIO FPGA Module

FPGA

User-Defined

CLIP

User-Defined

CLIP

LabVIEW

FPGA VI

DRAM 0

CLIP Socket

Socketed

CLIP

Fixed I/O

DRAM0 DRAM1

DRAM 1

CLIP Socket

Socketed

CLIP

Adapter Module

Fixed I/O

CLIP Socket

Socketed

CLIP

Fixed I/O

Adapter

Module

External

I/O Connector

8 | ni.com | NI 5782R User Manual and Specifications

The NI 5782 ships with socketed CLIP items that add module I/O to the LabVIEW project. The NI 5782 ships with the following CLIP items:

1. NI 5782 Multiple Sample CLIP—The analog input channels generate two samples per clock cycle at a clock rate that is half the sample rate. The analog output channels generate four samples per clock cycle at a clock rate that is one quarter of the sample rate. The AI default sample rate is 250 MHz, and the AO default sample rate is 500 MHz. The default clock rate for this CLIP is 125 MHz. You can set a lower sample rate by using an external Sample Clock.

This CLIP presents the data to the diagram in a decelerated format. The ADC data lands at half the rate as the ADC clock. The DAC data must be presented in four time samples per clock on each channel.

This CLIP provides access to two AI channels, two AO channels, eight bidirectional DIO channels, four bidirectional PFI channels, and an input clock selector that can be configured to use one of the following settings:

– Internal Sample Clock

– Internal Sample Clock locked to an external Reference Clock through the CLK IN

connector

– External Sample Clock through the CLK IN connector

– Internal Sample Clock locked to an external Reference Clock through

IoModSyncClock

– External Sample Clock through IoModSyncClock

This CLIP also contains an engine to program the CLK chip, ADCs, and DACs, either through predetermined settings for an easier instrument setup, or through a raw SPI address and data signals for a more advanced setup. The NI 5782 Multiple Sample CLIP is the default CLIP.

2. NI 5782 Single Sample CLIP—The analog input channels generate one sample per clock cycle and the analog output channels generate two samples per clock cycle. The default clock rate for the Multiple Sample CLIP is 250 MHz. The Sample Clock rates of AI (250 MHz) and AO (500 MHz) are the same as Multiple Sample CLIP. You can set lower sample rates with the external Sample Clock.

This CLIP presents the data to the diagram at a clock rate such that the ADC data lands at the same rate as the ADC clock. However, the DAC data must be presented in two time samples per clock on each channel.

– Internal Sample Clock

– Internal Sample Clock locked to an external Reference Clock through the CLK IN

connector

– External Sample Clock through the CLK IN connector

– Internal Sample Clock locked to an external Reference Clock through

IoModSyncClock

– External Sample Clock through IoModSyncClock

Refer to the NI FlexRIO Help for more information about NI FlexRIO CLIP items, how to configure the NI 5782 with a socketed CLIP, and for a list of available socketed CLIP signals.

Connecting Cables

•Use any 50Ω SMA cable to connect signals to the connectors on the front panel of your

NI 5782.

• Use the SHH19-H19-AUX cable (NI part number: 152629-01 or 152629-02) to connect to the DIO and PFI signals on the AUX I/O connector.

For more information about connecting I/O signals on your device, refer to the Appendix A:

Specifications section of this document.

Clocking

The NI 5782 clocks control the sample rate and other timing functions on the device. Table 4 contains information about the possible NI 5782 clock resources.

Table 4. NI 5782 Clock Sources

Clock Frequency Source Options

Internal Clock PLL Off

Internal Clock PLL On (IoModSyncClock)

Internal Clock PLL On (CLK IN)

External Clock (CLK IN)

500 MHz The internal voltage-controlled oscillator (VCO) acts

as a free-running clock.

500 MHz The internal VCO locks to PXI_CLK10 through

IoModSyncClock, which is available only through the backplane of NI PXIe-796xR devices.

500 MHz The internal VCO locks to an external Reference

Clock (10 MHz). Connect the external Reference Clock through the CLK IN front panel connector.

250 MHz to

1 GHz

Connect an external Sample Clock through the CLK IN front panel connector.

10 | ni.com | NI 5782R User Manual and Specifications

Using Your NI 5782R with a LabVIEW FPGA Example VI

Note You must install the software before running this example. Refer to the

NI FlexRIO FPGA Module Installation Guide and Specifications for more information about installing your software.

The NI FlexRIO Adapter Module Support software includes example projects to help you get started creating your LabVIEW FPGA application. This section explains how to use an existing LabVIEW FPGA example project to generate and acquire samples with the NI 5782R. This example requires at least one SMA cable to connect signals to your NI 5782R.

Note The examples available for your device depend on the version of the software

and driver you are using. For more information about which software versions are compatible with your device, visit the text field.

Each NI 5782R example project includes the following components:

• A LabVIEW FPGA VI that can be compiled and run on the FPGA embedded in the hardware

ni.com/info and enter rdsoftwareversion in

• A VI that runs on Windows and interacts with the LabVIEW FPGA VI

Note In the LabVIEW FPGA Module software, NI FlexRIO adapter modules are

referred to as IO Modules.

Complete the following steps to run an example that acquires a waveform on CH 0 of the NI 5782.

1. Connect one end of an SMA cable to AI 0 on the front panel of the NI 5782 and the other end of the cable to your device under test (DUT).

2. Launch LabVIEW.

3. Click Help»Find Examples to display the NI Example Finder.

4. In the NI Example Finder window, select Hardware Input and Output»FlexRIO» IO Modules»NI 5782.

5. Select NI 5782 - Getting Started.lvproj.

6. In the Project Explorer window, open NI 5782 - Getting Started (Host).vi under My Computer to open the host VI. The Open FPGA VI Reference function in this VI uses the NI 7952R as the FPGA target by default. If you are using an NI FlexRIO FPGA module other than the NI 7952R, complete the following steps to change to the FPGA VI to support your target.

a. Select Window»Show Block Diagram to open the VI block diagram.

b. On the block diagram, right-click the Open FPGA VI Reference (PXI-7952R)

function and select Configure Open FPGA VI Reference.

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National Instruments NI 5782R, 5782R Specifications

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