National Instruments NI 5412 User Manual

NI 5412 Specifications

NI PXI/PCI-5412 14-Bit 100 MS/s Arbitrary Waveform Generator

Unless otherwise noted, the following conditions were used for each
specification:

• Interpolation set to maximum allowed factor for a given sample rate.

• Signals terminated with 50 Ω.

• Low-Gain Amplifier Path set to 2 V
Path set to 12 V

• Sample clock set to 100 MS/s.

Typical values are representative of an average unit operating at room
temperature. Specifications are subject to change without notice. For the
most recent NI 5412 specifications, visit

To access all the NI 5412 documentation, including the NI Signal
Generators Getting Started Guide, which contains functional descriptions
of the NI 5412 signals, navigate to Start»Programs»National
Instruments»NI-FGEN»Documentation.

Caution Hot Surface Allow the NI 5412 to cool before removing it from the chassis to reduce

risk of burns. Use caution when handling because recently used NI 5412 devices may
exceed safe handling temperatures.

pk-pk

.

, and High-Gain Amplifier

pk-pk

ni.com/manuals.

Contents

CH 0 ........................................................................................................ 2

Sample Clock .......................................................................................... 7

Onboard Clock ........................................................................................ 10

Phase-Locked Loop (PLL) Reference Clock .......................................... 10

CLK IN ................................................................................................... 11

PFI 0 and PFI 1 ....................................................................................... 12

Start Trigger ............................................................................................ 13

Markers ................................................................................................... 15

Waveform and Instruction Memory Utilization...................................... 16

Calibration............................................................................................... 18

Power ...................................................................................................... 18

Software .................................................................................................. 19

Environment............................................................................................ 20

Safety, Electromagnetic Compatibility, and CE Compliance................. 22

Physical ...................................................................................................24

Where to Go for Support......................................................................... 25

CH 0

(Channel 0 Analog Output, Front Panel Connector)

Table 1.

Specification Val ue Comments

Number of
Channels

Connector SMB (jack) —

Output Voltage Characteristics

Output Paths The software-selectable Main Output Path setting provides

DAC
Resolution

Amplitude and Offset

Amplitude
Range

1 —

full-scale voltages from 12.00 V
50 Ω load. NI-FGEN uses either the Low-Gain Amplifier or
the High-Gain Amplifier when the Main Output Path is
selected, depending on the Gain attribute.

14 bits —

Path Load

Low-

Gain

Amplifier

High-

Gain

Amplifier

50 Ω 0.00564 2.00

1 kΩ 0.0107 3.81

Open 0.0113 4.00

50 Ω 0.0338 12.0

1 kΩ 0.0644 22.9

Open 0.0676 24.0

Minimum Value Maximum Value

to 5.64 mV

pk-pk

Amplitude (V

into a

pk-pk

) 1. Amplitude

pk-pk

values assume
the full scale
of the DAC is
utilized. If an
amplitude
smaller than
the minimum
value is
desired, then
waveforms less
than full scale
of the DAC can
be used.

—

Amplitude
Resolution

Offset Range Span of ±25% of Amplitude Range with increments

NI 5412 Specifications 2 ni.com

3 digits —

—

<0.0014% of Amplitude Range.

Table 1. (Continued)

Specification Val ue Comments

Maximum Output Voltage

Maximum

Path Load Maximum Output Voltage (V
Output
Vo l t a g e

Low-

Gain

Amplifier

50 Ω ±1.000

1 kΩ ±1.905

Open ±2.000

High-

Gain

Amplifier

50 Ω ±6.000

1 kΩ ±11.43

Open ±12.00

Accuracy

DC Accuracy ±0.2% of Amplitude ± 0.05% of Offset ± 500 µV

(within ±10 °C of self-calibration temperature)

±0.4% of Amplitude ± 0.05% of Offset ± 1 mV
(0 °C to 55 °C)

AC Amplitude

±1.0% of desired Amplitude ± 1 mV 50 kHz sine

Accuracy

Output Characteristics

Output

50 Ω or 75 Ω nominal, software-selectable. —

Impedance

) The Maximum

pk-pk

Output Voltage
of the NI 5412 is
determined by
the Amplitude
Range and the
Offset Range.

Calibrated for
high impedance
load.

wave.

Output

DC —

Coupling

Output Enable Software-selectable. When the Output Path is disabled, the

—
CH 0 Output is terminated to ground with a 1 W resistor
equal to the selected output impedance.

Maximum
Output
Overload

Waveform
Summing

The CH 0 output can be connected to a 50 Ω, ±12 V source
without sustaining any damage. No damage occurs if the
CH 0 output is shorted to ground indefinitely.

The CH 0 output supports waveform summing among
similar paths—specifically, the outputs of multiple NI 5412

—

—

signal generators can be connected directly together.

© National Instruments Corporation 3 NI 5412 Specifications

Table 1. (Continued)

Specification Val ue Comments

Frequency and Transient Response

Bandwidth 20 MHz –3 dB

Digital
Interpolation

Software-selectable Finite Impulse Response (FIR) filter.
Available interpolation factors are 2, 4, or 8.

Filter

Passband
Flatness

Pulse
Response

Low-Gain and High-Gain Amplifiers Path —

±1.0 dB from DC to 6 MHz

Path All values are

Low-Gain Amplifier High-Gain Amplifier

Rise/Fall Time <20 ns <20 ns

Aberration <5% <5%

—

typical.
Measured with a
1 m RG-223
cable.

NI 5412 Specifications 4 ni.com

2.0

1.6

1.2

0.8

0.4

0.0

Amplitude (V)

–0.4

–0.8

–1.2

–1.6

–2.0

0 0.2 0.4 0.6 0.8 1.0

Time (

µs)

Figure 1. Pulse Response, Low-Gain Amplifier Path 50 Ω Load

© National Instruments Corporation 5 NI 5412 Specifications

Table 1. (Continued)

Specification Val ue Comments

Suggested Maximum Frequencies for Common Functions

Function Path —

Low-Gain Amplifier High-Gain Amplifier

Sine 20 MHz 20 MHz

Square 5 MHz 5 MHz

Ramp 1 MHz 1 MHz

Triangle 1 MHz 1 MHz

Spectral Characteristics

Spurious-Free

Path Amplitude
Dynamic
Range
(SFDR)
without
Harmonics

Low-Gain Amplifier High-Gain Amplifier

1 MHz –70 dBc –70 dBc

10 MHz –65 dBc –65 dBc

20 MHz –60 dBc –60 dBc

0 ºC to 40 ºC

Path Amplitude
Total
Harmonic
Distortion
(THD)

Low-Gain Amplifier High-Gain Amplifier

1 MHz –59 dBc –51 dBc

10 MHz –52 dBc –40 dBc

20 MHz –45 dBc –37 dBc

–1 dBFS.
Measured from
DC to 50 MHz.
SFDR without
harmonics at low
amplitudes is
limited by a
–148 dBm/Hz
noise floor. All
values are
typical.

–1 dBFS.
Includes the 2
through the 6

nd

th

harmonic. All
values are
typical.

NI 5412 Specifications 6 ni.com

Table 1. (Continued)

Specification Val ue Comments

Spectral Characteristics (Continued)

Average Noise
Density

Path

Low-Gain 2 10 45 –134 –144

High­Gain

Amplitude

Range

V

pk-pk

12 25.6 251 –119 –145

dBm dBm/Hz

Average Noise Density

nV

-----------

Hz

dBFS/

Hz

Average Noise
Density at small
amplitudes is
limited by a
–148 dBm/Hz
noise floor.

Sample Clock

Table 2.

Specification Val ue Comments

Sources 1. Internal, Divide-by-N (N ≥ 1)

2. Internal, DDS-based, High-Resolution

3. External, CLK IN (SMB front panel connector)

4. NI PXI-5412: External, PXI Star trigger

(backplane connector)

5. NI PXI-5412: External, PXI_Trig<0..7>

(backplane connector)
NI PCI-5412: External, RTSI<0..7>

Refer to the

Onboard Clock

section for more
information
about Internal
Clock Sources.

© National Instruments Corporation 7 NI 5412 Specifications

Table 2. (Continued)

Specification Val ue Comments

Sample Rate Range and Resolution

Sample Clock
Source

Sample Rate Range Sample Rate Resolution

Divide-by-N 23.84 S/s to 100 MS/s Settable to (100 MS/s) / N

(1 ≤ N ≤ 4,194,304)

High-

10 S/s to 100 MS/s 1.06 µHz

Resolution

CLK IN 200 kS/s to 105 MS/s Resolution determined by

NI PXI-5412

PXI Star
Trigger

NI PXI-5412

10 S/s to 105 MS/s

10 S/s to 20 MS/s

external clock source.

External Sample Clock duty
cycle tolerance 40% to 60%.

PXI_Trig<0..7>

NI PCI-5412

10 S/s to 20 MS/s

RTSI<0..7>

Effective Sample Rate

Sample Rate

(MS/s)

10 S/s to

105 MS/s

12.5 MS/s to
105 MS/s

Interpolation

Effective Sample

Factor

1 (Off) 10 S/s to

105 MS/s

2 25 MS/s to

210 MS/s

Rate

—

Effective Sample
Rate =
(Interpolation
Factor) * (Sample
Rate)

10 MS/s to

100 MS/s

10 MS/s to

50 MS/s

4 40 MS/s to

400 MS/s

8 80 MS/s to

400 MS/s

Sample Clock Delay Range and Resolution

Sample Clock
Source

Delay Adjustment Range

Delay Adjustment

Resolution

—

Divide-by-N ±1 sample clock period <10 ps

High­Resolution

NI 5412 Specifications 8 ni.com

±1 sample clock period Sample Clock

Period/16,384

Table 2. (Continued)

Specification Val ue Comments

System Phase Noise and Jitter (10 MHz Carrier)

Sample Clock
Source

System Phase Noise

Density

(dBc/Hz) Offset

100 Hz 1 kHz 10 kHz

System Output Jitter

(Integrated from

100 Hz to 100 kHz)

NI PXI-5412 –100 –118 –120 <6 ps rms

NI PCI-5412 –90 –110 –120 <7 ps rms

External
Sample Clock
Input Jitter

Cycle-Cycle Jitter ±300 ps

Period Jitter ±1 ns

Tolerance

Sample Clock Exporting

Exported
Sample Clock
Destinations

1. PFI<0..1> (SMB front panel connectors)

2. NI PXI-5412: PXI_Trig<0..6> (backplane connector)

NI PCI-5412: RTSI<0..6>

Exported
Sample Clock
Destinations

Maximum Frequency Duty Cycle

PFI<0..1> 105 MHz 25% to 65%

1. High­Resolution
specifications
vary with
Sample Rate.

2. All values are
typical.

—

Exported Sample
Clocks can be
divided by integer
K (1 ≤ K ≤
4,194,304).

—

NI PXI-5412

20 MHz —

PXI_Trig<0..6>

NI PCI-5412

20 MHz —

RTSI<0..6>

© National Instruments Corporation 9 NI 5412 Specifications

Onboard Clock

(Internal VCXO)

Table 3.

Specification Val ue Comments

Clock Source Internal sample clocks can either be locked to a Reference

Clock using a phase-locked loop or be derived from the
onboard VCXO frequency reference.

Frequency
Accuracy

±25 ppm —

—

Phase-Locked Loop (PLL) Reference Clock

Table 4.

Specification Val ue Comments

Sources 1. NI PXI-5412—PXI_CLK10 (backplane connector)

NI PCI-5412—RTSI_7 (RTSI_CLK)

2. CLK IN (SMB front panel connector)

Frequency
Accuracy

When using the PLL, the Frequency Accuracy of the
NI 5412 is solely dependent on the Frequency Accuracy
of the PLL Reference Clock Source.

The PLL
Reference Clock
provides the
reference
frequency for the
phase-locked
loop.

—

Lock Time ≤ 200 ms. —

Frequency
Range

Duty Cycle
Range

Exported PLL
Reference
Clock
Destinations

NI 5412 Specifications 10 ni.com

5 MHz to 20 MHz in increments of 1 MHz.
Default of 10 MHz.

The PLL Reference Clock Frequency has to be accurate
to ±50 ppm.

40% to 60% —

1. PFI<0..1> (SMB front panel connectors)

2. NI PXI-5412—PXI_Trig<0..6> (backplane connector)
NI PCI-5412—RTSI<0..6>

—

—

CLK IN

(Sample Clock and Reference Clock Input, Front Panel Connector)

Table 5.

Specification Val ue Comments

Connector SMB (jack) —

Direction Input —

Destinations 1. Sample Clock

—

2. PLL Reference Clock

Frequency
Range

1 MHz to 105 MHz (Sample Clock destination and
sine waves)

—

200 kHz to 105 MHz (Sample Clock destination and
square waves)

5 MHz to 20 MHz (PLL Reference Clock destination)

Input Voltage
Range

Maximum

Sine wave: 0.65 V

pk-pk

to 2.8 V

pk-pk

into 50 Ω

—

(0 dBm to +13 dBm)

Square wave: 0.2 V

pk-pk

to 2.8 V

into 50 Ω

pk-pk

±10 V —

Input Overload

Input

50 Ω —

Impedance

Input Coupling AC —

© National Instruments Corporation 11 NI 5412 Specifications

PFI 0 and PFI 1

(Programmable Function Interface, Front Panel Connectors)

Table 6.

Specification Val ue Comments

Connectors Two SMB (jack) —

Direction Bi-directional —

Frequency
Range

As an Input (Trigger)

Destinations Start Trigger —

Maximum
Input Overload

V

IH

V

IL

Input
Impedance

As an Output (Event)

Sources 1. Sample Clock divided by integer K (1 ≤ K ≤ 4,194,304)

DC to 105 MHz —

–2 V to +7 V —

2.0 V

0.8 V

1 kΩ

—

2. Sample Clock Timebase (100 MHz) divided by
integer M (2 ≤ M ≤ 4,194,304)

3. PLL Reference Clock

4. Marker

5. Exported Start Trigger (Out Start Trigger)

Output
Impedance

Maximum
Output
Overload

NI 5412 Specifications 12 ni.com

50 Ω —

–2 V to +7 V —

Table 6. (Continued)

Specification Val ue Comments

V

OH

Minimum: 2.9 V (open load), 1.4 V (50 Ω load) Output drivers are

+3.3 V TTL
compatible.
Measured with a

V

OL

Rise/Fall Time

Maximum: 0.2 V (open load), 0.2 V (50 Ω load)

≤2.0 ns Load of 10 pF.

1 m cable.

(20% to 80%)

Start Trigger

Table 7.

Specification Val ue Comments

Sources 1. PFI<0..1> (SMB front panel connectors)

2. NI PXI-5412—PXI_Trig<0..7> (backplane connector)
NI PCI-5412—RTSI<0..7>

3. NI PXI-5412—PXI Star trigger (backplane connector)

4. Software (use function call)

5. Immediate (does not wait for a trigger). Default.

Modes 1. Single

—

—

2. Continuous

3. Stepped

4. Burst

Edge Detection Rising —

Minimum
Pulse Width

© National Instruments Corporation 13 NI 5412 Specifications

25 ns. Refer to ts1 at NI Signal Generators Help»Devices»
NI 5412»NI <bus>-5412»Triggering»Trigger Timing.

—

Table 7. (Continued)

Specification Val ue Comments

Delay from
Start Trigger to
CH 0 Analog
Output

Trigger Exporting

Exported
Trigger
Destinations

Exported
Trigger Delay

Exported
Trigger Pulse
Width

Interpolation Factor Typical Delay Refer to ts2 at

Digital Interpolation Filter
disabled.

2 57 Sample Clock

43 Sample Clock
Periods + 110 ns

Periods + 110 ns

NI Signal
Generators
Help»Devices»
NI 5412»
NI <bus>-5412»
Triggering»

4 63 Sample Clock

Trigger Timing.

Periods + 110 ns

8 64 Sample Clock

Periods + 110 ns

A signal used as a trigger can be routed out to any
destination listed in the Destinations specification
of Table 8.

65 ns (typical). Refer to ts3 at NI Signal Generators Help»

Devices»NI 5412»NI <bus>-5412»Triggering»Trigger
Timing.

>150 ns. Refer to ts4 at NI Signal Generators Help»
Devices»NI 5412»NI <bus>-5412»Triggering»Trigger
Timing.

—

—

—

NI 5412 Specifications 14 ni.com

Markers

Table 8.

Specification Val ue Comments

Destinations 1. PFI<0..1> (SMB front panel connectors)

2. NI PXI-5412—PXI_Trig<0..6> (backplane connector)
NI PCI-5412—RTSI<0..6>

Quantity One Marker per Segment. —

Quantum Marker position must be placed at an integer multiple of

four samples.

Width >150 ns. Refer to tm2 at NI Signal Generators Help»

Devices»NI 5412»NI <bus>-5412»Waveform
Generation»Marker Events.

Skew

Destination

PFI<0..1> ±2 Sample Clock Periods

NI PXI-5412

PXI_Trig<0..6>

NI PCI-5412 RTSI<0..6>

With Respect to Analog

Output

±2 Sample Clock Periods

Refer to tm1 at

NI Signal
Generators
Help»Devices»
NI 5412»
NI <bus>-5412»
Waveform
Generation»
Marker Events.

—

—

—

© National Instruments Corporation 15 NI 5412 Specifications

Waveform and Instruction Memory Utilization

Table 9.

Specification Val ue Comments

Memory Usage The NI 5412 uses the Synchronization and Memory Core

(SMC) technology in which waveforms and instructions
share onboard memory. Parameters, such as number of
segments in sequence list, maximum number of waveforms
in memory, and number of samples available for waveform
storage, are flexible and user defined.

Onboard
Memory Size

Output Modes Arbitrary Waveform mode and Arbitrary Sequence mode —

Arbitrary
Waveform
Mode

Arbitrary
Sequence
Mode

Minimum
Waveform Size
(Samples)

8 MB standard:
8,388,608 bytes

In Arbitrary Waveform mode, a single waveform is selected
from the set of waveforms stored in onboard memory and
generated.

In Arbitrary Sequence mode, a sequence directs the NI 5412
to generate a set of waveforms in a specific order. Elements
of the sequence are referred to as segments. Each segment is
associated with a set of instructions. The instructions
identify which waveform is selected from the set of
waveforms in memory, how many loops (iterations) of the
waveform are generated, and at which sample in the
waveform a marker output signal is sent.

Trigger Mode

Single 16 16

Continuous 16 96 @ >50 MS/s

32 MB option:
33,554,432 bytes

Arbitrary

Waveform Mode

256 MB option:
268,435,456 bytes

Arbitrary

Sequence Mode

32 @ ≤50 MS/s

The Minimum
Waveform Size
is sample rate
dependent in
Arbitrary
Sequence Mode.

—

—

—

—

Stepped 32 96 @ >50 MS/s

32 @ ≤50 MS/s

Burst 16 512 @ >50 MS/s

256 @ ≤50 MS/s

NI 5412 Specifications 16 ni.com

Table 9. (Continued)

Specification Val ue Comments

Loop Count 1 to 16,777,215.

—

Burst trigger: Unlimited

Quantum Waveform size must be an integer multiple of four samples. —

Memory Limits

8 MB Standard 32 MB Option 256 MB Option All trigger modes

Arbitrary
Waveform

4,194,176

Samples

16,777,088

Samples

134,217,600

Samples

except where
noted.

Mode,
Maximum
Waveform
Memory

Arbitrary
Sequence
Mode,

4,194,120

Samples

16,777,008

Samples

134,217,520

Samples

Condition: One
or two segments

in a sequence.
Maximum
Waveform
Memory

Arbitrary
Sequence
Mode,

65,000

Burst trigger:

8,000

262,000

Burst trigger:

32,000

2,097,000

Burst trigger:

262,000

Condition: One

or two segments

in a sequence.
Maximum
Waveforms

Arbitrary
Sequence
Mode,
Maximum

104,000

Burst trigger:

65,000

418,000

Burst trigger:

262,000

3,354,000

Burst trigger:

2,090,000

Condition:

Waveform

memory is

<4,000 samples.
Segments in a
Sequence

© National Instruments Corporation 17 NI 5412 Specifications

Calibration

Table 10.

Specification Val ue Comments

Self-Calibration An onboard, 24-bit ADC and precision voltage reference are

used to calibrate the DC gain and offset. The self-calibration
is initiated by the user through the software and takes
approximately 75 seconds to complete.

External
Calibration

Calibration
Interval

Warm-up Time 15 minutes —

The External Calibration calibrates the VCXO, voltage
reference, DC gain, and offset. Appropriate constants are
stored in nonvolatile memory.

Specifications valid within 2 years of External Calibration. —

—

—

Power

Table 11.

Specification Normal Operation Overload Operation Comments

Total Power 22 W 26 W Typical.

Overload
operation occurs
when CH 0 is
shorted to
ground.

NI 5412 Specifications 18 ni.com

Software

Table 12.

Specification Val ue Comments

Driver
Software

Application
Software

Soft Front
Panel/
Interactive
Configuration

NI-FGEN 2.3 or later version. NI-FGEN is an
IVI-compliant driver that allows you to configure, control,
and calibrate the NI 5412. NI-FGEN provides application
programming interfaces for many development
environments.

NI-FGEN provides programming interfaces for the
following application development environments:

•LabVIEW

™

• LabWindows

/CVI

™

• Measurement Studio

• Microsoft Visual C++ .NET

• Microsoft Visual C/C++

• Microsoft Visual Basic

The FGEN Soft Front Panel 2.3 or later supports interactive
control of the NI 5412. The FGEN Soft Front Panel is
included on the NI-FGEN driver CD.

Measurement & Automation Explorer (MAX) also provides
interactive configuration and test tools for the NI 5412.
MAX is also included on the NI-FGEN CD.

—

—

—

© National Instruments Corporation 19 NI 5412 Specifications

Environment

NI PXI-5412 Environment

Note To ensure that the NI PXI-5412 cools effectively, follow the guidelines in the

Maintain Forced-Air Cooling Note to Users included in the NI 5412 kit. The NI PXI-5412
is intended for indoor use only.

Table 13.

Specifications Val ue Comments

Operating
Temperature

Storage
Temperature

Operating
Relative
Humidity

Storage
Relative
Humidity

Operating
Shock

Storage Shock 50 g, half-sine, 11 ms pulse. Meets IEC-60068-2-27. Test

Operating
Vibration

0 ºC to +55 ºC in all NI PXI chassis except the following:

0 ºC to +45 ºC when installed in an NI PXI-101x or
NI PXI-1000B chassis.

Meets IEC-60068-2-1 and IEC-60068-2-2.

–25 ºC to +85 ºC. Meets IEC-60068-2-1 and
IEC-60068-2-2.

10% to 90%, noncondensing. Meets IEC-60068-2-56. —

5% to 95%, noncondensing. Meets IEC-60068-2-56. —

30 g, half-sine, 11 ms pulse. Meets IEC-60068-2-27. Test
profile developed in accordance with MIL-PRF-28800F.

profile developed in accordance with MIL-PRF-28800F.

5 Hz to 500 Hz, 0.31 g

. Meets IEC-60068-2-64. Spectral and jitter

rms

—

—

Spectral and jitter
specifications
could degrade.

—

specifications
could degrade.

Storage
Vibration

Altitude 2,000 m maximum (at 25 °C ambient temperature) —

Pollution
Degree

NI 5412 Specifications 20 ni.com

5 Hz to 500 Hz, 2.46 g
profile exceeds requirements of MIL-PRF-28800F, Class B.

2 —

. Meets IEC-60068-2-64. Test

rms

—

NI PCI-5412 Environment

Note To ensure that the NI PCI-5412 cools effectively, follow the guidelines in the

Maintain Forced-Air Cooling Note to Users included in the NI 5412 kit. Also, to maximize
airflow and extend the life of the device, leave any adjacent PCI slots empty. The
NI PCI-5412 is intended for indoor use only.

Table 14.

Specifications Val ue Comments

Operating

0 ºC to +45 ºC. Meets IEC-60068-2-1 and IEC-60068-2-2. —

Temperature

Storage
Temperature

Operating

–25 ºC to +85 ºC. Meets IEC-60068-2-1 and

—

IEC-60068-2-2.

10% to 90%, noncondensing. Meets IEC-60068-2-56. —
Relative
Humidity

Storage

5% to 95%, noncondensing. Meets IEC-60068-2-56. —
Relative
Humidity

Storage
Shock

Storage
Vibration

50 g, half-sine, 11 ms pulse. Meets IEC-60068-2-27. Test

profile developed in accordance with MIL-PRF-28800F.

5 Hz to 500 Hz, 2.46 g

. Meets IEC-60068-2-64. Test

rms

profile exceeds requirements of MIL-PRF-28800F, Class B.

—

—

Altitude 2,000 m maximum (at 25 °C ambient temperature) —

Pollution

2 —
Degree

© National Instruments Corporation 21 NI 5412 Specifications

Safety, Electromagnetic Compatibility, and CE Compliance

Table 15.

Specification Val ue Comments

Safety The NI 5412 meets the requirements of the following

standards for safety and electrical equipment for
measurement, control, and laboratory use:

• IEC 61010-1, EN 61010-1

• UL 61010-1

• CAN/CSA C22.2 No. 61010-1

Emissions EN 55011 Class A at 10 m

FCC Part 15A above 1 GHz

Immunity EN 61326:1997 + A2:2001, Table 1

Up to 4 mVpp noise (about –44 dBm) may be present
on the output during the conducted immunity test. Use
of the product at levels below –44 dBm will result in
self-recoverable errors.

For UL and
other safety
certifications,
refer to the
product label or
to

ni.com/

certification

search by model
number or
product line,
and click the
appropriate
link in the
Certification
column.

—

—

,

Good screening (shielding) techniques must be
employed throughout the user’s data acquisition
system.

NI 5412 Specifications 22 ni.com

Table 15. (Continued)

Specification Val ue Comments

EMC/EMI CE, C-Tick, and FCC Part 15 (Class A) Compliant

—

Notes:

1. This device is not intended for, and is restricted
from, use in residential areas.

2. For EMC compliance, operate this device with
shielded cabling.

3. When connected to other test objects, this product
may cause radio interference. If this occurs, you
may be required to take adequate measures to
reduce the interference.

This product meets the essential requirements of applicable European Directives as amended for
CE marking, as follows:

Low-Voltage

73/23/EEC —

Directive (safety)

Electromagnetic

89/336/EEC —
Compatibility
Directive (EMC)

Note: Refer to the Declaration of Conformity (DoC) for this product for any additional regulatory
compliance information. To obtain the DoC for this product, visit

ni.com/certification,

search by model number or product line, and click the appropriate link in the Certification column.

© National Instruments Corporation 23 NI 5412 Specifications

Physical

Table 16.

Specification Val ue Comments

NI PXI-5412 NI PCI-5412

Dimensions

Weight 340 g

Front Panel Connectors

Label Function(s) Connector Type —

CH 0 Analog Output SMB (jack)

CLK IN Sample clock input and PLL

PFI 0 Marker output, trigger input,

PFI 1 Marker output, trigger input,

Single 3U PXI slot.

CompactPCI compatible.

2.0 × 13.0 × 21.6 cm

(0.8 × 5.1 × 8.5 inches)

(11 oz)

reference clock input.

sample clock output,
exported trigger output, and
PLL reference clock output.

sample clock output,
exported trigger output, and
PLL reference clock output.

34.07 × 10.67 × 2.03 cm

(13.4 × 4.20 × 0.8 inches)

480 g

(17 oz)

SMB (jack)

SMB (jack)

SMB (jack)

—

—

NI PXI-5412 Only—Front Panel LED Indicators

Label Function For more

ACCESS LED The ACCESS LED indicates the status of the PCI bus and

the interface from the NI 5412 to the controller.

ACTIVE LED The ACTIVE LED indicates the status of the onboard

generation hardware of the NI 5412.

Included Cable

1 (NI part number 763541-01), 50 Ω, BNC Male to SMB
Plug, RG223/U, Double Shielded, 1 m cable.

NI 5412 Specifications 24 ni.com

information, refer
to the NI Signal

Generators Help.

—

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