National Instruments NAT9914 Reference Manual

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NAT9914

Reference Manual

June 1995 Edition

Part Number 370876A-01

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Limited Warranty

The NAT9914™ integrated circuit (“equipment”) is warranted against defects in material and workmanship under normal use and service for a period of one (1) year from the date of shipment from the National Instruments factory. During this period of one year, National Instruments shall at its sole option either repair, replace, or credit the Buyer for defective equipment if: (i) Buyer returns the equipment to National Instruments, FOB the National Instruments factory in Austin, Texas; (ii) Buyer notifies National Instruments promptly upon discovery of any defect in writing, including a detailed description of the defect; and (iii) upon examination of the returned equipment, National Instruments is satisfied that the circuit is defective and that the cause of such defect is not alteration or repair by someone other than National Instruments, neglect, accident, misuse, improper installation, or use contrary to any instructions issued by National Instruments.

A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work. Prior to issuance of an RMA by National Instruments, Buyer shall allow National Instruments the opportunity to inspect the equipment on-site at Buyer’s facility.

This warranty expires one year from date of original shipment regardless of any warranty performance during that warranty period. The warranty provided herein is Buyer’s sole and exclusive remedy for nonconformity of the equipment or for breach of any warranty. THE ABOVE IS IN LIEU OF ALL OTHER WARRANTIES EXPRESSED OR IMPLIED. NATIONAL INSTRUMENTS SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. BUYER’S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE BUYER. NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS, OR INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY THEREOF. This limitation of the liability of National Instruments will apply regardless of the form of action, whether in contract or tort, including negligence. National Instruments recommends against the use of its products as critical components in any life support devices or systems whose failure to perform can reasonably be expected to cause significant injury to a human. Buyer assumes all risk for such application and agrees to indemnify National Instruments for all damages which may be incurred due to use of the National Instruments standard devices in medical or life support applications. Any action against National Instruments must be brought within one year after the cause of action accrues.

National Instruments believes that the information in this manual is accurate. The document has been carefully reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition. The reader should consult National Instruments if errors are suspected. In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it.

Copyright

Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written consent of National Instruments Corporation.

Trademarks

NAT9914™ is a trademark of National Instruments Corporation.

Product and company names listed are trademarks or trade names of their respective companies.

WARNING REGARDING MEDICAL AND CLINICAL

USE OF NATIONAL INSTRUMENTS PRODUCTS

National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the part of the user or application designer. Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel, and all traditional medical safeguards, equipment, and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used. National Instruments products are NOT intended to be a substitute for any form of established process, procedure, or equipment used to monitor or safeguard human health and safety in medical or clinical treatment.

About This Manual ............................................................................................. xiii

Organization of This Manual ......................................................................... xiii

Conventions Used in This Manual................................................................. xiv

Related Documentation ................................................................................. xiv

Customer Communication ............................................................................. xv

Chapter 1 Introduction and General Description

IEEE 488 Capabilities.................................................................................... 1-1

CPU Interface Capabilities ............................................................................ 1-3

Typical System Interface ............................................................................... 1-4

Chapter 2 NAT9914 Architecture

NAT9914 Modes ........................................................................................... 2-3

Changing the NAT9914 Mode ........................................................ 2-3

....................................................................................... 2-1

Chapter 3 9914-Mode Interface Registers

9914 Register Map ......................................................................................... 3-1

The Page-In Condition ................................................................................... 3-3

Hidden Registers............................................................................................ 3-3

Accessory Read Register Map......................................................... 3-3

Accessory Register A (ACCRA) ..................................................... 3-5

Accessory Register B (ACCRB) ..................................................... 3-6

Accessory Register E (ACCRE) ..................................................... 3-8

Accessory Register F (ACCRF) ...................................................... 3-9

Accessory Register I (ACCRI)........................................................ 3-10

Address Register (ADR) ................................................................. 3-11

Address Status Register (ADSR)..................................................... 3-12

Auxiliary Command Register (AUXCR) ........................................ 3-15

Bus Control Register (BCR)/Bus Status Register (BSR) ................ 3-27

Command/Data Out Register (CDOR) ........................................... 3-29

Command Pass Through Register (CPTR) ..................................... 3-30

Data In Register (DIR) .................................................................... 3-31

End-of-String Register (EOSR)....................................................... 3-32

Internal Count Register (ICR) ......................................................... 3-33

Interrupt Mask Register 0 (IMR0)................................................... 3-35

Interrupt Status Register 0 (ISR0) ................................................... 3-35

Interrupt Mask Register 1 (IMR1)................................................... 3-39

Interrupt Status Register 1 (ISR1) ................................................... 3-39

....................................................................... 3-1

........................................................ 1-1

Contents

Interrupt Mask Register 2 (IMR2)................................................... 3-44

Interrupt Status Register 2 (ISR2) ................................................... 3-44

Parallel Poll Register (PPR) ............................................................ 3-48

Serial Poll Mode Register (SPMR) ................................................. 3-49

Serial Poll Status Register (SPSR) .................................................. 3-49

Chapter 4 7210-Mode Interface Registers

7210 Register Map ......................................................................................... 4-1

The Page-In State ........................................................................................... 4-3

How to Page-In................................................................................ 4-3

Hidden Registers............................................................................................ 4-3

Address Register Map ..................................................................... 4-3

Auxiliary Mode Register Map ......................................................... 4-4

Address Mode Register (ADMR) ................................................... 4-5

Address Register (ADR) ................................................................. 4-7

Address Register 0 (ADR0)............................................................. 4-8

Address Register 1 (ADR1)............................................................. 4-9

Address Status Register (ADSR)..................................................... 4-10

Auxiliary Mode Register (AUXMR)............................................... 4-13

Auxiliary Register A (AUXRA) ..................................................... 4-26

Auxiliary Register B (AUXRB) ...................................................... 4-28

Auxiliary Register E (AUXRE)....................................................... 4-30

Auxiliary Register F (AUXRF) ....................................................... 4-31

Auxiliary Register G (AUXRG) ..................................................... 4-32

Auxiliary Register I (AUXRI) ......................................................... 4-34

Bus Control Register (BCR)/Bus Status Register (BSR) ................ 4-36

Command/Data Out Register (CDOR) ........................................... 4-38

Command Pass Through Register (CPTR) ..................................... 4-39

Data In Register (DIR) .................................................................... 4-40

End-of-String Register (EOSR)....................................................... 4-41

Internal Count Register (ICR) ......................................................... 4-42

Internal Count Register 2 (ICR2) .................................................... 4-43

Interrupt Mask Register 0 (IMR0)................................................... 4-44

Interrupt Status Register 0 (ISR0) ................................................... 4-44

Interrupt Mask Register 1 (IMR1)................................................... 4-48

Interrupt Status Register 1 (ISR1) ................................................... 4-48

Interrupt Mask Register 2 (IMR2)................................................... 4-53

Interrupt Status Register 2 (ISR2) ................................................... 4-53

Parallel Poll Register (PPR) ............................................................ 4-57

Source/Acceptor Status Register (SASR) ....................................... 4-59

Serial Poll Mode Register (SPMR) ................................................. 4-61

Serial Poll Status Register (SPSR) .................................................. 4-61

Version Status Register (VSR)........................................................ 4-63

....................................................................... 4-1

NAT9914 Reference Manual vi © National Instruments Corp.

Chapter 5 Software Considerations

Chip Initialization Sequence .......................................................................... 5-1

1. Place the NAT9914 in 9914 Mode ............................................. 5-1

2. Make Sure the Local pon Message Is Asserted.......................... 5-1

3. Set the Clock Frequency............................................................. 5-2

4. Configure the Chip for GPIB Operation .................................... 5-2

A. Set the GPIB Address(es) ........................................... 5-2

B. Write the Initial Serial Poll Response ......................... 5-2

C. Configure the Initial Parallel Response ....................... 5-2

D. Set GPIB Handshake Parameters ................................ 5-2

5. Enable Interrupts ........................................................................ 5-3

6. Clear the Local pon Message ..................................................... 5-3

GPIB Talker or Listener Considerations ....................................................... 5-3

GPIB Addressing ............................................................................. 5-3

Logical and Physical Devices ........................................... 5-3

Normal and Extended Addressing .................................... 5-3

Implementing One Logical Device: Normal

Implementing One Logical Device: Extended

Implementing Two or More Logical Devices:

Using the edpa Bit ............................................................. 5-6

Detecting a GPIB Listener............................................................... 5-6

Programmed Implementation of a Talker and Listener................... 5-6

Sending GPIB Data Messages ....................................................................... 5-6

Basic Flow ....................................................................................... 5-6

Sending EOI or EOS ....................................................................... 5-7

T1 Delay Generation ....................................................................... 5-7

The T1 Delay .................................................................... 5-7

HSTS Definition ............................................................... 5-8

IEEE 488.1 Standard Requirements ................................. 5-8

T1 Delay: 9914 Mode ...................................................... 5-9

T1 Delay: 7210 Mode ...................................................... 5-9

Using nbaf ....................................................................................... 5-10

Receiving GPIB Data Messages .................................................................... 5-10

Basic Flow ....................................................................................... 5-10

Receiving END or EOS ................................................................... 5-10

Performing an RFD Holdoff on the Last Data Byte........................ 5-11

Using DMA/The ACCRQ* Pin ..................................................................... 5-11

Disabling ACCRQ* ......................................................................... 5-11

DMA Reads ..................................................................................... 5-12

DMA Writes .................................................................................... 5-12

Contents

................................................................................... 5-1

Addressing .......................................................... 5-4

Normal Addressing ............................................. 5-5

Extended Addressing .......................................... 5-5

Contents

Acceptor Handshake (AH) Holdoffs ............................................................. 5-12

The GPIB rdy Message and RFD Holdoffs..................................... 5-12

Generating the rdy Message.............................................. 5-13

Data-Receiving Modes...................................................... 5-13

Choosing a Data-Receiving Mode .................................... 5-14

DAC Holdoffs ................................................................................. 5-15

Determining When DAC Holdoffs Occur......................... 5-15

Device Status Reporting (Polling) ................................................................. 5-16

Requesting Service .......................................................................... 5-16

Asserting the SRQ Signal ................................................. 5-16

IEEE 488.2 Service Requesting ........................................ 5-16

TMS9914A-Style Service Requesting .............................. 5-16

Responding to Serial Polls............................................................... 5-17

Responding to Parallel Polls ........................................................... 5-17

Local Configuration .......................................................... 5-17

Remote Configuration ....................................................... 5-18

Disabling the Parallel Poll Response ................................ 5-18

Generating Hardware Interrupts .................................................................... 5-19

Remote/Local State Considerations ............................................................... 5-19

Device Triggering .......................................................................................... 5-19

Device Clearing ............................................................................................. 5-20

Chapter 6 Controller Software Considerations

System Controller Considerations ................................................................. 6-1

Becoming System Controller .......................................................... 6-1

Other System Controller Capabilities: Setting and

Clearing REN .................................................................... 6-2

Disabling System Controller Capabilities ....................................... 6-2

GPIB Controller Considerations .................................................................... 6-2

Initialization for Controllers ............................................................ 6-2

Three Basic Controller States.......................................................... 6-3

Idle Controller State .......................................................... 6-3

Active Controller State ..................................................... 6-3

Standby Controller State ................................................... 6-3

Determining the Active Basic Controller State................. 6-4

Changing Controller States ............................................................. 6-4

Idle State to Active State: Becoming CIC ....................... 6-4

Active State to Standby State............................................ 6-5

Standby State to Active State............................................ 6-5

Active State to Idle State: Passing Control ...................... 6-5

Sending Remote Multiline Messages (Commands) ........................ 6-6

Polling: Obtaining Status from Devices ......................................... 6-6

Conducting Serial Polls ..................................................... 6-7

Configuring Devices for Parallel Polls ............................. 6-7

Conducting Parallel Polls.................................................. 6-8

............................................................. 6-1

NAT9914 Reference Manual viii © National Instruments Corp.

Chapter 7 Hardware Considerations

Pin Descriptions ............................................................................................. 7-1

GPIB Transceiver Controls ............................................................. 7-1

TE...................................................................................... 7-1

CONT*.............................................................................. 7-1

GPIB Signal Pins ............................................................................. 7-2

GPIB Data Bus Pins ........................................................................ 7-2

CPU Register Control Pins.............................................................. 7-2

CE* and CPU Address Bus ............................................... 7-2

DBIN/WE* ....................................................................... 7-2

NAT9914 Data Bus ........................................................... 7-3

DMA Pins........................................................................................ 7-3

ACCRQ* ........................................................................... 7-3

ACCGR* ........................................................................... 7-3

Other Pins ........................................................................................ 7-3

INT* .................................................................................. 7-3

TR ..................................................................................... 7-4

RESET* ............................................................................ 7-4

CLK ................................................................................... 7-4

Interfacing to Common GPIB Transceivers .................................................. 7-6

Appendix A Common Questions

............................................................................................. A-1

Contents

................................................................................. 7-1

Appendix B Introduction to the GPIB

History of the GPIB ....................................................................................... B-1

The IEEE 488.1 Specification ....................................................................... B-2

IEEE 488.2 and SCPI Specifications ............................................................. B-2

Problems with IEEE 488.1 Compatible Devices............................. B-2

The IEEE 488.2 Solution................................................................. B-2

SCPI Specification........................................................................... B-3

GPIB Hardware Configuration ...................................................................... B-4

GPIB Signals and Lines................................................................... B-7

Data Lines ....................................................................................... B-7

Interface Management Lines ........................................................... B-8

Handshake Lines ............................................................................. B-11

.................................................................................. B-1

Interface Clear (IFC) ......................................................... B-8

Attention (ATN)................................................................ B-9

Remote Enable (REN) ...................................................... B-10

End-or-Identify (EOI) ....................................................... B-10

Service Request (SRQ) ..................................................... B-11

Not Ready For Data (NRFD) ............................................ B-11

Not Data Accepted (NDAC) ............................................. B-12

Data Valid (DAV) ............................................................. B-12

Three-Wire Handshake Process ........................................ B-13

Contents

Physical and Electrical Specifications ............................................. B-13

Controllers, Talkers, and Listeners ................................................................ B-14

Controllers ....................................................................................... B-14

Talkers and Listeners....................................................................... B-15

Data and Command Messages ....................................................................... B-17

GPIB Addressing Protocol............................................................................. B-17

Reading the Multiline Interface Command Messages Table .......... B-19

Secondary Addressing ..................................................................... B-19

Unaddressing Command Messages ................................................. B-19

Termination Methods ..................................................................................... B-19

EOS Method .................................................................................... B-20

EOI Method ..................................................................................... B-20

Count Method.................................................................................. B-20

Combinations of Termination Methods........................................... B-21

Serial Polling ................................................................................................. B-21

Servicing SRQs ............................................................................... B-21

Serial Polling Devices ..................................................................... B-21

Status Byte Model for IEEE 488.1 .................................................. B-23

ESR and SRE Registers ................................................................... B-23

Status Byte Model for IEEE 488.2 .................................................. B-23

Parallel Polling ............................................................................................... B-25

Overview of Parallel Polls ............................................................... B-25

Determining the Value of the PPR Message ..................... B-26

Configuring a Device for Parallel Polls ............................ B-26

Determining the PPE Message.......................................... B-27

Physical Representation of the PPR Message ................... B-27

Clearing and Triggering Devices ................................................................... B-28

Appendix C Standard Commands for Programmable Instruments (SCPI)

IEEE 488.2 Common Commands Required by SCPI ................................... C-2

SCPI Required Commands ............................................................................ C-3

SCPI Optional Commands ............................................................................. C-3

Programming with SCPI ................................................................................ C-4

Constructing SCPI Commands by Using the Hierarchical

Command Structure ......................................................................... C-5

Parsing SCPI Commands ................................................................ C-7

......... C-1

Appendix D Multiline Interface Command Messages

.................................................... D-1

Appendix E Mnemonics Key

..................................................................................................... E-1

Appendix F Customer Communication

NAT9914 Reference Manual x © National Instruments Corp.

............................................................................... F-1

Contents

Glossary.................................................................................................................... G-1

Index .......................................................................................................................... I-1

Figures

Figure 1-1. NAT9914 Implementation Block Diagram......................................... 1-4

Figure 2-1. NAT9914 Block Diagram ................................................................... 2-2

Figure 2-2. Changing the NAT9914 Mode............................................................ 2-3

Figure 3-1. GPIB I/O Hardware Configuration ..................................................... 3-28

Figure 4-1. GPIB I/O Hardware Configuration ..................................................... 4-37

Figure 6-1. Basic Controller States........................................................................ 6-3

Figure 7-1. CLK Signal Timing Diagram.............................................................. 7-5

Figure 7-2. Interfacing the NAT9914 to the 75160 and 75162 Transceivers........ 7-6

Figure B-1. Structure of the GPIB Standards ......................................................... B-3

Figure B-2. Linear Configuration ........................................................................... B-5

Figure B-3. Star Configuration ............................................................................... B-6

Figure B-4. GPIB Connector and Pin Assignments ............................................... B-7

Figure B-5. Three-Wire Handshake Process .......................................................... B-12

Figure B-6. System Setup Example ....................................................................... B-16

Figure B-7. Events During a Serial Poll ................................................................. B-22

Figure B-8. IEEE 488.2 Standard Status Structures ............................................... B-24

Figure B-9. Example Exchange of Messages During a Parallel Poll ..................... B-25

Figure C-1. Partial Command Categories .............................................................. C-4

Figure C-2. Simple Command Tree for the SENSe Command Subsystem ........... C-4

Figure C-3. Partial Command Tree for the SENSe Command Subsystem ............ C-5

Figure C-4. Partial Command Tree for the SOURce Command Subsystem ......... C-6

Figure C-5. Partial Command Tree for the TRIGger Command Subsystem ......... C-6

Contents

Tables

Table 1-1. NAT9914 IEEE 488 Interface Capabilities......................................... 1-1

Table 3-1. 9914-Mode Interface Registers ........................................................... 3-2

Table 3-2. Hidden Registers at the ACCR Offset ................................................ 3-3

Table 3-3. Auxiliary Command Summary ........................................................... 3-15

Table 3-4. Auxiliary Command Description ........................................................ 3-18

Table 4-1. 7210-Mode Register Map ................................................................... 4-2

Table 4-2. Hidden Registers at Offset 6 (ADR) ................................................... 4-3

Table 4-3. Hidden Registers at Offset 5 (AUXMR)............................................. 4-4

Table 4-4. Valid ADMR Patterns ......................................................................... 4-5

Table 4-5. Auxiliary Command Summary ........................................................... 4-14

Table 4-6. Auxiliary Command Description ........................................................ 4-17

Table 4-7. Clear Conditions for SISB Bit ............................................................ 4-35

Table 5-1. IEEE 488.1 Minimum T1 Delay Requirements.................................. 5-8

Table 5-2. T1 Delay Settings in 9914 Mode ........................................................ 5-9

Table 5-3. T1 Delay Settings in 7210 Mode ........................................................ 5-9

Table 5-4. ACCRQ* Pin Behavior ....................................................................... 5-11

Table 5-5. NAT9914 Data-Receiving Modes ...................................................... 5-14

Table 6-1. Active Basic Controller State.............................................................. 6-4

Table B-1. PPR Message Value ............................................................................ B-26

Table B-2. Determining the PPE Message............................................................ B-27

Table C-1. IEEE 488.2 Common Commands Required by SCPI ......................... C-2

Table C-2. SCPI Required Commands ................................................................. C-3

NAT9914 Reference Manual xii © National Instruments Corp.

About This Manual

This manual describes the programmable features of the NAT9914 and contains information that is suitable for programmers and engineers who wish to write software for the NAT9914.

This manual assumes that you are already familiar with general IEEE 488 concepts.

Organization of This Manual

This manual is organized as follows:

• Chapter 1, Introduction and General Description, explains the features and capabilities of the NAT9914.

• Chapter 2, NAT9914 Architecture, discusses the internal hardware architecture of the NAT9914.

• Chapter 3, 9914-Mode Interface Registers, contains NAT9914 address maps and detailed descriptions of the NAT9914 interface registers in 9914 mode.

• Chapter 4, 7210-Mode Interface Registers, contains NAT9914 address maps and detailed descriptions of the NAT9914 interface registers in 7210 mode.

• Chapter 5, Software Considerations, explains important NAT9914 programming considerations.

• Chapter 6, Controller Software Considerations, explains important GPIB Controller considerations.

• Chapter 7, Hardware Considerations, explains important NAT9914 hardwareinterfacing considerations, including a description of the pins.

• Appendix A, Common Questions, lists common questions and answers.

• Appendix B, Introduction to the GPIB, discusses the history of the GPIB, GPIB hardware configurations, and serial polling.

• Appendix C, Standard Commands for Programmable Instruments (SCPI), discusses the SCPI document, the required SCPI commands, and SCPI programming.

• Appendix D, Multiline Interface Command Messages, lists the multiline interface messages and describes the mnemonics and messages that correspond to the interface functions.

About This Manual

• Appendix E, Mnemonics Key, defines the mnemonics (abbreviations) that this manual uses for functions, remote messages, local messages, states, bits, registers, integrated circuits, and system functions.

• Appendix F, Customer Communication, contains forms you can use to request help from National Instruments or to comment on our products and manuals.

• The Glossary contains an alphabetical list and a description of the terms that this manual uses, including abbreviations, acronyms, metric prefixes, mnemonics, and symbols.

• The Index contains an alphabetical list of the key terms and topics that this manual uses, and it includes the page number where you can locate each term and topic.

Conventions Used in This Manual

This manual uses the following conventions.

italic Italic text denotes emphasis, a cross reference, or an

introduction to a key concept.

bold italic Bold italic text denotes a note, caution, or warning.

monospace Text in this font denotes programming examples.

IEEE 488 and IEEE 488 and IEEE 488.2 refer to the ANSI/IEEE IEEE 488.2 Standard 488.1-1987 and ANSI/IEEE Standard 488.2-1992,

respectively, which define the GPIB.

The Glossary lists abbreviations, acronyms, metric prefixes, mnemonics, symbols, and terms.

Customer Communication

National Instruments wants to receive your comments on our products and manuals. We are interested in the applications you develop with our products, and we want to help if you have problems with them. To make it easy for you to contact us, this manual contains comment and configuration forms for you to complete. These forms are in Appendix F, Customer Communication, at the end of this manual.

Chapter 1 Introduction and General Description

This chapter explains the features and capabilities of the NAT9914.

The NAT9914 is an IEEE 488.2 Controller chip designed to perform all the interface functions defined in the ANSI/IEEE Standard 488.1-1987 and the additional requirements and recommendations of the ANSI/IEEE Standard

488.2-1987. The NAT9914 manages the IEEE 488 interface functions with a set

of control and status registers that increase the throughput of driver software and simplify hardware and software design. The NAT9914 performs complete IEEE 488 Talker, Listener, and Controller functions and is software compatible with the NEC µPD7210 and TI TMS9914A chips.

The NAT9914 can be characterized as a bus translator: it converts messages and signals from the CPU into appropriate GPIB messages and signals. In GPIB terminology, the NAT9914 implements GPIB board and device functions to communicate with the central processor and memory. For the computer, the NAT9914 is an interface to the outside world.

IEEE 488 Capabilities

The National Instruments NAT9914 has the features necessary to provide a high-performance IEEE 488 interface. Table 1-1 lists the capabilities of the NAT9914 in terms of the IEEE 488 standard codes.

Table 1-1. NAT9914 IEEE 488 Interface Capabilities

Capability Code Description

SH1 Complete Source Handshake Capability

AH1 Complete Acceptor Handshake Capability;

DAC and RFD Holdoff on Certain Events

T5 Complete Talker Capability:

• Basic Talker

• Serial Poll

• Talk-Only Mode

• Unaddressed on MLA

• Send END or EOS

(continues)

Introduction and General Description Chapter 1

Table 1-1. NAT9914 IEEE 488 Interface Capabilities (Continued)

Capability Code Description

TE5 Complete Extended Talker Capability:

• Basic Extended Talker

• Serial Poll

• Talk-Only Mode

• Unaddressed on MSA & LPAS

• Send END or EOS

L3 Complete Listener Capability:

• Basic Listener

• Listen-Only Mode

• Unaddressed on MTA

• Detect END or EOS

LE3 Complete Extended Listener Capability:

• Basic Extended Listener

• Listen-Only Mode

• Unaddressed on MSA & TPAS

• Detect END or EOS

SR1 Complete Service Request Capability

RL1 Complete Remote/Local Capability

PP1 Remote Parallel Poll Configuration

PP2 Local Parallel Poll Configuration

DC1 Complete Device Clear Capability

DT1 Complete Device Trigger Capability

C1 through C5 Complete Controller Capability:

• System Controller

• Send IFC and Take Charge

• Send REN

• Respond to SRQ

• Send Interface Messages

• Received Control

• Parallel Poll

• Take Control Synchronously or Asynchronously

E2 Three-State Drivers (Open-Collector Drivers During Parallel

Polls)

NAT9914 Reference Manual 1-2 © National Instruments Corp.

Chapter 1 Introduction and General Description

The NAT9914 has complete Source and Acceptor Handshake capability. It can operate as a basic Talker or an extended Talker and can respond to a Serial Poll. If you place it in talk-only mode, it is unaddressed to talk when it receives its listen address. The NAT9914 GPIB interface can also operate as a basic Listener or an extended Listener. If you place it in listen-only mode, it is unaddressed to listen when it receives its talk address. The NAT9914 can request service from a Controller.

Device Clear and Trigger capability is included in the interface; the interpretation is software dependent.

Other GPIB features include the following:

• Messages not sent when there are no Listeners

• Automatic detection of EOS and/or New Line (NL) messages

• Programmable data transfer rates (T1 delays as short as 350 ns)

• Automatic processing of IEEE 488 commands and read-undefined commands

• Ability to use several addressing modes:

– Automatic single dual primary addressing detection

– Single primary with multiple secondary addressing

– Multiple primary addressing and multiple secondary addressing

CPU Interface Capabilities

• Software compatible with NEC µPD7210 and TI TMS9914A Controller chips

• DMA interface to the host system

• Flexible interrupt capabilities

• Uses only eight bytes of address space

Introduction and General Description Chapter 1

Typical System Interface

Figure 1-1 shows a block diagram of a typical application that uses the NAT9914 to implement an IEEE 488.2 interface.

CPU Bus

Control

Address

Decode

GPIB

XCVR

GPIB

Data

Interrupt

NAT9914

GPIB

XCVR

Figure 1-1. NAT9914 Implementation Block Diagram

In all applications, the NAT9914 must be connected to the GPIB via IEEE 488 compliant transceivers such as the 75160 and 75162, which are available from National Semiconductor and other vendors.

NAT9914 Reference Manual 1-4 © National Instruments Corp.

Chapter 2 NAT9914 Architecture

This chapter discusses the internal hardware architecture of the NAT9914.

The NAT9914 includes the following major components:

• Read/Write Control converts the CPU interface signals to read and write signals for each internal NAT9914 register.

• Internal NAT9914 Registers configure and control the operation of the NAT9914. They transfer data between the NAT9914 and the GPIB, report status information, and set the operating modes. Chapter 3, 9914-Mode Interface Registers, and Chapter 4, 7210-Mode Interface Registers, describe each register in detail.

• Interface Functions implement the interface functions described in the IEEE 488.1 standard. Some internal registers control the interface functions, and you can use other internal registers to monitor the status of interface functions. The interface functions drive and receive the GPIB control signals and generate the signals to control the GPIB transceivers.

• Message Decoders receive the GPIB data lines and decode the GPIB commands that affect the operation of the interface functions.

NAT9914 Architecture Chapter 2

Figure 2-1 contains a block diagram of the NAT9914.

D(7-0)

RS(2-0)

ACCRQ*

ACCGR*

INT* CLK

CE*

DBIN

WE*

Data-In

Read/

Write

Control

Command Pass Through

Command/Data Out

Address Status

Address Mode

Address

End-Of-String

Interrupt Mask 0, 1, 2

Interrupt Status 0, 1, 2

Internal Count

Internal Count 2

Serial Poll

Parallel Poll

Aux A, B, E, F, G, I

Compare Compare

Message

Decoder

Interface

Functions

SH1

AH1

T5/TE5

L3/LE3

SR1

RL1

PP1/PP2

DC1

DT1

C1-C5

RSV Gen

EOI Gen

STB Out

DIO(8-1)*

CONT* TE

SYNC

Bus Status

and Control

GPIB Control

RESET*

SASR

Auxiliary

Command Decoder

Version

Figure 2-1. NAT9914 Block Diagram

NAT9914 Reference Manual 2-2 © National Instruments Corp.

Chapter 2 NAT9914 Architecture

NAT9914 Modes

The NAT9914 has two basic modes of operation: 9914 mode and 7210 mode. In 9914 mode, the NAT9914 is software compatible with the TMS9914A IEEE 488 Controller. The NAT9914 has many registers and features that are not present in the TMS9914A. In 7210 mode, the NAT9914 is software compatible with the µPD7210 IEEE 488 Controller. The NAT9914 has many registers and features that are not present in the µPD7210.

Note: Throughout this manual, 7210 mode refers to the NEC µPD7210 software

compatibility mode, and 9914 mode refers to the TI TMS9914A software compatibility mode.

Changing the NAT9914 Mode

Figure 2-2 illustrates how you change the mode of the NAT9914.

sw9914 Auxiliary

Command

7210 Mode

sw7210 Auxiliary

Command

9914 Mode

Hardware Reset

Figure 2-2. Changing the NAT9914 Mode

Notice that the NAT9914 is in 9914 mode after a hardware reset. To change from 9914 mode to 7210 mode, write the sw7210 auxiliary command to the (9914 mode) Auxiliary Command Register (AUXCR). To change from 7210 mode to 9914 mode, write the sw9914 auxiliary command to the (7210 mode) Auxiliary Mode Register (AUXMR).

Chapter 3 9914-Mode Interface Registers

This chapter contains NAT9914 address maps and detailed descriptions of the NAT9914 interface registers in 9914 mode. For 7210-mode register descriptions, see Chapter 4, 7210-Mode Interface Registers.

9914 Register Map

Table 3-1 is the register bit map for the NAT9914 in 9914 mode.

Notice that bold-ruled cells distinguish six registers that are accessible only when the Page-In state is true. Refer to The Page-In Condition section that immediately follows the register map for more information.

9914-Mode Interface Registers Chapter 3

Table 3-1. 9914-Mode Interface Registers

Key

= 9914-Mode Paged Registers

= Read Register

= Write Register

76543210

ISR0 +0 INT0 INT1 BI BO END SPAS RLC MAC R

IMR0 +0 DMAO DMAI BI IE BO IE END IE SPAS IE RLC IE MA C IE W

ISR1 +1 GET ERR UNC APT DCAS MA SRQ IFC R

IMR1 +1 GET IE ERR IE UNC IE APT IE DCAS IE MA IE SRQ IE IFC IE W

ADSR +2 REM LLO ATN LPAS TPAS LA TA ulpa R

IMR2 +2 GLINT STBO IE NLEN 0 LLOC IE ATNI IE 0 CIC IE W

EOSR +2 EOS7 EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOS0 W

BCR +2 ATN DAV NDAC NRFD EOI SRQ IFC REN W

ACCR +2 ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0 W

BSR +3 ATN DAV NDAC NRFD EO I SRQ IFC REN R

AUXCR +3 C/S 0 0 F4 F3 F2 F1 F0 W

ISR2 +4 nba STBO NL EOS LLOC ATNI X CIC R

ADR +4 edpa dal dat A5 A4 A3 A2 A1 W

SPSR +5 S8 PEND S6 S5 S4 S3 S2 S1 R

SPMR +5 S8 rsv/RQS S6 S5 S4 S3 S2 S1 W

CPTR +6 CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0 R

PPR +6 PP8 PP7 PP6 PP5 PP4 PP3 PP2 PP1 W

DIR +7 DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 R

CDOR +7 DIO8 DIO7 DIO 6 DIO5 D IO4 DI O3 DI O2 DIO1 W

NAT9914 Reference Manual 3-2 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

The Page-In Condition

Four writable registers can appear at the same offset as the Address Status Register (ADSR) (offset 4). After a hardware or software reset, no writable register appears at the ADSR offset: the NAT9914 ignores writes to that offset.

One Page-In auxiliary command exists for each of the four registers. The host interface can make one of the four registers accessible by issuing the appropriate Page-In command to the Auxiliary Command Register (AUXCR). The paged-in register remains accessible at the ADSR offset until the host interface pages-in another register or issues the Clear Page-In Register auxiliary command.

When any one of the four writable registers is accessible at the ADSR offset, Interrupt Status Register 2 (ISR2) is accessible at the same offset as the Address Register (ADR), and the Serial Poll Status Register (SPSR) is accessible at the same offset as the Serial Poll Mode Register (SPMR).

Hidden Registers

In addition to the registers shown in Table 3-1, the NAT9914 contains hidden registers. All hidden registers are write-only registers. Two or more hidden registers can appear at the same offset. When you write an 8-bit pattern to these offsets, some of the bits determine which hidden register will be written. The other bits represent the value written to the register.

Accessory Read Register Map

Several hidden registers appear at the Accessory Register (ACCR) offset. Table 3-2 shows these hidden registers.

Table 3-2. Hidden Registers at the ACCR Offset

ICR 0010 F3 F2 F1 F0

ACCRA 1 0 0 BIN XEOS REOS 0 0

ACCRB 1 0 1 ISS INV LWC SPEOI ATCT

ACCRE 1100DHADT DHADC 0 0

ACCRF 1101DHATA DHALA DHUNTL DHALL

ACCRI 1110USTD PP1 0 DMAE

9914-Mode Interface Registers Chapter 3

Register Bit Descriptions

Some 7210-mode registers and 9914-mode registers share identical names. The 7210-mode registers are described in Chapter 4, 7210-Mode Interface Registers. If you are using the NAT9914 in 9914 mode, be sure to read the proper description for the 9914-mode registers.

All registers are listed in alphabetical order. The registers are alphabetized according to their mnemonics.

NAT9914 Reference Manual 3-4 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

Accessory Register A (ACCRA)

Attributes: Write only

Accessed at the same offset as ACCR

76543210

100BINXEOSREOS00

Accessory Register A (ACCRA) controls the EOS and END messages. The ch_rst auxiliary command or a hardware reset clears ACCRA.

Bit Mnemonic Description

4w BIN Binary bit

The BIN bit selects the length of the EOS message. If BIN = 1, the End-of-String Register (EOSR) is treated as an 8-bit byte. When BIN = 0, the EOSR is treated as a 7-bit register (for ASCII characters), and only a 7-bit comparison is done with the data on the GPIB.

3w XEOS Transmit END With EOS bit

The XEOS bit permits or prohibits automatic transmission of the GPIB END message at the same time as the EOS message when the NAT9914 is in Talker Active State (TACS). If XEOS = 1 and the byte in the Command/Data Out Register (CDOR) matches the contents of the EOSR, the EOI line is sent true along with the data.

2w REOS END On EOS Received bit

The REOS bit permits or prohibits setting the END bit (ISR0[3]r) when the NAT9914 receives the EOS message as a Listener. If REOS = 1 and the byte in the Data In Register (DIR) matches the byte in the EOSR, the END bit (ISR1[4]r) is set and the acceptor function treats the EOS character just as if it were received with EOI asserted.

9914-Mode Interface Registers Chapter 3

Accessory Register B (ACCRB)

Attributes: Write only

Accessed at the same offset as ACCR

76543210

1 0 1 ISS INV LWC SPEOI ATCT

Bit Mnemonic Description

4w ISS Individual Status Select bit

ISS determines the value of the NAT9914 ist message. When ISS = 1, ist takes on the value of the NAT9914 Service Request State (SRQS). (The NAT9914 is asserting the GPIB SRQ message when it is in SRQS.) If ISS = 0, ist takes on the value of the NAT9914 Parallel Poll Flag. You set and clear the Parallel Poll Flag by using the Set Parallel Poll Flag and Clear Parallel Poll Flag auxiliary commands. For more information, see The

ist Message section in Chapter 5, Software Considerations.

3w INV Invert bit

INV determines the polarity of the INT* pin.

INV Bit INT* Pin Polarity

0 Active Low

1 Active High

See the Generating Hardware Interrupts section in Chapter 5, Software Considerations.

2w LWC Listen When Controller bit

LWC enables the NAT9914 to accept command bytes that the NAT9914 sources when it is CIC. If LWC = 0, the NAT9914 does not accept command bytes sent by itself.

NAT9914 Reference Manual 3-6 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

ACCRB (continued)

Bit Mnemonic Description

1w SPEOI Send Serial Poll EOI bit

SPEOI determines whether the NAT9914 sends EOI when a Controller serial polls the NAT9914.

SPEOI EOI During Serial Polls

0 Sent False

1 Sent True

0w ATCT Automatic Take Control bit

If ATCT = 1, the NAT9914 can—without software intervention—take control when another CIC passes control to it. Use the CIC bit (ISR2[0] to determine when the NAT9914 receives control. See the GPIB Controller

Considerations section in Chapter 6, Controller Software Considerations.

9914-Mode Interface Registers Chapter 3

Accessory Register E (ACCRE)

Attributes: Write only

Accessed at the same offset as ACCR

7654 3 2 10

1 1 0 0 DHADT DHADC 0 0

Accessory Register E (ACCRE) determines how the NAT9914 uses a Data Accepted (DAC) holdoff. The ch_rst auxiliary command or a hardware reset clears ACCRE.

Each bit of ACCRE enables DAC holdoffs on a GPIB command or group of commands. When a GPIB Controller sends the specified command to the NAT9914, the Unrecognized Command (UNC) bit sets and the NAT9914 performs a DAC holdoff. See the DAC Holdoffs section in Chapter 5, Software Considerations.

Bit Mnemonic Description

3w DHADT DAC Holdoff On GET bit

2w DHADC DAC Holdoff On DCL Or SDC bit

NAT9914 Reference Manual 3-8 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

Accessory Register F (ACCRF)

Attributes: Write only

Accessed at the same offset as ACCR

7654 3 2 1 0

1101DHATA DHALA DHUNTL DHALL

Accessory Register F (ACCRF) determines how the NAT9914 uses a DAC holdoff. The ch_rst auxiliary command or a hardware reset clears ACCRF.

Each bit of ACCRF enables DAC holdoffs on a GPIB command or group of commands. When a GPIB Controller sends the specified command to the NAT9914, the UNC bit sets and the NAT9914 performs a DAC holdoff. See the DAC Holdoffs section in Chapter 5,

Software Considerations.

Bit Mnemonic Description

3w DHATA DAC Holdoff On All Talker Addresses bit

2w DHALA DAC Holdoff On All Listener Addresses bit

1w DHUNTL DAC Holdoff On The UNT Or UNL Command bit

0w DHALL DAC Holdoff On All UCG, ACG, And SCG Commands

bit

9914-Mode Interface Registers Chapter 3

Accessory Register I (ACCRI)

Attributes: Write only

Accessed at the same offset as ACCR

76543210

1110USTDPP10DMAE

Bit Mnemonic Description

3w USTD Ultra Short T1 Delay bit

If USTD = 1, the T1 delay can be as short as 350 ns. See the T1 Delay Generation section in Chapter 5, Software Considerations.

2w PP1 Parallel Poll bit 1

The PP1 bit permits or prohibits the NAT9914's ability to automatically respond to remote parallel poll configuration. If PP1 = 1, the NAT9914 can be configured remotely for parallel polls without software intervention.

The Acceptor Handshake does not perform a DAC holdoff or set the UNC bit when it receives a Parallel Poll Command (PPC or PPU).

If PP1 = 0, parallel polls must be configured through the Parallel Poll Register (PPR), and Parallel Poll commands must be monitored by UNC.

For more information, see the Automatic Remote

Configuration section in Chapter 5, Software Considerations.

0w DMAE DMA Enable bit

DMAE lets you use DMAO (IMR0[7]) and DMAI (IMR0[6]) to enable the ACCRQ* signal. See the Using

DMA/The ACCRQ* Pin section in Chapter 5, Software Considerations.

If DMAE = 0, ACCRQ* always asserts when the NAT9914 receives a data byte as a Listener or when the NAT9914 is a Talker and the CDOR is empty.

ACCRQ* is cleared by

pon + (read DIR) + (write CDOR)

NAT9914 Reference Manual 3-10 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

Address Register (ADR)

Attributes: Write only

76543210

edpa dal dat A5 A4 A3 A2 A1

ADR is used to load the primary GPIB address of the interface. See the GPIB Addressing section in Chapter 5, Software Considerations.

Bit Mnemonic Description

7w edpa Enable Dual Primary Addressing Mode bit

Setting edpa enables the dual primary addressing mode of the NAT9914. If edpa = 1, the NAT9914 ignores the least significant bit (A1) of its GPIB address. The NAT9914 then has two consecutive primary addresses. The Upper/Lower Primary Address (ulpa) bit in the Address Status Register indicates which address is active.

6w dal Disable Listener bit

Setting dal returns the NAT9914 Listener function to the Listener Idle State (LIDS) and forces the NAT9914 Listener function to remain in LIDS even if the chip receives its GPIB listen address or a lon auxiliary command.

5w dat Disable Talker bit

Setting dat returns the NAT9914 Talker function to the Talker Idle State (TIDS) and forces the Talker function to remain in TIDS even if the chip receives its GPIB talk address or a ton auxiliary command.

4–0w A[5–1] NAT9914 GPIB Address bits 5 through 1

A[5–1] specify the primary GPIB address of the NAT9914. The corresponding GPIB talk address is formed by adding hex 40 to A[5–1], while the corresponding GPIB listen address is formed by adding hex 20. A[5–1] should not be 11111 (binary) to prevent the corresponding talk and listen addresses from conflicting with the GPIB Untalk (UNT) and GPIB Unlisten (UNL) commands.

9914-Mode Interface Registers Chapter 3

Address Status Register (ADSR)

Attributes: Read only

76543210

REM LLO ATN LPAS TPAS LA TA ulpa

The Address Status Register (ADSR) contains information that you can use to monitor the NAT9914 GPIB address status.

Bit Mnemonic Description

7r REM Remote bit 6r LLO Local Lockout bit

REM and LLO indicate the status of the GPIB Remote/Local (RL1) function of the NAT9914.

LLO REM RL1 State

0 0 LOCS

0 1 REMS

1 0 LWLS

1 1 RWLS

For more information, see the Remote/Local State

Considerations section in Chapter 5, Software Considerations.

5r ATN Attention bit

ATN indicates the current level of the NAT9914 ATN pin. If ATN = 1, the ATN pin is asserted (active low).

4r LPAS Listener Primary Addressed State bit

LPAS indicates that the NAT9914 has accepted its primary listen address.

LPAS is cleared by

(PCG & ~MLA & ACDS) + pon

NAT9914 Reference Manual 3-12 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

ADSR (continued)

Bit Mnemonic Description

3r TPAS Talker Primary Addressed State bit

TPAS indicates that the NAT9914 has accepted its primary talk address.

TPAS is cleared by

(PCG & ~MTA & ACDS) + pon

2r LA Listener Active bit

LA = 1 when the NAT9914 has been addressed or programmed as a GPIB Listener—that is, the NAT9914 is in the Listener Active State (LACS) or the Listener Addressed State (LADS). The NAT9914 is addressed to listen when it receives its listen address from the CIC. You can also program the NAT9914 to listen by using the Listen-Only auxiliary command.

If the NAT9914 is addressed to listen, it is automatically unaddressed to talk.

LA is cleared by

pon + IFC + (UNL & ACDS)

1r TA Talker Active bit

TA = 1 when the NAT9914 has been addressed or programmed as the GPIB Talker—that is, the NAT9914 is in TACS, Talker Addressed State (TADS), or Serial Poll Active State (SPAS). The NAT9914 can be addressed to talk when it receives its talk address from the CIC. You can also program the NAT9914 to talk by using the Talk-Only auxiliary command.

If the NAT9914 is addressed to talk, it is automatically unaddressed to listen.

TA is cleared by

pon + IFC + (OTA & ACDS)

9914-Mode Interface Registers Chapter 3

ADSR (continued)

Bit Mnemonic Description

0r ulpa Upper/Lower Primary Address bit

ulpa indicates the least significant bit of the last primary address that the NAT9914 received.

Note: Only one Talker or Listener is active at a time.

ulpa indicates which, if either, NAT9914 Talker or Listener function is addressed or active.

The ch_rst auxiliary command clears the ulpa bit in the ADSR.

NAT9914 Reference Manual 3-14 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

Auxiliary Command Register (AUXCR)

Attributes: Write only

76543210

C/S 0 0 F4 F3 F2 F1 F0

Use the AUXCR to issue auxiliary commands. Two basic types of commands are implemented in the AUXCR: pulsed and static. Use static commands to enable (set) or disable (clear) various features of the NAT9914. The pulsed commands stay active for one clock pulse after the AUXCR has been written.

Note: Writes to the AUXCR should be separated by at least four clock cycles.

Table 3-3 summarizes the AUXCR auxiliary commands and Table 3-4 describes the AUXCR auxiliary commands.

Table 3-3. Auxiliary Command Summary

Hex

Code

00 80

01 81

02 pulsed rhdf Release RFD Holdoff

03 83

04 84

05 pulsed nbaf New Byte Available False

06 86

07 87

Type Mnemonic Auxiliary Command

static static

pulsed pulsed

static static

~swrst

swrst

nonvalid

valid

~hdfa

hdfa

~hdfe

hdfe

~fget

fget

~rtl

Clear Software Reset Set Software Reset

Nonvalid Release DAC Holdoff Valid Release DAC Holdoff

Clear Holdoff On All Data Set Holdoff On All Data

Clear Holdoff On END Only Set Holdoff On END Only

Clear Force Group Execute Trigger Set Force Group Execute Trigger

Clear Return To Local

rtl

Set Return To Local

(continues)

9914-Mode Interface Registers Chapter 3

AUXCR (continued)

Table 3-3. Auxiliary Command Summary (Continued)

Hex

Code

08 pulsed feoi Send EOI With The Next Byte

09 89

0A 8A

0B pulsed gts Go To Standby

0C pulsed tca Take Control Asynchronously

0D pulsed tcs Take Control Synchronously

0E 8E

0F 8F

10 90

11 pulsed rqc Request Control

12 pulsed rlc Release Control

Type Mnemonic Auxiliary Command

static static

~lon

lon

~ton

ton

~rpp

rpp

~sic

sic

~sre

sre

Clear Listen Only Set Listen Only

Clear Talk Only Set Talk Only

Clear Request Parallel Poll Set Request Parallel Poll

Clear Send Interface Clear Set Send Interface Clear

Clear Send Remote Enable Set Send Remote Enable

14 pulsed pts Pass Through Next Secondary

15 95

16 96

NAT9914 Reference Manual 3-16 © National Instruments Corp.

static

static static

~dai

dai

~stdl

stdl

~shdw

shdw

Clear Disable IMR2, IMR1, And IMR0 Interrupts Set Disable IMR2, IMR1, And IMR0 Interrupts

Clear Short T1 Delay Set Short T1 Delay

Clear Shadow Handshaking Set Shadow Handshaking

(continues)

Chapter 3 9914-Mode Interface Registers

AUXCR (continued)

Table 3-3. Auxiliary Command Summary (Continued)

Hex

Code

17 97

18 98

99 pulsed sw7210 Switch To 7210 Mode

1A 9A

1C pulsed ch_rst Chip Reset

1D 9D

1E pulsed piimr2 Page-In Interrupt Mask Register 2

1F pulsed pibcr Page-In Bus Control Register

9C pulsed clrpi Clear Page-In Registers

9E pulsed pieosr Page-In End-of-String Register

9F pulsed piaccr Page-In Accessory Register

Type Mnemonic Auxiliary Command

static static

pulsed pulsed

static static

~vstdl

vstdl

~rsv2

rsv2

reqf reqt

~ist

ist

Clear Very Short T1 Delay Set Very Short T1 Delay

Clear Request Service bit 2 Set Request Service bit 2

Request rsv False (reqf) Request rsv True (reqt)

Clear Parallel Poll Flag Set Parallel Poll Flag

Values not specified are reserved.

9914-Mode Interface Registers Chapter 3

AUXCR (continued)

Table 3-4. Auxiliary Command Description

Data

Pattern

(Hex)

00 80

01 81

Description

Clear Software Reset (~swrst) Set Software Reset (swrst)

The local swrst message places all GPIB interface functions into their idle states. swrst is equivalent to the GPIB local Power On (pon) message.

swrst is set by a hardware reset, the ch_rst auxiliary command, or the swrst auxiliary command. You should configure the NAT9914 while swrst is set. Configuration includes writing the address of the device into the ADR, writing mask values into the Interrupt Mask Registers, and selecting the desired features in the Auxiliary Command, Accessory, and Address Registers. When swrst is cleared, the device becomes logically existent on the GPIB.

Release DAC Holdoff (nonvalid) Release DAC Holdoff (valid)

These commands clear a DAC holdoff condition. When APT = 1, nonvalid indicates that the last GPIB command byte received from the Controller was an invalid secondary address. Valid indicates a valid secondary address.

A DAC holdoff caused by any other GPIB command byte should be released with the nonvalid command. See the DAC Holdoffs section in Chapter 5, Software Considerations.

02 Release RFD Holdoff (rhdf)

This command releases any Ready For Data (RFD) holdoffs that hdfa or hlde have caused.

03 83

NAT9914 Reference Manual 3-18 © National Instruments Corp.

Clear Holdoff On All Data (~hdfa) Set Holdoff On All Data (hdfa)

If hdfa is true, the NAT9914 performs an RFD holdoff after it receives a data byte. To complete the handshake, you must issue the rhdf command after the NAT9914 receives each byte. A hardware reset or the ch_rst auxiliary command clears hdfa. See The GPIB rdy Message and RFD Holdoffs section in Chapter 5, Software Considerations.

(continues)

Chapter 3 9914-Mode Interface Registers

AUXCR (continued)

Table 3-4. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

04 84

05 New Byte Available False (nbaf)

06 86

Clear Holdoff On END Only (~hdfe) Set Holdoff On END Only (hdfe)

If hdfe is true, the NAT9914 performs an RFD holdoff after it receives a data byte that satisfies the END condition. A hardware reset or the ch_rst auxiliary command clears hdfe. See The GPIB rdy Message and RFD Holdoffs section in Chapter 5, Software Considerations.

nbaf forces the local message, nba, to become false. This action prohibits the NAT9914 from sending the last byte written to the CDOR. See the Using nbaf section in Chapter 5, Software Considerations.

Clear Force Group Execute Trigger (~fget) Set Force Group Execute Trigger (fget)

These commands generate a trigger condition.

If the host interface issues ~fget, the TR pin pulses asserted for at least five clock cycles.

If the host interface issues fget, the TR pin asserts and remains asserted until the host interface issues ~fget.

Description

These commands do not set or clear the Group Execute Trigger (GET) bit.

07 87

Clear Return To Local (~rtl) Set Return To Local (rtl)

These commands set and clear the IEEE 488 rtl local message.

If the host interface issues the ~rtl command, the IEEE 488 rtl message pulses true.

If the host interface issues the rtl command, the IEEE 488 rtl message becomes true and remains true until the host interface issues ~rtl. A hardware reset or the ch_rst auxiliary command clears rtl.

(continues)

9914-Mode Interface Registers Chapter 3

AUXCR (continued)

Table 3-4. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

08 Send EOI With The Next Byte (feoi)

The Send EOI command causes the GPIB EOI line to go true with the next data byte transmitted.

09 89

0A 8A

0B Go To Standby (gts)

Clear Listen Only (~lon) Set Listen Only (lon)

lon forces the Listener function into the LACS. ~lon forces the Listener function to leave the LACS. The local message pon clears lon.

Clear Talk Only (~ton) Set Talk Only (ton)

ton forces the Talker function into the TACS. ~ton forces the Talker function to leave the TACS. The local message pon clears ton.

The gts command pulses the local gts message. If the NAT9914 is the Active Controller, gts forces the NAT9914 to become the Standby Controller and to unassert the GPIB ATN signal. See the Three Basic

Controller States section in Chapter 6, Controller Software Considerations.

Description

0C Take Control Asynchronously (tca)

The tca command pulses the local tca message. If the NAT9914 is the Standby Controller, tca forces the NAT9914 to become the Active Controller and to assert the GPIB ATN signal.

0D Take Control Synchronously (tcs)

The tcs command pulses the local tcs message. If the NAT9914 is the Standby Controller and an Active Listener, the tcs message forces the NAT9914 to become the Active Controller when the NAT9914 performs an RFD holdoff (that is, the AH function enters the Acceptor Not Ready State).

(continues)

NAT9914 Reference Manual 3-20 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

AUXCR (continued)

Table 3-4. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

0E 8E

0F 8F

Description

Clear Request Parallel Poll (~rpp) Set Request Parallel Poll (rpp)

The ~rpp and rpp commands set and clear the local rpp message. If the NAT9914 is the Active Controller, the rpp message forces the NAT9914 to send the Identify (IDY) message to all GPIB devices in the system and to conduct a parallel poll. After the NAT9914 has been conducting a parallel poll for at least 2 µs, the control program can read the Command Pass Through Register (CPTR) to obtain the parallel poll result, then the control program can end the parallel poll by issuing the ~rpp command. A hardware reset or the ch_rst auxiliary command clears rpp.

Clear Send Interface Clear (~sic) Set Send Interface Clear (sic)

The ~sic and sic commands clear and set the sic and rsc local messages. Setting sic and rsc forces the NAT9914 to become the System Controller and to assert the GPIB Interface Clear (IFC) signal. The control program must not issue the ~sic command until after IFC has been asserted at least 100 µs. A hardware reset or the ch_rst auxiliary command clears sic. See the System Controller Considerations section in Chapter 6, Controller Software Considerations.

Note: Before it issues the sic command, the control program must

ensure—by some means external to the NAT9914—that the GPIB transceivers are enabled to drive the GPIB IFC* signal.

10 90

Clear Send Remote Enable (~sre) Set Send Remote Enable (sre)

The ~sre and sre commands clear and set the sre and rsc local messages. Setting sre and rsc forces the NAT9914 to become the System Controller and to assert the GPIB Remote Enable (REN) signal. The control program must not issue the sre command until after REN has been unasserted at least 100 µs. A hardware reset or the ch_rst auxiliary command clears sre. See the System Controller Considerations section in Chapter 6, Controller Software Considerations.

Note: Before it issues the sre command, the control program must

ensure—by some means external to the NAT9914—that the GPIB transceivers are enabled to drive the GPIB REN* signal.

(continues)

9914-Mode Interface Registers Chapter 3

AUXCR (continued)

Table 3-4. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

11 Request Control (rqc)

If the NAT9914 is in the Idle Controller State, the rqc command forces the NAT9914 to become the Active Controller when it detects that the ATN signal is unasserted.

12 Release Control (rlc)

The rlc command forces the NAT9914 to become an Idle Controller and to unassert ATN.

13 93

14 Pass Through Next Secondary (pts)

Clear Disable IMR2, IMR1, And IMR0 Interrupts (~dai) Set Disable IMR2, IMR1, And IMR0 Interrupts (dai)

Issuing dai disables the interrupt pin. The Interrupt Status Registers and any holdoffs selected in the Interrupt Mask Register are not affected by the dai command. A hardware reset or the ch_rst auxiliary command clears dai. See the Generating Hardware Interrupts section in Chapter 5,

Software Considerations.

After you issue the pts command, UNC (ISR1[5]) sets when the NAT9914 receives a secondary command from the Controller.

Description

If PP1 = 0, you can use the pts command to implement remote parallel poll configuration.

Note: It is simpler to set the PP1 bit to implement remote parallel poll

configuration. When PP1 = 1, the NAT9914 interprets remote parallel poll configuration commands without software intervention.

If the NAT9914 receives the PPC command, UNC sets. When the control program detects UNC, the control program issues pts. UNC sets again when the Controller sends the Parallel Poll Enable (PPE) command. The control program reads the CPTR to obtain the PPE command, then the control program writes the appropriate value to the PPR.

(continues)

NAT9914 Reference Manual 3-22 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

AUXCR (continued)

Table 3-4. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

15 95

16 96

17 97

18 98

Description

Clear Short T1 Delay (~stdl) Set Short T1 Delay (stdl)

Issuing stdl makes the T1 delay time 1.1 µs. A hardware reset or the ch_rst auxiliary command clears stdl. See the T1 Delay Generation section in Chapter 5, Software Considerations.

Clear Shadow Handshaking (~shdw) Set Shadow Handshaking (shdw)

The shdw command places the NAT9914 in continuous mode. A hardware reset or the ch_rst auxiliary command clears shdw. See The

GPIB rdy Message and RFD Holdoffs section in Chapter 5, Software Considerations.

Clear Very Short T1 Delay (~vstdl) Set Very Short T1 Delay (vstdl)

Issuing vstdl reduces the T1 delay time to 500 ns. A hardware reset or the ch_rst auxiliary command clears vstdl. See the T1 Delay Generation section in Chapter 5, Software Considerations.

Clear Request Service bit 2 (~rsv2) Set Request Service bit 2 (rsv2)

The rsv2 bit performs the same function as the rsv bit in the SPMR, but it provides a means of requesting service that is independent of the SPMR. With rsv2, you can make minor updates to the SPMR without affecting the state of service request. rsv2 is cleared when the serial poll status byte is sent to the Controller during a serial poll (SPAS & APRS & STRS). A hardware reset or the ch_rst auxiliary command clears rsv2.

99 Switch To 7210 Mode (sw7210)

Issuing sw7210 places the NAT9914 into 7210 compatibility mode.

(continues)

9914-Mode Interface Registers Chapter 3

AUXCR (continued)

Table 3-4. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

1A 9A

1C Chip Reset (ch_rst)

Request rsv False (reqf) Request rsv True (reqt)

The reqt and reqf commands are inputs to the IEEE 488.2 Service Request Synchronization Circuit. Use these commands to set and clear the local rsv message. The local message pon clears reqf and reqt.

If STBO IE = 0, reqt and reqf are not issued immediately; they are issued on the write of the SPMR that follows the issuing of the reqt or reqf auxiliary command.

If STBO IE = 1, reqt and reqf are issued immediately. See the IEEE

488.2 Service Requesting section in Chapter 5, Software Considerations.

The Chip Reset command resets the NAT9914 to the following conditions:

• The local swrst message is set and the interface functions are placed in their idle states.

• The SPMR bits are cleared.

Description

• The EOS and New Line (NL) bits are cleared.

• The ACCRA, ACCRB, ACCRE, ACCRF, and ACCRI registers are cleared.

• The Parallel Poll Flag local message is cleared.

• The ulpa bit is cleared.

(continues)

NAT9914 Reference Manual 3-24 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

AUXCR (continued)

Table 3-4. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

1D 9D

1E Page-In Interrupt Mask Register 2 (piimr2)

Clear Parallel Poll Flag (~ist) Set Parallel Poll Flag (ist)

The ~ist and ist commands set and clear the Parallel Poll Flag. The value of the Parallel Poll Flag is used as the local ist message when bit four of ACCRB (ISS) = 0. The value of SRQS is used as the local ist message when ISS = 1. The ch_rst auxiliary command or a hardware reset clears the local ist message. See The ist Message section in Chapter 5, Software

Considerations.

Issuing piimr2 maps Interrupt Mask Register 2 (IMR2) to the ADSR offset. After this command is issued, you can access IMR2 at the ADSR offset until one of the following events occurs:

• A hardware reset occurs.

• The ch_rst auxiliary command is issued.

• Another register is paged into the ADSR offset.

• The Clear Page-In auxiliary command is issued.

Description

1F Page-In Bus Control Register (pibcr)

Issuing pibcr maps the Bus Control Register (BCR) to the ADSR offset. After this command is issued, you can access BCR at the ADSR offset until one of the following events occurs:

• A hardware reset occurs.

• The ch_rst auxiliary command is issued.

• Another register is paged into the ADSR offset.

• The Clear Page-In auxiliary command is issued.

(continues)

9914-Mode Interface Registers Chapter 3

AUXCR (continued)

Table 3-4. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

9C Clear Page-In Registers (clrpi)

Issuing clrpi removes the previously paged-in ACCR from the ADSR offset. After this command is issued, writes to offset 2 have no effect until a Page-In auxiliary command is issued.

9E Page-In End-of-String Register (pieosr)

Issuing pieosr maps the EOSR to the ADSR offset. After this command is issued, you can access the EOSR at the ADSR offset until one of the following events occurs:

• A hardware reset occurs.

• The ch_rst auxiliary command is issued.

• Another register is paged into the ADSR offset.

• The Clear Page-In auxiliary command is issued.

9F Page-In Accessory Register (piaccr)

Issuing piaccr maps the ACCR to the ADSR offset. After this command is issued, you can access the ACCR at the ADSR offset until one of the following events occurs:

Description

• A hardware reset occurs.

• The ch_rst auxiliary command is issued.

• Another register is paged into the ADSR offset.

• The Clear Page-In auxiliary command is issued.

NAT9914 Reference Manual 3-26 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

Bus Control Register (BCR)/Bus Status Register (BSR)

Attributes: Write only (BCR)

Read only (BSR)

76543210

ATN DAV NDAC NRFD EOI SRQ IFC REN

Bit Mnemonic Description

7r ATN GPIB Attention Status bit 7w ATN GPIB Attention Control bit

6r DAV GPIB Data Valid Status bit 6w DAV GPIB Data Valid Control bit

5r NDAC GPIB Not Data Accepted Status bit 5w NDAC GPIB Not Data Accepted Control bit

4r NRFD GPIB Not Ready For Data Status bit 4w NRFD GPIB Not Ready For Data Control bit

3r EOI GPIB End-or-Identify Status bit 3w EOI GPIB End-or-Identify Control bit

2r SRQ GPIB Service Request Status bit 2w SRQ GPIB Service Request Control bit

1r IFC GPIB Interface Clear Status bit 1w IFC GPIB Interface Clear Control bit

0r REN GPIB Remote Enable Status bit 0w REN GPIB Remote Enable Control bit

Reads of the Bus Status Register (BSR) return the status of the GPIB control lines at the time of the read. Write ones to bits in the BCR to assert the corresponding GPIB control lines.

9914-Mode Interface Registers Chapter 3

BCR/BSR (continued)

Because the NAT9914 is either transmitting or receiving a GPIB control line at any particular time and is not performing both actions simultaneously, setting a bit in the BCR may not automatically assert the corresponding line on the GPIB. If the NAT9914 is transmitting a GPIB line when the corresponding bit in the BCR is set, the NAT9914 asserts the GPIB line. If the NAT9914 is receiving a GPIB line when the corresponding bit in the BCR is set, the GPIB line is not asserted. However, in both these cases, the GPIB signal internal to the NAT9914 is logically ORed with the value of the BCR bit. Figure 3-1 illustrates the GPIB input/output hardware configuration.

Transmit Enable

GPIB Line Out BCR Bit

NDAC NRFD

SRQ

GPIB Line In

eliminates glitches in

REN & IFC

Figure 3-1. GPIB I/O Hardware Configuration

In Figure 3-1, Transmit Enable represents the internal signal that is true when the chip is driving a particular GPIB control line. GPIB Line Out represents the internal signal that is true when an interface function within the chip is attempting to assert a GPIB control signal. BCR Bit corresponds to the bit in the BCR. GPIB Line In represents the internal GPIB lines that are inputs to the GPIB interface functions and the BSR. The internal signals SRQ , NDAC, and NRFD are monitored by the interface functions even when they are not driven onto the pin. For this reason, the internal value of these signals is ORed with the external value.

Because the BSR samples the GPIB control lines from the GPIB transceiver—not the actual GPIB bus—the direction of each line determines the validity of each bit. Generally, when a signal is an input, the BSR reflects its true bus status, while an output signal reflects only the NAT9914 value of that particular line. Under normal GPIB operation, this restriction on the validity of the BSR should not be too limiting, because the lines that are typically monitored are valid when they are monitored. For example, the Service Request (SRQ) line is valid in the BSR when the NAT9914 is CIC, which is also when the SRQ line is monitored.

NAT9914 Reference Manual 3-28 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

Command/Data Out Register (CDOR)

Attributes: Write only

76543210

DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1

Bit Mnemonic Description

7–0w DIO[8–1] GPIB data lines DIO[8–1]

The CDOR moves data from the CPU to the GPIB when the interface is the GPIB Talker or Controller. Writing to the CDOR sets the local message, nba. When nba is true, the Source Handshake (SH) function can transfer the data or command in the CDOR to other GPIB devices. Writing to the CDOR also

• Clears the Byte Out (BO) bit.

• Clears the ACCRQ* signal (unless DMAE = 1 and DMAO = 0).

The host interface can write to the CDOR at offset 7 or by performing a DMA write operation.

The CDOR and the DIR use separate latches. A read of the DIR does not change data in the CDOR. The CDOR is a transparent latch; thus, the GPIB data bus (DIO(8–1)) reflects changes on the CPU data bus during write cycles to the CDOR.

9914-Mode Interface Registers Chapter 3

Command Pass Through Register (CPTR)

Attributes: Read only

76543210

CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0

The host interface can examine the GPIB Data Input/Output (DIO) lines by reading the CPTR. The CPTR has no storage; the host interface should read the CPTR only during a DAC holdoff. See the DAC Holdoffs section in Chapter 5, Software Considerations.

Bit Mnemonic Description

7–0r CPT[7–0] Command Pass Through bits 7 through 0

NAT9914 Reference Manual 3-30 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

Data In Register (DIR)

Attributes: Read only

76543210

DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1

Bit Mnemonic Description

7–0r DIO[8–1] GPIB data lines DIO[8–1]

The DIR holds data that the NAT9914 receives when the NAT9914 is a Listener. The NAT9914 latches GPIB data into the DIR when LACS & ACDS is true.

Latching data into the DIR causes the Data In (DI) bit to set. Usually, latching data into the DIR causes an RFD holdoff. (See The GPIB rdy Message and RFD Holdoffs section in Chapter 5, Software Considerations.)

The host interface can read the DIR at offset 7 or by performing a DMA read operation. Reading the DIR also

• Clears the Byte In (BI) bit.

• Can clear an RFD holdoff (depending on several other conditions).

• Clears the ACCRQ* signal (unless DMAE = 1 and DMAI = 0).

The DIR and the CDOR use separate latches. When the host interface writes to the CDOR, data in the DIR is not changed.

9914-Mode Interface Registers Chapter 3

End-of-String Register (EOSR)

Attributes: Write only

76543210

EOS7 EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOS0

The EOSR holds the byte that the NAT9914 uses to detect the end of a GPIB data block transfer. The NAT9914 compares data it receives to a 7- or 8-bit byte (ASCII or binary—depending on the BIN bit) in the EOSR in order to detect the end of a block of data.

If the NAT9914 is a Listener and REOS = 1, the END bit is set in Interrupt Status Register 0 (ISR0) whenever the received data byte matches the EOSR. If the NAT9914 is a Talker and XEOS = 1, the END message (GPIB EOI* line asserted low) is sent along with a data byte whenever the data byte matches the EOSR.

Bit Mnemonic Description

7–0w EOS[7–0] End-of-String bits 7 through 0

NAT9914 Reference Manual 3-32 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

Internal Count Register (ICR)

Attributes: Write only

Accessed at the same offset as ACCR

76543210

0010F3F2F1F0

The Internal Count Register (ICR) determines the internal clock frequency of the NAT9914.

Note: The ICR resets to 00100101 (5 MHz).

Bit Mnemonic Description

3–0w F(3–0) Clock Frequency

These bits, in addition to MICR (ICR2[0]), determine the length of certain delays that are required by the IEEE 488 standard. You should set these bits according to the frequency of the signal driving the CLK pin. For proper operation, set F(3–0) and MICR as follows:

Clock

Frequency

1 0 0001

2 0 0010

3 0 0011

4 0 0100

5 0 0101

6 0 0110

7 0 0111

8 0 1000

10 1 0101

16 1 1000

20 1 1010

MICR F(3–0)

9914-Mode Interface Registers Chapter 3

ICR (continued)

For more information, see the Internal Count Register 2 (ICR2) section in Chapter 4, 7210-Mode Interface Registers, and the Set the Clock Frequency section in Chapter 5, Software Considerations.

NAT9914 Reference Manual 3-34 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

Interrupt Mask Register 0 (IMR0)

Attributes: Write only

76543210

DMAO DMAI BI IE BO IE END IE SPAS IE RLC IE MAC IE

Interrupt Status Register 0 (ISR0)

Attributes: Read only

Bits are cleared when read

76543210

INT0 INT1 BI BO END SPAS RLC MAC

ISR0 contains Interrupt Status bits. Interrupt Mask Register 0 (IMR0) contains Interrupt Enable bits that directly correspond to the Interrupt Status bits in ISR0. As a result, ISR0 and IMR0 service six possible interrupt conditions; each condition has an associated Interrupt Status bit and an Interrupt Enable bit. If an Interrupt Enable bit is true when the corresponding status condition or event occurs, the NAT9914 can generate a hardware interrupt request. See the Generating Hardware Interrupts section in Chapter 5, Software Considerations.

Bits in ISR0 are set and cleared regardless of the status of the Interrupt bits in IMR0. If an interrupt condition occurs at the same time the host interface is reading ISR0, the NAT9914 does not set the corresponding Interrupt Status bit until the read is finished. A hardware reset clears all bits in IMR0.

Bit Mnemonic Description

7r INT0 Interrupt Register 0 Interrupt bit

INT0 is set when an unmasked status bit in ISR0 is set.

7w DMAO DMA Output Enable bit

If DMAE = 1 (ACCRI[0]), DMAO enables the NAT9914 to assert the ACCRQ* pin as a GPIB Talker. The NAT9914 asserts ACCRQ* when it is ready to accept another byte in the CDOR. ACCRQ* does not assert if the NAT9914 is not a Talker. See the Using DMA/The

ACCRQ* Pin section in Chapter 5, Software Considerations.

If DMAE = 0, write 0 to DMAO.

9914-Mode Interface Registers Chapter 3

IMR0/ISR0 (continued)

Bit Mnemonic Description

6r INT1 Interrupt Register 1 Interrupt bit

INT1 is set when an unmasked status bit in Interrupt Status Register 1 (ISR1) is set.

6w DMAI DMA Input Enable bit

If DMAE = 1 (ACCRI[0]), DMAI enables the NAT9914 to assert the ACCRQ* pin as a GPIB Listener. The NAT9914 asserts ACCRQ* when the DIR contains a byte for the host interface to read. See the Using

DMA/The ACCRQ* Pin section in Chapter 5, Software Considerations.

If DMAE = 0, write 0 to DMAI.

5r BI Byte In bit 5w BI IE Byte In Interrupt Enable bit

BI indicates that a data byte has been received in the DIR. An RFD holdoff must be cleared before the NAT9914 accepts the next data byte.

BI is set by

LACS & ACDS & ~(continuous mode)

BI is cleared by

swrst + (read ISR0) + (read DIR)

4r BO Byte Out bit 4w BO IE Byte Out Interrupt Enable bit

BO indicates that the NAT9914 is the Active Controller or Talker and that the CDOR does not contain a byte to send over the GPIB. BO sets again after each byte has been sent and the source handshake has returned to SGNS.

BO is set by

(CACS + TACS) & SGNS & ~nba

BO is cleared by

swrst + (read ISR0) + (write CDOR)

NAT9914 Reference Manual 3-36 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

IMR0/ISR0 (continued)

Bit Mnemonic Description

3r END End Received bit 3w END IE End Received Interrupt Enable bit

END sets when the NAT9914, as a Listener, receives a data byte satisfying the END condition. A data byte satisfies the END condition if one of the following conditions is true:

• REOS = 1 and the data byte matches the contents of the EOSR.

• NLEN = 1 and the data byte matches the ASCII new line character (hex 0A).

• The GPIB EOI signal is asserted when the byte is received.

That is, END is set by

(EOI + EOS & REOS + NL & NLEN) & LACS & ACDS

END is cleared by

swrst + (read ISR0)

2r SPAS Serial Poll Active State bit 2w SPAS IE Serial Poll Active State Interrupt Enable bit

SPAS indicates that the Controller has serial polled the NAT9914 in response to the NAT9914 requesting service.

SPAS is set by

[STRS & SPAS & APRS] becoming false

SPAS is cleared by

swrst + (read ISR0)

1r RLC Remote/Local Change bit 1w RLC IE Remote/Local Change Interrupt Enable bit

RLC is set when a change occurs in the REM bit, ADSR[7]r. See the Remote/Local State Considerations section in Chapter 5, Software Considerations.

RLC is cleared by

swrst + (read ISR0)

9914-Mode Interface Registers Chapter 3

IMR0/ISR0 (continued)

Bit Mnemonic Description

0r MAC My Address Change bit 0w MAC IE My Address Change Interrupt Enable bit

MAC indicates that the NAT9914 has received a command from the Controller and that this command has changed the addressed state of the NAT9914.

If the NAT9914 is using secondary addressing, MAC sets only when the NAT9914 becomes unaddressed. If edpa = 1, MAC does not set when the Controller readdresses the NAT9914 at the NAT9914's other primary address.

MAC is set by

ACDS & (MTA & ~TADS & ~APT IE + OTA & TADS + MLA & ~LADS & ~APT IE + UNL & LADS)

MAC is cleared by

swrst + (read ISR0)

NAT9914 Reference Manual 3-38 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

Interrupt Mask Register 1 (IMR1)

Attributes: Write only

7654 3 210

GET IE ERR IE UNC IE APT IE DCAS IE MA IE SRQ IE IFC IE

Interrupt Status Register 1 (ISR1)

Attributes: Read only

Bits are cleared when read

76543210

GET ERR UNC APT DCAS MA SRQ IFC

ISR1 contains Interrupt Status bits. Interrupt Mask Register 1 (IMR1) contains Interrupt Enable bits that directly correspond to the Interrupt Status bits in ISR1. As a result, ISR1 and IMR1 service interrupt conditions; each condition has an associated Interrupt Status bit and an Interrupt Enable bit. If an Interrupt Enable bit is true when the corresponding status condition or event occurs, the NAT9914 can generate a hardware interrupt request. See the Generating Hardware Interrupts section in Chapter 5, Software Considerations.

Bits in ISR1 are set and cleared regardless of the status of the Interrupt bits in IMR1. If an interrupt condition occurs at the same time the host interface is reading ISR1, the NAT9914 does not set the corresponding Interrupt Status bit until the read is finished. A hardware reset clears all bits in IMR1.

The interrupts GET, UNC, APT, DCAS, and MA are set in response to commands received over the bus. If the corresponding Interrupt Enable bit is set, a DAC holdoff occurs when the interrupt sets.

Bit Mnemonic Description

7r GET Group Execute Trigger bit 7w GET IE Group Execute Trigger Interrupt Enable bit

GET indicates that the NAT9914 received the GPIB GET command while the NAT9914 was a GPIB Listener.

9914-Mode Interface Registers Chapter 3

IMR1/ISR1 (continued)

Bit Mnemonic Description

If GET IE = 1, a DAC holdoff occurs when the interrupt condition occurs. The TR pin goes high when the interrupt condition occurs and remains high until the DAC holdoff is released.

If GET IE = 0, the TR pin pulses high.

GET is set by

GET & LADS & ACDS

GET is cleared by

swrst + (read ISR1)

6r ERR Error bit 6w ERR IE Error Interrupt Enable bit

ERR sets when the Source Handshake becomes active (enters the Source Delay State, or SDYS) and finds that the NDAC and NRFD lines are both unasserted on the GPIB. This condition indicates that there are no acceptors on the GPIB.

ERR is set by

SDYS & EXTDAC & RFD

ERR is cleared by

swrst + (read ISR1)

5r UNC Unrecognized Command bit 5w UNC IE Unrecognized Command Interrupt Enable bit

UNC flags the occurrence of several types of GPIB commands. UNC sets when the NAT9914 accepts any unrecognized Universal Command Group (UCG) command.

If the NAT9914 is an addressed Listener, UNC sets when the NAT9914 accepts any unrecognized Addressed Command Group (ACG) command.

NAT9914 Reference Manual 3-40 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

IMR1/ISR1 (continued)

Bit Mnemonic Description

UNC flags the first secondary command that the NAT9914 accepts after the host interface issues the Pass Through Next secondary auxiliary command. UNC can also flag the occurrence of commands that you specify when you set the AUXRE[3–2]w or AUXRF[3–0]w bits.

If UNC IE = 1, the NAT9914 performs a DAC holdoff when UNC sets. The host interface releases the DAC holdoff by issuing the Release DAC Holdoff auxiliary command. Read undefined commands by using the CPTR.

UNC is set by

ACDS & UCG & ~(LLO + SPE + SPD + DCL +

PPU & PP1)

+ ACDS & ACG & ~(GET + GTL

+ SDC + TCT + PPC & PP1) & LADS + SCG & PTS & ACDS + DHADT & GET & ACDS + DHADC & (SDC + DCL) & ACDS + DHATA & TAG & ~UNT & ACDS + DHALA & LAG & ~UNL & ACDS + DHUNTL & (UNT + UNL) & ACDS + DHALL & ATN & ACDS

UNC is cleared by

swrst + (read ISR1)

4r APT Address Pass Through bit 4w APT IE Address Pass Through Interrupt Enable bit

Setting APT IE enables secondary addressing. If the last primary command accepted was a primary talk or listen address of the NAT9914, APT sets when the NAT9914 accepts a secondary command. The secondary command is a secondary GPIB address that can be read in the CPTR. See the Implementing One Logical Device:

Extended Addressing section in Chapter 5, Software Considerations.

Note: When the host interface uses secondary

addressing, it must check APT.

9914-Mode Interface Registers Chapter 3

IMR1/ISR1 (continued)

Bit Mnemonic Description

If APT IE = 1, the NAT9914 performs a DAC holdoff when APT sets. The host interface releases the DAC holdoff by issuing the Release DAC Holdoff auxiliary command.

APT is set by

(TPAS + LPAS) & SCG & ACDS

APT is cleared by

swrst + (read ISR1)

3r DCAS Device Clear Active State bit 3w DCAS IE Device Clear Active State Interrupt Enable bit

DCAS indicates that either the NAT9914 received the GPIB Device Clear (DCL) command or that the NAT9914 was a Listener and received the GPIB Selected Device Clear (SDC) command.

If DCAS IE = 1, the NAT9914 performs a DAC holdoff when DCAS sets. The host interface releases the DAC holdoff by issuing the Release DAC Holdoff auxiliary command.

DCAS is set by

ACDS & (DCL + SDC & LADS)

DCAS is cleared by

swrst + (read ISR1)

2r MA My Address bit 2w MA IE My Address Interrupt Enable bit

MA sets when the NAT9914 accepts its primary talk or listen address.

If MA IE = 1, the NAT9914 performs a DAC holdoff when MA sets. The host interface releases the DAC holdoff by issuing the Release DAC Holdoff auxiliary command.

NAT9914 Reference Manual 3-42 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

IMR1/ISR1 (continued)

Bit Mnemonic Description

MA is set by

(MLA + MTA) & ACDS & ~SPMS & ~APT IE

MA is cleared by

swrst + (read ISR1)

1r SRQ Service Request bit 1w SRQ IE Service Request Interrupt Enable bit

The SRQ bit indicates that the NAT9914 received a GPIB SRQ message while the NAT9914 was the CIC.

The SRQ bit is cleared by

swrst + (read ISR1)

0r IFC Interface Clear bit 0w IFC IE Interface Clear Interrupt Enable bit

IFC sets on the assertion of the GPIB IFC signal.

IFC is cleared by

swrst + (read ISR1)

9914-Mode Interface Registers Chapter 3

Interrupt Mask Register 2 (IMR2)

Attributes: Write only

76543210

GLINT STBOIENLEN 0 LLOCIEATNI

0 CIC IE

Interrupt Status Register 2 (ISR2)

Attributes: Read only

76543210

nba STBO NL EOS LLOC ATNI X CIC

ISR2 contains Interrupt Status bits and Internal Status bits. IMR2 contains Interrupt Enable bits and Internal Control bits. As a result, ISR2 and IMR2 service several possible interrupt conditions; each condition has an associated Interrupt Status bit and an Interrupt Enable bit. If an Interrupt Enable bit is true when the corresponding status condition or event occurs, the NAT9914 can generate a hardware interrupt request. See the Generating Hardware Interrupts section in Chapter 5, Software Considerations.

Bits in ISR2 are set and cleared regardless of the status of the Interrupt bits in IMR2. If an interrupt condition occurs at the same time the host interface is reading ISR2, the NAT9914 does not set the corresponding Interrupt Status bit until the read is finished. A hardware reset clears all bits in IMR2 except the Global Interrupt Enable (GLINT) bit.

Bit Mnemonic Description

7r nba New Byte Available local message bit

nba is true when the local variable nba is true. nba is set on writes to the CDOR and cleared on entrance to the Source Transfer State (STRS), pon, or nbaf.

7w GLINT Global Interrupt Enable bit

GLINT enables the NAT9914 to assert the INT* pin. If GLINT = 0, INT* does not assert. See the Generating

Hardware Interrupts section in Chapter 5, Software Considerations.

NAT9914 Reference Manual 3-44 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

IMR2/ISR2 (continued)

Bit Mnemonic Description

6r STBO Status Byte Out bit 6w STBO IE Status Byte Out Interrupt Enable bit

STBO is set when the NAT9914 enters SPAS when STBO IE = 1. After STBO sets, the control program should write the current STB to the SPMR. The current Status Byte (STB) is then transmitted to the GPIB as the STB. Writing the SPMR clears STBO.

STBO IE determines how the NAT9914 requests service and responds to serial polls.

If STBO IE = 0, the rsv bit in the SPMR can be used to request service. When the GPIB Controller serial polls the NAT9914, the NAT9914 transmits the current value of the SPMR.

If STBO IE = 1, the rsv bit in the SPMR has no effect on the Service Request (SR1 function and rsv must be generated through the reqt auxiliary command. When the GPIB Controller serial polls the NAT9914, STBO sets. In response to STBO, the host interface writes a byte to the SPMR, then the NAT9914 transmits this byte as the Serial Poll response.

For more information, see the IEEE 488.2 Service Requesting section and the Responding to Serial Polls section in Chapter 5, Software Considerations.

STBO is set by

STBO IE & SPAS

STBO is cleared by

swrst + (write SPMR) + ~SPAS

5r NL New Line Receive bit

NL indicates that the last data byte that the NAT9914 received was an ASCII new line character.

NL is set by

LACS & NL & ACDS

NL is cleared by

swrst + (LACS & ~NL & ACDS)

9914-Mode Interface Registers Chapter 3

IMR2/ISR2 (continued)

Bit Mnemonic Description

5w NLEN New Line End Enable bit

If NLEN = 1, the NAT9914 treats the 7-bit ASCII new line character (0A hex) as an EOS character. The Acceptor Handshake function responds to the acceptance of a new line character in the same manner as if EOI were sent.

4r EOS End-of-String bit

EOS indicates that REOS = 1 and that the last data byte the NAT9914 received matched the contents of the EOSR.

EOS is set by

LACS & EOS & REOS & ACDS

EOS is cleared by

swrst + (LACS & ~EOS & ACDS) + ~REOS

3r LLOC Local Lockout Change bit 3w LLOC IE Local Lockout Change Interrupt Enable bit

LLOC is set by

any change in the LLO bit

LLOC is cleared by

ch_rst + (read ISR0)

See the Remote/Local State Considerations section in Chapter 5, Software Considerations.

2r ATNI ATN Interrupt bit 2w ATNI IE ATN Interrupt Enable bit

ATN is set by

(ATN) becoming true

ATN is cleared by

ch_rst + read ISR0

1r X Don't care bit

NAT9914 Reference Manual 3-46 © National Instruments Corp.

Chapter 3 9914-Mode Interface Registers

IMR2/ISR2 (continued)

Bit Mnemonic Description

0r CIC Controller-In-Charge bit 0w CIC IE Controller-In-Charge Interrupt Enable bit

CIC indicates whether the NAT9914 is the Controller-inCharge.

CIC = ~(CIDS + CADS)

9914-Mode Interface Registers Chapter 3

Parallel Poll Register (PPR)

Attributes: Write only

76543210

PP8 PP7 PP6 PP5 PP4 PP3 PP2 PP1

Bit Mnemonic Description

7–0w PP8–PP1 When a Controller initiates a parallel poll, the NAT9914

drives the contents of the PPR on the GPIB DIO lines using open-collector drivers. If PP8–PP1 = 00 (hex), none of the lines (DIO(8–1)) are asserted during a parallel poll.

The PPR is double buffered. If the PPR is written during a parallel poll, the new value is held until the parallel poll ends. When the parallel poll ends, the register is updated, so the control program can update the parallel poll response asynchronously to the GPIB.

A hardware reset or the ch_rst auxiliary command clears PPR. The host interface can load PPR while swrst = 1.

See the Responding to Parallel Polls section in Chapter 5,

Software Considerations.

Chapter 3 9914-Mode Interface Registers

Serial Poll Mode Register (SPMR)

Attributes: Write only

76543210

S8 rsv/RQS S6 S5 S4 S3 S2 S1

Serial Poll Status Register (SPSR)

Attributes: Read only

76543210

S8PENDS6S5S4 S3S2S1

Bit Mnemonic Description

7r, S8 Serial Poll Status bit 8 7w

5–0r, S[6–1] Serial Poll Status bits 6 through 1 5–0w

These bits send device- or system-dependent status information over the GPIB when the Controller serial polls the NAT9914.

When STBO IE = 0, the NAT9914 transmits a byte of status information, SPMR[7–0], to the CIC if the CIC serial polls the NAT9914. The SPMR bits S[8, 6–1] are double buffered. If the host interface writes to the SPMR during a serial poll when SPAS is active, the NAT9914 saves the value. The NAT9914 updates the SPMR when the NAT9914 exits SPAS.

When STBO IE = 1 and the Controller serial polls the NAT9914, the STBO interrupt condition sets. The host interface should write the STB and the Request Service (RQS) bit to the SPMR in response to an STBO interrupt.

Issuing the ch_rst auxiliary command clears these bits.

9914-Mode Interface Registers Chapter 3

SPMR/SPSR (continued)

Bit Mnemonic Description

6r PEND Pending bit

PEND sets when rsv = 1. PEND clears when the NAT9914 is in the Negative Poll Response State (NPRS) and the local rsv message is false. By reading the PEND status bit, you can confirm that a request was accepted and that the STB was transmitted (PEND = 0).

6w rsv/RQS Request Service/ RQS bit

When STBO IE = 0, bit 6 is the rsv bit. The rsv bit generates the GPIB local rsv message. When rsv = 1 and the GPIB Controller is not serial polling the NAT9914, the NAT9914 enters the SRQS and asserts the GPIB SRQ signal. When the Controller reads the STB during the poll, the NAT9914 clears rsv. The rsv bit is also cleared by a hardware reset or by writing 0 to it. Issuing the ch_rst auxiliary command also clears rsv.

When STBO IE = 1, bit 6 is the RQS bit. When the Controller serial polls the NAT9914, the STBO interrupt condition sets. The host interface should write the STB and the RQS bit to the SPMR in response to an STBO interrupt. The NAT9914 transfers the STB and RQS to the Controller during that particular serial poll. A hardware reset clears RQS. Issuing the ch_rst auxiliary command also clears RQS.

See the Requesting Service section in Chapter 5, Software

Considerations.

Chapter 4 7210-Mode Interface Registers

This chapter contains NAT9914 address maps and detailed descriptions of the NAT9914 interface registers in 7210 mode. For 9914-mode register descriptions, see Chapter 3, 9914-Mode Interface Registers.

7210 Register Map

Table 4-1 is the register bit map for the NAT9914 in 7210 mode.

Notice that bold-ruled cells distinguish seven registers that are accessible only when the Page-In state is true. Refer to The Page-In State section that immediately follows the register map for more information.

7210-Mode Interface Registers Chapter 4

7210 Mode Only

Table 4-1. 7210-Mode Register Map

Key

= 7210-Mode Paged Registers

= Read Register

= Write Register

76543210

DIR +0 DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 R

CDOR +0 DIO8 DIO7 DIO 6 DIO5 D IO4 DI O3 DI O2 DIO1 W

ISR1 +1 CPT APT DET END RX DEC ERR DO DI R

IMR1 +1 CPT IE APT IE DET IE END IE DEC IE ERR IE DO IE DI IE W

ISR2 +2 INT SRQI LOK REM CO LOKC REMC ADSC R

IMR2 +2 0 SRQI IE DMAO D MAI CO IE LO KC IE REMC IE ADSC IE 2

SPSR +3 S8 PEND S6 S5 S4 S3 S2 S1 R

VSR+3V3V2V1V0 X X X XR

ICR2+310SLOW0000MICRW

SPMR +3 S8 rsv/RQS S6 S5 S4 S3 S2 S1 W

ADSR +4 CIC ATN* SPMS LPAS TPAS LA TA MJMN R

ADMR +4 ton lon TRM1 TRM0 0 0 ADM1 ADM0 W

CPTR +5 CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0 R

SASR +5 nba AEHS ANHS1 ANHS2 ADHS ACRDY SH1A SH1B R

AUXMR +5 AUX7 AUX6 AUX5 AUX4 AUX3 AUX2 AUX1 AUX0 W

ADR0 +6 X DT0 D L0 AD5-0 AD4-0 AD 3-0 AD 2-0 AD1 -0 R

ISR0 +6 nba STBO NL EOS IFCI ATNI X SYNC R

IMR0 +6 GLINT STBO 1E NLEN BTO IFCI IE ATNI IE 0 SYNC IE W

ADR +6 ARS DT DL AD5 AD4 AD3 AD2 AD1 W

ADR1 +7 EO I DT1 D L1 AD5-1 AD4-1 A D3-1 AD 2-1 AD1 -1 R

BSR +7 ATN DAV NDAC NRFD EO I SRQ IFC REN R

BCR +7 ATN DAV NDAC NRFD EOI SRQ IFC REN W

EOSR +7 EOS7 EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOS0 W

Chapter 4 7210-Mode Interface Registers

7210 Mode Only

The Page-In State

At some offsets, Table 4-1 shows two readable or two writable registers. The registers in the bold-ruled cells in Table 4-1 are accessible only when the Page-In state is true. For each register in a bold-ruled cell, the corresponding register in a non-bold–ruled cell is accessible only when the Page-In state is false.

How to Page-In

The NAT9914 enters the Page-In state when the host interface writes the Page-In auxiliary command to the Auxiliary Mode Register (AUXMR). The NAT9914 registers appear at their Page-In state offset for the first register access after the Page-In command. The NAT9914 leaves the Page-In state at the end of the first register access after the Page-In command.

Hidden Registers

In addition to the registers shown in Table 4-1, the NAT9914 contains hidden registers. All hidden registers are write-only registers. Two or more hidden registers can appear at the same offset. When you write an 8-bit pattern to these offsets, some of the bits determine which hidden register will be written. The other bits represent the value written to the register.

Address Register Map

The NAT9914 has two address registers: ADR1 and ADR0. Table 4-1 shows the offsets for the readable portion of ADR1 and ADR0. The writable portion of ADR0 and ADR1 appears at the offset of the Address Register (ADR) shown in Table 4-1. Table 4-2 shows the bit map for the two writable address registers.

Table 4-2. Hidden Registers at Offset 6 (ADR)

ADR0 0 DT0 DL0 AD5–0 AD4–0 AD3–0 AD2–0 AD1–0

ADR1 1 DT1 DL1 AD5–1 AD4–1 AD3–1 AD2–1 AD1–1

7210-Mode Interface Registers Chapter 4

7210 Mode Only

Auxiliary Mode Register Map

Several hidden registers appear at the AUXMR offset. Table 4-3 shows these hidden registers.

Table 4-3. Hidden Registers at Offset 5 (AUXMR)

PPR 0 1 1 U S P3 P2 P1

AUXRA 1 0 0 BIN XEOS REOS HLDE HLDA

AUXRB 1 0 1 ISS INV TRI SPEOI CPT

AUXRE 1100DHADT DHADC DHDT DHDC

AUXRF 1101DHATA DHALA DHUNTL DHALL

AUXRG 0100NTNL RPP2 DISTCT CHES

AUXRI 1110USTD PP2 0 SISB

ICR 0010 F3 F2 F1 F0

ENABLE

Register Bit Descriptions

Some 7210-mode registers and 9914-mode registers share identical names. The 9914-mode registers are described in Chapter 3, 9914-Mode Interface Registers. If you are using the NAT9914 in 7210 mode, be sure to read the proper description for the 7210-mode registers.

All registers are listed in alphabetical order. The registers are alphabetized according to their mnemonics.

Chapter 4 7210-Mode Interface Registers

7210 Mode Only

Address Mode Register (ADMR)

Attributes: Write only

76543210

ton lon TRM1 TRM0 0 0 ADM1 ADM0

The host interface can put the NAT9914 into one of six GPIB addressing modes by writing to the Address Mode Register (ADMR). The values of ADMR (7–6; 3–0) are undefined after a hardware reset. Before the host interface can clear Power On (pon), it must write a valid pattern to the ADMR.

Table 4-4. Valid ADMR Patterns

Hex Value

ADMR*

30 No Addressing

The Controller cannot address the NAT9914 to become a Talker or Listener in no-addressing mode.

31 Normal Dual Addressing

The NAT9914 can implement one or two logical devices by using normal dual addressing.

See the GPIB Addressing section in Chapter 5, Software Considerations.

32 Extended Single Addressing

Extended single addressing mode implements the Extended Listener and Extended Talker functions, as defined in the IEEE 488 standard, without intervention from the host interface.

See the GPIB Addressing section in Chapter 5, Software Considerations.

33 Extended Dual Addressing

Extended dual addressing mode implements the Extended Listener and Extended Talker functions, as defined in the IEEE 488 standard. This mode requires intervention from the host interface.

GPIB Addressing Mode

See the GPIB Addressing section in Chapter 5, Software Considerations.

(continues)

7210-Mode Interface Registers Chapter 4

7210 Mode Only

ADMR (continued)

Table 4-4. Valid ADMR Patterns (Continued)

Hex Value

ADMR*

70 Listen Only (lon)

The NAT9914 becomes a GPIB Listener and enters the Listener Active State (LACS). Do not use lon if a GPIB Controller is present in the GPIB system.

The host interface should write a hex 30 (No Addressing) to the ADMR immediately after writing lon to the ADMR. To force the NAT9914 to exit LACS, issue the local unlisten (lul) auxiliary command.

B0 Talk Only (ton)

The NAT9914 becomes a GPIB Talker. Do not use ton if a GPIB Controller is present in the GPIB system.

The host interface should write a hex 30 (No Addressing) to the ADMR immediately after writing ton to the ADMR. To force the NAT9914 to exit the Talker Active State (TACS), issue the local untalk (lut) auxiliary command.

* The hex values in Table 4-4 assume that TRM1 = 1 and TRM0 = 1.

Bit Mnemonic Description

GPIB Addressing Mode

5–4w TRM[1–0] Transmit/Receive Mode bits

These bits have no effect. A hardware reset clears TRM1 and TRM0.

Chapter 4 7210-Mode Interface Registers

7210 Mode Only

Address Register (ADR)

Attributes: Write only

76543210

ARS DT DL AD5 AD4 AD3 AD2 AD1

Writing to the ADR loads the internal registers ADR0 and ADR1. You must load both ADR0 and ADR1 for all addressing modes.

Bit Mnemonic Description

7w ARS Address Register Select bit

If ARS = 1, writing to the ADR loads the seven low-order bits of ADR into internal register ADR1. If ARS = 0, writing to the ADR loads the seven low-order bits into ADR0.

6w DT Disable Talker bit

DT = 1 disables recognition of the GPIB talk address formed from AD[5–1]. ADR0 and ADR1 have independent DT bits.

5w DL Disable Listener bit

DL = 1 disables recognition of the GPIB listen address formed from AD[5–1]. ADR0 and ADR1 have independent DL bits.

4–0w AD[5–1] NAT9914 GPIB Address bits 5 through 1

These bits specify the GPIB address of the NAT9914. The corresponding GPIB talk address is formed by adding hex 40 to AD[5–1], while the corresponding GPIB listen address is formed by adding hex 20 to AD[5–1]. The value written to AD[5–1] should not be 11111 (binary), because the corresponding talk and listen addresses would conflict with the GPIB Untalk (UNT) and GPIB Unlisten (UNL) commands.

ADR0 and ADR1 have independent AD[5–1] bits.

7210-Mode Interface Registers Chapter 4

7210 Mode Only

Address Register 0 (ADR0)

Attributes: Read only

76543210

X DT0 DL0 AD5–0 AD4–0 AD3–0 AD2–0 AD1–0

Address Register 0 (ADR0) reflects the internal GPIB address status of the NAT9914. In extended single addressing mode, ADR0 indicates the address and enable bits for the primary GPIB address of the NAT9914. In the dual primary addressing modes, ADR0 indicates the NAT9914 major primary GPIB address.

Bit Mnemonic Description

7r X Reads back a 1 or 0.

6r DT0 Disable Talker 0 bit

If DT0 = 1, the primary (or major) Talker function is not enabled, and ADR0 is not compared with GPIB Talker addresses.

If DT0 = 0, the NAT9914 responds to a GPIB talk address matching bits AD[5–0 through 1–0].

5r DL0 Disable Listener 0 bit

If DL0 = 1, the primary (or major) Listener function is not enabled, and ADR0 is not compared with GPIB Listener addresses.

If DL0 = 0, the NAT9914 responds to a GPIB listen address matching bits AD[5–0 through 1–0].

4–0r AD[5–0 – 1–0] NAT9914 GPIB Address bits 5–0 through 1–0

These are the lower 5 bits of the NAT9914 GPIB primary (or major) address. The primary talk address is formed by adding hex 40 to AD[5–0 through 1–0], while the primary listen address is formed by adding hex 20.

Chapter 4 7210-Mode Interface Registers

7210 Mode Only

Address Register 1 (ADR1)

Attributes: Read only

76543210

EOI DT1 DL1 AD5–1 AD4–1 AD3–1 AD2–1 AD1–1

Address Register 1 (ADR1) indicates the status of the GPIB address and enable bits for the secondary address of the NAT9914 if extended single addressing is used. ADR1 indicates the minor primary address of the NAT9914 if dual primary addressing is used.

Bit Mnemonic Description

7r EOI End-or-Identify bit

EOI indicates the value of the GPIB EOI line that is latched when a data byte is received by the NAT9914 GPIB Acceptor Handshake (AH) function. If EOI = 1, the EOI line was asserted with the received byte. EOI is cleared by issuing the Chip Reset auxiliary command. EOI is updated after each byte is received.

6r DT1 Disable Talker 1 bit

If DT1 = 1, the secondary (or minor) Talker function is not enabled—that is, the GPIB secondary address (or minor primary talk address) is not compared with this register.

5r DL1 Disable Listener 1 bit

If DL1 = 1, the secondary (or minor) Listener function is not enabled—that is, the GPIB secondary address (or minor primary listen address) is not compared with this register.

4–0r AD[5–1 – 1–1] NAT9914 GPIB Address bits 5–1 through 1–1

These bits indicate the NAT9914 secondary or minor address. Form the secondary address by adding hex 60 to bits AD[5–1 through 1–1]. Form the minor talk address by adding hex 40 to AD[5–1 through 1–1]. Form the listen address by adding a hex 20.

7210-Mode Interface Registers Chapter 4

7210 Mode Only

Address Status Register (ADSR)

Attributes: Read only

76543210

CIC ATN* SPMS LPAS TPAS LA TA MJMN

The Address Status Register (ADSR) contains information that you can use to monitor the NAT9914 GPIB address status.

Bit Mnemonic Description

7r CIC Controller-In-Charge bit

CIC = ~(CIDS + CADS)

CIC indicates that the NAT9914 GPIB Controller function is either in an active state with ATN* asserted or a standby state with ATN* unasserted. The Controller function is in an idle state (CIDS or CADS) if CIC = 0.

6r ATN* Attention* bit

ATN* is a status bit that indicates the current level of the GPIB ATN* signal. If ATN* = 0, the GPIB ATN* signal is asserted.

5r SPMS Serial Poll Mode State bit

If SPMS = 1, the NAT9914 GPIB Talker (T) or Talker Extended (TE) function is enabled to participate in a serial poll.

SPMS is set by

SPE & ACDS

SPMS is cleared by

(SPD & ACDS) + pon + IFC

Chapter 4 7210-Mode Interface Registers

7210 Mode Only

ADSR (continued)

Bit Mnemonic Description

4r LPAS Listener Primary Addressed State bit

LPAS indicates that the NAT9914 has received its primary listen address. See the Address Mode Register (ADMR) section, which is located earlier in this chapter.

LPAS is cleared by

(PCG & ~MLA & ACDS) + pon

3r TPAS Talker Primary Addressed State bit

TPAS indicates that the NAT9914 has received its primary GPIB talk address. See the Address Mode Register (ADMR) section, which is located earlier in this chapter.

TPAS is cleared by

(PCG & ~MTA & ACDS) + pon

2r LA Listener Active bit

LA = 1 when the NAT9914 has been addressed or programmed as a GPIB Listener—that is, the NAT9914 is in the LACS or the Listener Addressed State (LADS). The NAT9914 is addressed to listen when it receives its listen address from the CIC. The NAT9914 can also be programmed to listen by using the Listen-Only (lon) bit in the ADMR.

If the NAT9914 is addressed to talk, it is automatically unaddressed to listen.

LA is also cleared by

(UNL & ACDS) + IFC + pon + (lun & CACS) + lul

1r TA Talker Active bit

TA = 1 when the NAT9914 has been addressed or programmed as the GPIB Talker—that is, the NAT9914 is in the TACS, the Talker Addressed State (TADS), or the

7210-Mode Interface Registers Chapter 4

7210 Mode Only

ADSR (continued)

Bit Mnemonic Description

Serial Poll Active State (SPAS). The NAT9914 can be addressed to talk when it receives its talk address from the CIC. It can also be programmed to talk by using the TalkOnly (ton) bit in the ADMR.

If the NAT9914 is addressed to listen, it is automatically unaddressed to talk.

TA is also cleared by

(OTA & ACDS) + IFC + pon + lut

0r MJMN Major-Minor bit

MJMN indicates whether the information in the other ADSR bits applies to the NAT9914 major or minor Talker and Listener functions. MJMN = 1 when the NAT9914 receives its GPIB minor talk address or minor listen address. MJMN clears when the NAT9914 receives its major talk or major listen address. The pon message also clears MJMN.

Note: Only one Talker or Listener can be active at a

time. The MJMN bit indicates which, if either, of the NAT9914 Talker and Listener functions is addressed or active.

MJMN is always 0 unless the normal or extended dual primary addressing mode is enabled. See the Address Mode Register (ADMR) section, which is located earlier in this chapter.

Chapter 4 7210-Mode Interface Registers

7210 Mode Only

Auxiliary Mode Register (AUXMR)

Attributes: Write only

Permits access to hidden registers

76543210

AUX7 AUX6 AUX5 AUX4 AUX3 AUX2 AUX1 AUX0

Use the AUXMR to issue auxiliary commands and to write the following eight hidden registers:

• Parallel Poll Register (PPR)

• Auxiliary Register A (AUXRA)

• Auxiliary Register B (AUXRB)

• Auxiliary Register E (AUXRE)

• Auxiliary Register F (AUXRF)

• Auxiliary Register G (AUXRG)

• Auxiliary Register I (AUXRI)

• Internal Counter Register (ICR)

Note: You should issue commands at intervals of at least 4 clock periods.

For more information, see the Hidden Registers section, which is located earlier in this chapter.

7210-Mode Interface Registers Chapter 4

7210 Mode Only

AUXMR (continued)

Table 4-5 summarizes the AUXMR auxiliary commands and Table 4-6 describes the AUXMR auxiliary commands.

Table 4-5. Auxiliary Command Summary

Hex

Code*

00 Immediate Execute Power-On (pon)

01 Clear Parallel Poll Flag (~ist)

02 Chip Reset (chip_reset)

03 Finish Handshake (rhdf)

04 Trigger (trig)

05 Clear Or Pulse Return To Local (rtl)

06 Send EOI (seoi)

07 Nonvalid Secondary Command Or

Address (nonvalid)

08† Request Control Command (rqc)

09 Set Parallel Poll Flag (ist)

0A† Release Control Command (rlc)

0B† Untalk Command (lut)

0C† Unlisten Command (lul)

Auxiliary Command

0D Set Return To Local (rtl)

0E† New Byte Available False (nbaf)

0F Valid Secondary Command or Address

(valid)

10 Go To Standby (gts)

(continues)

Chapter 4 7210-Mode Interface Registers

7210 Mode Only

AUXMR (continued)

Table 4-5. Auxiliary Command Summary (Continued)

Hex

Code*

Take Control Asynchronously (tca)

Take Control Synchronously (tcs)

Take Control Synchronously On End (tcse)

Listen (ltn)

Listen In Continuous Mode (ltn and cont)

Local Unlisten (lun)

14 Disable System Control (~rsc)

15† Switch To 9914 Mode Command

(sw9914)

Clear IFC (~sic & rsc)

Set IFC (sic & rsc)

Clear REN (~sre & rsc)

Set REN (sre & rsc)

18†

Request rsv True (reqt)

19†

Request rsv False (reqf)

1D Execute Parallel Poll (rppl)

50† Page-In Additional Registers (page-in)

Auxiliary Command

51† Holdoff Handshake Immediately (hldi)

54† Clear DET (ISR1[5]r) Command

55† Clear END (ISR1[4]r) Command

56† Clear DEC (ISR1[3]r) Command

57† Clear ERR (ISR1[2]r) Command

58† Clear SRQI (ISR2[6]r) Command

59† Clear LOKC (ISR2[2]r) Command

5A† Clear REMC (ISR2[1]r) Command

(continues)

7210-Mode Interface Registers Chapter 4

7210 Mode Only

AUXMR (continued)

Table 4-5. Auxiliary Command Summary (Continued)

Hex

Code*

5B† Clear ADSC (ISR2[0]r) Command

5C† Clear IFCI (ISR0[3]r) Command

5D† Clear ATNI (ISR0[2]r) Command

5E†

Clear SYNC (ISR0[0]r) Command

5F†

Set SYNC (ISR0[0]r) Command

* Represents all eight bits of the AUXMR. † Denotes an auxiliary command not available

in the NEC µPD7210.

Auxiliary Command

Chapter 4 7210-Mode Interface Registers

7210 Mode Only

AUXMR (continued)

Table 4-6. Auxiliary Command Description

Data

Pattern

(Hex)

00 Immediate Execute Power-On (pon)

The Immediate Execute Power-On auxiliary command sets the local pon message true, then clears it. If the local pon message is already asserted, the pon auxiliary command simply clears the local pon message. The following figure illustrates the behavior of the local pon message:

local pon message

true

chip_reset aux. command

When the local pon message is true, the NAT9914 holds all GPIB interface functions in their idle states.

01 09

Clear Parallel Poll Flag (~ist) Set Parallel Poll Flag (ist)

Description

start of pon aux.

command pulse

end of pon aux.

command pulse

These commands set and clear the Parallel Poll Flag. The value of the Parallel Poll Flag is used as the local message ist when AUXRB[4]w = 0. The value of the Service Request State (SRQS) is used as ist when ISS = 1. The Chip Reset auxiliary command or a hardware reset clears ist.

(continues)

7210-Mode Interface Registers Chapter 4

7210 Mode Only

AUXMR (continued)

Table 4-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

02 Chip Reset

The Chip Reset auxiliary command resets the NAT9914 to the following conditions:

• The local pon message is set and the interface functions are

• The Serial Poll Mode Register (SPMR) bits are cleared.

• The TRM[1–0] bits are cleared.

• The EOI bit is cleared.

• The AUXRA, AUXRB, AUXRE, AUXRF, AUXRG, and

• The Parallel Poll Flag is cleared.

• The Bus Control Register (BCR) is cleared.

The interface functions remain in their idle states until they are released by an Immediate Execute pon command. While the interface functions are in their idle states, the host interface can program the NAT9914 writable bits to their desired states.

Description

placed in their idle states.

AUXRI registers are cleared.

03 Finish Handshake (rhdf)

The Finish Handshake command finishes a GPIB handshake that was stopped because of a Holdoff On RFD condition.

04 Trigger (trig)

The Trigger command generates a high pulse on the TR pin. The Device Execute Trigger (DET) bit is not set by issuing the Trigger command.

(continues)

Chapter 4 7210-Mode Interface Registers

7210 Mode Only

AUXMR (continued)

Table 4-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

06 Send EOI (seoi)

07 Nonvalid Secondary Command Or Address (nonvalid)

Clear Or Pulse Return To Local (rtl) Set Return To Local (rtl)

The two Return To Local commands implement the rtl message as defined by the IEEE 488 standard. If the host interface writes 05 hex, the rtl message is generated in the form of a pulse. If rtl is already set, the rtl command clears it. If the host interface writes 0D hex, the rtl command is set and remains set until either the 05 hex rtl command is issued or the Chip Reset auxiliary command is issued.

The seoi command forces the GPIB EOI line to go true with the next data byte transmitted. The EOI line is cleared upon completion of the handshake for that byte. When NTNL = 0, the NAT9914 recognizes the seoi command only if TACS = 1—that is, the NAT9914 is in the Talker Active State.

The nonvalid command releases a DAC (Data Accepted) holdoff. If APT = 1, the NAT9914 operates as if an Other Secondary Address (OSA) message had been received.

Description

08* Request Control Command (rqc)

If the NAT9914 is in the Idle Controller State, the rqc command forces the NAT9914 to become the Active Controller when it detects that the ATN signal is unasserted.

0A* Release Control Command (rlc)

The rlc command forces the NAT9914 to become an Idle Controller and to unassert ATN.

0B* Untalk (lut)

The lut command issues the local unt message, forcing the Talker function to enter the Talker Idle State (TIDS).

(continues)

7210-Mode Interface Registers Chapter 4

7210 Mode Only

AUXMR (continued)

Table 4-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

0C* Unlisten (lul)

The lul command issues the local unl message, forcing the Listener function to enter the Listener Idle State (LIDS).

0E* New Byte Available False (nbaf)

nbaf forces the local message, nba, to become false. This action prohibits the NAT9914 from sending the last byte written to the Command/Data Out Register (CDOR). See the Using nbaf section in Chapter 5, Software Considerations.

0F Valid Secondary Command Or Address (valid)

The valid command releases a DAC holdoff. If APT = 1, the NAT9914 operates as if a My Secondary Address (MSA) message had been received.

10 Go To Standby (gts)

The gts command pulses the local gts message. If the NAT9914 is the Active Controller, gts forces the NAT9914 to become the Standby Controller and to unassert the GPIB ATN signal. See the Three Basic

Controller States section in Chapter 6, Controller Software Considerations.

Description

11 Take Control Asynchronously (tca)

The tca command pulses the local tca message. If the NAT9914 is the Standby Controller, tca forces the NAT9914 to become the Active Controller and to assert the GPIB ATN signal. See the Standby State

to Active State section in Chapter 6, Controller Software Considerations.

(continues)

Chapter 4 7210-Mode Interface Registers

7210 Mode Only

AUXMR (continued)

Table 4-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

12 Take Control Synchronously (tcs)

The tcs command sets the local tcs message. If the NAT9914 is the Standby Controller and an Active Listener, the tcs message forces the NAT9914 to become the Active Controller when the NAT9914 performs an RFD (Ready For Data) holdoff—that is, the AH function enters the Acceptor Not Ready State (ANRS). The local tcs message clears when the NAT9914 becomes the Active Controller by this method or if the NAT9914 becomes an Idle Controller. See the

Standby State to Active State section in Chapter 6, Controller Software Considerations.

13 Listen (ltn)

The ltn command pulses the local ltn message. If the NAT9914 is the Active Controller, the local ltn message forces the NAT9914 to become an Addressed Listener. The ltn command can also take the NAT9914 out of the continuous data-receiving mode (see ltn & cont command).

14 Disable System Control (~rsc)

The ~rsc command, a hardware reset, or the Chip Reset auxiliary command clears the local rsc message.

Description

15* Switch To 9914A Mode (sw9914)

This command places the NAT9914 in 9914 compatibility mode.

16 Clear IFC (~sic & rsc)

The ~sic & rsc command clears the local sic message and sets the local rsc messages. This action forces the NAT9914 to become the System Controller and to unassert the GPIB Interface Clear (IFC) signal.

(continues)

7210-Mode Interface Registers Chapter 4

7210 Mode Only

AUXMR (continued)

Table 4-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

17 Clear REN (~sre & rsc)

The ~sre & rsc command clears the local sre message and sets the local rsc messages. This action forces the NAT9914 to become the System Controller and to unassert the GPIB Remote Enable (REN) signal.

18* 19*

1A Take Control Synchronously On END (tcse)

Request rsv True (reqt) Request rsv False (reqf)

The reqt and reqf commands are inputs to the IEEE 488.2 Service Request Synchronization Circuitry. These commands set and clear the local rsv message.

If STBO IE = 1, the reqt and reqf commands are issued immediately. If STBO IE = 0, the reqt and reqf commands are not issued immediately: they are issued on the write of the SPMR that follows the issuing of the reqt or reqf auxiliary command.

The tcse command forces the local tcs message to set when the NAT9914 accepts a byte satisfying the END condition (see the END RX bit, ISR1[4], description that is in the Interrupt Status Register 1 section in this chapter). If the NAT9914 is the Standby Controller and an Active Listener, the tcs message forces the NAT9914 to become the Active Controller when the NAT9914 performs an RFD holdoff—that is, when the AH function enters ANRS. The local tcs message (and the END detection circuitry) clears when the NAT9914 becomes the Active Controller by this method or if the NAT9914 becomes an Idle Controller.

Description

(continues)

Chapter 4 7210-Mode Interface Registers

7210 Mode Only

AUXMR (continued)

Table 4-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

1B Listen In Continuous Mode (ltn & cont)

The ltn & cont command pulses the local ltn message. If the NAT9914 is the Active Controller, the local ltn message forces the NAT9914 to become an Addressed Listener.

The ltn & cont command also places the NAT9914 in continuous mode regardless of the settings of the AUXRA[1–0] bits. If the NAT9914 enters continuous mode because of the ltn & cont command, it remains in continuous mode until it becomes unaddressed to Listen—that is, the Listener (L) or LE function enters LIDS—or until the control program issues the ltn command.

1C Local Unlisten (lun)

The lun command pulses the local lun message. If the NAT9914 is the Active Controller, the local lun message forces it to become an Unaddressed Listener—that is, the L or LE function enters LIDS.

1D Execute Parallel Poll (rpp1)

The rpp1 command sets the local rpp message. If the NAT9914 is the Active Controller, the rpp message forces it to send the Identify (IDY) message to all GPIB devices in the system and to conduct a parallel poll. The rpp message clears when the NAT9914 completes a parallel poll or becomes an Idle Controller.

Description

1E Set IFC (sic & rsc)

The sic & rsc command sets the local sic and rsc messages. This action forces the NAT9914 to become the System Controller and to assert the GPIB IFC signal. The local message pon or the ~rsc auxiliary command clears sic.

1F Set REN (sre & rsc)

The sre & rsc command sets the local sre and rsc messages. This action forces the NAT9914 to become the System Controller and to assert the GPIB REN signal. The local message pon or the ~rsc auxiliary command clears sic.

(continues)

7210-Mode Interface Registers Chapter 4

7210 Mode Only

AUXMR (continued)

Table 4-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

50* Page-In Additional Registers (page-in)

The Page-In command forces the NAT9914 to enter the Page-In state. The Page-In state makes several registers accessible. See The Page- In State section, which is located at the beginning of this chapter.

51* Holdoff Handshake Immediately (hldi)

This command forces the Acceptor Handshake function to immediately perform an RFD holdoff. Issuing this command forces a transition into ANRS, where the handshake is held off until a finish handshake auxiliary command is issued.

54* Clear DET

This command clears the DET bit (ISR1[5]r). Use this command to clear the DET bit when SISB = 1.

55* Clear END

This command clears the END bit (ISR1[4]r). Use this command to clear the END bit when SISB = 1.

56* Clear DEC

Description

This command clears the DEC bit (ISR1[3]r). Use this command to clear the DEC bit when SISB = 1.

57* Clear ERR

This command clears the ERR bit (ISR1[2]r). Use this command to clear the ERR bit when SISB = 1.

58* Clear SRQI Command

This command clears the Service Request (SRQI) bit if SISB = 1. See the SRQI bit description that is in the Interrupt Status Register 2 (ISR2) section in this chapter.

(continues)

Chapter 4 7210-Mode Interface Registers

7210 Mode Only

AUXMR (continued)

Table 4-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

59* Clear LOKC

This command clears the LOKC bit (ISR2[2]r). Use this command to clear the LOKC bit when SISB = 1.

5A* Clear REMC

This command clears the REMC bit (ISR2[1]r). Use this command to clear the REMC bit when SISB = 1.

5B* Clear ADSC

This command clears the ADSC bit (ISR2[0]r). Use this command to clear the ADCS bit when SISB = 1.

5C* Clear IFCI

This command clears the IFCI bit (ISR0[3]r). Use this command to clear the IFCI bit when SISB = 1.

5D* Clear ATNI

This command clears the ATNI bit (ISR0[2]r). Use this command to clear the ATNI bit when SISB = 1.

Description

5E* 5F*

* Denotes an auxiliary command not available in the µPD7210.

Clear SYNC Set SYNC

These commands start or reset the SYNC function.

7210-Mode Interface Registers Chapter 4

7210 Mode Only

Auxiliary Register A (AUXRA)

Attributes: Write only

Accessed at the same offset as AUXMR

76543210

1 0 0 BIN XEOS REOS HLDE HLDA

AUXRA controls the EOS and END messages and specifies the RFD holdoff mode. The Chip Reset auxiliary command or a hardware reset clears AUXRA. You write to AUXRA at the same offset as the AUXMR.

Bit Mnemonic Description

4w BIN Binary bit

3w XEOS Transmit END With EOS bit

XEOS permits or prohibits automatic transmission of the GPIB END message at the same time as the EOS message when the NAT9914 is in TACS. If XEOS = 1 and the byte in the CDOR matches the contents of the EOSR, the EOI line is sent true along with the data.

2w REOS END On EOS Received bit

The REOS bit permits or prohibits setting the END bit (ISR1[4]r) when the NAT9914 receives the EOS message as a Listener. If REOS = 1 and the byte in the Data In Register (DIR) matches the byte in the EOSR, the END RX bit (ISR1[4]r) is set and the acceptor function treats the EOS character just as if it were received with EOI asserted.

Chapter 4 7210-Mode Interface Registers

7210 Mode Only

AUXRA (continued)

Bit Mnemonic Description

1w, 0w HLDE Holdoff On End bit

HLDA Holdoff On All Data bit

HLDE and HLDA together determine the GPIB data-receiving mode.

HLDE HLDA Data-Receiving Mode

0 0 Normal Handshake Mode

0 1 RFD Holdoff on All Data Mode

1 0 RFD Holdoff on END Mode

1 1 Continuous Mode

Issuing the ltn & cont auxiliary command can also place the NAT9914 in the continuous data-receiving mode. The NAT9914 enters continuous mode regardless of the value of HLDE and HLDA. In this situation, the NAT9914 remains in continuous mode until you issue the ltn auxiliary command or the NAT9914 becomes unaddressed to listen (by entering the LIDS).

7210-Mode Interface Registers Chapter 4

7210 Mode Only

Auxiliary Register B (AUXRB)

Attributes: Write only

Accessed at the same offset as AUXMR

76543210

1 0 1 ISS INV TRI SPEOI CPT

ENABLE

AUXRB affects several interface functions. The Chip Reset auxiliary command or a hardware reset clears AUXRB. You write to AUXRB at the same offset as the AUXMR.

Bit Mnemonic Description

4w ISS Individual Status Select bit

ISS determines the value of the NAT9914 ist message. When ISS = 1, ist takes on the value of the NAT9914 SRQS. (The NAT9914 asserts the GPIB SRQ message when it is in SRQS.) If ISS = 0, ist takes on the value of the NAT9914 Parallel Poll Flag. You set and clear the Parallel Poll Flag by using the Set Parallel Poll Flag and Clear Parallel Poll Flag auxiliary commands. See the

Parallel Polling section in Appendix B, Introduction to the GPIB.

3w INV Invert bit

INV determines the polarity of the INT* pin.

INV Bit INT* Pin Polarity

0 Active Low

1 Active High

2w TRI Three-State Timing bit

TRI determines the NAT9914 GPIB Source Handshake Timing (T1). Clearing TRI sets the low-speed timing (T1 ≥ 2 µs). Setting TRI enables the NAT9914 to use a shorter T1 delay. See the T1 Delay Generation section in Chapter 5, Software Considerations.

National Instruments NAT9914 Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Limited Warranty

Copyright

Trademarks

Contents

Figures

Tables

About This Manual

Organization of This Manual

Conventions Used in This Manual

Related Documentation

Customer Communication

Chapter 1 Introduction and General Description

IEEE 488 Capabilities

Table 1-1. NAT9914 IEEE 488 Interface Capabilities

CPU Interface Capabilities

Typical System Interface

Chapter 2 NAT9914 Architecture

Figure 2-1. NAT9914 Block Diagram

Changing the NAT9914 Mode

Figure 2-2. Changing the NAT9914 Mode

Chapter 3 9914-Mode Interface Registers

9914 Register Map

Table 3-1. 9914-Mode Interface Registers

The Page-In Condition

Hidden Registers

Accessory Read Register Map

Table 3-2. Hidden Registers at the ACCR Offset

Register Bit Descriptions

Accessory Register A (ACCRA)

Accessory Register B (ACCRB)

Accessory Register E (ACCRE)

Accessory Register F (ACCRF)

Accessory Register I (ACCRI)

Address Register (ADR)

Address Status Register (ADSR)

Table 3-3. Auxiliary Command Summary

Table 3-4. Auxiliary Command Description

Figure 3-1. GPIB I/O Hardware Configuration

Command/Data Out Register (CDOR)

Data In Register (DIR)

End-of-String Register (EOSR)

Internal Count Register (ICR)

Interrupt Mask Register 1 (IMR1)

Interrupt Status Register 1 (ISR1)

Interrupt Mask Register 2 (IMR2)

Interrupt Status Register 2 (ISR2)

Parallel Poll Register (PPR)

Serial Poll Mode Register (SPMR)

Serial Poll Status Register (SPSR)

Chapter 4 7210-Mode Interface Registers

7210 Register Map

Table 4-1. 7210-Mode Register Map

The Page-In State

How to Page-In

Hidden Registers

Address Register Map

Table 4-2. Hidden Registers at Offset 6 (ADR)

Auxiliary Mode Register Map

Table 4-3. Hidden Registers at Offset 5 (AUXMR)

Register Bit Descriptions

Address Mode Register (ADMR)

Table 4-4. Valid ADMR Patterns

Address Register (ADR)

Address Register 1 (ADR1)

Address Status Register (ADSR)

Auxiliary Mode Register (AUXMR)

Table 4-5. Auxiliary Command Summary

Table 4-6. Auxiliary Command Description

Auxiliary Register A (AUXRA)

Auxiliary Register B (AUXRB)