National Instruments NAT7210 NAT7210 Reference Manual

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NAT7210

Reference Manual

June 1995 Edition

Part Number 370875A-01

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Limited Warranty

The NAT7210™ integrated circuit (“equipment”) is warranted against defects in material and workmanship under normal use and service for a period of one (1) year from the date of shipment from the National Instruments factory. During this period of one year, National Instruments shall at its sole option either repair, replace, or credit the Buyer for defective equipment if: (i) Buyer returns the equipment to National Instruments, FOB the National Instruments factory in Austin, Texas; (ii) Buyer notifies National Instruments promptly upon discovery of any defect in writing, including a detailed description of the defect; and (iii) upon examination of the returned equipment, National Instruments is satisfied that the circuit is defective and that the cause of such defect is not alteration or repair by someone other than National Instruments, neglect, accident, misuse, improper installation, or use contrary to any instructions issued by National Instruments.

A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work. Prior to issuance of an RMA by National Instruments, Buyer shall allow National Instruments the opportunity to inspect the equipment on-site at Buyer’s facility.

This warranty expires one year from date of original shipment regardless of any warranty performance during that warranty period. The warranty provided herein is Buyer’s sole and exclusive remedy for nonconformity of the equipment or for breach of any warranty. THE ABOVE IS IN LIEU OF ALL OTHER WARRANTIES EXPRESSED OR IMPLIED. NATIONAL INSTRUMENTS SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. BUYER’S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE BUYER. NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS, OR INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY THEREOF. This limitation of the liability of National Instruments will apply regardless of the form of action, whether in contract or tort, including negligence. National Instruments recommends against the use of its products as critical components in any life support devices or systems whose failure to perform can reasonably be expected to cause significant injury to a human. Buyer assumes all risk for such application and agrees to indemnify National Instruments for all damages which may be incurred due to use of the National Instruments standard devices in medical or life support applications. Any action against National Instruments must be brought within one year after the cause of action accrues.

National Instruments believes that the information in this manual is accurate. The document has been carefully reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition. The reader should consult National Instruments if errors are suspected. In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it.

Copyright

Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written consent of National Instruments Corporation.

Trademarks

NAT7210™ is a trademark of National Instruments Corporation. Product and company names listed are trademarks or trade names of their respective

companies.

WARNING REGARDING MEDICAL AND CLINICAL

USE OF NATIONAL INSTRUMENTS PRODUCTS

National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the part of the user or application designer. Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel, and all traditional medical safeguards, equipment, and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used. National Instruments products are NOT intended to be a substitute for any form of established process, procedure, or equipment used to monitor or safeguard human health and safety in medical or clinical treatment.

About This Manual ............................................................................................. xiii

Organization of This Manual ......................................................................... xiii

Conventions Used in This Manual................................................................. xiv

Related Documentation ................................................................................. xiv

Customer Communication ............................................................................. xv

Chapter 1 Introduction and General Description

IEEE 488 Capabilities.................................................................................... 1-1

CPU Interface Capabilities ............................................................................ 1-3

Typical System Interface ............................................................................... 1-4

Chapter 2 NAT7210 Architecture

NAT7210 Modes ........................................................................................... 2-3

Changing the NAT7210 Mode ........................................................ 2-3

....................................................................................... 2-1

Chapter 3 7210-Mode Interface Registers

7210 Register Map ......................................................................................... 3-1

The Page-In State ........................................................................................... 3-3

How to Page-In................................................................................ 3-3

Hidden Registers............................................................................................ 3-3

Address Register Map ..................................................................... 3-3

Auxiliary Mode Register Map ......................................................... 3-4

Address Mode Register (ADMR) ................................................... 3-5

Address Register (ADR) ................................................................. 3-8

Address Register 0 (ADR0)............................................................. 3-9

Address Register 1 (ADR1)............................................................. 3-10

Address Status Register (ADSR)..................................................... 3-11

Auxiliary Mode Register (AUXMR)............................................... 3-14

Auxiliary Register A (AUXRA) ..................................................... 3-27

Auxiliary Register B (AUXRB) ...................................................... 3-29

Auxiliary Register E (AUXRE)....................................................... 3-31

Auxiliary Register F (AUXRF) ....................................................... 3-32

Auxiliary Register G (AUXRG) ..................................................... 3-33

Auxiliary Register I (AUXRI) ......................................................... 3-35

Bus Control Register (BCR)/Bus Status Register (BSR) ................ 3-37

Command/Data Out Register (CDOR) ........................................... 3-39

Command Pass Through Register (CPTR) ..................................... 3-40

Data In Register (DIR) .................................................................... 3-41

End-of-String Register (EOSR)....................................................... 3-42

....................................................................... 3-1

........................................................ 1-1

Contents

Internal Count Register (ICR) ......................................................... 3-43

Internal Count Register 2 (ICR2) .................................................... 3-44

Interrupt Mask Register 0 (IMR0)................................................... 3-45

Interrupt Status Register 0 (ISR0) ................................................... 3-45

Interrupt Mask Register 1 (IMR1)................................................... 3-49

Interrupt Status Register 1 (ISR1) ................................................... 3-49

Interrupt Mask Register 2 (IMR2)................................................... 3-54

Interrupt Status Register 2 (ISR2) ................................................... 3-54

Parallel Poll Register (PPR) ............................................................ 3-58

Source/Acceptor Status Register (SASR) ....................................... 3-60

Serial Poll Mode Register (SPMR) ................................................. 3-62

Serial Poll Status Register (SPSR) .................................................. 3-62

Version Status Register (VSR)........................................................ 3-64

Chapter 4 9914-Mode Interface Registers

9914 Register Map ......................................................................................... 4-1

The Page-In Condition ................................................................................... 4-3

Hidden Registers............................................................................................ 4-3

Accessory Read Register Map......................................................... 4-3

Accessory Register A (ACCRA) ..................................................... 4-5

Accessory Register B (ACCRB) ..................................................... 4-6

Accessory Register E (ACCRE) ..................................................... 4-8

Accessory Register F (ACCRF) ...................................................... 4-9

Accessory Register I (ACCRI)........................................................ 4-10

Address Register (ADR) ................................................................. 4-11

Address Status Register (ADSR)..................................................... 4-12

Auxiliary Command Register (AUXCR) ........................................ 4-15

Bus Control Register (BCR)/Bus Status Register (BSR) ................ 4-28

Command/Data Out Register (CDOR) ........................................... 4-30

Command Pass Through Register (CPTR) ..................................... 4-31

Data In Register (DIR) .................................................................... 4-32

End-of-String Register (EOSR)....................................................... 4-33

Internal Count Register (ICR) ......................................................... 4-34

Interrupt Mask Register 0 (IMR0)................................................... 4-35

Interrupt Status Register 0 (ISR0) ................................................... 4-35

Interrupt Mask Register 1 (IMR1)................................................... 4-39

Interrupt Status Register 1 (ISR1) ................................................... 4-39

Interrupt Mask Register 2 (IMR2)................................................... 4-44

Interrupt Status Register 2 (ISR2) ................................................... 4-44

Parallel Poll Register (PPR) ............................................................ 4-48

Serial Poll Mode Register (SPMR) ................................................. 4-49

Serial Poll Status Register (SPSR) .................................................. 4-49

....................................................................... 4-1

NAT7210 Reference Manual vi © National Instruments Corp.

Chapter 5 Software Considerations

Chip Initialization Sequence .......................................................................... 5-1

1. Place the NAT7210 in 7210 Mode ............................................. 5-1

2. Make Sure the Local pon Message Is Asserted.......................... 5-1

3. Set the Clock Frequency............................................................. 5-1

4. Configure the Chip for GPIB Operation .................................... 5-2

A. Set the GPIB Address(es) .......................................... 5-2

B. Write the Initial Serial Poll Response........................ 5-2

C. Configure Initial Parallel Response ........................... 5-2

D. Set GPIB Handshake Parameters ............................... 5-2

5. Enable Interrupts ........................................................................ 5-2

6. Clear the Local pon Message ..................................................... 5-3

GPIB Talker or Listener Considerations ....................................................... 5-3

GPIB Addressing ............................................................................. 5-3

Logical and Physical Devices ........................................... 5-3

Normal and Extended Addressing .................................... 5-3

Implementing One Logical Device: Normal

Addressing ........................................................................ 5-3

Implementing One Logical Device: Extended

Addressing ........................................................................ 5-4

Implementing Two Logical Devices: Normal

Addressing ........................................................................ 5-4

Implementing Two Logical Devices: Extended

Addressing ........................................................................ 5-5

Implementing Three or More Logical Devices:

Normal Addressing ........................................................... 5-5

Implementing Three or More Logical Devices:

Extended Addressing ........................................................ 5-6

Programmed Implementation of a Talker and Listener................... 5-7

Detecting a GPIB Listener............................................................... 5-7

Sending GPIB Data Messages ....................................................................... 5-7

Basic Flow ....................................................................................... 5-7

Sending EOI or EOS ....................................................................... 5-8

Using DMA ..................................................................................... 5-8

T1 Delay Generation ....................................................................... 5-8

The T1 Delay .................................................................... 5-8

HSTS Definition ............................................................... 5-9

IEEE 488.1 Standard Requirements ................................. 5-9

T1 Delay: 7210 Mode ...................................................... 5-10

T1 Delay: 9914 Mode ...................................................... 5-10

Using nbaf ......................................................................... 5-11

Receiving GPIB Data Messages .................................................................... 5-11

Basic Flow ....................................................................................... 5-11

Receiving END or EOS ................................................................... 5-11

Performing an RFD Holdoff on the Last Data Byte........................ 5-12

Using DMA ..................................................................................... 5-12

Acceptor Handshake Holdoffs ....................................................................... 5-12

Contents

................................................................................... 5-1

Contents

The GPIB rdy Message and RFD Holdoffs..................................... 5-12

Generating the rdy Message.............................................. 5-13

Immediate RFD Holdoff ................................................... 5-13

Data-Receiving Modes...................................................... 5-13

Choosing a Data-Receiving Mode .................................... 5-14

DAC Holdoffs ................................................................................. 5-14

Determining When DAC Holdoffs Occur......................... 5-15

Device Status Reporting (Polling) ................................................................. 5-15

Requesting Service .......................................................................... 5-15

Asserting the SRQ Signal ................................................. 5-15

IEEE 488.2 Service Requesting ........................................ 5-16

7210-Style Service Requesting ......................................... 5-16

Responding to Serial Polls............................................................... 5-16

Responding to Parallel Polls ........................................................... 5-17

The ist Message ................................................................. 5-17

Remote Configuration ....................................................... 5-17

Local Configuration .......................................................... 5-17

Disabling the Parallel Poll Response ................................ 5-18

Generating Hardware Interrupts .................................................................... 5-18

Remote/Local State Considerations ............................................................... 5-18

Device Triggering .......................................................................................... 5-19

Device Clearing ............................................................................................. 5-19

Chapter 6 Controller Software Considerations

System Controller Considerations ................................................................. 6-1

Becoming System Controller .......................................................... 6-1

Other System Controller Capabilities: Setting and

Clearing REN .................................................................... 6-2

Disabling System Controller Capabilities ....................................... 6-2

GPIB Controller Considerations .................................................................... 6-2

Three Basic Controller States.......................................................... 6-2

Idle Controller State .......................................................... 6-2

Active Controller State ..................................................... 6-3

Standby Controller State ................................................... 6-3

Determining the Basic Controller State ............................ 6-3

Changing Controller States ............................................................. 6-3

Idle State to Active State: Becoming CIC ....................... 6-3

Active State to Standby State............................................ 6-4

Standby State to Active State............................................ 6-4

Active State to Idle State: Passing Control ...................... 6-5

Sending Remote Multiline Messages (Commands) ........................ 6-5

Polling: Obtaining Status from Devices ......................................... 6-5

Conducting Serial Polls ..................................................... 6-6

Configuring Devices for Parallel Polls ............................. 6-6

Conducting Parallel Polls.................................................. 6-7

............................................................. 6-1

NAT7210 Reference Manual viii © National Instruments Corp.

Chapter 7 Hardware Considerations

Pin Descriptions ............................................................................................. 7-1

GPIB Transceiver Controls ............................................................. 7-1

T/R1 .................................................................................. 7-1

T/R2 and T/R3 .................................................................. 7-1

GPIB Signal Pins ............................................................................. 7-2

GPIB Data Bus Pins ........................................................................ 7-3

CPU Register Control Pins.............................................................. 7-3

CS* and the CPU Address Bus ......................................... 7-3

RD*/WR* ......................................................................... 7-3

CPU Data Bus ................................................................... 7-3

DMA Pins........................................................................................ 7-3

DRQ .................................................................................. 7-3

DACK* ............................................................................. 7-4

Other Pins ........................................................................................ 7-4

INT.................................................................................... 7-4

RESET .............................................................................. 7-4

CLK ................................................................................... 7-5

Interfacing to Common GPIB Transceivers .................................................. 7-6

Appendix A Common Questions

............................................................................................. A-1

Contents

................................................................................. 7-1

Appendix B Introduction to the GPIB

History of the GPIB ....................................................................................... B-1

The IEEE 488.1 Specification ....................................................................... B-2

IEEE 488.2 and SCPI Specifications ............................................................. B-2

Problems with IEEE 488.1 Compatible Devices............................. B-2

The IEEE 488.2 Solution................................................................. B-2

SCPI Specification........................................................................... B-3

GPIB Hardware Configuration ...................................................................... B-4

GPIB Signals and Lines................................................................... B-7

Data Lines ....................................................................................... B-7

Interface Management Lines ........................................................... B-8

Handshake Lines ............................................................................. B-11

Physical and Electrical Specifications ............................................. B-13

.................................................................................. B-1

Interface Clear (IFC) ......................................................... B-8

Attention (ATN)................................................................ B-9

Remote Enable (REN) ...................................................... B-10

End-or-Identify (EOI) ....................................................... B-10

Service Request (SRQ) ..................................................... B-11

Not Ready For Data (NRFD) ............................................ B-11

Not Data Accepted (NDAC) ............................................. B-12

Data Valid (DAV) ............................................................. B-12

Three-Wire Handshake Process ........................................ B-13

Contents

Controllers, Talkers, and Listeners ................................................................ B-14

Controllers ....................................................................................... B-14

Talkers and Listeners....................................................................... B-15

Data and Command Messages ....................................................................... B-17

GPIB Addressing Protocol............................................................................. B-17

Reading the Multiline Interface Command Messages Table .......... B-19

Secondary Addressing ..................................................................... B-19

Unaddressing Command Messages ................................................. B-19

Termination Methods ..................................................................................... B-19

EOS Method .................................................................................... B-20

EOI Method ..................................................................................... B-20

Count Method.................................................................................. B-20

Combinations of Termination Methods........................................... B-21

Serial Polling ................................................................................................. B-21

Servicing SRQs ............................................................................... B-21

Serial Polling Devices ..................................................................... B-21

Status Byte Model for IEEE 488.1 .................................................. B-23

ESR and SRE Registers ................................................................... B-23

Status Byte Model for IEEE 488.2 .................................................. B-23

Parallel Polling ............................................................................................... B-25

Overview of Parallel Polls ............................................................... B-25

Determining the Value of the PPR Message ..................... B-26

Configuring a Device for Parallel Polls ............................ B-26

Determining the PPE Message.......................................... B-27

Physical Representation of the PPR Message ................... B-27

Clearing and Triggering Devices ................................................................... B-28

Appendix C Standard Commands for Programmable Instruments (SCPI)

IEEE 488.2 Common Commands Required by SCPI ................................... C-2

SCPI Required Commands ............................................................................ C-3

SCPI Optional Commands ............................................................................. C-3

Programming with SCPI ................................................................................ C-4

Constructing SCPI Commands by Using the Hierarchical

Command Structure ......................................................................... C-5

Parsing SCPI Commands ................................................................ C-7

......... C-1

Appendix D Multiline Interface Command Messages

.................................................... D-1

Appendix E Mnemonics Key

..................................................................................................... E-1

Appendix F Customer Communication

............................................................................... F-1

Glossary.................................................................................................................... G-1

NAT7210 Reference Manual x © National Instruments Corp.

Contents

Index.......................................................................................................................... I-1

Figures

Figure 1-1. NAT7210 Implementation Block Diagram......................................... 1-4

Figure 2-1. NAT7210 Block Diagram ................................................................... 2-2

Figure 2-2. Changing the NAT7210 Mode............................................................ 2-3

Figure 3-1. GPIB I/O Hardware Configuration ..................................................... 3-38

Figure 4-1. GPIB I/O Hardware Configuration ..................................................... 4-29

Figure 6-1. Basic Controller States........................................................................ 6-2

Figure 7-1. CLK Signal Timing Diagram.............................................................. 7-5

Figure 7-2. Interfacing the NAT7210 to the 75160 and 75162 Transceivers........ 7-6

Figure B-1. Structure of the GPIB Standards ......................................................... B-3

Figure B-2. Linear Configuration ........................................................................... B-5

Figure B-3. Star Configuration ............................................................................... B-6

Figure B-4. GPIB Connector and Pin Assignments ............................................... B-7

Figure B-5. Three-Wire Handshake Process .......................................................... B-12

Figure B-6. System Setup Example ....................................................................... B-16

Figure B-7. Events During a Serial Poll ................................................................. B-22

Figure B-8. IEEE 488.2 Standard Status Structures ............................................... B-24

Figure B-9. Example Exchange of Messages During a Parallel Poll ..................... B-25

Figure C-1. Partial Command Categories .............................................................. C-4

Figure C-2. Simple Command Tree for the SENSe Command Subsystem ........... C-4

Figure C-3. Partial Command Tree for the SENSe Command Subsystem ............ C-5

Figure C-4. Partial Command Tree for the SOURce Command Subsystem ......... C-6

Figure C-5. Partial Command Tree for the TRIGger Command Subsystem ......... C-6

Contents

Tables

Table 1-1. NAT7210 IEEE 488 Interface Capabilities......................................... 1-1

Table 3-1. 7210-Mode Register Map ................................................................... 3-2

Table 3-2. Hidden Registers at Offset 6 (ADR) ................................................... 3-3

Table 3-3. Hidden Registers at Offset 5 (AUXMR)............................................. 3-4

Table 3-4. Valid ADMR Patterns ......................................................................... 3-5

Table 3-5. Auxiliary Command Summary ........................................................... 3-15

Table 3-6. Auxiliary Command Description ........................................................ 3-18

Table 3-7. Clear Conditions for SISB Bit ............................................................ 3-36

Table 4-1. 9914-Mode Interface Registers ........................................................... 4-2

Table 4-2. Hidden Registers at the ACCR Offset ................................................ 4-3

Table 4-3. Auxiliary Command Summary ........................................................... 4-15

Table 4-4. Auxiliary Command Description ........................................................ 4-18

Table 5-1. IEEE 488.1 Minimum T1 Delay Requirements.................................. 5-9

Table 5-2. T1 Delay Settings in 7210 Mode ........................................................ 5-10

Table 5-3. T1 Delay Settings in 9914 Mode ........................................................ 5-10

Table 5-4. Parallel Poll Register Example ........................................................... 5-18

Table 6-1. Basic Controller State ......................................................................... 6-3

Table B-1. IEEE 488.1 Standard Status Data Structure........................................ B-23

Table B-2. PPR Message Value ............................................................................ B-26

Table B-3. Determining the PPE Message............................................................ B-27

Table C-1. IEEE 488.2 Common Commands Required by SCPI ......................... C-2

Table C-2. SCPI Required Commands ................................................................. C-3

NAT7210 Reference Manual xii © National Instruments Corp.

About This Manual

This manual describes the programmable features of the NAT7210 and contains information that is suitable for programmers and engineers who wish to write software for the NAT7210.

This manual assumes that you are already familiar with general IEEE 488 concepts.

Organization of This Manual

This manual is organized as follows:

• Chapter 1, Introduction and General Description, explains the features and capabilities of the NAT7210.

• Chapter 2, NAT7210 Architecture, discusses the internal hardware architecture of the NAT7210.

• Chapter 3, 7210-Mode Interface Registers, contains NAT7210 address maps and detailed descriptions of the NAT7210 interface registers in 7210 mode.

• Chapter 4, 9914-Mode Interface Registers, contains NAT7210 address maps and detailed descriptions of the NAT7210 interface registers in 9914 mode.

• Chapter 5, Software Considerations, explains important NAT7210 programming considerations, including chip initialization, Talkers and Listeners, message reception, and holdoffs.

• Chapter 6, Controller Software Considerations, explains important system and GPIB Controller considerations.

• Chapter 7, Hardware Considerations, explains important NAT7210 hardwareinterfacing considerations, including a description of the pins.

• Appendix A, Common Questions, lists common questions and answers.

• Appendix B, Introduction to the GPIB, discusses the history of the GPIB, GPIB hardware configurations, and serial polling.

• Appendix C, Standard Commands for Programmable Instruments (SCPI), discusses the SCPI document, the required SCPI commands, and SCPI programming.

• Appendix D, Multiline Interface Command Messages, lists the multiline interface messages and describes the mnemonics and messages that correspond to the interface functions.

About This Manual

• Appendix E, Mnemonics Key, defines the mnemonics (abbreviations) that this manual uses for functions, remote messages, local messages, states, bits, registers, integrated circuits, and system functions.

• Appendix F, Customer Communication, contains forms you can use to request help from National Instruments or to comment on our products and manuals.

• The Glossary contains an alphabetical list and a description of the terms, including abbreviations, acronyms, metric prefixes, mnemonics, and symbols, that this manual uses.

• The Index contains an alphabetical list of the key terms and topics that this manual uses, and it includes the page number where you can locate each term and topic.

Conventions Used in This Manual

This manual uses the following conventions. italic Italic text denotes emphasis, a cross reference, or an

introduction to a key concept.

bold italic Bold italic text denotes a note, caution, or warning. monospace Text in this font denotes programming examples. IEEE 488 and IEEE 488 and IEEE 488.2 refer to the ANSI/IEEE

IEEE 488.2 Standard 488.1-1987 and ANSI/IEEE Standard 488.2-1992,

respectively, which define the GPIB.

The Glossary lists abbreviations, acronyms, metric prefixes, mnemonics, symbols, and terms.

Customer Communication

National Instruments wants to receive your comments on our products and manuals. We are interested in the applications you develop with our products, and we want to help if you have problems with them. To make it easy for you to contact us, this manual contains comment and configuration forms for you to complete. These forms are in Appendix F, Customer Communication, at the end of this manual.

Chapter 1 Introduction and General Description

This chapter explains the features and capabilities of the NAT7210. The NAT7210 is an IEEE 488.2 Controller chip designed to perform all the

interface functions defined in the ANSI/IEEE Standard 488.1-1987 and the additional requirements and recommendations of the ANSI/IEEE Standard

488.2-1987. The NAT7210 manages the IEEE 488 interface functions with a set

of control and status registers that increase the throughput of driver software and simplify hardware and software design. The NAT7210 performs complete IEEE 488 Talker, Listener, and Controller functions and is software compatible with the NEC µPD7210 and TI TMS9914A chips.

The NAT7210 can be characterized as a bus translator: it converts messages and signals from the CPU into appropriate GPIB messages and signals. In GPIB terminology, the NAT7210 implements GPIB board and device functions to communicate with the central processor and memory. For the computer, the NAT7210 is an interface to the outside world.

IEEE 488 Capabilities

The National Instruments NAT7210 has the features necessary to provide a high-performance IEEE 488 interface. Table 1-1 lists the capabilities of the NAT7210 in terms of the IEEE 488 standard codes.

Table 1-1. NAT7210 IEEE 488 Interface Capabilities

Capability Code Description

SH1 Complete Source Handshake Capability AH1 Complete Acceptor Handshake Capability;

DAC and RFD Holdoff on Certain Events

T5 Complete Talker Capability:

• Basic Talker

• Serial Poll

• Talk-Only Mode

• Unaddressed on MLA

• Send END or EOS

(continues)

Introduction and General Description Chapter 1

Table 1-1. NAT7210 IEEE 488 Interface Capabilities (Continued)

Capability Code Description

TE5 Complete Extended Talker Capability:

• Basic Extended Talker

• Serial Poll

• Talk-Only Mode

• Unaddressed on MSA & LPAS

• Send END or EOS

L3 Complete Listener Capability:

• Basic Listener

• Listen-Only Mode

• Unaddressed on MTA

• Detect END or EOS

LE3 Complete Extended Listener Capability:

• Basic Extended Listener

• Listen-Only Mode

• Unaddressed on MSA & TPAS

• Detect END or EOS

SR1 Complete Service Request Capability

RL1 Complete Remote/Local Capability

PP1 Remote Parallel Poll Configuration

PP2 Local Parallel Poll Configuration DC1 Complete Device Clear Capability DT1 Complete Device Trigger Capability

C1 through C5 Complete Controller Capability:

• System Controller

• Send IFC and Take Charge

• Send REN

• Respond to SRQ

• Send Interface Messages

• Received Control

• Parallel Poll

• Take Control Synchronously or Asynchronously

E2 Three-State Drivers (Open-Collector Drivers During Parallel

Polls)

NAT7210 Reference Manual 1-2 © National Instruments Corp.

Chapter 1 Introduction and General Description

The NAT7210 has complete Source and Acceptor Handshake capability. It can operate as a basic Talker or an extended Talker and can respond to a Serial Poll. If you place it in talk-only mode, it is unaddressed to talk when it receives its listen address. The NAT7210 GPIB interface can also operate as a basic Listener or an extended Listener. If you place it in listen-only mode, it is unaddressed to listen when it receives its talk address. The NAT7210 can request service from a Controller.

Device Clear and Trigger capability is included in the interface; the interpretation is software dependent.

Other GPIB features include the following:

• Messages not sent when there are no Listeners

• Automatic detection of EOS and/or NL messages

• Automatic bus synchronization detection

• Programmable data transfer rates (T1 delays as short as 350 ns)

• Programmable GPIB transceiver support

• Automatic processing of IEEE 488 commands and read-undefined commands

• Ability to use six addressing modes: – Automatic single or dual primary addressing detection – Automatic single primary with single secondary address detection – Single or dual primary with multiple secondary addressing – Multiple primary addressing

CPU Interface Capabilities

• Software compatible with NEC µPD7210 and TI TMS9914A Controller chips

• DMA interface to the host system

• Flexible interrupt capabilities

• Uses only eight bytes of address space

Introduction and General Description Chapter 1

Typical System Interface

Figure 1-1 shows a block diagram of a typical application that uses the NAT7210 to implement an IEEE 488.2 interface.

CPU Bus

Control

Address

Decode

GPIB

XCVR

GPIB

Data

Interrupt

NAT7210

GPIB

XCVR

Figure 1-1. NAT7210 Implementation Block Diagram

In all applications, the NAT7210 must be connected to the GPIB via IEEE 488 compliant transceivers such as the 75160 and 75162, which are available from National Semiconductor and other vendors. The NAT7210 has control signals that let it easily interface to several different types of transceivers.

NAT7210 Reference Manual 1-4 © National Instruments Corp.

Chapter 2 NAT7210 Architecture

This chapter discusses the internal hardware architecture of the NAT7210. The NAT7210 includes the following major components:

• Read/Write Control converts the CPU interface signals to read and write signals for each internal NAT7210 register.

• Internal NAT7210 Registers configure and control the operation of the NAT7210. They transfer data between the NAT7210 and the GPIB, report status information, and set the operating modes. Chapter 3, 7210-Mode Interface Registers, and Chapter 4, 9914-Mode Interface Registers, describe each register in detail.

• Interface Functions implement the interface functions described in the IEEE 488.1 standard. Some internal registers control the interface functions, and you can use other internal registers to monitor the status of interface functions. The interface functions drive and receive the GPIB control signals and generate the signals to control the GPIB transceivers.

• Message Decoders receive the GPIB data lines and decode the GPIB commands that affect the operation of the interface functions.

NAT7210 Architecture Chapter 2

Figure 2-1 contains a block diagram of the NAT7210.

D(7-0)

RS(2-0)

CS* RD*

WR*

DRQ

DACK*

Read/

Write

Control

Data-In

Command Pass Through

Command/Data Out

Address Status

Address Mode

Address

End-Of-String

Interrupt Mask 0, 1, 2

Compare Compare

Message

Decoder

Interface

Functions

SH1

AH1

T5/TE5

L3/LE3

SR1

RL1

DIO(8-1)*

T/R3 T/R2

T/R1

INT

CLK

RESET

Interrupt Status 0, 1, 2

Internal Count

Internal Count 2

Serial Poll

Parallel Poll

Aux A, B, E, F, G, I

SASR

Auxiliary

Command Decoder

Version

Figure 2-1. NAT7210 Block Diagram

PP1/PP2

DC1 DT1

C1-C5

RSV Gen

EOI Gen

STB Out

SYNC

Bus Status

and Control

GPIB Control

NAT7210 Reference Manual 2-2 © National Instruments Corp.

Chapter 2 NAT7210 Architecture

NAT7210 Modes

The NAT7210 has two basic modes of operation: 7210 mode and 9914 mode. In 7210 mode, the NAT7210 is software compatible with the µPD7210 IEEE 488 Controller. The NAT7210 has many registers and features that are not present in the µPD7210. In 9914 mode, the NAT7210 is software compatible with the TMS9914A IEEE 488 Controller. The NAT7210 has many registers and features that are not present in the TMS9914A.

Note: Throughout this manual, 7210 mode refers to the NEC µPD7210 software

compatibility mode, and 9914 mode refers to the TI TMS9914A software compatibility mode.

Changing the NAT7210 Mode

Figure 2-2 illustrates how you change the mode of the NAT7210.

sw9914 Auxiliary

Command

7210 Mode

sw7210 Auxiliary

Command

9914 Mode

Hardware Reset

Figure 2-2. Changing the NAT7210 Mode

Notice that the NAT7210 is in 7210 mode after a hardware reset. To change from 7210 mode to 9914 mode, write the sw9914 auxiliary command to the (7210 mode) Auxiliary Mode Register (AUXMR). To change from 9914 mode to 7210 mode, write the sw7210 auxiliary command to the (9914 mode) Auxiliary Command Register (AUXCR).

Chapter 3 7210-Mode Interface Registers

This chapter contains NAT7210 address maps and detailed descriptions of the NAT7210 interface registers in 7210 mode. For 9914-mode register descriptions, see Chapter 4, 9914-Mode Interface Registers.

7210 Register Map

Table 3-1 is the register bit map for the NAT7210 in 7210 mode. Notice that bold-ruled cells distinguish seven registers that are accessible only when the

Page-In state is true. Refer to The Page-In State section that immediately follows the register map for more information.

7210-Mode Interface Registers Chapter 3

Table 3-1. 7210-Mode Register Map

Key

= 7210-Mode Paged Registers

= Read Register

= Write Register

76543210

DI R +0 DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 R CDOR +0 DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 W

ISR1 +1 CPT APT DET END RX DEC ERR D O DI R IMR1 +1 CPT IE APT IE DET IE END IE DEC IE ERR IE DO IE DI IE W

ISR2 +2 INT SRQI LOK REM C O LOKC REMC ADSC R IMR2 +2 0 SRQI IE DMAO DMAI CO IE LOKC IE REMC IE ADSC IE 2

SPSR +3 S8 PEND S6 S5 S4 S3 S2 S 1 R VSR +3 V3 V2 V1 V0 X X X X R ICR2 +3 1 0 SLOW 0000MICR W SPMR +3 S8 rsv/RQS S6 S5 S4 S3 S2 S1 W

ADSR +4 CIC ATN* SPMS LPAS TPAS LA TA MJMN R ADMR +4 ton lon TRM1 TRM0 0 0 ADM1 ADM0 W

CPTR +5 CPT 7 CPT6 CPT 5 CPT4 CPT3 CPT2 CPT1 CPT0 R SASR +5 nba AEHS ANHS1 ANHS2 ADHS ACRDY SH1A SH1B R AUXMR +5 AUX7 AUX6 AUX5 AUX4 AUX3 AUX2 AUX1 AUX0 W

ADR0 +6 X DT0 DL0 AD5-0 AD4-0 AD3-0 AD2-0 AD1-0 R ISR0 +6 nba STBO NL EOS IFCI ATNI X SYNC R IMR0 +6 GLINT STBO 1E NLEN BTO IFCI IE ATNI IE 0 SYNC IE W ADR +6 ARS DT DL AD5 AD4 AD3 AD2 AD1 W

ADR1 +7 EOI DT1 DL1 AD5-1 AD4-1 AD3-1 AD2-1 AD1-1 R BSR +7 ATN DA V NDAC NRFD EOI SRQ IFC REN R BCR +7 ATN DAV NDAC NRFD EOI SRQ IFC REN W EOSR +7 EOS7 EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOS0 W

NAT7210 Reference Manual 3-2 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

The Page-In State

At some offsets, Table 3-1 shows two readable or two writable registers. The shaded registers in Table 3-1 are accessible only when the Page-In state is true. For each shaded register, the corresponding unshaded register is accessible only when the Page-In state is false.

How to Page-In

The NAT7210 enters the Page-In state when the host interface writes the Page-In auxiliary command to the Auxiliary Mode Register (AUXMR). The NAT7210 registers appear at their Page-In state offset for the first register access after the Page-In command. The NAT7210 leaves the Page-In state at the end of the first register access after the Page-In command.

Hidden Registers

In addition to the registers shown in Table 3-1, the NAT7210 contains hidden registers. All hidden registers are write-only registers. Two or more hidden registers can appear at the same offset. When you write an 8-bit pattern to these offsets, some of the bits determine which hidden register will be written. The other bits represent the value written to the register.

Address Register Map

The NAT7210 has two address registers: ADR1 and ADR0. Table 3-1 shows the offsets for the readable portion of ADR1 and ADR0. The writable portion of ADR0 and ADR1 appears at the offset of the Address Register (ADR) shown in Table 3-1. Table 3-2 shows the bit map for the two writable address registers.

Table 3-2. Hidden Registers at Offset 6 (ADR)

ADR0 0 DT0 DL0 AD5–0 AD4–0 AD3–0 AD2–0 AD1–0 ADR1 1 DT1 DL1 AD5–1 AD4–1 AD3–1 AD2–1 AD1–1

7210-Mode Interface Registers Chapter 3

Auxiliary Mode Register Map

Several hidden registers appear at the AUXMR offset. Table 3-3 shows these hidden registers.

Table 3-3. Hidden Registers at Offset 5 (AUXMR)

PPR 0 1 1 U S P3 P2 P1 AUXRA 1 0 0 BIN XEOS REOS HLDE HLDA AUXRB 1 0 1 ISS INV TRI SPEOI CPT

AUXRE 1100DHADT DHADC DHDT DHDC

AUXRF 1101DHATA DHALA DHUNTL DHALL

AUXRG 0100NTNL RPP2 DISTCT CHES

AUXRI 1110USTD PP2 0 SISB

ICR 0010 F3 F2 F1 F0

ENABLE

Register Bit Descriptions

Some 7210-mode registers and 9914-mode registers share identical names. The 9914-mode registers are described in Chapter 4, 9914-Mode Interface Registers. If you are using the NAT7210 in 7210 mode, be sure to read the proper description for the 7210-mode registers.

All registers are listed in alphabetical order. The registers are alphabetized according to their mnemonics.

NAT7210 Reference Manual 3-4 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Address Mode Register (ADMR)

Attributes: Write only

76543210

ton lon TRM1 TRM0 0 0 ADM1 ADM0

The host interface can put the NAT7210 into one of six GPIB addressing modes by writing to the Address Mode Register (ADMR). The values of ADMR (7–6; 3–0) are undefined after a hardware reset. Before the host interface can clear pon, it must write a valid pattern to the ADMR.

Table 3-4. Valid ADMR Patterns

Hex Value

ADMR*

30 No Addressing

The Controller cannot address the NAT7210 to become a Talker or Listener in no-addressing mode.

31 Normal Dual Addressing

The NAT7210 can implement one or two logical devices by using normal dual addressing.

See the GPIB Addressing section in Chapter 5, Software Considerations.

33 Extended Dual Addressing

Extended Single Addressing

Extended single addressing mode implements the Extended Listener and Extended Talker functions, as defined in the IEEE 488 standard, without intervention from the host interface.

See the GPIB Addressing section in Chapter 5, Software Considerations.

Extended dual addressing mode implements the Extended Listener and Extended Talker functions, as defined in the IEEE 488 standard. This mode requires intervention from the host interface.

GPIB Addressing Mode

See the GPIB Addressing section in Chapter 5, Software Considerations.

(continues)

7210-Mode Interface Registers Chapter 3

ADMR (continued)

Table 3-4. Valid ADMR Patterns (Continued)

Hex Value

ADMR*

70 Listen Only (lon)

The NAT7210 becomes a GPIB Listener and enters the Listener Active State (LACS). Do not use lon if a GPIB Controller is present in the GPIB system.

The host interface should write a hex 30 (No Addressing) to the ADMR immediately after writing lon to the ADMR. To force the NAT7210 to exit LACS, issue the unlisten (lul) auxiliary command.

B0 Talk Only (ton)

The NAT7210 becomes a GPIB Talker. Do not use ton if a GPIB Controller is present in the GPIB system.

The host interface should write a hex 30 (No Addressing) to the ADMR immediately after writing ton to the ADMR. To force the NAT7210 to exit TACS, issue the local untalk (lut) auxiliary command.

* The hex values in Table 3-4 assume that TRM1 = 1 and TRM0 = 1.

GPIB Addressing Mode

NAT7210 Reference Manual 3-6 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

ADMR (continued)

Bit Mnemonic Description

5–4w TRM[1–0] Transmit/Receive Mode bit

TRM1 and TRM0 control the function of the NAT7210 T/R2 and T/R3 output pins in the following manner:

TRM1 TRM0 T/R2 T/R3

0 0 EOIOE TRIG 0 1 CIC TRIG 1 0 CIC EOIOE 1 1 CIC PE

Key:

EOIOE = GPIB EOI signal output enable

TACS + SPAS + CIC & ~(CSBS +

CSHS) CIC = Controller-in-Charge (CIDS + CADS) TRIG = Trigger (pulses when DTAS = 1 or a

trigger auxiliary command is issued) PE = Pull-up enable (CIC + -(PPAS))

A hardware reset clears TRM1 and TRM0.

Note: In many applications, the NAT7210 is

interfaced to a 75160 and a 75162 GPIB transceiver. In these applications, TRM1 and TRM0 should always be set.

7210-Mode Interface Registers Chapter 3

Address Register (ADR)

Attributes: Write only

76543210

ARS DT DL AD5 AD4 AD3 AD2 AD1

Writing to the Address Register (ADR) loads the internal registers ADR0 and ADR1. You must load both ADR0 and ADR1 for all addressing modes. See the GPIB Addressing section in Chapter 5, Software Considerations.

Bit Mnemonic Description

7w ARS Address Register Select bit

If ARS = 1, writing to the ADR loads the seven low-order bits of ADR into internal register ADR1. If ARS = 0, writing to the ADR loads the seven low-order bits into ADR0.

6w DT Disable Talker bit

DT = 1 disables recognition of the GPIB talk address formed from AD[5–1]. ADR0 and ADR1 have independent DT bits.

5w DL Disable Listener bit

DL = 1 disables recognition of the GPIB listen address formed from AD[5–1]. ADR0 and ADR1 have independent DL bits.

4–0w AD[5–1] NAT7210 GPIB Address bits 5 through 1

These bits specify the GPIB address of the NAT7210. The corresponding GPIB talk address is formed by adding hex 40 to AD[5–1], while the corresponding GPIB listen address is formed by adding hex 20 to AD[5–1]. The value written to AD[5–1] should not be 11111 (binary), because the corresponding talk and listen addresses would conflict with the GPIB Untalk (UNT) and GPIB Unlisten (UNL) commands.

ADR0 and ADR1 have independent AD[5–1] bits.

NAT7210 Reference Manual 3-8 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Address Register 0 (ADR0)

Attributes: Read only

76543210 X DT0 DL0 AD5–0 AD4–0 AD3–0 AD2–0 AD1–0

Address Register 0 (ADR0) reflects the internal GPIB address status of the NAT7210. In extended single addressing mode, ADR0 indicates the address and enable bits for the primary GPIB address of the NAT7210. In the dual primary addressing modes, ADR0 indicates the NAT7210 major primary GPIB address. See the GPIB Addressing section in Chapter 5, Software Considerations.

Bit Mnemonic Description

7r X Reads back a 1 or 0.

6r DT0 Disable Talker 0 bit

If DT0 = 1, the primary (or major) Talker function is not enabled, and ADR0 is not compared with GPIB Talker addresses.

If DT0 = 0, the NAT7210 responds to a GPIB talk address matching bits AD[5–0 through 1–0].

5r DL0 Disable Listener 0 bit

If DL0 = 1, the primary (or major) Listener function is not enabled, and ADR0 is not compared with GPIB Listener addresses.

If DL0 = 0, the NAT7210 responds to a GPIB listen address matching bits AD[5–0 through 1–0].

4–0r AD[5–0 – 1–0] NAT7210 GPIB Address bits 5–0 through 1–0

These are the lower 5 bits of the NAT7210 GPIB primary (or major) address. The primary talk address is formed by adding hex 40 to AD[5–0 through 1–0], while the primary listen address is formed by adding hex 20.

7210-Mode Interface Registers Chapter 3

Address Register 1 (ADR1)

Attributes: Read only

76543210

EOI DT1 DL1 AD5–1 AD4–1 AD3–1 AD2–1 AD1–1

Address Register 1 (ADR1) indicates the status of the GPIB address and enable bits for the secondary address of the NAT7210 if extended single addressing is used. ADR1 indicates the minor primary address of the NAT7210 if dual primary addressing is used. See the GPIB Addressing section in Chapter 5, Software Considerations.

Bit Mnemonic Description

7r EOI End-or-Identify bit

EOI indicates the value of the GPIB EOI line that is latched when a data byte is received by the NAT7210 GPIB Acceptor Handshake (AH) function. If EOI = 1, the EOI line was asserted with the received byte. EOI is cleared by issuing the Chip Reset auxiliary command. EOI is updated after each byte is received.

6r DT1 Disable Talker 1 bit

If DT1 = 1, the secondary (or minor) Talker function is not enabled—that is, the GPIB secondary address (or minor primary talk address) is not compared with this register.

5r DL1 Disable Listener 1 bit

If DL1 = 1, the secondary (or minor) Listener function is not enabled—that is, the GPIB secondary address (or minor primary listen address) is not compared with this register.

4–0r AD[5–1 – 1–1] NAT7210 GPIB Address bits 5–1 through 1–1

These bits indicate the NAT7210 secondary or minor address. Form the secondary address by adding hex 60 to bits AD[5–1 through 1–1]. Form the minor talk address by adding hex 40 to AD[5–1 through 1–1]. Form the listen address by adding a hex 20.

NAT7210 Reference Manual 3-10 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Address Status Register (ADSR)

Attributes: Read only

76543210

CIC ATN* SPMS LPAS TPAS LA TA MJMN

The Address Status Register (ADSR) contains information that you can use to monitor the NAT7210 GPIB address status.

Bit Mnemonic Description

7r CIC Controller-In-Charge bit

CIC = ~(CIDS + CADS) CIC indicates that the NAT7210 GPIB Controller

function is either in an active state with ATN* asserted or a standby state with ATN* unasserted. The Controller function is in an idle state (CIDS or CADS) if CIC = 0.

6r ATN* Attention* bit

ATN* is a status bit that indicates the current level of the GPIB ATN* signal. If ATN* = 0, the GPIB ATN* signal is asserted.

5r SPMS Serial Poll Mode State bit

If SPMS = 1, the NAT7210 GPIB Talker (T) or Talker Extended (TE) function is enabled to participate in a serial poll.

SPMS is set by

SPE & ACDS

SPMS is cleared by

(SPD & ACDS) + pon + IFC

7210-Mode Interface Registers Chapter 3

ADSR (continued)

Bit Mnemonic Description

4r LPAS Listener Primary Addressed State bit

LPAS indicates that the NAT7210 has received its primary listen address. See the Address Mode Register (ADMR) section in this chapter.

LPAS is cleared by

(PCG & ~MLA & ACDS) + pon

3r TPAS Talker Primary Addressed State bit

TPAS indicates that the NAT7210 has received its primary GPIB talk address. See the Address Mode Register (ADMR) section in this chapter.

TPAS is cleared by

(PCG & ~MTA & ACDS) + pon

2r LA Listener Active bit

LA = 1 when the NAT7210 has been addressed or programmed as a GPIB Listener—that is, the NAT7210 is in the Listener Active State (LACS) or the Listener Addressed State (LADS). The NAT7210 is addressed to listen when it receives its listen address from the CIC. The NAT7210 can also be programmed to listen by using the Listen-Only (lon) bit in the ADMR.

If the NAT7210 is addressed to talk, it is automatically unaddressed to listen.

LA is also cleared by

(UNL & ACDS) + IFC + pon + (lun & CACS) + lul

1r TA Talker Active bit

TA = 1 when the NAT7210 has been addressed or programmed as the GPIB Talker—that is, the NAT7210 is in the Talker Active State (TACS), the Talker Addressed

NAT7210 Reference Manual 3-12 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

ADSR (continued)

Bit Mnemonic Description

State (TADS), or the Serial Poll Active State (SPAS). The NAT7210 can be addressed to talk when it receives its talk address from the CIC. It can also be programmed to talk by using the Talk-Only (ton) bit in the ADMR.

If the NAT7210 is addressed to listen, it is automatically unaddressed to talk.

TA is also cleared by

(OTA & ACDS) + IFC + pon + lut

0r MJMN Major-Minor bit

MJMN indicates whether the information in the other ADSR bits applies to the NAT7210 major or minor Talker and Listener functions. MJMN = 1 when the NAT7210 receives its GPIB minor talk address or minor listen address. MJMN clears when the NAT7210 receives its major talk or major listen address. The pon message also clears MJMN.

Note: Only one Talker or Listener can be active at a

time. The MJMN bit indicates which, if either, of the NAT7210 Talker and Listener functions is addressed or active.

MJMN is always 0 unless the normal or extended dual primary addressing mode is enabled. See the Address

Mode Register (ADMR) section in this chapter.

7210-Mode Interface Registers Chapter 3

Auxiliary Mode Register (AUXMR)

Attributes: Write only

Permits access to hidden registers

76543210

AUX7 AUX6 AUX5 AUX4 AUX3 AUX2 AUX1 AUX0

Use the AUXMR to issue auxiliary commands and to write the following eight hidden registers:

• Parallel Poll Register (PPR)

• Auxiliary Register A (AUXRA)

• Auxiliary Register B (AUXRB)

• Auxiliary Register E (AUXRE)

• Auxiliary Register F (AUXRF)

• Auxiliary Register G (AUXRG)

• Auxiliary Register I (AUXRI)

• Internal Counter Register (ICR)

Note: You should issue commands at intervals of at least 4 clock periods.

For more information, see the Hidden Registers section, which is located earlier in this chapter.

NAT7210 Reference Manual 3-14 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

AUXMR (continued)

Table 3-5 summarizes the AUXMR auxiliary commands and Table 3-6 describes the AUXMR auxiliary commands.

Table 3-5. Auxiliary Command Summary

Hex

Code*

00 Immediate Execute Power-On (pon) 01 Clear Parallel Poll Flag (~ist) 02 Chip Reset (chip_reset) 03 Finish Handshake (rhdf) 04 Trigger (trig) 05 Clear Or Pulse Return To Local (rtl) 06 Send EOI (seoi) 07 Nonvalid Secondary Command Or

Address (nonvalid) 08† Request Control Command (rqc) 09 Set Parallel Poll Flag (ist) 0A† Release Control Command (rlc) 0B† Untalk Command (lut) 0C† Unlisten Command (lul)

Auxiliary Command

0D Set Return To Local 0E† New Byte Available False (nbaf) 0F Valid Secondary Command or Address

(valid) 10 Go To Standby (gts)

(continues)

7210-Mode Interface Registers Chapter 3

AUXMR (continued)

Table 3-5. Auxiliary Command Summary (Continued)

Hex

Code*

11 12 1A

13 1B 1C

14 Disable System Control (~rsc) 15† Switch To 9914 Mode Command (sw9914) 16

1E 17

1F 18†

19† 1D Execute Parallel Poll (rppl) 50† Page-In Additional Registers (page-in) 51† Holdoff Handshake Immediately (hldi)

Take Control Asynchronously (tca) Take Control Synchronously (tcs) Take Control Synchronously On End (tcse)

Listen (ltn) Listen In Continuous Mode (ltn and cont) Local Unlisten (lun)

Clear IFC (~sic & rsc) Set IFC (sic & rsc)

Clear REN (~sre & rsc) Set REN (sre & rsc)

Request rsv True (reqt) Request rsv False (reqf)

Auxiliary Command

54† Clear DET (ISR1[5]r) Command 55† Clear END (ISR1[4]r) Command 56† Clear DEC (ISR1[3]r) Command 57† Clear ERR (ISR1[2]r) Command 58† Clear SRQI (ISR2[6]r) Command 59† Clear LOKC (ISR2[2]r) Command 5A† Clear REMC (ISR2[1]r) Command

(continues)

NAT7210 Reference Manual 3-16 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

AUXMR (continued)

Table 3-5. Auxiliary Command Summary (Continued)

Hex

Code*

5B† Clear ADSC (ISR2[0]r) Command 5C† Clear IFCI (ISR0[3]r) Command 5D† Clear ATNI (ISR0[2]r) Command 5E†

5F† * Represents all eight bits of the AUXMR.

† Denotes an auxiliary command not available

Clear SYNC (ISR0[0]r) Command Set SYNC (ISR0[0]r) Command

in the NEC µPD7210.

Auxiliary Command

7210-Mode Interface Registers Chapter 3

AUXMR (continued)

Table 3-6. Auxiliary Command Description

Data

Pattern

(Hex)

00 Immediate Execute Power-On (pon)

The Immediate Execute Power-On auxiliary command sets the local pon message true, then clears it. If the local pon message is already asserted, the pon auxiliary command simply clears the local pon message. The following figure illustrates the behavior of the local pon message:

Description

start of pon aux.

local pon

command pulse

message

true

end of pon aux.

command pulse

HW reset +

chip_reset aux. command

When the local pon message is true, the NAT7210 holds all GPIB interface functions in their idle states.

01 09

NAT7210 Reference Manual 3-18 © National Instruments Corp.

Clear Parallel Poll Flag (~ist) Set Parallel Poll Flag (ist)

These commands set and clear the Parallel Poll Flag. The value of the Parallel Poll Flag is used as the local message ist when AUXRB[4]w = 0. The value of SRQS is used as ist when ISS = 1. A hardware reset or the Chip Reset auxiliary command clears ist.

(continues)

Chapter 3 7210-Mode Interface Registers

AUXMR (continued)

Table 3-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

02 Chip Reset

The Chip Reset auxiliary command resets the NAT7210 to the following conditions:

• The local pon message is set and the interface functions are

• The SPMR bits are cleared.

• The TRM[1–0] bits are cleared.

• The EOI bit is cleared.

• The AUXRA, AUXRB, AUXRE, AUXRF, AUXRG, and

• The Parallel Poll Flag is cleared.

• The BCR is cleared. The interface functions remain in their idle states until they are

released by an Immediate Execute pon command. While the interface functions are in their idle states, the host interface can program the NAT7210 writable bits to their desired states.

Description

placed in their idle states.

AUXRI registers are cleared.

03 Finish Handshake (rhdf)

The Finish Handshake command finishes a GPIB handshake that was stopped because of a Holdoff On RFD condition.

See The GPIB rdy Message and RFD Holdoffs section in Chapter 5, Software Considerations.

(continues)

7210-Mode Interface Registers Chapter 3

AUXMR (continued)

Table 3-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

04 Trigger (trig)

The Trigger command generates a high pulse on the T/R 3 pin when TRM1 = 0. The DET bit is not set by issuing the Trigger command.

06 Send EOI (seoi)

07 Nonvalid Secondary Command Or Address (nonvalid)

Clear Or Pulse Return To Local (rtl) Set Return To Local (rtl)

The two Return To Local commands implement the rtl message as defined by the IEEE 488 standard. If the host interface writes 05 hex, the rtl message is generated in the form of a pulse. If rtl is already set, the rtl command clears it. If the host interface writes 0D hex, the rtl command is set and remains set until either the 05 hex rtl command is issued or a Chip Reset auxiliary command is issued.

The seoi command causes the GPIB End-or-Identify (EOI) line to go true with the next data byte transmitted. The EOI line is cleared upon completion of the handshake for that byte. When NTNL = 0, the NAT7210 recognizes the seoi command only if TACS = 1—that is, the NAT7210 is in the Talker Active State.

Description

The nonvalid command releases a DAC (Data Accepted) holdoff. If APT = 1, the NAT7210 operates as if an Other Secondary Address (OSA) message had been received.

08* Request Control Command (rqc)

If the NAT7210 is in the Idle Controller State, the rqc command forces the NAT7210 to become the Active Controller when it detects that the ATN signal is unasserted.

0A* Release Control Command (rlc)

The rlc command forces the NAT7210 to become an Idle Controller and to unassert ATN.

(continues)

NAT7210 Reference Manual 3-20 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

AUXMR (continued)

Table 3-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

0B* Untalk (lut)

The lut command issues the local unt message, forcing the Talker function to enter TIDS.

0C* Unlisten (lul)

The lul command issues the local unl message, forcing the Listener function to enter LIDS.

0E* New Byte Available False (nbaf)

nbaf forces the local message, nba, to become false. This action prohibits the NAT7210 from sending the last byte written to the Command/Data Our Register (CDOR). See the Using nbaf section in Chapter 5, Software Considerations.

0F Valid Secondary Command Or Address (valid)

The valid command releases a DAC holdoff. If APT = 1, the NAT7210 operates as if a My Secondary Address (MSA) message had been received.

10 Go To Standby (gts)

Description

The gts command pulses the local gts message. If the NAT7210 is the Active Controller, gts causes the NAT7210 to become the Standby Controller and to unassert the GPIB ATN signal. See the

Three Basic Controller States section in Chapter 6, Controller Software Considerations.

11 Take Control Asynchronously (tca)

The tca command pulses the local tca message. If the NAT7210 is the Standby Controller, tca causes the NAT7210 to become the Active Controller and to assert the GPIB ATN signal. See the

Standby State to Active State section in Chapter 6, Controller Software Considerations.

(continues)

7210-Mode Interface Registers Chapter 3

AUXMR (continued)

Table 3-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

12 Take Control Synchronously (tcs)

The tcs command sets the local tcs message. If the NAT7210 is the Standby Controller and an Active Listener, the tcs message causes the NAT7210 to become the Active Controller when the NAT7210 performs an RFD holdoff—that is, the AH function enters ANRS. The local tcs message clears when the NAT7210 becomes the Active Controller by this method or if the NAT7210 becomes an Idle Controller. See the Standby State to Active State section in Chapter 6, Controller Software Considerations.

13 Listen (ltn)

The ltn command pulses the local ltn message. If the NAT7210 is the Active Controller, the local ltn message causes the NAT7210 to become an Addressed Listener. The ltn command can also take the NAT7210 out of the continuous data-receiving mode (see ltn & cont command).

14 Disable System Control (~rsc)

The ~rsc command, a hardware reset, or the Chip Reset auxiliary command clears the local rsc message. See the System Controller

Considerations section in Chapter 6, Controller Software Considerations.

Description

15* Switch To 9914A Mode (sw9914)

This command places the NAT7210 in 9914 compatibility mode.

16 Clear IFC (~sic & rsc)

The ~sic & rsc command clears the local sic message and sets the local rsc messages. This action causes the NAT7210 to become the System Controller and to unassert the GPIB IFC signal. See the

System Controller Considerations section in Chapter 6, Controller Software Considerations.

(continues)

NAT7210 Reference Manual 3-22 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

AUXMR (continued)

Table 3-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

17 Clear REN (~sre & rsc)

The ~sre & rsc command clears the local sre message and sets the local rsc messages. This action causes the NAT7210 to become the System Controller and to unassert the GPIB REN signal. See the

System Controller Considerations section in Chapter 6, Controller Software Considerations.

18* 19*

1A Take Control Synchronously On END (tcse)

Request rsv True (reqt) Request rsv False (reqf)

The reqt and reqf commands are inputs to the IEEE 488.2 Service Request Synchronization Circuitry. These commands set and clear the local rsv message.

If STBO IE = 1, the reqt and reqf commands are issued immediately. If STBO IE = 0, the reqt and reqf commands are not issued immediately: they are issued on the write of the SPMR that follows the issuing of the reqt or reqf auxiliary command.

The tcse command causes the local tcs message to set when the NAT7210 accepts a byte satisfying the END condition (see the END RX bit ISR1[4]). If the NAT7210 is the Standby Controller and an Active Listener, the tcs message causes the NAT7210 to become the Active Controller when the NAT7210 performs an RFD holdoff— that is, when the AH function enters ANRS. The local tcs message (and the END detection circuitry) clears when the NAT7210 becomes the Active Controller by this method or if the NAT7210 becomes an Idle Controller.

Description

(continues)

7210-Mode Interface Registers Chapter 3

AUXMR (continued)

Table 3-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

1B Listen In Continuous Mode (ltn & cont)

The ltn & cont command pulses the local ltn message. If the NAT7210 is the Active Controller, the local ltn message causes the NAT7210 to become an Addressed Listener.

The ltn & cont command also places the NAT7210 in continuous mode regardless of the settings of the AUXRA[1–0] bits (see The GPIB rdy Message and RFD Holdoffs section in Chapter 5). If the NAT7210 enters continuous mode because of the ltn & cont command, it remains in continuous mode until the NAT7210 becomes unaddressed to Listen—that is, the L or LE function enters LIDS—or until the control program issues the ltn command.

1C Local Unlisten (lun)

The lun command pulses the local lun message. If the NAT7210 is the Active Controller, the local lun message causes the NAT7210 to become an Unaddressed Listener—that is, the L or LE function enters LIDS.

1D Execute Parallel Poll (rpp1)

The rpp1 command sets the local rpp message. If the NAT7210 is the Active Controller, the rpp message causes the NAT7210 to send the IDY message to all GPIB devices in the system and to conduct a parallel poll. (See the Conducting Parallel Polls section in Chapter 6.) The rpp message clears when the NAT7210 completes a parallel poll or becomes an Idle Controller.

Description

1E Set IFC (sic & rsc)

The sic & rsc command sets the local sic and rsc messages. The local message pon or the ~rsc auxiliary command also clears sic. This action causes the NAT7210 to become the System Controller and to assert the GPIB IFC signal. See the System Controller

Considerations section in Chapter 6, Controller Software Considerations.

(continues)

NAT7210 Reference Manual 3-24 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

AUXMR (continued)

Table 3-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

1F Set REN (sre & rsc)

The sre & rsc command sets the local sre and rsc messages. The local message pon or the ~rsc auxiliary command also clears sre. This action causes the NAT7210 to become the System Controller and to assert the GPIB REN signal. See the System Controller

Considerations section in Chapter 6, Controller Software Considerations.

50* Page-In Additional Registers (page-in)

The Page-In command causes the NAT7210 to enter the Page-In state. The Page-In state makes several registers accessible. See The Page-In State section located at the beginning of this chapter.

51* Holdoff Handshake Immediately (hldi)

This command forces the Acceptor Handshake function to immediately perform an RFD holdoff. Issuing this command forces a transition into ANRS, where the handshake is held off until a finish handshake auxiliary command is issued.

54* Clear DET

This command clears the DET bit (ISR1[5]r). Use this command to clear the DET bit when SISB = 1.

Description

55* Clear END

This command clears the END bit (ISR1[4]r). Use this command to clear the END bit when SISB = 1.

56* Clear DEC

This command clears the DEC bit (ISR1[3]r). Use this command to clear the DEC bit when SISB = 1.

57* Clear ERR

This command clears the ERR bit (ISR1[2]r). Use this command to clear the ERR bit when SISB = 1.

(continues)

7210-Mode Interface Registers Chapter 3

AUXMR (continued)

Table 3-6. Auxiliary Command Description (Continued)

Data

Pattern

(Hex)

58* Clear SRQI Command

This command clears the SRQI bit if SISB = 1. See the SRQI bit description that is in the Interrupt Status Register 2 (ISR2) section in this chapter.

59* Clear LOKC

This command clears the LOKC bit (ISR2[2]r). Use this command to clear the LOKC bit when SISB = 1.

5A* Clear REMC

This command clears the REMC bit (ISR2[1]r). Use this command to clear the REMC bit when SISB = 1.

5B* Clear ADSC

This command clears the ADSC bit (ISR2[0]r). Use this command to clear the ADCS bit when SISB = 1.

5C* Clear IFCI

This command clears the IFCI bit (ISR0[3]r). Use this command to clear the IFCI bit when SISB = 1.

Description

5D* Clear ATNI

This command clears the ATNI bit (ISR0[2]r). Use this command to clear the ATNI bit when SISB = 1.

5E* 5F*

* Denotes an auxiliary command not available in the µPD7210.

NAT7210 Reference Manual 3-26 © National Instruments Corp.

Clear SYNC Set SYNC

These commands start or reset the SYNC function.

Chapter 3 7210-Mode Interface Registers

Auxiliary Register A (AUXRA)

Attributes: Write only

Accessed at the same offset as AUXMR

76543210 1 0 0 BIN XEOS REOS HLDE HLDA

AUXRA controls the End-of-String (EOS) and END messages and specifies the RFD holdoff mode. The Chip Reset auxiliary command or a hardware reset clears AUXRA. You write to AUXRA at the same offset as the AUXMR.

Bit Mnemonic Description

4w BIN Binary bit

The BIN bit selects the length of the EOS message. If BIN = 1, the End-of-String Register (EOSR) is treated as an 8-bit byte. When BIN = 0, the EOSR is treated as a 7-bit register (for ASCII characters), and only a 7-bit comparison is done with the data on the GPIB.

3w XEOS Transmit END With EOS bit

XEOS permits or prohibits automatic transmission of the GPIB END message at the same time as the EOS message when the NAT7210 is in TACS. If XEOS = 1 and the byte in the CDOR matches the contents of the EOSR, the EOI line is sent true along with the data.

2w REOS END On EOS Received bit

The REOS bit permits or prohibits setting the END bit (ISR1[4]r) when the NAT7210 receives the EOS message as a Listener. If REOS = 1 and the byte in the DIR matches the byte in the EOSR, the END RX bit (ISR1[4]r) is set and the acceptor function treats the EOS character just as if it were received with EOI asserted.

7210-Mode Interface Registers Chapter 3

AUXRA (continued)

Bit Mnemonic Description

1w, 0w HLDE Holdoff On End bit

HLDA Holdoff On All Data bit

HLDE and HLDA together determine the GPIB data-receiving mode.

HLDE HLDA Data-Receiving Mode

0 0 Normal Handshake Mode 0 1 RFD Holdoff on All Data Mode 1 0 RFD Holdoff on END Mode 1 1 Continuous Mode

For more information, see The GPIB rdy Message and

RFD Holdoffs section in Chapter 5, Software Considerations.

Issuing the ltn & cont auxiliary command can also place the NAT7210 in the continuous data-receiving mode. The NAT7210 enters continuous mode regardless of the value of HLDE and HLDA. In this situation, the NAT7210 remains in continuous mode until you issue the ltn auxiliary command or the NAT7210 becomes unaddressed to listen (by entering the LIDS).

NAT7210 Reference Manual 3-28 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Auxiliary Register B (AUXRB)

Attributes: Write only

Accessed at the same offset as AUXMR

76543210 1 0 1 ISS INV TRI SPEOI CPT

ENABLE

AUXRB affects several interface functions. The Chip Reset auxiliary command or a hardware reset clears AUXRB. You write to AUXRB at the same offset as the AUXMR.

Bit Mnemonic Description

4w ISS Individual Status Select bit

ISS determines the value of the NAT7210 ist message. When ISS = 1, ist takes on the value of the NAT7210 Service Request State (SRQS). (The NAT7210 asserts the GPIB SRQ message when it is in SRQS.) If ISS = 0, ist takes on the value of the NAT7210 Parallel Poll Flag. You set and clear the Parallel Poll Flag by using the Set Parallel Poll Flag and Clear Parallel Poll Flag auxiliary commands. See the Parallel Polling section in Appendix B, Introduction to the GPIB.

3w INV Invert bit

INV determines the polarity of the INT pin.

INV Bit INT Pin Polarity

0 Active High 1 Active Low

2w TRI Three-State Timing bit

TRI determines the NAT7210 GPIB Source Handshake Timing (T1). Clearing TRI sets the low-speed timing (T1 ≥ 2 µs). Setting TRI enables the NAT7210 to use a shorter T1 delay. See the T1 Delay Generation section in Chapter 5, Software Considerations.

7210-Mode Interface Registers Chapter 3

AUXRB (continued)

Bit Mnemonic Description

1w SPEOI Send Serial Poll EOI bit

SPEOI determines whether the NAT7210 sends EOI when a Controller serial polls the NAT7210.

SPEOI EOI During Serial Polls

0 Sent False 1 Sent True

0w CPT ENABLE Command Pass Through Enable bit

The CPT ENABLE bit permits or prohibits detecting undefined GPIB commands and permits or prohibits setting the CPT bit (ISR1[7]r).

NAT7210 Reference Manual 3-30 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Auxiliary Register E (AUXRE)

Attributes: Write only

Accessed at the same offset as AUXMR

7654 3 2 1 0 1100DHADT DHADC DHDT DHDC

AUXRE determines when the NAT7210 performs a DAC holdoff. The Chip Reset auxiliary command or a hardware reset clears AUXRE.

Each bit of AUXRE enables DAC holdoffs on a GPIB command or group of commands. When a GPIB Controller sends the specified command to the NAT7210, the CPT bit sets and the NAT7210 performs a DAC holdoff. See the DAC Holdoffs section in Chapter 5,

Software Considerations.

Bit Mnemonic Description

3w DHADT DAC Holdoff On GET Command bit

2w DHADC DAC Holdoff On DCL Or SDC Command bit

1w DHDT DAC Holdoff On DTAS Command bit

0w DHDC DAC Holdoff On DCAS Command bit

7210-Mode Interface Registers Chapter 3

Auxiliary Register F (AUXRF)

Attributes: Write only

Accessed at the same offset as AUXMR

765432 1 0 1101DHATA DHALA DHUNTL DHALL

AUXRF determines how the NAT7210 uses a DAC holdoff. The Chip Reset auxiliary command or a hardware reset clears AUXRF.

Each bit of AUXRF enables DAC holdoffs on a GPIB command or group of commands. When a GPIB Controller sends the specified command to the NAT7210, the CPT bit sets and the NAT7210 performs a DAC holdoff. See the DAC Holdoffs section in Chapter 5,

Software Considerations.

Bit Mnemonic Description

3w DHATA DAC Holdoff On All Talker Addresses Command bit

2w DHALA DAC Holdoff On All Listener Addresses Command bit

1w DHUNTL DAC Holdoff On The UNT Or UNL Command bit

0w DHALL DAC Holdoff On All UCG, ACG, And SCG Commands

bit

NAT7210 Reference Manual 3-32 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Auxiliary Register G (AUXRG)

Attributes: Write only

Accessed at the same offset as AUXMR

76543210 0100NTNL RPP2 DISTCT CHES

Bit Mnemonic Description

3w NTNL No Talking When No Listener bit

Set NTNL to prevent the NAT7210 from sourcing data (talking) when there is no external Listener, to modify the setting of the ERR bit, to modify the way the nba local message is cleared, and to change the EOI generation function. If the NAT7210 is used in an IEEE 488.2 device, you should set NTNL.

If NTNL = 0, the following actions occur:

• The NAT7210 handshake function enters STRS after the T1 delay has elapsed and NRFD is unasserted.

• The ERR bit is set on TACS & SDYS & DAC & RFD or SIDS & (write CDOR) or the transition from SDYS to SIDS.

• The local nba message is cleared upon entering SIDS or STRS.

• The Send EOI auxiliary command is ignored or forgotten upon exiting TACS.

If NTNL = 1, the following actions occur:

• The NAT7210 handshake function does not make the transition from SDYS to STRS unless an external Listener exists—that is, a device on the GPIB is asserting NDAC.

• The ERR bit is set when the T1 delay has elapsed and TACS & SDYS & EXTDAC & RFD (where EXTDAC refers to some device on the GPIB asserting NDAC).

7210-Mode Interface Registers Chapter 3

AUXRG (continued)

Bit Mnemonic Description

• The local nba message is cleared upon entering STRS and ~SPAS.

• The Send EOI auxiliary command is cleared upon entering SDYS or STRS.

2w RPP2 Request Parallel Poll 2 bit

If RPP2 = 1, the local rpp message is true. Clearing RPP2 clears rpp. If the NAT7210 is the Active Controller, setting rpp causes the NAT7210 to conduct a parallel poll. See the Conducting Parallel Polls section in Chapter 6, Controller Software Considerations.

1w DISTCT Disable Automatic Take Control bit

If DISTCT = 1, the NAT7210 considers the GPIB TCT message undefined. If the GPIB Controller tries to pass control to the NAT7210, the NAT7210 will not become a Controller. You usually set DISTCT if the NAT7210 is a talk-only or listen-only device.

If DISTCT = 0, the NAT7210 recognizes TCT. Another Controller may pass control to the NAT7210 without software intervention.

0w CHES Clear Holdoff On End Select bit

CHES determines how long the NAT7210 remembers that it detected an END condition.

If CHES = 0, the NAT7210 remembers the detection of the END condition until the host interface issues the Release Handshake Holdoff auxiliary command.

If CHES = 1, the NAT7210 remembers the detection of the END condition until the Release Handshake Holdoff auxiliary command is issued or the DIR is read when the NAT7210 is in the normal handshake holdoff mode—that is, HLDE and HLDA = 0.

NAT7210 Reference Manual 3-34 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Auxiliary Register I (AUXRI)

Attributes: Write only

Accessed at the same offset as AUXMR

76543210 1110USTDPP20SISB

Bit Mnemonic Description

3w USTD Ultra Short T1 Delay bit

USTD sets the value of the T1 delay (used by the Source Handshake function for data setup) to 350 ns for the second and subsequent data bytes sent after ATN unasserts. If USTD = 0, the TRI bit (AUXRB[2]w) determines the value of T1. See the T1 Delay Generation section in Chapter 5, Software Considerations.

2w PP2 Parallel Poll bit 2

If PP2 = 0, the NAT7210 responds to parallel polls in the same manner as the µPD7210—that is, it supports Parallel Poll functions PP1 and PP2 simultaneously. However, a contradiction arises because PP1 requires the interface to be configured by remote GPIB commands, and PP2 requires the interface to be configured locally and ignore remote GPIB commands.

When PP2 = 1, the chip ignores remote GPIB commands—that is, PPC and PPU are treated as undefined commands, allowing a true implementation of PP2. In addition, setting PP2 and U (PPR[4]w) lets the NAT7210 support PP0 (no Parallel Poll response). See the Parallel Polling section in Appendix B.

0w SISB Static Interrupt Status Bits bit

If SISB = 0, reading ISR0, ISR1, or ISR2 clears the bits of the register that is read (ISR0, ISR1, or ISR2).

7210-Mode Interface Registers Chapter 3

AUXRI (continued)

If SISB = 1, the bits remain set until a certain condition is met. Table 3-7 lists the condition that clears each interrupt status bit when SISB = 1.

Table 3-7. Clear Conditions for SISB Bit

Bit Clear Condition when SISB = 1

ADSC pon + clearADSC + ton + lon APT pon + valid + nonvalid ATNI pon + clearATNI CO pon + ~CACS + ~SGNS + nba CPT pon + read CPTR DEC pon + clearDEC DET pon + clearDET DI pon + (finish handshake) * (Holdoff mode) + read DIR DO pon + ~TACS + ~SGNS + nba END pon + clearEND ERR pon + clearERR IFC I pon + clearIFCI LOKC pon + clearLOKC REMC pon + clearREMC SRQI pon + clearSRQI

Note: Interrupt Status bits STBO and SYNC are not

affected by the SISB bit.

NAT7210 Reference Manual 3-36 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Bus Control Register (BCR)/Bus Status Register (BSR)

Attributes: Write only (BCR)

Read only (BSR)

76543210 ATN DA V NDAC NRFD EOI SRQ IFC REN ATN DA V NDAC NRFD EOI SRQ IFC REN

Bit Mnemonic Description

7r ATN GPIB Attention Status bit 7w ATN GPIB Attention Control bit

6r DAV GPIB Data Valid Status bit 6w DAV GPIB Data Valid Control bit

5r NDAC GPIB Not Data Accepted Status bit 5w NDAC GPIB Not Data Accepted Control bit

4r NRFD GPIB Not Ready For Data Status bit 4w NRFD GPIB Not Ready For Data Control bit

3r EOI GPIB End-or-Identify Status bit 3w EOI GPIB End-or-Identify Control bit

2r SRQ GPIB Service Request Status bit 2w SRQ GPIB Service Request Control bit

1r IFC GPIB Interface Clear Status bit 1w IFC GPIB Interface Clear Control bit

0r REN GPIB Remote Enable Status bit 0w REN GPIB Remote Enable Control bit

Reads of the Bus Status Register (BSR) return the status of the GPIB control lines at the time of the read. Write ones to bits in the Bus Control Register (BCR) to assert the corresponding GPIB control lines.

7210-Mode Interface Registers Chapter 3

BCR/BSR (continued)

Because the NAT7210 is either transmitting or receiving a GPIB control line at any particular time and is not performing both actions simultaneously, setting a bit in the BCR may not automatically assert the corresponding line on the GPIB. If the NAT7210 is transmitting a GPIB line when the corresponding bit in the BCR is set, the NAT7210 asserts the GPIB line. If the NAT7210 is receiving a GPIB line when the corresponding bit in the BCR is set, the GPIB line is not asserted. However, in both these cases, the GPIB signal internal to the NAT7210 is logically ORed with the value of the BCR bit. Figure 3-1 illustrates the GPIB input/output hardware configuration.

Transmit Enable

GPIB Line Out BCR Bit

NDAC NRFD

SRQ

GPIB Line In

eliminates

glitches in

REN & IFC

Figure 3-1. GPIB I/O Hardware Configuration

In Figure 3-1, Transmit Enable represents the internal signal that is true when the chip is driving a particular GPIB control line. GPIB Line Out represents the internal signal that is true when an interface function within the chip is attempting to assert a GPIB control signal. BCR Bit corresponds to the bit in the BCR. GPIB Line In represents the internal GPIB lines that are inputs to the GPIB interface functions and the BSR. The internal signals SRQ, NDAC, and NRFD are monitored by the interface functions even when they are not driven onto the pin. For this reason, the internal value of these signals is ORed with the external value.

Because the BSR samples the GPIB control lines from the GPIB transceiver—not the actual GPIB bus—the direction of each line determines the validity of each bit. Generally, when a signal is an input, the BSR reflects its true bus status, while an output signal reflects only the NAT7210 value of that particular line. Under normal GPIB operation, this restriction on the validity of the BSR should not be too limiting, because the lines that are typically monitored are valid when they are monitored. For example, the SRQ line is valid in the BSR when the NAT7210 is CIC, which is also when the SRQ line will be monitored.

NAT7210 Reference Manual 3-38 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Command/Data Out Register (CDOR)

Attributes: Write only

76543210

DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1

Bit Mnemonic Description

7–0w DIO[8–1] GPIB data lines DIO[8–1]

The CDOR moves data from the CPU to the GPIB when the interface is the GPIB Talker or Controller. Writing to the CDOR sets the local message, nba. When nba is true, the Source Handshake (SH) function can transfer the data or command in the CDOR to other GPIB devices. Writing to the CDOR also

• Clears the Data Out (DO) bit.

• Clears the DRQ signal (unless DMAO = 0). The host interface can write to the CDOR at offset 0 or by

performing a DMA write operation. The CDOR and the DIR use separate latches. A read of

the DIR does not change data in the CDOR. The CDOR is a transparent latch; thus, the GPIB data bus (DIO(8–1)) reflects changes on the CPU data bus during write cycles to the CDOR.

7210-Mode Interface Registers Chapter 3

Command Pass Through Register (CPTR)

Attributes: Read only

76543210

CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0

The host interface can examine the GPIB DIO lines by reading the Command Pass Through Register (CPTR). The CPTR has no storage; the host interface should read the CPTR only during a DAC holdoff. See the DAC Holdoffs section in Chapter 5, Software

Considerations.

Bit Mnemonic Description

7–0r CPT[7–0] Command Pass Through bits 7 through 0

NAT7210 Reference Manual 3-40 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Data In Register (DIR)

Attributes: Read only

76543210

DIO8 DIO7 DIO6 DIO5 DI04 DIO3 DIO2 DIO1

Bit Mnemonic Description

7–0r DIO[8–1] GPIB data lines DIO[8–1]

The Data In Register (DIR) holds data that the NAT7210 receives when the NAT7210 is a Listener. The NAT7210 latches GPIB data into the DIR when LACS & ACDS is true.

Latching data into the DIR causes the DI bit (ISR1[0]) to set, unless the NAT7210 is in continuous mode (see AUXMR[1:0]). Usually, latching data into the DIR causes an RFD holdoff (see The GPIB rdy Message and

RFD Holdoffs section in Chapter 5, Software Considerations).

The host interface can read the DIR at offset 0 or by asserting the DACK* and RD* pins. Reading the DIR also

• Clears DI (ISR1[0]).

• Clears the DRQ signal if DMAI (IMR2[4]) is set.

• Clears an RFD holdoff (depending on several other conditions).

The DIR and the CDOR use separate latches. When the host interface writes to the CDOR, data in the DIR is not changed.

7210-Mode Interface Registers Chapter 3

End-of-String Register (EOSR)

Attributes: Write only

76543210

EOS7 EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOS0

EOSR holds the byte that the NAT7210 uses to detect the end of a GPIB data block transfer. The NAT7210 compares data it receives to a 7- or 8-bit byte (ASCII or binary—depending on the BIN bit) in the EOSR in order to detect the end of a block of data.

If the NAT7210 is a Listener and REOS = 1, the END bit is set in ISR1 whenever the received data byte matches the EOSR. If the NAT7210 is a Talker and XEOS = 1, the END message (GPIB EOI* line asserted low) is sent along with a data byte whenever the data byte matches the EOSR.

Bit Mnemonic Description

7–0w EOS[7–0] End-of-String bits 7 through 0

NAT7210 Reference Manual 3-42 © National Instruments Corp.

Chapter 3 7210-Mode Interface Registers

Internal Count Register (ICR)

Attributes: Write only

76543210 0010F3F2F1F0

ICR determines the internal clock frequency of the NAT7210. You write to the ICR at the same offset as the AUXMR.

Note: The ICR resets to 00101000 (8 MHz). Bit Mnemonic Description

3–0 F(3–0) Clock Frequency

These bits, in addition to MICR (ICR2[0]), determine the length of certain delays that are required by the IEEE 488 standard. You should set these bits according to the frequency of the signal driving the CLK pin. For proper operation, set F(3–0) and MICR as follows:

Clock

Frequency

1 0 0001 2 0 0010 3 0 0011 4 0 0100 5 0 0101 6 0 0110 7 0 0111

8 0 1000 10 1 0101 16 1 1000 20 1 1010

MICR F(3–0)

7210-Mode Interface Registers Chapter 3

Internal Count Register 2 (ICR2)

Attributes: Write only

76543210 1 0 SLOW 0 0 0 0 MICR

Bit Mnemonic Description

5w SLOW Slow Handshake bit

Setting this bit enables circuitry that increases the time NRFD* or NDAC* must be unasserted before the NAT7210 responds to the unassertion.

If SLOW = 1, NRFD* and NDAC* must be unasserted for at least 400 ns before the NAT7210 responds to the unassertion.

0w MICR Modify Internal Count Register

Setting this bit modifies the meaning of the bits in the Internal Count Register. For more details, see the Internal

Count Register (ICR) section in this chapter.

Chapter 3 7210-Mode Interface Registers

Interrupt Mask Register 0 (IMR0)

Attributes: Write only

76543210

GLINT STBOIENLEN 0 IFCI IE ATNI

0 SYNC

Interrupt Status Register 0 (ISR0)

Attributes: Read only

76543210

nba STBO NL EOS IFCI ATNI X SYNC

Interrupt Status Register 0 (ISR0) contains Interrupt Status bits and Internal Status bits. Interrupt Mask Register 0 (IMR0) contains Interrupt Enable bits and Internal Control bits. If an Interrupt Enable is true when the corresponding status condition or event occurs, the NAT7210 can generate a hardware interrupt request. See the Generating Hardware Interrupts section in Chapter 5, Software Considerations.

Bits in ISR0 are set and cleared regardless of the status of bits in IMR0. If an interrupt condition occurs at the same time the host interface is reading ISR0, the NAT7210 does not set the corresponding Interrupt Status bit until the read is finished. A hardware reset clears all bits in IMR0 except GLINT, which is set.

Bit Mnemonic Description

7r nba New Byte Available local message bit

nba reflects the status of the local New Byte Available message.

nba is set on writes to the CDOR. nba is cleared by pon + nbaf + (NTNL & SIDS) + STRS

7w GLINT Global Interrupt Enable bit

GLINT enables the NAT7210 to assert the INT pin. If GLINT = 0, the INT pin does not assert. See the

Generating Hardware Interrupts section in Chapter 5, Software Considerations.

7210-Mode Interface Registers Chapter 3

IMR0/ISR0 (continued)

Bit Mnemonic Description

6r STBO Status Byte Out bit 6w STBO IE Status Byte Out Interrupt Enable bit

STBO IE determines how the NAT7210 requests service and responds to serial polls. See the Serial Polling section in Appendix B, Introduction to the GPIB.

If STBO IE = 0, the rsv bit in SPMR can be used to request service. When the GPIB Controller serial polls the NAT7210, the NAT7210 transmits the current value of SPMR.

If STBO IE = 1, the rsv bit in the SPMR has no effect on the Service Request (SR1) function and rsv must be generated through the reqt auxiliary command. STBO sets when the GPIB Controller serial polls the NAT7210. In response to STBO, the host interface writes a byte to SPMR, then the NAT7210 transmits this byte as the Serial Poll response.

STBO is set by

STBO IE & SPAS

STBO is cleared by

pon + (write SPMR) + ~SPAS

5r NL New Line Receive bit

NL is set when the NAT7210 accepts the ASCII new line character from the GPIB data bus.

NL is set by

LACS & NL & ACDS

NL is cleared by

pon + (LACS & ~NL & ACDS)

Chapter 3 7210-Mode Interface Registers

IMR0/ISR0 (continued)

Bit Mnemonic Description

5w NLEN New Line End Enable bit

If NLEN = 1, the NAT7210 treats the 7-bit ASCII new line character (0A hex) as an EOS character. The Acceptor Handshake function responds to the acceptance of a new line character in the same manner as if EOI were sent.

4r EOS End-of-String bit

The EOS bit indicates that the END bit in ISR1 was set by the acceptance of the End-of-String character.

EOS is set by

LACS & EOS & REOS & ACDS

EOS is cleared by

pon + (LACS & ~EOS & ACDS) + ~REOS

3r IFCI IFC Interrupt bit 3w IFCI IE IFC Interrupt Enable bit

IFCI is set on the assertion of the GPIB IFC* line. IFCI is cleared by

pon + (read ISR0) & ~SISB + clearIFCI

2r ATNI ATN Interrupt bit 2w ATNI IE ATN Interrupt Enable bit

ATNI is set on the assertion of the ATN* line. ATNI is cleared by

pon + (read ISR0) & ~SISB + clearATNI

1r X Don’t care bit

7210-Mode Interface Registers Chapter 3

IMR0/ISR0 (continued)

Bit Mnemonic Description

0r SYNC GPIB Synchronization bit 0w SYNC IE GPIB Synchronization Interrupt Enable bit

SYNC reflects the status of GPIB handshake lines after a transfer. SYNC is set at the completion of a transfer when the GPIB handshake is complete. An interrupt is generated when SYNC IE and SYNC are set.

Chapter 3 7210-Mode Interface Registers

Interrupt Mask Register 1 (IMR1)

Attributes: Write only

76543210

CPT IE APT IE DET IE END IE DEC IE ERR IE DO IE DI IE

Interrupt Status Register 1 (ISR1)

Attributes: Read only

Bits are cleared when read if SISB = 0

76543210

CPT APT DET END RX DEC ERR D O DI

Interrupt Status Register 1 (ISR1) contains eight Interrupt Status bits. Interrupt Mask Register 1 (IMR1) contains eight Interrupt Enable bits that directly correspond to the Interrupt Status bits in ISR1. As a result, ISR1 and IMR1 service eight possible interrupt conditions; each condition has an associated Interrupt Status bit and an Interrupt Enable bit. If an Interrupt Enable bit is true when the corresponding status condition or event occurs, the NAT7210 can generate a hardware interrupt request. See the Generating Hardware Interrupts section in Chapter 5, Software Considerations.

Bits in ISR1 are set and cleared regardless of the status of the Interrupt bits in IMR1. If an interrupt condition occurs at the same time the host interface is reading ISR1, the NAT7210 does not set the corresponding Interrupt Status bit until the read is finished. A hardware reset clears all bits in IMR1.

Bit Mnemonic Description

7r CPT Command Pass Through bit 7w CPT IE Command Pass Through Interrupt Enable bit

The CPT bit can flag the occurrence of two types of GPIB commands: undefined commands and user-specified commands.

When CPT ENAB = 1, the CPT bit flags the occurrence of undefined commands and all following secondary commands. The CPT bit flags undefined Address Command Group (ACG) commands only when the NAT7210 is an addressed Talker or Listener. The host interface can read the CPTR to determine the command the NAT7210 received.

7210-Mode Interface Registers Chapter 3

IMR1/ISR1 (continued)

Bit Mnemonic Description

The CPT bit also flags the occurrence of commands that you specify when you set the AUXRE[3–0] or AUXRF[3–0] bits.

When the CPT bit flags a command, the NAT7210 remains in a DAC Holdoff state until the host interface writes the valid or invalid auxiliary command to the AUXMR.

CPT is set by

[UCG + ACG & (TADS + LADS)] & undefined & ACDS & CPT ENABLE + UDPCF & SCG & ACDS & CPT ENABLE + DHADT & GET & ACDS + DHADC & (SDC + DCL) & ACDS + DHATA & TAG & ~UNT & ACDS + DHALA & LAG & ~UNL & ACDS + DHUNTL & (UNT + UNL) & ACDS + DHALL & ATN & ACDS

CPT is cleared by

pon + (read ISR1) & ~SISB + (read CPTR) & SISB

UDPCF is set by

[UCG + ACG & (TADS + LADS)] & undefined & ACDS & CPT ENAB

UDPCF is cleared by

[(UCG + ACG) & defined + TAG + LAG] & ACDS + ~(CPT ENAB) + pon

6r APT Address Pass Through bit 6w APT IE Address Pass Through Interrupt Enable bit

APT indicates that the NAT7210 has received a secondary GPIB address. The host interface can read the secondary GPIB address in the CPTR.

Note: If the application program uses extended dual

addressing, it must check this bit.

Chapter 3 7210-Mode Interface Registers

IMR1/ISR1 (continued)

Bit Mnemonic Description

When APT sets, the NAT7210 enters the DAC Holdoff state. When the host interface writes the valid or invalid auxiliary command to the AUXMR, the NAT7210 exits the DAC Holdoff state.

APT is set by

ADM1 & ADM0 & (TPAS + LPAS) & SCG & ACDS

APT is cleared by

pon + (read ISR1) & ~SISB + (valid + nonvalid) & SISB

5r DET Device Execute Trigger bit 5w DET IE Device Execute Trigger Interrupt Enable bit

DET indicates that the NAT7210 received the GPIB Group Execute Trigger (GET) command while the NAT7210 was a GPIB Listener.

DET is set by

DTAS = GET & LADS & ACDS

DET is cleared by

pon + (read ISR1) & ~SISB + clearDET

4r END RX End Received bit 4w END IE End Received Interrupt Enable bit

END RX sets when the NAT7210, as a Listener, receives a data byte satisfying the END condition. A data byte satisfies the END condition if one of the following conditions is true:

• REOS = 1 and the data byte matches the contents of the EOSR.

• NLEN = 1 and the data byte matches the ASCII new line character (hex 0A).

• The GPIB EOI signal is asserted when the byte is received.

7210-Mode Interface Registers Chapter 3

IMR1/ISR1 (continued)

Bit Mnemonic Description

END RX is set by

(EOI + EOS & REOS + NL & NLEN) & ACDS & LACS

END RX is cleared by

pon + (read ISR1) & ~SISB + clearEND

3r DEC Device Clear bit 3w DEC IE Device Clear Interrupt Enable bit

DEC indicates that either the NAT7210 received the GPIB Device Clear (DCL) command or that the NAT7210 was a GPIB Listener and received the GPIB Selected Device Clear (SDC) command.

DEC is set by

DCAS = (SDC & LADS + DCL) & ACDS

DEC is cleared by

pon + (read ISR1) & ~SISB + clearDEC

2r ERR Error bit 2w ERR IE Error Interrupt Enable bit

The definition of ERR depends on NTNL. When NTNL = 0, ERR indicates that the contents of the CDOR have been lost. ERR sets when the NAT7210 sends data over the GPIB while no Listener exists on the GPIB. ERR also sets when a byte is written to the CDOR during SIDS or when a transition from SDYS to SIDS occurs.

When NTNL = 1, ERR indicates that the source handshake has attempted to send data or commands across the bus but has found no Listeners (that is, NDAC and NRFD were unasserted). Data is not lost. The SH function does not source the data or command until a Listener appears (that is, NDAC asserts).

Chapter 3 7210-Mode Interface Registers

IMR1/ISR1 (continued)

Bit Mnemonic Description

ERR is set by

~NTNL & TACS & SDYS & DAC & RFD + ~NTNL & SIDS & (write CDOR) + ~NTNL & (SDYS to SIDS) + NTNL & SDYS & EXTDAC & RFD

ERR is cleared by

pon + (read ISR1) & ~SISB + clearERR

1r DO Data Out bit 1w DO IE Data Out Interrupt Enable bit

DO indicates that the NAT7210, as GPIB Talker, is ready to accept another data byte into the CDOR. This data byte will be transmitted to the GPIB. DO clears when a byte is written to the CDOR or when the NAT7210 ceases to be the Active Talker.

DO is set by

TACS & SGNS & ~nba

DO is cleared by

~TACS + ~SGNS + nba + (read ISR1) & ~SISB

0r DI Data In bit 0w DI IE Data In Interrupt Enable Bit

DI indicates that the NAT7210, as a GPIB Listener, has accepted a data byte from the GPIB Talker.

DI is set by

LACS & ACDS & ~(continuous mode)

DI is cleared by

pon + (read ISR1 & ~SISB) + (Finish Handshake & Holdoff mode) + (read DIR)

7210-Mode Interface Registers Chapter 3

Interrupt Mask Register 2 (IMR2)

Attributes: Write only

76543210 0 SRQI DMAO DMAI CO IE LOKCIEREMCIEADSC

Interrupt Status Register 2 (ISR2)

Type: 7210 mode Attributes: Read only

Bits clear when read if SISB = 0

76543210

INT SRQI LOK REM CO LOKC REMC ADSC

Interrupt Status Register 2 (ISR2) contains Interrupt Status bits and Internal Status bits. Interrupt Mask Register 2 (IMR2) contains Interrupt Enable bits and Internal Control bits. If an Interrupt Enable is true when the corresponding status condition or event occurs, the NAT7210 can generate a hardware interrupt request. See the Generating Hardware Interrupts section in Chapter 5, Software Considerations.

Bits in ISR2 are set and cleared regardless of the status of the bits in IMR2. If an interrupt condition occurs at the same time the host interface is reading ISR2, the NAT7210 does not set the corresponding Interrupt Status bit until the read is finished. A hardware reset clears all bits in IMR2.

Bit Mnemonic Description

7r INT Interrupt bit

This bit is the logical OR of the Enabled Interrupt Status bits in ISR0, ISR1, and ISR2.

Chapter 3 7210-Mode Interface Registers

IMR2/ISR2 (continued)

Bit Mnemonic Description

INT is set by

GLINT & [(CPT & CPT IE) + (APT & APT IE) + (DET & DET IE) + (ERR & ERR IE) + (END RX & END IE) + (DEC & DEC IE) + (DO & DO IE) + (DI & DI IE) + (REMC & REMC IE) + (SRQI IE & SRQI) + (LOKC & LOKC IE) + (CO IE & CO) + (ADSC & ADSC IE) + (STBO IE & STBO) + (IFCI IE & IFCI) + (ATNI IE & ATNI) + (SYNC IE & SYNC)]

6r SRQI Service Request bit 6w SRQI IE Service Request Interrupt Enable bit

SRQI indicates that the NAT7210, as CIC, received a GPIB Service Request (SRQ) message. SRQI is normally edge sensitive; however, consider the following sequence of events:

1. SRQ asserts, which asserts SRQI.

2. The control program clears SRQI, but SRQ remains asserted.

3. The NAT7210 serial polls a device.

4. The device sends the RQS message to the NAT7210 in response to the serial poll.

5. SRQ remains asserted because another device (not the one being serial polled) is asserting SRQ.

In the situation outlined above, SRQI sets at the end of the serial poll, even if SRQ never unasserts. In addition, if the control program issues the clear SRQI auxiliary command while SRQ is asserted, the NAT7210 clears SRQI for one clock pulse and then sets SRQI again.

SRQI is set by

(CIC & SRQ & -(RQS & DAV)) becoming true where RQS = DIO7 & ~ATN & SPMS

SRQI is cleared by

pon + (read ISR2) & ~SISB + clearSRQI

7210-Mode Interface Registers Chapter 3

IMR2/ISR2 (continued)

Bit Mnemonic Description

5r LOK Lockout bit 4r REM Remote bit

LOK and REM indicate the status of the GPIB Remote/Local (RL1) function of the NAT7210.

LOK REM RL1 State

0 0 LOCS 0 1 REMS 1 0 LWLS 1 1 RWLS

See the Remote/Local State Considerations section in Chapter 5, Software Considerations.

5w DMAO DMA Output Enable bit

If DMAO = 1, the DRQ pin asserts when the NAT7210, as a GPIB Talker, is ready to accept another data byte into the CDOR.

4w DMAI DMA Input Enable bit

If DMAI = 1, the DRQ pin asserts to indicate that the NAT7210, as a GPIB Listener, has accepted a data byte from the GPIB Talker.

3r CO Command Out bit 3w CO IE Command Out Interrupt Enable bit

CO = 1 indicates that the CDOR is empty and that another command can be written to it for transmission over the GPIB without overwriting a previous command.

CO is set by

CACS & SGNS & ~nba

Chapter 3 7210-Mode Interface Registers

IMR2/ISR2 (continued)

Bit Mnemonic Description

CO is cleared by

(read ISR2) & ~SISB + ~CACS + ~SGNS + cdba

2r LOKC Lockout Change bit 2w LOKC IE Lockout Change Interrupt Enable bit

LOKC sets when no change occurs in the LOK bit, ISR2[5]r.

LOKC is set by

any change in LOK

LOKC is cleared by

pon + (read ISR2) & ~SISB + clearLOKC

1r REMC Remote Change bit 1w REMC IE Remote Change Interrupt Enable bit

REMC sets when no change occurs in the REM bit, ISR2[4]r.

REMC is set by

any change in REM

REMC is cleared by

pon + (read ISR2) & ~SISB + clearREMC

0r ADSC Addressed Status Change bit 0w ADSC IE Addressed Status Change Interrupt Enable bit

ADSC sets when one of the following ADSR bits changes: TA, LA, CIC, or MJMN.

ADSC is set by

[(any change in TA) + (any change in LA) + (any change in CIC) + (any change in MJMN)] & ~(lon + ton)

ADSC is cleared by

pon + (read ISR2) & ~SISB + clearADSC + lon + ton

7210-Mode Interface Registers Chapter 3

Parallel Poll Register (PPR)

Attributes: Write only

Accessed at the same offset as AUXMR

76543210 0 1 1 U S P3 P2 P1

You use the Parallel Poll Register (PPR) to locally configure the manner in which the NAT7210 responds to a parallel poll. You write to the PPR at the same offset as the AUXMR. See the Parallel Polling section in Appendix B, Introduction to the GPIB.

When you use remote Parallel Poll Configuration (IEEE 488 capability code PP1), do not write to the PPR: writing to the PPR after it is remotely configured corrupts the configuration. The NAT7210 implements remote configuration fully and automatically without software assistance. However, you must still set or clear the individual status (ist) message (by using Set/Clear Parallel Poll Flag auxiliary commands) according to pre-established system protocol convention.

When you use the local Parallel Poll Configuration (capability code PP2), write to the PPR in advance of a poll. If PP2 (AUXRI[2]w) = 0, the contents written to the PPR are overwritten if the Controller sends a Parallel Poll command (such as PPE or PPD while in PACS or PPU) that causes the remote configuration to override the local configuration. If PP2 = 1, the reception of parallel poll commands does not affect the contents of the PPR and the local configuration determines the response during parallel polls.

Bit Mnemonic Description

4w U Unconfigure bit

The U bit determines whether the NAT7210 is locally configured to participate in parallel polls. If U = 1, the NAT7210 does not participate in parallel polls unless it is remotely configured to do so. If the host interface sets U, it should clear S and P[3–1] simultaneously.

If U = 0, the NAT7210 participates in parallel polls and responds in the manner defined by PPR[3] through PPR[0] and by ist. S and P[3–1] are the same as the bits of the same name in the PPE message, and the I/O write operation to the PPR is the same as the receipt of the PPE message from the GPIB Controller.

Chapter 3 7210-Mode Interface Registers

PPR (continued)

Bit Mnemonic Description

3w S Status Bit Polarity (Sense) bit

S indicates the polarity, or sense, of the NAT7210 local ist message. The following table describes the function of S.

S ist State of DIO Line

(Selected by P[3–1]

During a Parallel Poll)

0 0 Low Voltage—Logic 1 0 1 Unasserted—Logic 0 1 0 Unasserted—Logic 0 1 1 Low Voltage—Logic 1

Note: The DIO lines must be driven with open-

collector drivers during parallel polls.

2–0w P[3–1] Parallel Poll Response bits 3 through 1

P[3–1] indicate which of the eight DIO lines is asserted during a parallel poll. The following table shows the signal on which the NAT7210 responds to parallel polls.

P[3–1] Signals on which NAT7210

Responds to Parallel Polls

000 001 010 011

100 101 110 111

For examples of PPR configuration, see Chapter 6, Controller Software Considerations.

DIO1 DIO2 DIO3 DIO4

DIO5 DIO6 DIO7 DIO8

7210-Mode Interface Registers Chapter 3

Source/Acceptor Status Register (SASR)

Attributes: Read only

76543210

nba AEHS ANHS1 ANHS2 ADHS ACRDY SH1A SH1B

The Source/Acceptor Status Register (SASR) contains status bits that you can use to determine the state of the Source and Acceptor functions.

Bit Mnemonic Description

7r nba New Byte Available local message

6r AEHS Acceptor End Holdoff State bit

5r ANHS1 Acceptor Not Ready Holdoff bit

4r ANHS2 Acceptor Not Ready Holdoff Immediately bit

3r ADHS Acceptor Data Holdoff State bit

2r ACRDY Acceptor Ready State bit

Use this bit to determine the state of the Acceptor Handshake. By monitoring the LA and ATN bits in the ADSR, the DAV bit in the BSR, and the ADHS and ACRDY bits, you can determine the state of the Acceptor Handshake function as described below:

AIDS = ~ATN & ~LA ANRS = ~AIDS & ~ACRDY & ~DAV ACRS = ~AIDS & ACRDY & ~DAV ACDS = ~AIDS & ACRDY & DAV

+ ~AIDS & ~ACRDY & DAV & ATN &

ADHS

AWNS = ~AIDS & ~ACRDY & DAV & ~(ATN &

ADHS)

Chapter 3 7210-Mode Interface Registers

SASR (continued)

Bit Mnemonic Description

1–0r SH1A, SH1B Source Handshake State bits

Use these bits to determine the state of the Source Handshake interface function. By monitoring the TA, Serial Poll Mode State (SPMS), ATN bits in the ADSR, and the SH1A and SH1B bits, you can determine the state of the Source Handshake function as described below:

SIDS = ~(TACS & ~ATN + CIC & ATN) SGNS = ~SIDS & ~SH1A & ~SH1B SDYS = ~SIDS & SH1A STRS = ~SIDS & ~SH1A & SH1B

7210-Mode Interface Registers Chapter 3

Serial Poll Mode Register (SPMR)

Attributes: Write only

76543210

S8 rsv/RQS S6 S5 S4 S3 S2 S1

Serial Poll Status Register (SPSR)

Attributes: Read only

76543210

S8PENDS6S5S4S3S2S1

Bit Mnemonic Description

7r, S8 Serial Poll Status bit 8 7w

5–0r, S[6–1] Serial Poll Status bits 6 through 1 5–0w

These bits send device- or system-dependent status information over the GPIB when the Controller serial polls the NAT7210.

When STBO IE = 0, the NAT7210 transmits a byte of status information, SPMR[7–0], to the CIC if the CIC serial polls the NAT7210. The SPMR bits S[8, 6–1] are double buffered. If the host interface writes to the SPMR during a serial poll when SPAS is active, the NAT7210 saves the value. The NAT7210 updates the SPMR when the NAT7210 exits SPAS.

When STBO IE = 1 and the Controller serial polls the NAT7210, the STBO interrupt condition sets. The host interface should write the STB and the RQS bit to the SPMR in response to an STBO interrupt.

Issuing the Chip Reset auxiliary command clears these bits.

Chapter 3 7210-Mode Interface Registers

SPMR/SPSR (continued)

Bit Mnemonic Description

6r PEND Pending bit

PEND sets when rsv = 1. PEND clears when the NAT7210 is in the Negative Poll Response State (NPRS) and the local Request Service (rsv) message is false. By reading the PEND status bit, you can confirm that a request was accepted and that the Status Byte (STB) was transmitted (PEND = 0).

6w rsv/RQS Request Service/ RQS bit

When STBO IE = 0, bit 6 is the rsv bit. The rsv bit generates the GPIB local rsv message. When rsv = 1 and the GPIB Controller is not serial polling the NAT7210, the NAT7210 enters the Service Request State (SRQS) and asserts the GPIB SRQ signal. When the Controller reads the STB during the poll, the NAT7210 clears rsv. The rsv bit is also cleared by a hardware reset or by writing 0 to it. Issuing the Chip Reset auxiliary command also clears rsv.

When STBO IE = 1, bit 6 is the RQS bit. When the Controller serial polls the NAT7210, the STBO interrupt condition sets. The host interface should write the STB and the RQS bit to the SPMR in response to an STBO interrupt. The NAT7210 transfers the STB and RQS to the Controller during that particular serial poll. A hardware reset clears RQS. Issuing the Chip Reset auxiliary command also clears RQS.

7210-Mode Interface Registers Chapter 3

Version Status Register (VSR)

Attributes: Read only

76543210

V3 V2 V1 V0 X X X X

The Version Status Register (VSR) contains a value that is unique to each NAT7210 revision. You can use the VSR to distinguish a NAT7210 from a µPD7210. Future versions of the NAT7210 may read 10XX.

Bit Mnemonic Description

7–4r V[3 –0] The version number of the NAT7210APD is 1000.

3–0r X Don’t care bits

Chapter 4 9914-Mode Interface Registers

This chapter contains NAT7210 address maps and detailed descriptions of the NAT7210 interface registers in 9914 mode. For 7210-mode register descriptions, see Chapter 3, 7210-Mode Interface Registers.

9914 Register Map

Table 4-1 is the register bit map for the NAT7210 in 9914 mode. Notice that bold-ruled cells distinguish six registers that are accessible only when the

Page-In state is true. Refer to The Page-In Condition section that immediately follows the register map for more information.

9914-Mode Interface Registers Chapter 4

9914 Mode Only

Table 4-1. 9914-Mode Interface Registers

Key

= 9914-Mode Paged Registers

= Read Register

= Write Register

76543210

ISR0 +0 INT0 INT1 BI BO END SPAS RLC MAC R IMR0 +0 DMAO DMAI BI IE BO IE END IE SPAS IE RLC IE MAC IE W

ISR1 +1 GET ERR UNC APT DCAS MA SRQ IFC R IMR1 +1 GET IE ERR IE UNC IE APT IE DCAS IE MA IE SRQ IE IFC IE W

ADSR +2 REM LLO ATN LPAS TPAS LA TA ulpa R IMR2 +2 GLINT STBO IE NLEN 0 LLOC IE ATNI IE 0 CIC IE W EOSR +2 EOS7 EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOS0 W BCR +2 ATN DAV NDAC NRFD EOI SRQ IFC REN W ACCR +2 ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0 W

BSR +3 ATN DA V NDAC NRFD EOI SRQ IFC REN R AUXCR +3 C/S 0 0 F 4 F3 F2 F1 F0 W

ISR2 +4 nba STBO NL EOS LLOC ATNI X CIC R ADR +4 edpa dal dat A5 A4 A3 A2 A1 W

SPSR +5 S8 PEND S6 S5 S4 S3 S2 S1 R SPMR +5 S8 rsv/RQS S6 S5 S4 S3 S2 S1 W

CPTR +6 CPT 7 CPT6 CPT5 CPT4 CPT3 CPT 2 CPT1 CPT0 R PPR +6 PP8 PP7 PP6 PP5 PP4 PP3 PP2 PP1 W

DI R +7 DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 R CDOR +7 DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 W

Chapter 4 9914-Mode Interface Registers

9914 Mode Only

The Page-In Condition

Four writable registers can appear at the same offset as the Address Status Register (ADSR) (offset 4). After a hardware or software reset, no writable register appears at the ADSR offset: the NAT7210 ignores writes to that offset.

One Page-In auxiliary command exists for each of the four registers. The host interface can make one of the four registers accessible by issuing the appropriate Page-In command to the Auxiliary Command Register (AUXCR). The paged-in register remains accessible at the ADSR offset until the host interface pages-in another register or issues the Clear Page-In Register auxiliary command.

When any one of the four writable registers is accessible at the ADSR offset, Interrupt Status Register 2 (ISR2) is accessible at the same offset as ADR, and the Serial Poll Status Register (SPSR) is accessible at the same offset as the Serial Poll Mode Register (SPMR).

Hidden Registers

In addition to the registers shown in Table 4-1, the NAT7210 contains hidden registers. All hidden registers are write-only registers. Two or more hidden registers can appear at the same offset. When you write an 8-bit pattern to these offsets, some of the bits determine which hidden register will be written. The other bits represent the value written to the register.

Accessory Read Register Map

Several hidden registers appear at the ACCR offset. Table 4-2 shows these hidden registers.

Table 4-2. Hidden Registers at the ACCR Offset

ICR 0010 F3 F2 F1 F0 ACCA 1 0 0 BIN XEOS REOS 0 0 ACCB 1 0 1 ISS INV LWC SPEOI ATCT

ACCE 1100DHADT DHADC 0 0 ACCF 1101DHATA DHALA DHUNTL DHALL

ACCI 1110USTD PP1 0 DMAE

9914-Mode Interface Registers Chapter 4

9914 Mode Only

Register Bit Descriptions

Some 7210-mode registers and 9914-mode registers share identical names. The 7210-mode registers are described in Chapter 3, 7210-Mode Interface Registers. If you are using the NAT7210 in 9914 mode, be sure to read the proper description for the 9914-mode registers.

All registers are listed in alphabetical order. The registers are alphabetized according to their mnemonics.

Chapter 4 9914-Mode Interface Registers

9914 Mode Only

Accessory Register A (ACCRA)

Attributes: Write only

Accessed at the same offset as ACCR

76543210 100BINXEOSREOS00

Accessory Register A (ACCRA) controls the EOS and END messages. A hardware reset or the ch_rst auxiliary command clears ACCRA.

Bit Mnemonic Description

4w BIN Binary bit

The BIN bit selects the length of the EOS message. If BIN = 1, the EOSR is treated as an 8-bit byte. When BIN = 0, the EOSR is treated as a 7-bit register (for ASCII characters), and only a 7-bit comparison is done with the data on the GPIB.

3w XEOS Transmit END With EOS bit

The XEOS bit permits or prohibits automatic transmission of the GPIB END message at the same time as the EOS message when the NAT7210 is in Talker Active State (TACS). If XEOS = 1 and the byte in the CDOR matches the contents of the EOSR, the EOI line is sent true along with the data.

2w REOS END On EOS Received bit

The REOS bit permits or prohibits setting the END bit (ISR0[3]r) when the NAT7210 receives the EOS message as a Listener. If REOS = 1 and the byte in the DIR matches the byte in the EOSR, the END bit (ISR1[4]r) is set and the acceptor function treats the EOS character just as if it were received with EOI asserted.

9914-Mode Interface Registers Chapter 4

9914 Mode Only

Accessory Register B (ACCRB)

Attributes: Write only

Accessed at the same offset as ACCR

76543210 1 0 1 ISS INV LWC SPEOI ATCT

Bit Mnemonic Description

4w ISS Individual Status Select bit

ISS determines the value of the NAT7210 ist message. When ISS = 1, ist takes on the value of the NAT7210 SRQS. (The NAT7210 is asserting the GPIB SRQ message when it is in SRQS.) If ISS = 0, ist takes on the value of the NAT7210 Parallel Poll Flag. You set and clear the Parallel Poll Flag by using the Set Parallel Poll Flag and Clear Parallel Poll Flag auxiliary commands.

3w INV Invert bit

INV determines the polarity of the INT pin.

INV Bit INT Pin Polarity

0 Active High 1 Active Low

See the Generating Hardware Interrupts section in Chapter 5, Software Considerations.

2w LWC Listen When Controller bit

LWC enables the NAT7210 to accept command bytes that the NAT7210 sources when it is CIC. If LWC = 0, the NAT7210 does not accept command bytes sent by the NAT7210.

Chapter 4 9914-Mode Interface Registers

9914 Mode Only

ACCRB (continued)

Bit Mnemonic Description

1w SPEOI Send Serial Poll EOI bit

SPEOI determines whether the NAT7210 sends EOI when a Controller serial polls the NAT7210.

SPEOI EOI During Serial Polls

0 Sent False 1 Sent True

0w ATCT Automatic Take Control bit

If ATCT = 1, the NAT7210 can—without software intervention—take control when another CIC passes control to the NAT7210. Use the CIC bit (ISR2[0] to determine when the NAT7210 receives control. See the

GPIB Controller Considerations section in Chapter 6, Controller Software Considerations.

9914-Mode Interface Registers Chapter 4

9914 Mode Only

Accessory Register E (ACCRE)

Attributes: Write only

Accessed at the same offset as ACCR

7654 3 2 10 1 1 0 0 DHADT DHADC 0 0

Accessory Register E (ACCRE) determines how the NAT7210 uses a Data Accepted (DAC) holdoff. A hardware reset or the ch_rst auxiliary command clears ACCRE.

Each bit of ACCRE enables DAC holdoffs on a GPIB command or group of commands. When a GPIB Controller sends the specified command to the NAT7210, the Unrecognized Command (UNC) bit sets and the NAT7210 performs a DAC holdoff. See the DAC Holdoffs section in Chapter 5, Software Considerations.

Bit Mnemonic Description

3w DHADT DAC Holdoff On GET bit

2w DHADC DAC Holdoff On DCL Or SDC bit

Chapter 4 9914-Mode Interface Registers

9914 Mode Only

Accessory Register F (ACCRF)

Attributes: Write only

Accessed at the same offset as ACCR

7654 3 2 1 0 1101DHATA DHALA DHUNTL DHALL

Accessory Register F (ACCRF) determines how the NAT7210 uses a DAC holdoff. A hardware reset or the ch_rst auxiliary command clears ACCRF.

Each bit of ACCRF enables DAC holdoffs on a GPIB command or group of commands. When a GPIB Controller sends the specified command to the NAT7210, the UNC bit sets and the NAT7210 performs a DAC holdoff. See the DAC Holdoffs section in Chapter 5,

Software Considerations.

Bit Mnemonic Description

3w DHATA DAC Holdoff On All Talker Addresses bit

2w DHALA DAC Holdoff On All Listener Addresses bit

1w DHUNTL DAC Holdoff On The UNT Or UNL Command bit

0w DHALL DAC Holdoff On All UCG, ACG, And SCG Commands

bit

9914-Mode Interface Registers Chapter 4

9914 Mode Only

Accessory Register I (ACCRI)

Attributes: Write only

Accessed at the same offset as ACCR

76543210 1110USTDPP10DMAE

Bit Mnemonic Description

3w USTD Ultra Short T1 Delay bit

If USTD = 1, the T1 delay can be as short as 350 ns. See the T1 Delay Generation section in Chapter 5, Software Considerations.

2w PP1 Parallel Poll bit 1

The PP1 bit permits or prohibits the NAT7210’s ability to automatically respond to remote parallel poll configuration. If PP1 = 1, the NAT7210 can be configured remotely for parallel polls without software intervention.

The Acceptor Handshake does not perform a DAC holdoff or set the UNC bit when it receives a Parallel Poll Command (PPC or PPU).

If PP1 = 0, parallel polls must be configured through the PPR, and Parallel Poll commands must be monitored by UNC.

0w DMAE DMA Enable bit

DMAE lets you use DMAO (IMR0[7]) and DMAI (IMR0[6]) to enable the DRQ signal.

If DMAE = 0, DRQ always asserts when the NAT7210 receives a data byte as a Listener or when the NAT7210 is a Talker and the CDOR is empty.

DRQ is cleared by

pon + (read DIR) + (write CDOR)

Chapter 4 9914-Mode Interface Registers

9914 Mode Only

Address Register (ADR)

Attributes: Write only

76543210

edpa dal dat A5 A4 A3 A2 A1

ADR is used to load the primary GPIB address of the interface.

Bit Mnemonic Description

7w edpa Enable Dual Primary Addressing Mode bit

Setting edpa enables the dual primary addressing mode of the NAT7210. If edpa = 1, the NAT7210 ignores the least significant bit (A1) of its GPIB address. The NAT7210 then has two consecutive primary addresses. The ulpa bit in the Address Status Register indicates which address is active.

6w dal Disable Listener bit

Setting dal returns the NAT7210 Listener function to LIDS and forces the NAT7210 Listener function to remain in LIDS even if the chip receives its GPIB listen address or a lon auxiliary command.

5w dat Disable Talker bit

Setting dat returns the NAT7210 Talker function to TIDS and forces the Talker function to remain in TIDS even if the chip receives its GPIB talk address or a ton auxiliary command.

4–0w A[5–1] NAT7210 GPIB Address bits 5 through 1

A[5–1] specify the primary GPIB address of the NAT7210. The corresponding GPIB talk address is formed by adding hex 40 to A[5–1], while the corresponding GPIB listen address is formed by adding hex 20. A[5–1] should not be 11111 (binary) to prevent the corresponding talk and listen addresses from conflicting with the GPIB UNT and GPIB UNL commands.

9914-Mode Interface Registers Chapter 4

9914 Mode Only

Address Status Register (ADSR)

Attributes: Read only

76543210

REM LLO ATN LPAS TPAS LA TA ulpa

The Address Status Register (ADSR) contains information that you can use to monitor the NAT7210 GPIB address status.

Bit Mnemonic Description

7r REM Remote bit 6r LLO Local Lockout bit

REM and LLO indicate the status of the GPIB Remote/Local (RL1) function of the NAT7210.

LLO REM RL1 State

0 0 LOCS 0 1 REMS 1 0 LWLS 1 1 RWLS

5r ATN Attention bit

ATN indicates the current level of the NAT7210 ATN pin. If ATN = 1, the ATN pin is asserted (active low).

4r LPAS Listener Primary Addressed State bit

LPAS indicates that the NAT7210 has accepted its primary listen address.

LPAS is cleared by

(PCG & ~MLA & ACDS) + pon

Chapter 4 9914-Mode Interface Registers

9914 Mode Only

ADSR (continued)

Bit Mnemonic Description

3r TPAS Talker Primary Addressed State bit

TPAS indicates that the NAT7210 has accepted its primary talk address.

TPAS is cleared by

(PCG & ~MTA & ACDS) + pon

2r LA Listener Active bit

LA = 1 when the NAT7210 has been addressed or programmed as a GPIB Listener—that is, the NAT7210 is in LACS or LADS. The NAT7210 is addressed to listen when it receives its listen address from the CIC. You can also program the NAT7210 to listen by using the Listen-Only auxiliary command.

If the NAT7210 is addressed to listen, it is automatically unaddressed to talk.

LA is cleared by

pon + IFC + (UNL & ACDS)

1r TA Talker Active bit

TA = 1 when the NAT7210 has been addressed or programmed as the GPIB Talker—that is, the NAT7210 is in TACS, TADS, or SPAS. The NAT7210 can be addressed to talk when it receives its talk address from the CIC. You can also program the NAT7210 to talk by using the Talk-Only auxiliary command.

If the NAT7210 is addressed to talk, it is automatically unaddressed to listen.

TA is cleared by

pon + IFC + (OTA & ACDS)

9914-Mode Interface Registers Chapter 4

9914 Mode Only

ADSR (continued)

Bit Mnemonic Description

0r ulpa Upper/Lower Primary Address bit

ulpa indicates the least significant bit of the last primary address that the NAT7210 received.

Note: Only one Talker or Listener is active at a time.

ulpa indicates which, if either, NAT7210 Talker or Listener function is addressed or active.

The ch_rst auxiliary command clears the ulpa bit in the ADSR.

National Instruments NAT7210 NAT7210 Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Limited Warranty

Copyright

Trademarks

Contents

Figures

Tables

About This Manual

Organization of This Manual

Conventions Used in This Manual

Related Documentation

Customer Communication

Chapter 1 Introduction and General Description

IEEE 488 Capabilities

Table 1-1. NAT7210 IEEE 488 Interface Capabilities

CPU Interface Capabilities

Typical System Interface

Figure 1-1. NAT7210 Implementation Block Diagram

Chapter 2 NAT7210 Architecture

Figure 2-1. NAT7210 Block Diagram

NAT7210 Modes

Changing the NAT7210 Mode

Figure 2-2. Changing the NAT7210 Mode

Chapter 3 7210-Mode Interface Registers

7210 Register Map

Table 3-1. 7210-Mode Register Map

The Page-In State

How to Page-In

Hidden Registers

Address Register Map

Table 3-2. Hidden Registers at Offset 6 (ADR)

Auxiliary Mode Register Map

Table 3-3. Hidden Registers at Offset 5 (AUXMR)

Register Bit Descriptions

Address Mode Register (ADMR)

Table 3-4. Valid ADMR Patterns

Address Register (ADR)

Address Register 0 (ADR0)

Address Register 1 (ADR1)

Address Status Register (ADSR)

Auxiliary Mode Register (AUXMR)

Table 3-5. Auxiliary Command Summary

Table 3-6. Auxiliary Command Description

Auxiliary Register A (AUXRA)

Auxiliary Register B (AUXRB)

Auxiliary Register E (AUXRE)

Auxiliary Register F (AUXRF)

Auxiliary Register G (AUXRG)

Auxiliary Register I (AUXRI)

Table 3-7. Clear Conditions for SISB Bit

Bus Control Register (BCR)/Bus Status Register (BSR)

Figure 3-1. GPIB I/O Hardware Configuration

Command/Data Out Register (CDOR)

Command Pass Through Register (CPTR)

Data In Register (DIR)

End-of-String Register (EOSR)

Internal Count Register (ICR)

Internal Count Register 2 (ICR2)

Interrupt Mask Register 0 (IMR0)

Interrupt Status Register 0 (ISR0)

Interrupt Mask Register 1 (IMR1)

Interrupt Status Register 1 (ISR1)

Interrupt Mask Register 2 (IMR2)

Interrupt Status Register 2 (ISR2)

Parallel Poll Register (PPR)

Source/Acceptor Status Register (SASR)

Serial Poll Mode Register (SPMR)

Serial Poll Status Register (SPSR)

Version Status Register (VSR)

Chapter 4 9914-Mode Interface Registers

9914 Register Map

Table 4-1. 9914-Mode Interface Registers

The Page-In Condition

Hidden Registers

Accessory Read Register Map

Table 4-2. Hidden Registers at the ACCR Offset

Register Bit Descriptions