National Instruments NAT4882 NAT4882 Programmer Reference Manual

Download

NAT4882

Programmer Reference Manual

October 1993 Edition

Part Number 320383-01

National Instruments Corporate Headquarters

6504 Bridge Point Parkway Austin, TX 78730-5039 (512) 794-0100 Technical support fax: (800) 328-2203

(512) 794-5678

Branch Offices:

Australia (03) 879 9422, Austria (0662) 435986, Belgium 02/757.00.20, Canada (Ontario) (519) 622-9310, Canada (Québec) (514) 694-8521, Denmark 45 76 26 00, Finland (90) 527 2321, France (1) 48 14 24 24, Germany 089/741 31 30, Italy 02/48301892, Japan (03) 3788-1921, Mexico 95 800 010 0793, Netherlands 03480-33466, Norway 32-84 84 00, Singapore 2265886, Spain (91) 640 0085, Sweden 08-730 49 70, Switzerland 056/20 51 51, Taiwan 02 377 1200, U.K. 0635 523545

Limited Warranty

The NAT4882® integrated circuit (“equipment”) is warranted against defects in material and workmanship under normal use and service for a period of one (1) year from the date of shipment from the National Instruments factory. During this period of one year, National Instruments shall at its sole option either repair, replace, or credit the Buyer for defective equipment if: (i) Buyer returns the equipment to National Instruments, FOB the National Instruments factory in Austin, Texas; (ii) Buyer notifies National Instruments promptly upon discovery of any defect in writing, including a detailed description of the defect; and (iii) upon examination of the returned equipment, National Instruments is satisfied that the circuit is defective and that the cause of such defect is not alteration or repair by someone other than National Instruments, neglect, accident, misuse, improper installation, or use contrary to any instructions issued by National Instruments.

A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work. Prior to issuance of a RMA by National Instruments, Buyer shall allow National Instruments the opportunity to inspect the equipment onsite at Buyer’s facility.

This warranty expires one year from date of original shipment regardless of any warranty performance during that warranty period. The warranty provided herein is Buyer’s sole and exclusive remedy for nonconformity of the equipment or for breach of any warranty. THE ABOVE IS IN LIEU OF ALL OTHER WARRANTIES EXPRESSED OR IMPLIED. NATIONAL INSTRUMENTS SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. BUYER’S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE BUYER. NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS, OR INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY THEREOF. This limitation of the liability of National Instruments will apply regardless of the form of action, whether in contract or tort, including negligence. National Instruments recommends against the use of its products as critical components in any life support devices or systems whose failure to perform can reasonably be expected to cause significant injury to a human. Buyer assumes all risk for such application and agrees to indemnify National Instruments for all damages which may be incurred due to use of the National Instruments standard devices in medical or life support applications. Any action against National Instruments must be brought within one year after the cause of action accrues.

National Instruments believes that the information in this manual is accurate. The document has been carefully reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition. The reader should consult National Instruments if errors are suspected. In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it.

Copyright

Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written consent of National Instruments Corporation.

Trademarks

NAT4882® is a trademark of National Instruments Corporation. Product and company names listed are trademarks or trade names of their respective companies.

WARNING REGARDING MEDICAL AND CLINICAL USE

OF NATIONAL INSTRUMENTS PRODUCTS

National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the part of the user or application designer. Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel, and all traditional medical safeguards, equipment, and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used. National Instruments products are NOT intended to be a substitute for any form of established process, procedure, or equipment used to monitor or safeguard human health and safety in medical or clinical treatment.

About This Manual

Organization of This Manual...............................................................................ix

Conventions Used in This Manual.......................................................................x

Related Documents..............................................................................................x

Customer Communication...................................................................................x

Chapter 1 Introduction and General Description

NAT4882 Features...............................................................................................1-1

NAT4882 Functional Description........................................................................1-2

GPIB Capabilities ................................................................................................1-5

Interrupt Capabilities............................................................................................1-7

7210 Mode Interrupts...............................................................................1-7

9914 Mode Interrupts...............................................................................1-8

Addressing Schemes............................................................................................1-9

Chapter 2 NAT4882 Interface Registers

7210 Mode Registers ...........................................................................................2-2

Data In Register (DIR).............................................................................2-5

Command/Data Out Register (CDOR)....................................................2-6

Interrupt Status Register 1 (ISR1)............................................................2-7

Interrupt Mask Register 1 (IMR1)...........................................................2-7

Interrupt Status Register 2 (ISR2)............................................................2-14

Interrupt Mask Register 2 (IMR2)...........................................................2-14

Serial Poll Status Register (SPSR)...........................................................2-19

Serial Poll Mode Register (SPMR)..........................................................2-19

Key Status Register (KSR) ......................................................................2-21

Key Control Register (KCR)....................................................................2-22

Address Status Register (ADSR).............................................................2-24

Address Mode Register (ADMR)............................................................2-27

Command Pass Through Register (CPTR)..............................................2-30

Source/Acceptor Status Register (SASR)................................................2-32

Auxiliary Mode Register (AUXMR).......................................................2-34

Hidden Registers......................................................................................2-44

Parallel Poll Register (PPR).........................................................2-44

Auxiliary Register A (AUXRA)..................................................2-47

Auxiliary Register B (AUXRB)...................................................2-49

Auxiliary Register E (AUXRE)...................................................2-51

Auxiliary Register F (AUXRF)....................................................2-53

Auxiliary Register G (AUXRG)..................................................2-55

Auxiliary Register I (AUXRI).....................................................2-57

Auxiliary Register J (AUXRJ).....................................................2-60

................................................................................2-1

..............................................................1-1

Contents

Address Register 0 (ADR0).....................................................................2-62

Address Register (ADR)..........................................................................2-63

Interrupt Status Register 0 (ISR0)............................................................2-64

Interrupt Mask Register 0 (IMR0)...........................................................2-64

Address Register 1 (ADR1).....................................................................2-68

End Of String Register (EOSR)...............................................................2-70

Bus Status Register (BSR).......................................................................2-71

Bus Control Register (BCR)....................................................................2-71

9914 Mode Registers ...........................................................................................2-74

Interrupt Status Register 0 (ISR0)............................................................2-76

Interrupt Mask Register 0 (IMR0)...........................................................2-76

Interrupt Status Register 1 (ISR1)............................................................2-81

Interrupt Mask Register 1 (IMR1)...........................................................2-81

Address Status Register (ADSR).............................................................2-87

Interrupt Mask Register 2 (IMR2)...........................................................2-90

End Of String Register (EOSR)...............................................................2-92

Bus Control Register (BCR)....................................................................2-93

Hidden Registers......................................................................................2-95

Accessory Register A (ACCRA).................................................2-95

Accessory Register B (ACCRB)..................................................2-97

Accessory Register E (ACCRE)..................................................2-99

Accessory Register F (ACCRF)...................................................2-100

Accessory Register I (ACCRI) ....................................................2-102

Accessory Register J (ACCRJ)....................................................2-104

Bus Status Register (BSR).......................................................................2-106

Auxiliary Command Register (AUXCR).................................................2-107

Interrupt Status Register 2 (ISR2)............................................................2-116

Address Register (ADR)..........................................................................2-119

Serial Poll Status Register (SPSR)...........................................................2-120

Serial Poll Mode Register (SPMR)..........................................................2-120

Command Pass Through Register (CPTR)..............................................2-122

Parallel Poll Register (PPR).....................................................................2-124

Data In Register (DIR).............................................................................2-125

Data Out Register (DOR).........................................................................2-126

Chapter 3 NAT4882 Programming Considerations

Initialization.........................................................................................................3-1

The NAT4882 as GPIB Controller......................................................................3-3

System Controller ....................................................................................3-3

Becoming Controller-In-Charge (CIC) and Active Controller................3-3

Sending Remote Multiline Messages (Commands).................................3-4

Going from Active to Standby Controller................................................3-4

Going from Standby to Active Controller................................................3-5

Going from Active to Idle Controller ......................................................3-5

The NAT4882 as GPIB Talker and Listener .......................................................3-6

Programmed Implementation of Talker and Listener..............................3-6

NAT4882 Programmer Reference Manual vi © National Instruments Corporation

..........................................................3-1

Addressed Implementation of Talker and Listener..................................3-6

Address Mode 1...........................................................................3-7

Address Mode 2...........................................................................3-7

Address Mode 3...........................................................................3-7

Sending and Receiving Messages........................................................................3-8

Sending and Receiving END or EOS ......................................................3-9

Performing an RFD Holdoff on the Last Data Byte................................3-9

Aborting a Data Transmission.................................................................3-10

Serial Polls...........................................................................................................3-10

Conducting Serial Polls............................................................................3-10

Requesting Service...................................................................................3-10

Responding to Serial Polls.......................................................................3-11

Parallel Polls ........................................................................................................3-11

Conducting a Parallel Poll........................................................................3-12

Responding to a Parallel Poll...................................................................3-13

Interrupts..............................................................................................................3-14

Direct Memory Access (DMA)............................................................................3-14

Synchronization Detection...................................................................................3-14

Timeouts...............................................................................................................3-15

Global Timeouts.......................................................................................3-15

Byte Timeouts..........................................................................................3-15

Contents

Appendix A Multiline Interface Command Messages

..........................................................A-1

Appendix B Mnemonics Key

.........................................................................................................B-1

Appendix C Customer Communication

.....................................................................................C-1

Glossary.............................................................................................................Glossary-1

Index.........................................................................................................................Index-1

Contents

Figures

Figure 1-1. NAT4882 Implementation Block Diagram..............................................1-2

Figure 1-2. NAT4882 Block Diagram........................................................................1-4

Figure 2-1. 7210 Mode Register Map.........................................................................2-3

Figure 2-2. 7210 Mode Hidden Registers...................................................................2-4

Figure 2-3. GPIB I/O Hardware Configuration for µPD7210 Mode..........................2-72

Figure 2-4. 9914 Mode Interface Registers................................................................2-74

Figure 2-5. 9914 Mode Hidden Registers...................................................................2-75

Figure 2-6. GPIB I/O Hardware Configuration for TMS9914A Mode......................2-93

Tables

Table 1-1. NAT4882 IEEE 488 Interface Capabilities.............................................1-5

Table 2-1. Clues to Understanding Mnemonics........................................................2-2

Table 2-2. Multiline GPIB Commands Recognized by the GPIB Chip in

µPD7210 Mode........................................................................................2-30

Table 2-3. Auxiliary Command Summary................................................................2-35

Table 2-4. Auxiliary Command Description.............................................................2-37

Table 2-5. Clear Conditions for SISB Bit.................................................................2-58

Table 2-6. Timeout Values in µPD7210 Mode.........................................................2-60

Table 2-7. Timeout Values in TMS9914A Mode.....................................................2-104

Table 2-8. Auxiliary Command Summary................................................................2-108

Table 2-9. Auxiliary Command Description.............................................................2-110

Table 2-10. Multiline GPIB Commands Recognized by the NAT4882 in

9914A Mode ............................................................................................2-122

NAT4882 Programmer Reference Manual viii © National Instruments Corporation

About This Manual

The NAT4882 is an application-specific integrated circuit developed by National Instruments. The NAT4882 is an IEEE 488.2 Controller chip designed to perform all the interface functions defined in the IEEE 488.1-1987 standard and the additional requirements of the IEEE 488.2-1987 standard. The NAT4882 performs complete IEEE 488 Talker, Listener, and Controller functions and is software compatible with the NEC µPD7210 and TI TMS9914A GPIB controller chips. The NAT4882 provides the core of a complete, high-speed IEEE 488.2 interface.

This manual describes the programmable features of the NAT4882 and contains information suitable for programmers and engineers who wish to write software for the NAT4882.

Organization of This Manual

This manual is divided into the following sections and appendixes:

• Chapter 1, Introduction and General Description, contains a list of NAT4882 features, a functional description of the NAT4882, a list of GPIB and interrupt capabilities, and a discussion of the addressing scheme used by the NAT4882.

• Chapter 2, NAT4882 Interface Registers, contains information on the use of the NAT4882 internal program registers. It also contains NAT4882 address maps and detailed descriptions of the NAT4882 interface registers.

• Chapter 3, NAT4882 Programming Considerations, explains important considerations for programming the NAT4882 in 7210 mode.

• Appendix A, Multiline Interface Command Messages, lists the multiline interface messages and describes the mnemonics and messages that correspond to the interface functions. These functions include initializing the bus, addressing and unaddressing devices, and setting device modes for local or remote programming. The multiline interface messages are IEEE 488defined commands that are sent and received with ATN TRUE.

• Appendix B, Mnemonics Key, is an easy reference table that defines the mnemonics (abbreviations) used throughout this manual for functions, remote messages, local messages, states, bits, registers, integrated circuits, and system functions.

• Appendix C, Customer Communication, contains forms you can use to request help from National Instruments or to comment on our products and manuals.

• The Glossary contains an alphabetical list and description of terms used in this manual, including acronyms, abbreviations, metric prefixes, mnemonics, and symbols.

• The Index contains an alphabetical list of key terms and topics used in this manual, including the page number where you can find each one.

About This Manual

Conventions Used in This Manual

The following conventions are used to distinguish elements of text throughout this manual: italic Italic text denotes emphasis, a cross reference, or an introduction to a

key concept.

7210 mode 7210 mode is used throughout this manual to refer to the NEC

µPD7210 software compatibility mode.

9914 mode 9914 mode is used throughout this manual to refer to the TI

TMS9914A software compatibility mode.

IEEE 488 and IEEE 488 and IEEE 488.2 are used throughout this manual to refer to IEEE 488.2 the ANSI/IEEE Standard 488.1-1987 and the ANSI/IEEE Standard

488.2-1987, respectively, which define the GPIB.

Abbreviations, acronyms, metric prefixes, mnemonics, symbols, and terms are listed in the Glossary.

Customer Communication

National Instruments wants to receive your comments on our products and manuals. We are interested in the applications you develop with our products, and we want to help if you have problems with them. To make it easy for you to contact us, this manual contains comment and configuration forms for you to complete. These forms are in Appendix C, Customer

Communication, at the end of this manual.

NAT4882 Programmer Reference Manual x © National Instruments Corporation

Chapter 1 Introduction and General Description

This chapter contains a list of NAT4882 features, a functional description of the NAT4882, a list of GPIB and interrupt capabilities, and a discussion of the addressing scheme used by the NAT4882.

The NAT4882 is an IEEE 488.2 Controller chip designed to perform all the interface functions defined in the IEEE 488.1-1987 specification and the additional requirements and recommendations of the IEEE 488.2-1987 specification. The NAT4882 manages the IEEE 488 interface functions with a set of control and status registers that increase the throughput of driver software and simplify hardware and software design. The NAT4882 performs complete IEEE 488 Talker, Listener, and Controller functions and is software-compatible with the NEC µPD7210 and TI TMS9914A chips. The compatibility mode can be determined by either hardware or software. The NAT4882 is a surface-mountable 68-pin Plastic Leaded Chip Carrier (PLCC) part.

NAT4882 Features

The National Instruments NAT4882 has all the features necessary to provide a high-performance IEEE 488 interface. These features include the following:

• Can use all IEEE 488.1 interface functions and IEEE 488.2 requirements

- Source Handshake (SH1)

- Acceptor Handshake (AH1)

- Talker or Extended Talker (T5 or TE5)

- Listener or Extended Listener (L3 or LE3)

- Service Request (SR1)

- Remote/Local (RL1)

- Parallel Poll remote configuration (PP1) local configuration (PP2)

- Device Clear (DC1)

- Device Trigger (DT1)

- Controller, all capabilities (C1-C5)

- Busline Monitoring

- Preferred Implementation of requesting service

Introduction and General Description Chapter 1

• Can use six addressing modes

- Automatic single or dual primary addressing detection

- Automatic single primary with single secondary address detection

- Single or dual primary with multiple secondary addressing

- Multiple primary addressing

• Software-compatible with NEC µPD7210 and TI TMS9914A Controller chips

• Automatic EOS and/or NL message detection

• DMA support with automatic END message generation or automatic holdoff on terminal count

• Ability to detect bus synchronization

• Programmable T1 delay (2 µsec, 500 nsec, or 350 nsec)

• Automatic IEEE 488 command processing and undefined command read capability

• Programmable bus transceiver support (Texas Instruments, National Semiconductor, Motorola, Intel)

NAT4882 Functional Description

The NAT4882 can be characterized as a bus translator, converting messages and signals from the CPU into appropriate GPIB messages and signals. In GPIB terminology, the NAT4882 implements GPIB board and device functions to communicate with the central processor and memory. For the computer, the NAT4882 is an interface to the outside world.

Figure 1-1 shows a block diagram of a typical application using the NAT4882 to implement an IEEE 488.2 interface.

NAT4882 Programmer Reference Manual 1-2 © National Instruments Corporation

Chapter 1 Introduction and General Description

CPU Bus

Control

Address

Decode

GPIB

XCVR

GPIB

NAT4882

Data

GPIB

Interrupt

XCVR

Figure 1-1. NAT4882 Implementation Block Diagram

In all applications, the NAT4882 must be connected to the GPIB via special transceivers. The NAT4882 supplies the control signals necessary to interface to the IEEE 488 bus using several different types of transceivers, such as the 75160 and 75162 from National Semiconductor or Texas Instruments.

The NAT4882 interfaces to a CPU or local bus. Data is transferred to and from the registers of NAT4882 from the local bus to perform configuration, check status, or transfer data across the IEEE 488 bus. The NAT4882 can interrupt the CPU on many conditions. The NAT4882 also can use a Direct Memory Access (DMA) Controller for enhanced transfer speed.

Figure 1-2 shows a block diagram of the NAT4882.

Introduction and General Description Chapter 1

D(7-0)

CS*

RS2-0

RD*

Accen

WR*

Paged

DRQ

Swap

Dack*

T/C

INT

CLK

Read/ Write Control

Data-In

Command Pass Through

Command/Data Out

Address Status

Address Mode

Address 0/1

End-Of-String

Interrupt Mask 0, 1, 2

Interrupt Status 0, 1, 2

Timer

Serial Poll

CompareCompare

Message Decoder

Interface

Functions

SH1

AH1

T5/TE5

L3/LE3

SR1

RL1

PP1/PP2

DC1

DT1

C1-C5

DIO(8-1)*

T/R3 T/R2*

TE MA

REM LOK

TRIG

CIC SC

Reset*

Mode

Parallel Poll

Aux A, B, E, F, G, I

SASR

Auxiliary

Command Decoder

KEY/CSR

Figure 1-2. NAT4882 Block Diagram

RSV Gen

EOI Gen

STB Out

SYNC

Bus Status

and Control

GPIB Control

Keyrst* KeyDQ Keyclk

NAT4882 Programmer Reference Manual 1-4 © National Instruments Corporation

Chapter 1 Introduction and General Description

The interface includes the following major components:

• Read/Write Control converts the CPU signals presented to the NAT4882 to read and write signals for each internal register.

• Internal NAT4882 Registers configure and control the operation of the NAT4882. They transfer data between the NAT4882 and the GPIB bus, report status information, and set the operating modes. Each register is described in detail in Chapter 2, NAT4882 Interface Registers.

• Interface Functions implement the interface functions described in the IEEE 488.1-1978 specification. The interface functions are controlled by some of the internal registers, and you can use other internal registers to monitor their status. The interface functions drive and receive the GPIB control signals and generate the signals to control the GPIB transceivers.

• Message Decoding receives the GPIB data lines and decodes the GPIB commands that affect the operation of the interface functions.

GPIB Capabilities

Table 1-1 lists the capabilities of the NAT4882 in terms of the IEEE 488 standard codes.

Table 1-1. NAT4882 IEEE 488 Interface Capabilities

Capability Code Description

SH1 Complete Source Handshake capability AH1 Complete Acceptor Handshake capability, DAC and RFD

Holdoff on certain events

T5 Complete Talker capability

Basic Talker Serial Poll Talk Only mode Unaddressed on MLA Send END or EOS Dual primary addressing

TE5 Complete Extended Talker capability

Basic Extended Talker Serial Poll Talk Only mode Unaddressed on MSA*LPAS Send END or EOS Dual extended addressing with software assist

(continues)

Introduction and General Description Chapter 1

Table 1-1. NAT4882 IEEE 488 Interface Capabilities (continued)

Capability Code Description

L3 Complete Listener capability

Basic Listener Listen Only mode Unaddressed on MTA Detect END or EOS Dual primary addressing

LE3 Complete Extended Listener capability

Basic Extended Listener Listen Only mode Unaddressed on MSA*TPAS Detect END or EOS

Dual extended addressing with software assist SR1 Complete Service Request capability RL1 Complete Remote/Local capability with software

interpretation PP1 Remote Parallel Poll configuration PP2 Local Parallel Poll configuration with software assist

DC1 Complete Device Clear capability with software interpretation DT1 Complete Device Trigger capability with software

interpretation

C1 through C5 Complete Controller capability

System Controller Send IFC and take charge Send REN Respond to SRQ Send interface messages Received control Parallel Poll Take control synchronously or asynchronously

E1, E2 Provides an output signal (T/R3) that can be used to switch

the GPIB transceivers from Three-state drivers to open

Collector drivers during Parallel Polls

The NAT4882 has complete Source and Acceptor Handshake capability. It can operate as a basic Talker or Extended Talker and can respond to a Serial Poll. If you place it in a talk-only mode, it is unaddressed to talk when it receives its listen address. The NAT4882 GPIB interface can also operate as a basic Listener or Extended Listener. If you place it in a listen-only mode, it is unaddressed to listen when it receives its talk address. The NAT4882 can request service from another Controller. The ability to place the NAT4882 in local mode is software-dependent. The interface can conduct a Parallel Poll, although local configuration requires software assistance.

NAT4882 Programmer Reference Manual 1-6 © National Instruments Corporation

Chapter 1 Introduction and General Description

Device Clear and Trigger capability is included in the interface, but the interpretation is softwaredependent.

The NAT4882 includes all Controller functions, as specified by the IEEE 488 standard. These functions include the capability to do the following:

• Act as System Controller

• Initialize the interface

• Send Remote Enable

• Respond to Service Request

• Send multiline command messages

• Receive control

• Pass control

• Conduct a Parallel Poll

• Take control synchronously or asynchronously

Interrupt Capabilities

You can enable and disable NAT4882 interrupt sources individually by using the three Interrupt Mask Registers (IMR0, IMR1, and IMR2). All unmasked interrupt conditions in the NAT4882 are logically combined (ORed) before being driven on the NAT4882 IRQ line.

7210 Mode Interrupts

The interrupt conditions in 7210 mode are as follows:

• GPIB Data In (DI)

• GPIB Data Out (DO)

• END received (END RX)

• GPIB Command Out (CO)

• Remote Mode Change (REMC)

• GPIB Handshake Errors (ERR)

• Lockout Change (LOKC)

Introduction and General Description Chapter 1

• Address Status Change (ADSC)

• Secondary Address received (APT)

• Service Request received (SRQI)

• Trigger command received (DET)

• Device Clear received (DEC)

• Unrecognized command received (CPT)

• Status Byte Out (STBO)

• Interface Clear (IFC)

• Attention (ATN)

• Time Out (TO)

• GPIB Synchronized (SYNC) For more information on the 7210 mode interrupt conditions, refer to Interrupt Status Register 0,

1, and 2 in the 7210 Mode Registers section of Chapter 2, NAT4882 Interface Registers.

9914 Mode Interrupts

The interrupt conditions in 9914 mode are as follows:

• GPIB Byte In (BI)

• GPIB Byte Out (BO)

• END message received (END)

• Serial Poll Active State (SPAS)

• Remote/Local Change (RLC)

• My Address Change (MAC)

• Group Execute Trigger (GET)

• Transmit Error (ERR)

• Unrecognized Command (UNC)

• Secondary Address received (APT)

• Device Clear Active State (DCAS)

NAT4882 Programmer Reference Manual 1-8 © National Instruments Corporation

Chapter 1 Introduction and General Description

• My Address (MA)

• Service Request received (SRQ)

• Interface Clear (IFC)

• Status Byte Out (STBO)

• Local Lockout Change (LLOC)

• Attention (ATN)

• Time Out (TO)

• Controller-in-Charge (CIC) For more information on the 9914 mode interrupt conditions, refer to Interrupt Status

Addressing Schemes

Because the NAT4882 was designed to be completely compatible with the NEC µPD7210 or TI TMS9914A, only three register select lines are available, providing access to eight register locations. To include the additional features of the NAT4882, there are two methods of accessing additional registers: the hidden registers method and the paged registers method. The NAT4882 comes out of reset with a completely compatible register map so that existing software for either chip can run with no modification. By accessing these additional registers, features can be invoked under software control.

Hidden registers have always been a part of the µPD7210 chip, but their number has increased in the NAT4882, and their use has been expanded to the TMS9914A chip. Hidden registers provide additional write-only registers by using part of the data byte being written as an address. The upper three or four bits of a write to the Auxiliary Mode Register (AUXMR) in 7210 mode or the Accessory Register (ACCR) in 9914 mode select the register to be written. The lower four or five bits contain the data written to the register.

You can add additional readable and writeable registers to the 7210 mode by using one of two methods to page them into the locations of existing registers. If you issue the page-in auxiliary command, the additional registers are paged in until after the next CPU access to the NAT4882. If you use this method, you must issue the page-in command before every access to a paged register. Alternately, you can page in the registers by asserting the Page-In pin during an access. If you use this method, you can connect the Page-In pin to an additional address line, so that the paged registers appear at a different offset, and the NAT4882 occupies sixteen register locations. This method is the more efficient of the two, and is recommended unless it is necessary that the NAT4882 only occupy eight register locations.

Introduction and General Description Chapter 1

The TMS9914A chip has two unused readable locations and one unused writeable location that are used to add additional registers. Four additional write-only registers, located at the same offset, are added to the 9914 mode, and are made available by issuing a page-in command. Each register has its own page-in command, and unlike in the 7210 mode, a CPU access does not page out a register. You can only page out a register by issuing the page-in command of another register or by issuing the clear page-in command. The two unused readable locations are used for two new read-only registers after any page-in command has been issued. If no page-in command is issued, the NAT4882 does not drive the data bus when an unused location is accessed. The ACCEN pin indicates when registers have been paged in.

NAT4882 Programmer Reference Manual 1-10 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

This chapter contains information on the use of the NAT4882 internal program registers. It also contains NAT4882 address maps and detailed descriptions of the NAT4882 interface registers.

Software written for the NAT4882 controls the GPIB interface through a set of hardware registers. The internal registers of the NAT4882 IEEE 488.2 Controller are mapped between offsets 0 and 7 hex. Many of the registers are read-only or write-only. Some registers are not storage registers at all, but buffers through which status signals can be read or through which control signals can be sent. Two special register types are also located in the NAT4882: multiple hidden registers are accessed through a single register space by using the upper data bits to distinguish the registers; Paged registers are made accessible by writing a command to the NAT4882 before accessing the register.

The NAT4882 operates in two different compatibility modes: NEC µPD7210 mode and TI 9914A mode. The registers are mapped differently for the two modes and some registers exist in only one of the modes.

Note: Throughout this manual, 7210 mode is used to refer to the NEC µPD7210 software

compatibility mode, and 9914 mode is used to refer to the TI TMS9914A software compatibility mode.

Register Description Format

The remainder of this chapter describes each register in the 7210 and 9914 compatibility modes. Each register description gives the address, type, word size, and bit map of the register, followed by a detailed description of each bit.

The bit map of each register shows a diagram of the register with the most significant bit (bit 7 for an 8-bit register) shown on the left, and the least significant bit (bit 0) shown on the right. A square is used to represent each bit. Each bit is labeled with a name inside its square. An asterisk (*) after the bit name indicates that the signal is active low. An asterisk is equivalent to an overbar.

In many of the registers, several bits are labeled with an X, indicating don't care bits. When one of these registers is read, the don't care bits may appear set or cleared but should be ignored, as they have no significance. When a register is written to, these bits should be written as zeros.

The terms set, set true, and set to one are synonymous. The terms clear, set false, set to zero, and clear to zero are synonymous. The meanings of preset and reset are determined by the context in which they are used. Bit signatures are written in uppercase letters.

The term addressed indicates that the interface has been configured to perform a function from the GPIB side, while the term programmed means that it has been configured from the CPU interface side. This distinction is important to make, because many functions, such as making the interface a Talker or Listener, can be activated from either side.

NAT4882 Interface Registers Chapter 2

Where it is necessary to specify a particular bit of a register, the bit position appears as a decimal number in square brackets after the mnemonic. For example, ISR1[1] indicates the DI bit of Interrupt Status Register 1.

A minus sign (-) indicates logical negation. An ampersand (&) represents AND, and a plus sign (+) represents OR in logical expressions.

All numbers, except register offsets, are decimal unless specified otherwise. Register offsets are given in hexadecimal notation.

Uppercase mnemonics are used for control, status, data registers, register contents, and interface functions, as well as GPIB remote messages, commands, and logic states as defined in the IEEE 488 standard.

After a mnemonic of a name is defined, the mnemonic is used thereafter. Appendix B, Mnemonics Key, contains a list of all mnemonics used in this manual, along with their type and name. Mnemonics are assigned to messages, states, registers, bits, functions, and integrated circuits. Most mnemonics contain some clue to their meaning. Table 2-1 contains a list of clues to look for.

Table 2-1. Clues to Understanding Mnemonics

Clue Mnemonic Probably Stands For:

Ends in IE Interrupt enable bit

Ends in EN Enable bit

4 letters,

ends in S

Ends in R,

R0, R1, R2

3 letters,

uppercase

3 letters,

lowercase

7210 Mode Registers

Interface function as defined in the IEEE 488 standard

GPIB program register

Remote GPIB message

Local GPIB message

The 7210 mode register group consists of 31 registers. Figure 2-1 shows the register map for the 7210 mode registers, and Figure 2-2 shows the 7210 mode

hidden registers. The 7210 hidden registers are accessed by writing to the auxiliary mode register (AUXMR). The upper three or four bits written to the AUXMR determine which hidden register will be accessed, and the lower four or five bits are written to that hidden register as shown in Figure 2-2. The non-shaded registers in Figure 2-1 are normally available in 7210 mode.

NAT4882 Programmer Reference Manual 2-2 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

The paged registers in 7210 mode, which are shaded in Figure 2-1, can be accessed using two methods. You can issue the Page-In auxiliary command, which makes the paged registers available during the next CPU access to the NAT4882. After this paged access, the registers are paged out. Alternately, you can assert the Page-In pin of the NAT4882 during the access to make the paged registers available. The Page-In pin would commonly be connected as an additional address line so that the paged registers would appear at an address different from the standard 7210 registers, unless address space was limited.

The sections following Figures 2-1 and 2-2 contain detailed function descriptions of all 31 7210 mode registers.

Key = 7210 Mode Paged Registers

R = Read Register W = Write Register

7 6 5 4 3 2 1 0

DIR CDOR

ISR1 IMR1

ISR2 IMR2

SPSR KSR KCR SPMR

ADSR ADMR

CPTR SASR AUXMR

ADR0 ISR0 IMR0 ADR

DI7

CDO7

CPT

CPT IE

INT

CIC

ton

CPT7

cdba

CNT2

cdba

GLINT

ARS

DI6

CDO6

APT

APT IE

SRQI

SRQI IE

PEND

SWAP

rsv/RQS

ATN*

lon

CPT6 AEHS CNT1

DT0

STBO

STBO IE

DI5

CDO5

DET

DET IE

LOK

DMAO

MSTD

SPMS

TRM1

CPT5

ANHS1

CNT0

DL0

NLEE

DI4

CDO4

END RX

END IE

REM

DMAI

NO T1

LP AS

TRM0

CPT4

ANHS2

COM4

AD5-0

EOS BTO AD5

DI3

CDO3

DEC

DEC IE

CO IE

KEYDQ

KEYCLK

TPAS

CPT3

ADHS

COM3

AD4-0

IFCI

IFCI IE

AD4

DI2

CDO2

ERR

ERR IE

LOKC

LOKC IE

MODE

KEYDATEN

CPT2

ACRDY

COM2

AD3-0

ATNI

ATNI IE

AD3

DI1

CDO1

DO IE

REMC

REMC IE

KEYDATA

ADM1

CPT1 SH1A

COM1

AD2-0

TO IE

AD2

DI0

CDO0

DI IE

ADSC

ADSC IE

KEYRST*

MJMN

ADM0

CPT0 SH1B

COM0

AD1-0

SYNC

SYNC IE

AD1

R W W

R W

R W W

ADR1 BSR BCR EOSR

EOI ATN S ATN C

EOS7

DT1

DAV S

DAV C

EOS6

DL1 NDAC S NDAC C

EOS5

AD5-1

NRFD S

NRFD C

EOS4

AD4-1 EOI S EOI C

EOS3

AD3-1

SRQ S

SRQ C

EOS2

AD2-1 IFC S

IFC C

EOS1

AD1-1

REN S

REN C

EOS0

Figure 2-1. 7210 Mode Register Map

R W W

NAT4882 Interface Registers Chapter 2

Key W = Write Register

7 6 5 4 3 2 1 0

AUXMR CNT2 CNT1 CNT0 COM4 COM3 COM2 COM1

PPR 0 1 1 U S P3 P2 P1

AUXRA 1 0 0 BIN XEOS REOS HLDE HLDA

AUXRB 1 0 1 ISS INV TRI SPEOI CPT EN

AUXRE 1 1 0 0 DHADT DHADC DHDT DHDC

AUXRF 1 1 0 1 DHATA DHALA DHUNTL DHALL

COM0

AUXRG 0 1 0 0 NTNL RPP2 DISTCT CHES

AUXRI 1 1 1 0 USTD PP2 ACC SISB

AUXRJ 1 1 1 1 TM3 TM2 TM1 TM0

Figure 2-2. 7210 Mode Hidden Registers

NAT4882 Programmer Reference Manual 2-4 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Data In Register (DIR)

Access: location 0 (not affected by the page-in auxiliary command or the Page-In pin) Mode: µPD7210 Attributes: Read-Only

76543210R

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

The Data In Register (DIR) moves data from the GPIB to the computer when the interface is a Listener. Incoming information is separately latched by this register when a write to the Command/Data Out Register (CDOR) takes place, and is not destroyed. If the TLC is not in continuous mode, GPIB data is latched in this register when ACDS1 & ~ATN and the DI bit in ISR1 is set . The Not Ready For Data (NRFD) message is asserted until the byte is read from the DIR. The Acceptor Handshake (AH) completes automatically after the byte is read unless the TLC is in Ready For Data (RFD) Holdoff mode. In that case, the GPIB Handshake is not finished until the Finish Handshake (FH) auxiliary command is issued telling the NAT4882 to release the Holdoff. By using the RFD Holdoff mode, the same byte may be read several times or a GPIB Talker may be held off until the program is ready to proceed. This register can also be read by asserting the DACK* and RD* pins. For more information on the RFD Holdoff mode, refer to the Auxiliary Register A description later in this chapter.

DI1 is the least significant bit of the data byte and corresponds to GPIB data line DIO1. DI8 is the most significant bit of the data byte and corresponds to GPIB DIO8.

Bit Mnemonic Description

7-0r DIR[7-0] GPIB Data lines DIO[8-1]

NAT4882 Interface Registers Chapter 2

Command/Data Out Register (CDOR)

Access: location 0 (not affected by the page-in auxiliary command or the Page-In pin) Mode: µPD7210 Attributes: Write-Only

76543210

CDO7 CDO6 CDO5 CDO4 CDO3 CDO2 CDO1 CDO0

The Command/Data Out Register (CDOR) moves data from the computer to the GPIB when the interface is the GPIB Talker or the Active Controller. Outgoing data is separately latched by this register and is not destroyed by a read from the DIR. When a byte is written to the CDOR, the NAT4882 GPIB Source Handshake (SH) function is initiated (that is, the local message nba is true) and the byte is transferred to the GPIB. This register is also written on the assertion of the WR* signal when DACK* is asserted. The CDOR is a transparent latch; therefore, changes on the CPU data bus (D(7:0)) during write cycles to the CDOR are reflected on the GPIB data bus (DIO(8:1)).

Bit Mnemonic Description

7-0w CDO[7-0] GPIB Data lines DIO[8-1]

NAT4882 Programmer Reference Manual 2-6 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Interrupt Status Register 1 (ISR1)

Access: location 1 (not affected by the page-in auxiliary command or the Page-In pin) Mode: µPD7210 Attributes: Read-Only

Bits are cleared when read and SISB=0

Interrupt Mask Register 1 (IMR1)

Access: location 1 (not affected by the page-in auxiliary command or the Page-In pin) Mode: µPD7210 Attributes: Write-Only

76543210R

CPT APT DET END RX DEC ERR DO DI

CPT IE APT IE DET IE END IE DEC IE ERR IE DO IE DI IE

The Interrupt Status Register 1 (ISR1) is made up of eight Interrupt Status bits. The Interrupt Mask Register 1 (IMR1) is made up of eight Interrupt Enable bits that directly correspond to the Interrupt Status bits in ISR1. As a result, ISR1 and IMR1 service eight possible interrupt conditions, where each condition has an Interrupt Status bit and an Interrupt Enable bit associated with it. If the Interrupt Enable bit and the GLINT bit (in ISR0) is true when the corresponding status condition or event occurs, a hardware interrupt request is generated. Bits in ISR1 are set and cleared by the NAT4882 regardless of the status of the Interrupt bits in IMR1. If an interrupt condition occurs at the same time ISR1 is being read, the NAT4882 holds off setting the corresponding Status bit until the read has finished. All bits in IMR1 are cleared by a hardware reset.

Bit Mnemonic Description

7r CPT Command Pass Through bit 7w CPT IE Command Pass Through Interrupt Enable bit

The CPT bit flags the occurrence of any GPIB command not recognized by the NAT4882, and all following GPIB secondary commands when the Command Pass Through feature is enabled by the CPT ENAB bit, AUXRB[0]w. Any GPIB command message not decoded by the NAT4882 is treated as an undefined command (see Table 2-3 for a list of commands recognized in 7210 mode). However, any addressed command is automatically ignored when the NAT4882 is not addressed. The CPT can also flag the occurrence of a GPIB command or group of commands specified by the AUXRE[3-2]w or AUXRF[3-0]w bits.

NAT4882 Interface Registers Chapter 2

Bit Mnemonic Description

Undefined commands are read using the Command Pass Through Register (CPTR). The NAT4882 holds off the GPIB Acceptor Handshake in the Accept Data State (ACDS) until the program writes the Valid or Non-Valid auxiliary command function code to the AUXMR. If CPT ENAB is cleared, undefined commands are simply ignored. However, commands specified by the AUXRE[3-2]w and AUXRF[3-0]w are still flagged.

CPT is set by:

[UCG + ACG & (TADS + LADS)] & undefined & ACDS & CPT ENAB + UDPCF & SCG & ACDS1 & CPT ENAB + DHADT & GET & ACDS + DHADC & (SDC + DCL) & ACDS + DHATA & TAG & ~UNT & ACDS + DHALA & LAG & ~UNL & ACDS + DHUNTL & (UNT + UNL) & ACDS + DHALL & (UCG + ACG + SCG) & ACDS

CPT is cleared by:

pon + (read ISR1) & ~SISB + (read CPT) & SISB

Notes

UCG: GPIB Universal Command Group message ACG: GPIB Addressed Command Group message GET: GPIB Group Execute Trigger message SDC: GPIB Selected Device Clear message DCL: GPIB Device Clear message UNT: GPIB Untalk message UNL: GPIB Unlisten message TADS: GPIB Talker Addressed State LADS: GPIB Listener Addressed State defined: GPIB command automatically recognized and

executed by NAT4882

undefined: GPIB command not automatically recognized and

executed by NAT4882 ACDS: GPIB Accept Data State CPT ENAB: AUXRB[0]w SISB: AUXRI[0]w DHADT: AUXRE[3]w DHADC: AUXRE[2]w DHATA: AUXRF[3]w DHALA: AUXRF[2]w DHUNTL: AUXRF[1]w DHALL: AUXRF[0]w UDPCF: Undefined Primary Command Function SCG: GPIB Secondary Command Group message pon: Power On Reset

NAT4882 Programmer Reference Manual 2-8 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Bit Mnemonic Description

TAG: GPIB Talk Address Group message LAG: GPIB Listen Address Group message read ISR1: Read the Interrupt Status Register 1 read CPTR: Read of the Command Pass Through Register

UDPCF is set by:

[UCG + ACG & (TADS + LADS)] & undefined & ACDS & CPT ENAB

UDPCF is cleared by:

[(UCG + ACG) & defined + TAG + LAG] & ACDS + -(CPT ENAB) + pon

6r APT Address Pass Through 6w APT IE Address Pass Through Interrupt Enable

The APT bit indicates that a secondary GPIB address has been received and is available in the CPTR for inspection.

Note: The application program must check this bit when using

NAT4882 address mode 3.

When APT is set, the Data Accepted (DAC) message is held and the GPIB Handshake stops until either the Valid or Non-Valid auxiliary command is issued.

APT is set by:

ADM1 & ADM0 & (TPAS + LPAS) & SCG & ACDS

APT is cleared by:

pon + (read ISR1) & ~SISB + (Valid + Non-Valid) & SISB

Notes

ADM1: Address Mode Register bit 1, ADMR[1]w ADM0: Address Mode Register bit 0, ADMR[0]w SISB: Static Interrupt Status bits, AUXRI[0]w Valid: Valid Auxiliary Command issued Non-Valid: Non-Valid Auxiliary Command issued TPAS: GPIB Talker Primary Addressed State LPAS: GPIB Listener Primary Addressed State SCG: GPIB Secondary Command Group ACDS: GPIB Accept Data State pon: Power On Reset read ISR1: Read the Interrupt Status Register 1

NAT4882 Interface Registers Chapter 2

Bit Mnemonic Description

5r DET Device Execute Trigger bit 5w DET IE Device Execute Trigger Interrupt Enable bit

The DET bit indicates that the GPIB Group Execute Trigger (GET) command was received while the NAT4882 was a GPIB Listener–that is, while the NAT4882 was in DTAS.

DET is set by:

DTAS = GET & LADS & ACDS

DET is cleared by:

pon + (read ISR1) & ~SISB + clearDET

Notes

DTAS: GPIB Device Trigger Active State pon: Power On Reset read ISR1: Read the Interrupt Status Register 1 SISB: Static Interrupt Status Bits, AUXRI[0]w clearDET: clearDET Auxiliary Command issued

4r END RX End Received bit 4w END IE End Received Interrupt Enable bit

The END RX bit is set when the NAT4882 is a Listener and the GPIB uniline message, END, is received with a data byte from the GPIB Talker, when the data byte in the DIR matches the contents of the End Of String Register (EOSR) and REOS is set, or when the data byte in the DIR matches the ASCII newline character (hex 0A) and NLEE is set. The END bit is always set before the DI bit when a byte that sets END is received.

END RX is set by:

LACS & (EOI + EOS & REOS + NL & NLEE) & ACDS

END RX is cleared by:

pon + (read ISR1) & ~SISB + clearEND

Notes

LACS: GPIB Listener Active State EOI: GPIB End Or Identify Signal EOS: GPIB End Of String message NL: ASCII 'Newline' message (hex 0A) ACDS: GPIB Accept Data State

NAT4882 Programmer Reference Manual 2-10 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Bit Mnemonic Description

pon: Power On Reset read ISR1: Read the Interrupt Status Register 1 REOS: END on EOS Received bit, AUXRA[2]w SISB: Static Interrupt Status Bits, AUXRI[0]w NLEE: New Line End Enable, IMR0[5]w clearEND: clearEND Auxiliary Command issued

3r DEC Device Clear bit 3w DEC IE Device Clear Interrupt Enable bit

The DEC bit indicates that either the NAT4882 received the GPIB Device Clear (DCL) command or that the NAT4882 received the GPIB Selected Device Clear (SDC) command while it was a GPIB Listener. The NAT4882 is in DCAS.

DEC is set by:

DCAS = (SDC & LADS + DCL) & ACDS

DEC is cleared by:

pon + (read ISR1) & ~SISB + clearDEC

Notes

DCAS: GPIB Device Clear Active State pon: Power On Reset read ISR1: Read the Interrupt Status Register 1 SISB: Static Interrupt Status Bits, AUXRI[0]w clearDEC: clearDEC Auxiliary Command issued

2r ERR Error bit 2w ERR IE Error Interrupt Enable bit

The definition of the ERR bit depends on the status of the NTNL bit. If NTNL=0, the ERR bit indicates that the contents of the CDOR have been lost. ERR is set when data is sent over the GPIB without a specified Listener, when a byte is written to the CDOR during SIDS, or when a transition from SDYS to SIDS has occurred. If NTNL=1, the ERR bit indicates that the Source Handshake is attempting to send data or commands across the bus and finds that there are no Listeners– that is, that NDAC and NRFD are unasserted. Data is not lost, because the Source Handshake will attempt to source the data or command as soon as a Listener appears.

NAT4882 Interface Registers Chapter 2

Bit Mnemonic Description

ERR is set by:

~NTNL & TACS & SDYS & DAC & RFD + ~NTNL & SIDS & (write CDOR) + ~NTNL & (SDYS to SIDS) + NTNL & SDYS & EXTDAC & RFD

ERR is cleared by:

pon + (read ISR1) & ~SISB + clearERR

Notes

TACS: GPIB Talker Active State SDYS: GPIB Source Delay State DAC: GPIB Data Accepted message EXTDAC: GPIB Data Accepted message asserted by a device

other than the NAT4882 Acceptor Handshake RFD: GPIB Ready For Data message SIDS: GPIB Source Idle State write CDOR: Writing to the Command/Data Out Register SDYS to SIDS: Transition from GPIB Source Delay State to

Source Idle State pon: Power On Reset SISB: Static Interrupt Status Bits, AUXRI[0]w NTNL: No Talking when No Listener bit, AUXRG[3]w clearERR: clearERR Auxiliary Command issued read ISR1: Read the Interrupt Status Register 1

1r DO Data Out bit 1w DO IE Data Out Interrupt Enable bit

The DO bit indicates that the NAT4882, as GPIB Talker, is ready to accept another data byte from the CPU for transmission to the GPIB. The DO bit is cleared when a byte is written to the CDOR or when the NAT4882 ceases to be the Active Talker.

DO is set by:

(TACS & SGNS & ~nba)

DO is cleared by:

~(TACS) + ~(SGNS) + nba + (read ISR1) & ~SISB

Notes

TACS: GPIB Talker Active State SGNS: GPIB Source Generate State nba: New Byte Available Local Message SISB: Static Interrupt Status Bits, AUXRI[0]w read ISR1: Read the Interrupt Status Register 1

NAT4882 Programmer Reference Manual 2-12 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Bit Mnemonic Description

0r DI Data In bit 0w DI IE Data In Interrupt Enable bit

The DI bit indicates that the NAT4882, as a GPIB Listener, has accepted a data byte from the GPIB Talker.

DI is set by:

LACS & ACDS & ~(continuous mode)

DI is cleared by:

pon + (read ISR1) & ~SISB + (Finish Handshake) & (Holdoff mode) + (read DIR)

Notes

LACS: GPIB Listener Active State ACDS: GPIB Accept Data State continuous mode: Listen in Continuous Mode auxiliary command in

effect SISB: Static Interrupt Status Bits, AUXRI[0]w pon: Power On Reset read ISR1: Read the Interrupt Status Register 1 finish Handshake: Finish Handshake auxiliary command issued Holdoff mode: RFD Holdoff state read DIR: Read Data In Register

NAT4882 Interface Registers Chapter 2

Interrupt Status Register 2 (ISR2)

Access: location 2 (not affected by the page-in auxiliary command or the Page-In pin) Mode: µPD7210 Attributes: Read-Only

Bits clear when read if SISB=0

Interrupt Mask Register 2 (IMR2)

Access: location 2 (not affected by the page-in auxiliary command or the Page-In pin) Mode: µPD7210 Attributes: Write-Only

76543210R

INT SRQI LOK REM CO LOKC REMC ADSC

0 SRQI IE DMAO DMAI CO IE LOKC IE REMC IE ADSC IE

The Interrupt Status Register 2 (ISR2) consists of six Interrupt Status bits and two Internal Status bits. The Interrupt Mask Register 2 (IMR2) consists of five Interrupt Enable bits and two Internal Control bits. If the Interrupt Enable and GLINT bits (in ISR0) are true when the corresponding status condition or event occurs, an interrupt request is generated. Bits in ISR2 are set and cleared regardless of the status of the bits in IMR2. If the NAT4882 must set or clear a bit or bits in ISR2 while ISR2 is being read, the NAT4882 holds off setting or clearing the bit or bits until the read is finished. All bits in IMR2 are cleared on a hardware reset.

Bit Mnemonic Description

7r INT Interrupt bit

This bit is the logical OR of all the Enabled Interrupt Status bits in ISR0, ISR1 and ISR2, each one ANDed with its Interrupt Enable bit.

INT is set by:

Global IE & [(CPT & CPT IE) + (APT & APT IE) + (DET & DET IE) + (ERR & ERR IE) + (END RX & END IE) + (DEC & DEC IE) + (DO & DO IE) + (DI & DI IE) + (SRQI & SRQI IE) + (REMC & REMC IE) + (CO & CO IE) + (LOKC & LOKC IE) + (ADSC & ADSC IE) + (STBO IE & STBO) + (IFCI IE & IFCI) + (ATNI IE & ATNI) + (TO IE & TO) + (SYNC IE & SYNC)]

NAT4882 Programmer Reference Manual 2-14 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Bit Mnemonic Description

Notes

Global IE: Enable Interrupt on Command Pass Through bit CPT: Command Pass Through bit CPT IE: Enable Interrupt on Command Pass Through bit APT: Address Pass Through bit APT IE: Enable Interrupt on Address Pass Through bit DET: Device Execute Trigger bit DET IE: Enable Interrupt on Device Execute Trigger bit ERR: Error bit ERR IE: Enable Interrupt on Error bit END RX: End Received bit END IE: Enable Interrupt on End Received bit DEC: Device Clear bit DEC IE: Enable Interrupt on Device Clear bit DO: Data Out bit DO IE: Enable Interrupt on Data Out bit DI: Data In bit DI IE: Enable Interrupt on Data In bit SRQI: Service Request Input bit SRQI IE: Enable Interrupt on Service Request Input bit REMC: Remote Change bit REMC IE: Enable Interrupt on Remote Change bit CO: Command Output bit CO IE: Enable Interrupt on Command Output bit LOKC: Lockout Change bit LOKC IE: Enable Interrupt on Lockout Change bit ADSC: Address Status Change bit ADSC IE: Enable Interrupt on Address Status Change bit STBO: Status Byte Out bit STBO IE: Enable Interrupt on Status Byte Out bit IFCI: IFC Assertion bit IFCI IE: Enable Interrupt on IFC Assertion bit ATNI: ATN Assertion bit ATNI IE: Enable Interrupt ATN Assertion bit TO: Time Out bit TO IE: Enable Interrupt on Time Out bit SYNC: Synchronize bit SYNC IE: Enable Interrupt on Synchronize bit

7w 0 Unused bit

Write zero to this bit.

6r SRQI Service Request Input bit 6w SRQI IE Service Request Input Interrupt Enable bit

The SRQI bit indicates that a GPIB Service Request (SRQ) message has been received while the NAT4882 was Controller-In-Charge (CIC). The term ~(RQS & DAV) ensures

NAT4882 Interface Registers Chapter 2

Bit Mnemonic Description

that if SRQ remains asserted while serial polling a device in APRS, the SRQI bit will be set again, indicating that another device is also requesting service. In version 2 of the NAT4882 (NAT4882B), if the clear SRQI auxiliary command is issued and SRQ is still asserted, the SRQI bit clears for one clock pulse and is set again. In version 1 (NAT4882A), the command clears the SRQI bit, and it is not reset. Refer to the Key Status Register (KSR) to determine the version number of your NAT4882 chip.

SRQI is set when:

(CIC & SRQ & -(RQS & DAV)) becomes true

where RQS = DIO7 & ~ATN & SPMS

SRQI is cleared by:

pon + (read ISR2) & ~SISB + clearSRQI

Notes

CIC: GPIB Controller-In-Charge SRQ: GPIB Service Request message RQS: GPIB Request Service message SISB: Static Interrupt Status Bits, AUXRI[0]w clearSRQI: clearSRQI Auxiliary Command Issued DAV: GPIB Data Valid message pon: Power On Reset read ISR2: Read Interrupt Status Register 2

5r LOK Lockout bit

LOK is used, along with the REM bit, to indicate the status of the NAT4882 GPIB Remote/Local (RL) function. If set, the LOK bit indicates that the NAT4882 is in Local With Lockout State (LWLS) or Remote With Lockout State (RWLS). LOK is a Non-Interrupt bit.

5w DMAO DMA Out Enable bit

Setting DMAO enables the NAT4882 to assert the DRQ line when the set DO condition occurs. Once asserted the NAT4882 will keep the DRQ pin asserted until the set DO condition is false.

4r REM Remote bit

This bit is set when the NAT4882 GPIB RL function is in either Remote State (REMS) or Remote With Lockout State (RWLS). The NAT4882 RL function transfers to one of these states when the System Controller has asserted the Remote Enable line (REN), and the CIC addresses the NAT4882 as a Listener.

NAT4882 Programmer Reference Manual 2-16 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Bit Mnemonic Description

4w DMAI DMA Input Enable bit

Setting DMAI enables the NAT4882 to assert the DRQ line when the set DI condition occurs. Once asserted, the NAT4882 keeps the DRQ pin asserted until any of the clear DI conditions (except read ISR1) occurs.

3r CO Command Out bit 3w CO IE Command Out Interrupt Enable bit

CO = 1 indicates that the CDOR is empty and that another command can be written to it for transmission over the GPIB without overwriting a previous command.

CO is set by:

(CACS & SGNS & ~nba)

CO is cleared by:

(read ISR2) & ~SISB + ~CACS + ~SGNS + cdba

Notes

CACS: GPIB Controller Active State SGNS: GPIB Source Generate State SISB: Static Interrupt Status Bits, AUXRI[0]w nba: New Byte Available local message read ISR2: Read the Interrupt Status Register 2

2r LOKC Lockout Change bit 2w LOKC IE Lockout Change Interrupt Enable bit

LOKC is set if there is a change in the LOK bit, ISR2[5]r, (LOCS<– >LWLS or REMS<–>RWLS).

LOKC is set by any change in LOK. LOKC is cleared by:

pon + (read ISR2) & ~SISB + clearLOKC

Notes

LOK: ISR2[5]r pon: Power On Reset SISB: Static Interrupt Status Bits, AUXRI[0]w clearLOKC: clearLOKC auxiliary command issued read ISR2: Read the Interrupt Status Register 2

NAT4882 Interface Registers Chapter 2

Bit Mnemonic Description

1r REMC Remote Change bit 1w REMC IE Remote Change Interrupt Enable bit

REMC is set when there is a change in the REM bit, ISR2[4]r, (LOCS<–>REMS or LWLS<–>RWLS).

REMC is set by any change in REM. REMC is cleared by:

pon + (read ISR2) & ~SISB + clearREMC

Notes

REM: ISR2[4]r pon: Power On Reset SISB: Static Interrupt Status Bits, AUXRI[0]w clearREMC: clearREMC auxiliary command issued read ISR2: Read the Interrupt Status Register 2

0r ADSC Addressed Status Change bit 0w ADSC IE Addressed Status Change Interrupt Enable bit

ADSC is set when there is a change in one of the four bits TA, LA, CIC, MJMN of the Address Status Register (ADSR).

ADSC is set by:

[(any change in TA) + (any change in LA) + (any change in CIC) + (any change in MJMN)] & -(lon + ton)

ADSC is cleared by:

pon + (read ISR2) & ~SISB + clearADSC + lon + ton

Notes

TA: Talker Active bit, ADSR[1]r LA: Listener Active bit, ADSR[2]r CIC: Controller-In-Charge bit, ADSR[7]r MJMN: Major/Minor bit, ADSR[0]r lon: Listen Only bit, ADMR[6]w ton: Talk Only bit, ADMR[7]w pon: Power On Reset SISB: Static Interrupt Status Bits, AUXRI[0]w clearADSC: clearADSC auxiliary command issued read ISR2: Read the Interrupt Status Register 2 ADSR: Address Status Register ADMR: Address Mode Register

NAT4882 Programmer Reference Manual 2-18 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Serial Poll Status Register (SPSR)

Access: location 3 (except immediately after the page-in auxiliary command is issued or if

the Page-In pin is asserted)

Mode: µPD7210 Attributes: Read-Only

Serial Poll Mode Register (SPMR)

Access: location 3 (except immediately after the page-in auxiliary command is issued or if

the Page-In pin is asserted)

Mode: µPD7210 Attributes: Write-Only

76543210R

S8 PEND S6 S5 S4 S3 S2 S1

S8 rsv/RQS S6 S5 S4 S3 S2 S1

Bit Mnemonic Description

7r S8 Serial Poll Status bit 8 7w, 5-0r, S[6-1] Serial Poll Status bits 6 through 1 5-0w

Cleared by issuing the Chip Reset auxiliary command. These bits send device- or system-dependent status information over the GPIB when the NAT4882 is serial polled. When STBO IE = 0 and the NAT4882, as the GPIB Talker, receives the GPIB multiline Serial Poll Enable (SPE) command message, the NAT4882 transmits a byte of status information, SPMR[7- 0], to the Controller-In-Charge after the Controller Goes to Standby and becomes an Active Listener. In this mode, the SPMR bits S[8,6-1] are double-buffered and if the register is written to while the device is addressed during a serial poll (serial poll active state, SPAS), the value written is saved. These bits are updated when SPAS is terminated. When STBO IE = 1, the device STB should be written to these bits in response to an STBO interrupt and the value written will be sourced as the STB during that particular serial poll.

NAT4882 Interface Registers Chapter 2

Bit Mnemonic Description

6r PEND Pending bit

PEND is set when rsv=1. PEND is cleared when the NAT4882 is in Negative Poll Response State [NPRS] and the local Request Service message [rsv] is false. Reading the PEND status bit can confirm that a request was accepted and that the Status Byte (STB) was transmitted (PEND=0).

6w rsv/RQS Request Service/ RQS bit

When STBO IE = 0, bit 6 is the rsv bit. The rsv bit generates the GPIB local rsv message. When rsv is set and the GPIB Active Controller is not serial polling the NAT4882, the NAT4882 enters the Service Request State (SRQS) and asserts the GPIB SRQ signal. When the Active Controller reads the STB during the poll, the NAT4882 clears rsv at the Affirmative Poll Response State (APRS). The rsv bit is also cleared by pon, by issuing the Chip Reset auxiliary command, or by writing a zero (0) to it.

When STBO IE = 1, bit 6 is the RQS bit. The RQS bit should be written in response to an STBO interrupt along with the STB. The value written to the RQS bit is sourced on GPIB DIO7 (RQS) along with the STB during that particular serial poll.

NAT4882 Programmer Reference Manual 2-20 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Key Status Register (KSR)

Access: location 3 (immediately after the page-in auxiliary command is issued or if

the Page-In pin is asserted)

Mode: µPD7210 Attributes: Read-Only

76543210R

V3 V2 V1 V0 KEYDQ MODE 0 0

The Key Status Register contains a value unique to each version of the NAT4882 and can be used to distinguish itself from a standard µPD7210. It is also used to read data from an electronic key, if attached.

Bit Mnemonic Description

7-4r V[3-0] The version number of the NAT4882. NAT4882A reads 0001.

NAT4882B reads 0010.

3r KEYDQ Key Data bit

KEYDQ returns the logic value of the KEYDQ pin. If you are using an electronic key, the KEYDATEN bit in the KEY Register must be cleared to read data from the key. Key data bits are read from the key memory on the rising edge of KEYCLK.

2r MODE MODE bit

MODE returns the logic value of the MODE pin. The MODE pin determines which mode the NAT4882 functions in following a hardware reset. If MODE = 0, the NAT4882 functions in the 9914 mode following a hardware reset. If MODE = 1, the NAT4882 functions in the 7210 mode following a hardware reset.

1-0r 0 Reserved. These bits always read back zero.

NAT4882 Interface Registers Chapter 2

Key Control Register (KCR)

Access: location 3 (immediately after the page-in auxiliary command is issued or if the Page-In pin is asserted)

Mode: µPD7210 Attributes: Write-Only

76543210 0 SWAP MSTD NO T1

KEY CLK

The Key Register is a write-only register that can be used to control a hardware key.

Bit Mnemonic Description

KEY

DATEN

KEY

DATA

KEY

RST*

7w 0 Unused bit

Write zero to this bit.

6w SWAP Swap bit

The SWAP* pin of the NAT4882 is sampled during a hard reset to set the power on value of the SWAP bit. The bit is set if SWAP* is low when RESET* unasserts. The SWAP bit rearranges the order of the 9914 mode registers for use by the Turbo488 ASIC.

5w MSTD Maximum Speed T1 Delay bit

When set, this bit reduces the T1 delay to 200 nsec (four clocks at 20 MHz). This setting provides the maximum Source Handshake speed for interfaces that have the necessary 150 nsec of setup on the D7-0 bus (for example, the Turbo488 ASIC) before unasserting WR*.

4w NO T1 No T1 Delay bit

When set, the NAT4882 has a very short T1 delay, between 1 and 2 clock periods. It should be used for test purposes only.

3w KEYCLK Key Clock bit

This bit controls the KEYCLK output pin. Setting KEYCLK drives the KEYCLK pin low. Clearing KEYCLK drives the KEYCLK pin high. This bit must be toggled to read or write data to an electronic key using the KEYDATA bit. If KEYDATEN is set to one, the data in KEYDATA is written to the key on the falling edge of KEYCLK . If KEYDATEN is cleared, data is read from the key and placed at the KEYDQ bit in the KSR on the rising edge of KEYCLK.

NAT4882 Programmer Reference Manual 2-22 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Bit Mnemonic Description

Note: The active edges of KEYCLK contradict the DS1204 data

sheet because the KEYCLK bit is inverted before being presented to the hardware keys.

2w KEYDATEN Key Data Enable bit

This bit must be set to one to write data into the key. If it is cleared, data can be read from the key.

1w KEYDATA Key Data bit

This bit holds the data to be written into the key memory. The data bit is written into the key memory on the rising edge of the KEYCLK signal.

0w KEYRST* Key Reset bit

This bit must be set to one to initiate a key data transfer, and must remain set to one throughout the entire data transfer. Clearing this bit terminates a key data transfer.

NAT4882 Interface Registers Chapter 2

Address Status Register (ADSR)

Access: location 4 (not affected by the page-in auxiliary command or the Page-In pin) Mode: µPD7210 Attributes: Read-Only

76543210R

CIC ATN* SPMS LPAS TPAS LA TA MJMN

The Address Status Register (ADSR) contains information that can be used to monitor the TLC GPIB address status.

Bit Mnemonic Description

7r CIC Controller-In-Charge bit

CIC = ~(CIDS + CADS) CIC indicates that the NAT4882 GPIB Controller function is in an

active or standby state, with ATN* on or off, respectively. The Controller function is in an idle state (CIDS) or addressed state (CADS) if CIC = 0.

6r ATN* Attention* bit

ATN* is a Status bit that indicates the current level of the GPIB ATN* signal. If ATN* = 0, the GPIB ATN* signal is asserted.

5r SPMS Serial Poll Mode State bit

If SPMS = 1, the NAT4882 GPIB Talker (T) or Talker Extended (TE) function is enabled to participate in a serial poll. SPMS is set when the GPIB Active Controller has issued the GPIB Serial Poll Enable (SPE) command message. SPMS is cleared when the GPIB SPD (Serial Poll Disable) command is received, either by pon or by the assertion of the GPIB IFC signal.

4r LPAS Listener Primary Addressed State bit

The LPAS bit is used when the NAT4882 is configured for extended GPIB addressing and, when set, indicates that the NAT4882 has received its primary listen address. In mode 3 addressing (see Address Mode Register in this chapter), LPAS = 1 indicates that the secondary address received on the next GPIB command may represent the NAT4882 extended (secondary) GPIB listen address. LPAS is cleared by a primary command that is not the TLCs primary listen address, by pon, or by the Chip Reset auxiliary command.

NAT4882 Programmer Reference Manual 2-24 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Bit Mnemonic Description

3r TPAS Talker Primary Addressed State bit

TPAS is used when the NAT4882 is configured for extended GPIB addressing, and, when set, indicates that the NAT4882 has received its primary GPIB talk address. In extended mode addressing (mode 3 addressing), TPAS = 1 indicates that the secondary address being received as the next GPIB command may represent the NAT4882 extended (secondary) GPIB talk address. TPAS is cleared by a primary command that is not the TLCs primary talk address, by pon, or by the Chip Reset auxiliary command.

2r LA Listener Active bit

LA is set when the NAT4882 has been addressed or programmed as a GPIB Listener–that is, the NAT4882 is in the Listener Active State (LACS) or the Listener Addressed State (LADS). The NAT4882 can be addressed to listen either by sending its own listen or extended listen address while it is CIC or by receiving its listen address from another CIC. It can also be programmed to listen using the Listen Only (lon) bit in the Address Mode Register (ADMR).

If the NAT4882 is addressed to listen, it is automatically unaddressed to talk. LA is cleared by the UNL GPIB command, by the assertion of the GPIB IFC signal, by pon, by issuing the Chip Reset auxiliary command, by issuing the local unlisten auxiliary command (lun) while in CACS, or by issuing the unlisten auxiliary command (lul).

1r TA Talker Active bit

TA is set when the NAT4882 has been addressed or programmed as the GPIB Talker–that is, when the NAT4882 is in the Talker Active State (TACS), the Talker Addressed State (TADS), or the Serial Poll Active State (SPAS). The NAT4882 can be addressed to talk either by sending its own talk or extended talk address while it is CIC or by receiving its talk address from another CIC. It can also be programmed to talk using the Talk Only (ton) bit in the ADMR.

If the NAT4882 is addressed to talk, it is automatically unaddressed to listen. TA is cleared upon receiving an Other Talk Address (OTA), the assertion of the GPIB IFC signal, by pon, by issuing the Chip Reset auxiliary command, or by issuing the untalk auxiliary command (lut).

NAT4882 Interface Registers Chapter 2

Bit Mnemonic Description

0r MJMN Major-Minor bit

The MJMN bit indicates whether the information in the other ADSR bits applies to the NAT4882 major or minor Talker and Listener functions. MJMN is set to one when the NAT4882 GPIB minor talk address or minor listen address is received. MJMN is cleared on receipt of the NAT4882 major talk or major listen address.

Note: Only one Talker or Listener can be active at any one time;

thus, the MJMN bit indicates which, if either, of the NAT4882 Talker and Listener functions is addressed or active.

MJMN is always zero unless a dual primary addressing mode (mode 1 or mode 3) is enabled (see Address Mode Register in this chapter). The MJMN bit is cleared by pon or by issuing the Chip Reset auxiliary command.

NAT4882 Programmer Reference Manual 2-26 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Address Mode Register (ADMR)

Access: location 4 (not affected by the page-in auxiliary command or the Page-In pin) Mode: µPD7210 Attributes: Write-Only

76543210

ton lon TRM1 TRM0 0 0 ADM1 ADM0

Bit Mnemonic Description

7w ton Talk-Only bit

Setting ton programs the NAT4882 to become a GPIB Talker. If ton is set, the lon, ADM1, and ADM0 bits should be cleared. Use this method in place of the addressing method when the NAT4882 will be only a Talker.

Note: Clearing ton does not, by itself, take the NAT4882 out of

GPIB Talker Active State (TACS). You must also execute the Chip Reset or Immediate Execute pon auxiliary commands, receive another Talk Address, send the local untalk auxiliary command, or detect the assertion of the GPIB IFC signal to get the NAT4882 to exit TACS.

6w lon Listen-Only bit

Setting lon programs the NAT4882 to become a GPIB Listener. If lon is set, ton, ADM1, and ADM0 should be cleared.

Note: Clearing lon does not, by itself, take the NAT4882 out of

GPIB Listener Active State (LACS). You must also execute the Chip Reset or Immediate Execute pon auxiliary commands, receive an Unlisten command, send the local unlisten auxiliary command while in CACS, send the unlisten auxiliary command, or detect the assertion of the GPIB IFC signal to get the NAT4882 to exit LACS.

NAT4882 Interface Registers Chapter 2

Bit Mnemonic Description

5-4w TRM[1-0] Transmit/Receive Mode bit

TRM1 and TRM0 control the function of the NAT4882 T/R2* and T/R3 output pins in the following manner:

TRM1 TRM0 T/R2* T/R3

0 0 EOIOE* TRIG 0 1 CIC* TRIG 1 0 CIC* EOI OE

1 1 CIC* PE Key EOIOE* = Not GPIB EOI signal output enable

~(TACS + SPAS + CIC & ~(CSBS + CSHS)) CIC* = Not Controller-In-Charge (CIDS + CADS) TRIG = Trigger (pulses when DTAS = 1 or a trigger

auxiliary command is issued) PE = Pull-up Enable (CIC + -(PPAS))

3-2w 0 Reserved bits

Write zeros to these bits.

1-0w ADM[1-0] Address Mode bits 1 through 0

These bits specify the addressing mode that is in effect–that is, the manner in which the information in ADR0 and ADR1 is interpreted (see Address Register 0 and Address Register 1 later in this chapter). If both bits are zero, the NAT4882 does not respond to GPIB address commands; instead, the ton and lon bits are used to program the Talker and Listener functions, respectively. The ton and lon bits must be cleared if mode 1, 2, or 3 addressing is selected, and the ADM[1-0] bits must be cleared if either of the bits ton or lon are set.

Mode ADM1 ADM0 Title

0 0 0 Talk-Only (ton)/Listen-Only (lon) 1 0 1 Normal dual addressing 2 1 0 Extended single addressing 3 1 1 Extended dual addressing

In mode 1, ADR0 and ADR1 contain the major and minor addresses, respectively, for dual primary GPIB address applications–that is, the NAT4882 responds to two GPIB addresses, a major one and a minor one. The MJMN bit in the ADSR indicates which address was received. In applications that

NAT4882 Programmer Reference Manual 2-28 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Bit Mnemonic Description

only require that the NAT4882 respond to one address, the major Talker and Listener function is used and the minor Talker and Listener functions should be disabled. The minor Talker and Listener functions can be disabled by setting the Disable Talker (DT) and Disable Listener (DL) bits in ADR1 (see ADR and ADR1 later in this chapter).

In mode 2 (ADM1 = 1, ADM0 = 0), the NAT4882 recognizes primary and secondary GPIB address bytes. Both GPIB address bytes must be received to enable the NAT4882 to talk or listen. Thus, mode 2 addressing implements the Extended Talker and Extended Listener functions as defined in IEEE 488, without requiring computer program intervention. In mode 2, ADR0 and ADR1 contain the NAT4882 primary and secondary GPIB addresses, respectively.

In mode 3 (ADM1 = 1 and ADM0 = 1), the NAT4882 handles addressing just as it does in mode 1, except that each major or minor GPIB primary address must be followed by a secondary address. All secondary GPIB addresses must be verified by computer program when mode 3 is used. When the NAT4882 is in Talker Primary Addressed State (TPAS) or Listener Primary Addressed State (LPAS) and a secondary address byte is received on the GPIB DIO lines, the APT bit of ISR2 is set and the secondary GPIB address may be inspected in the CPTR. The NAT4882 Acceptor Handshake is held up in the Accept Data State (ACDS) until the Valid or Non-Valid auxiliary command is written to the AUXMR, signaling a valid or invalid secondary address, respectively, to the NAT4882.

ADM0 and ADM1 should both be cleared when either of the two programmable bits ton or lon is set.

NAT4882 Interface Registers Chapter 2

Command Pass Through Register (CPTR)

Access: location 5 (except immediately after the page-in auxiliary command or if the

Page-In pin is asserted)

Mode: µPD7210 Attributes: Read-Only

76543210R

CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0

Bit Mnemonic Description

7-0r CPT[7-0] Command Pass Through bits 7 through 0

These bits transfer undefined multiline GPIB command messages from the GPIB DIO lines to the computer. When the CPT feature is enabled (CPT ENAB = 1, AUXRB[0]w), any GPIB Primary Command Group (PCG) message not decoded by the NAT4882 is treated as an undefined command. Table 2-2 lists the multiline GPIB commands recognized by the µPD7210 chip. All GPIB Secondary Command Group (SCG) messages following an undefined GPIB PCG message are also treated as undefined. In such a case, when an undefined GPIB message is encountered, it is held in the CPTR and the NAT4882 Acceptor Handshake function is held off in ACDS until a Valid or Not Valid auxiliary command is written to the AUXMR. The CPTR is also used to inspect secondary addresses when addressing mode 3 is used. The NAT4882 Acceptor Handshake function is held off in ACDS until the Valid or Non-Valid auxiliary command is written to the AUXMR. Recognized commands that the NAT4882 has been programmed to Holdoff on via AUXRE[3-0] or AUXRF[3-0] may be inspected in the CPTR.

Table 2-2. Multiline GPIB Commands Recognized by the GPIB Chip

in µPD7210 Mode

Hex Number Message Description

01 GTL Go To Local 04 SDC Selected Device Clear 05 PPC* Parallel Poll Configure 08 GET Group Execute Trigger

(continues)

NAT4882 Programmer Reference Manual 2-30 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Bit Mnemonic Description

Table 2-2. Multiline GPIB Commands Recognized by the GPIB Chip

in µPD7210 Mode (continued)

Hex Number Message Description

09 TCT† Take Control 11 LLO Local Lockout 14 DCL Device Clear 15 PPU* Parallel Poll Unconfigure 18 SPE Serial Poll Enable 19 SPD Serial Poll Disable

20-3E MLA My Listen Address

3F UNL Unlisten

40-5E MTA My Talk Address

5F UNT Untalk

60-6F MSA, PPE My Secondary Address or

Parallel Poll Enable

70-7F MSA,

PPD

My Secondary Address or Parallel Poll Disable

† TCT is treated as an undefined command if DISTCT is set. * PPC and PPU are treated as undefined commands if PP2 is

set.

The CPTR is read during a NAT4882-initiated Parallel Poll operation to fetch the Parallel Poll response. When using the local rpp1 message, the PPR message is latched into the CPTR when CPPS is set, and is held valid until either CIDS is set or a command byte is sent over the GPIB. When using the local rpp2 message the PPR message is not latched into the CPTR and must be read before rpp2 is cleared.

NAT4882 Interface Registers Chapter 2

Source/Acceptor Status Register (SASR)

Access: location 5 (immediately after the page-in auxiliary command is issued or if the

Page-In pin is asserted)

Mode: µPD7210 Attributes: Read-Only

76543210R

cdba AEHS ANHS1 ANHS2 ADHS ACRDY SH1A SH1B

The Source/Acceptor Status Register contains status bits that indicate the state of the Source and Acceptor Functions.

Bit Mnemonic Description

7r cdba Command/Data byte available local message 6r AEHS Acceptor End Holdoff State bit 5r ANHS1 Acceptor Not Ready Holdoff State bit 4r ANHS2 Acceptor Not Ready Holdoff Immediately State bit 3r ADHS Acceptor Data Holdoff State bit 2r ACRDY Acceptor Ready State bit

This bit can be used to determine the state of the Acceptor Handshake. By monitoring the LA and ATN bits in ADSR, the DAV bit in the BSR, and the ADHS and ACRDY bits, you can determine the state of the Acceptor Handshake function as described below:

AIDS = ~ATN + ~LA ANRS = ~AIDS & ~ACRDY & ~DAV ACRS = ~AIDS & ACRDY & ~DAV ACDS = ~AIDS & ACRDY & DAV

+ ~AIDS & ~ACRDY & DAV &ATN & ADHS

AWNS = ~AIDS & ~ACRDY & DAV & ~(ATN & ADHS)

NAT4882 Programmer Reference Manual 2-32 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Bit Mnemonic Description

1-0r SH1A Source Handshake State bits

SH1B These bits can be used to determine the state of the source handshake.

By monitoring the TA, SPMS, and ATN bits in the ADSR, and the SH1A and SH1B bits, you can determine the state of the source handshake function as described below:

SIDS = ~(TACS & ~ATN + CIC & ATN) SGNS = ~SIDS & ~SH1A & ~SH1B SDYS = ~SIDS & SH1A STRS = ~SIDS & ~SH1A & SH1B

NAT4882 Interface Registers Chapter 2

Auxiliary Mode Register (AUXMR)

Access: location 5 (not affected by the page-in auxiliary command or the Page-In pin) Mode: µPD7210 Attributes: Write-Only,

Permits Access to Hidden Registers

76543210

CNT2 CNT1 CNT0 COM4 COM3 COM2 COM1 COM0

The AUXMR is used to issue auxiliary commands. It is also used to write the eight hidden registers:

• Parallel Poll Register (PPR)

• Auxiliary Register A (AUXRA)

• Auxiliary Register B (AUXRB)

• Auxiliary Register E (AUXRE)

• Auxiliary Register F (AUXRF)

• Auxiliary Register G (AUXRG)

• Auxiliary Register I (AUXRI)

• Auxiliary Register J (AUXRJ) Table 2-4 shows the implementation of the control and command codes. Note: Commands should be issued at intervals of at least 200 nsec (four clock cycles at

20 MHz).

Bit Mnemonic Description

7-5w CNT[2-0] Control Code bits 2 through 0

These bits specify the control code–that is, the manner in which the information in bits COM[4-0] is to be used. If CNT[2-0] are equal to 000 or 010, the special function selected by COM[4-0] is executed. Otherwise, the hidden register selected by CNT[2-0] and COM[4] is loaded with the data from COM[4-0].

4-0w COM[4-0] Command Code bits 4 through 0

These bits specify the command code of the special function if the control code is 000 or 010. Table 2-3 summarizes the implemented special functions. The special functions can either enable/disable a feature or initiate an action within the NAT4882.

NAT4882 Programmer Reference Manual 2-34 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Bit Mnemonic Description

Table 2-4 explains the details of each special function. If the control code is not 000 or 010, these bits are written to one of the hidden registers, as indicated by the control code in CNT[2-0].

Table 2-3. Auxiliary Command Summary

Control

(CNT2-0)

2 1 0

Function Code* (COM4-COM0)

4 3 2 1 0

Hex

Code**

Auxiliary Command

0 0 0 0 0 0 0 0 00 Immediate Execute power-on (pon) 0 0 0 0 0 0 1 0 02 Chip Reset (chip reset) 0 0 0 0 0 0 1 1 03 Finish Handshake (rhdf) 0 0 0 0 0 1 0 0 04 Trigger (trig) 0 0 0

0 0 0

0 0 1 0 1 0 1 1 0 1

clear or pulse Return to Local set Return to Local (rtl)

0 0 0 0 0 1 1 0 06 Send EOI (seoi)

Non-Valid Secondary Command or

0 0 0 0 0 1 1 1 07

Address (non valid) Valid Secondary Command or

0 0 0 0 1 1 1 1 0F

Address (valid) 0 0 0 0 1 0 0 0 08† Request Control Command (rqc) 0 0 0

0 0 0

0 0 0 0 1 0 1 0 0 1

01 09

Clear Parallel Poll Flag (~ist)

Set Parallel Poll Flag (ist) 0 0 0 0 1 0 1 0 0A† Release Control Command (rlc) 0 0 0 0 1 0 1 1 0B† Untalk Command (lut) 0 0 0 0 1 1 0 0 0C† Unlisten Command (lul) 0 0 0 0 1 1 1 0 0E† New Byte Available False (nbaf) 0 0 0 1 0 0 0 0 10 Go To Standby (gts) 0 0 0

0 0 0 0 0 0

1 0 0 0 1 1 0 0 1 0 1 1 0 1 0

11 12

Take Control Asynchronously (tca)

Take Control Synchronously (tcs)

Take Control Synchronously on

End (tcse) 0 0 0

0 0 0

1 0 0 1 1 1 1 0 1 1

Listen (ltn)

Listen in Continuous Mode (ltn and

cont) 0 0 0

1 1 1 0 0

Local Unlisten (lun)

(continues)

NAT4882 Interface Registers Chapter 2

Table 2-3. Auxiliary Command Summary (continued)

Control

(CNT2-0)

2 1 0

Function Code* (COM4-COM0)

4 3 2 1 0

Hex

Code**

Auxiliary Command

0 0 0 1 0 1 0 0 14 Disable System Control (~rsc) 0 0 0 1 0 1 0 1 15† Switch to 9914A Mode Command 0 0 0

0 0 0 0 0 0

0 0 0

1 1 1 1 0 1 0 1 1 0

1 1 1 1 1 1 0 1 1 1

1 1 0 0 0 1 1 0 0 1

18† 19†

Set IFC (sic & rsc)

Clear IFC (~sic & rsc)

Set REN (sre & rsc)

Clear REN (~sre & rsc)

Request rsv True (reqt)

Request rsv False (reqf) 0 0 0 1 1 1 0 1 1D Execute Parallel Poll (rppl) 0 1 0 1 0 0 0 0 50† Page-In Additional Registers

Holdoff Handshake Immediately 0 1 0 1 0 0 0 1 51†

0 1 0 0 1 0

1 0 0 1 0 1 0 0 1 1

52† 53†

(hldi)

Reserved

Reserved 0 1 0 1 0 1 0 0 54† Clear DET (ISR1[5]r) Command 0 1 0 1 0 1 0 1 55† Clear END (ISR1[4]r) Command 0 1 0 1 0 1 1 0 56† Clear DEC (ISR1[3]r) Command 0 1 0 1 0 1 1 1 57† Clear ERR (ISR1[2]r) Command 0 1 0 1 1 0 0 0 58† Clear SRQI (ISR2[6]r) Command 0 1 0 1 1 0 0 1 59† Clear LOKC (ISR2[2]r) Command 0 1 0 1 1 0 1 0 5A† Clear REMC (ISR2[1]r) Command 0 1 0 1 1 0 1 1 5B† Clear ADSC (ISR2[0]r) Command 0 1 0 1 1 1 0 0 5C† Clear IFCI (ISR0[3]r) Command 0 1 0 1 1 1 0 1 5D† Clear ATNI (ISR0[2]r) Command 0 1 0

0 1 0

1 1 1 1 0 1 1 1 1 1

5E† 5F†

Clear SYNC (ISR0[0]r) Command Set SYNC (ISR0[0]r) Command

* CNT[2-0] set to 000 or 010 binary **Represents all eight bits of the Auxiliary Mode Register † Denotes an auxiliary command not available in a standard µPD7210

NAT4882 Programmer Reference Manual 2-36 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Table 2-4 shows the functions that are executed when the AUXMR Control Code (CNT[2-0]) is loaded with 000 or 010 (binary) and the Command Code (COM[4-0]) is loaded.

Table 2-4. Auxiliary Command Description

Data Pattern

(Hex)

00 Immediate Execute Power-On (pon)

This command generates the local message, pon, that places the following GPIB interface function into their idle states: AIDS Acceptor Idle State CIDS Controller Idle State LIDS Listener Idle State LOCS Local State LPIS Listener Primary Idle State NPRS Negative Poll Response State PPIS Parallel Poll Idle State PUCS Parallel Poll to Unaddressed to Configure State SIDS Source Idle State SIIS System Control Interface Clear Idle State SPIS Serial Poll Idle State SRIS System Control Remote Enable Idle State TIDS Talker Idle State TPIS Talker Primary Idle State

If the command is sent while a pon message is already active (by either an external rest pulse or the Chip Reset auxiliary command, the pon local message becomes false.

Description

02 Chip Reset

The Chip Reset command resets the NAT4882. The NAT 4882 is reset via the chip reset to the following conditions:

• The local pon message is set and the interface functions are placed in their idle states.

• All bits of the SPMR are cleared.

• The EOI bit is cleared.

• All bits of the AUXRA, AUXRB, AUXRE, AUXRF, AUXRG, AUXRI, and AUXRJ are cleared.

• The Parallel Poll Flag and RSC local message are cleared.

• The TRM0 bit and the TRM1 bit are cleared.

The interface functions are held in their idle states until released by an Immediate Execute pon command. Between these commands, the NAT4882 writeable bits can be programmed to their desired states.

03 Finish Handshake (rhdf)

The Finish Handshake command finishes a GPIB Handshake that was stopped because of a Holdoff on RFD condition.

(continues)

NAT4882 Interface Registers Chapter 2

Table 2-4. Auxiliary Command Description (continued)

Data Pattern

(Hex)

04 Trigger (trig)

Trigger command generates a high pulse on the TRIG pin and the T/R3 pin when TRM1 = 0. The Trigger command performs the same function as if the DET (Device Trigger) bit (ISR1[5]r) were set. The DET bit is not set by issuing the Trigger command.

Return To Local (rtl) Return to Local (rtl)

The two Return to Local commands implement the rtl message as defined by IEEE 488. When COM3 is zero, the message is generated in the form of a pulse. If rtl is already set, this command clears it. When COM3 is set, the rtl command is set and remains set until the rtl command is issued with COM3 cleared or a chip reset auxiliary command is issued.

06 Send EOI (seoi)

The Send EOI command causes the GPIB End Or Identify (EOI) line to go true with the next data byte transmitted. The EOI line is cleared upon completion of the Handshake for that byte. The NAT4882 recognizes the Send EOI command only if TACS = 1 (that is, the NAT4882 is the Talker Active State) when NTNL = 0.

Description

07 Non-Valid Secondary Command or Address (non-valid)

The Non-Valid command releases the GPIB DAC message held off by the Address Pass Through (APT) bit. The NAT4882 operates as if an Other Secondary Address (OSA) message has been received. This command also releases a DAC holdoff due to the Command Pass Through (CPT) bit being set.

0F Valid Secondary Command or Address (valid)

The Valid command releases the GPIB DAC message held off by APT and allows the NAT4882 to function as if a My Secondary Address (MSA) message had been received. The Valid command release the DAC holdoff (ADHS) when enabled because of CPT conditions or DCAS or DTAS is in holdoff state.

01 09

Clear Parallel Poll Flag (ist) Set Parallel Poll Flag

These commands set the Parallel Poll Flag equal to the value of COM3. The value of the Parallel Poll Flag is used as the local message ist when AUXRB[4]w = 0. The value of SRQS is used as the ist when ISS = 1. ist is cleared by a chip or hardware reset.

(continues)

NAT4882 Programmer Reference Manual 2-38 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Table 2-4. Auxiliary Command Description (continued)

Data Pattern

Description

(Hex)

10 Go To Standby (gts)

The Go To Standby command sets the local message gts if the NAT4882 is in Controller Active State (CACS). If gts is true, the ATN line is set to false and the Controller enters CSBS. If the NAT4882 leaves CACS, gts is cleared.

11 Take Control Asynchronously (tca)

The Take Control Asynchronously command pulses the local message tca. When this command is issued, the Controller regains control and asserts the ATN line.

12 Take Control Synchronously (tcs)

The Take Control Synchronously command sets the local message tcs. The local message tcs should be issued when the NAT4882 is in Controller Standby State (CSBS). The local message tcs is cleared when the NAT4882 enters CAWS, CIDS or CADS.

1A Take Control Synchronously on END (tsce)

The Take Control Synchronously on END command sets the local message tcs when the data block transfer End message (END bit equal to one) is generated at CSBS. The tcs message is cleared when the NAT4882 enters CAWS, CIDS, or CADS.

13 Listen (ltn)

The listen command generates the local message ltn in the form of a pulse. It should be issued when the Controller is in CACS.

1B Listen in Continuous Mode (ltn & cont)

The Listen in Continuous Mode command generates the local message ltn in the form of a pulse and places the NAT4882 in continuous mode. In continuous mode, the local message rdy is issued when the Acceptor Not Ready State (ANRS) is initiated unless data block transfer end is detected (END RX bit equals one). When END is detected, the NAT4882 is placed in the RFD Holdoff state, preventing generation of the rdy message. In continuous mode, the DI bit is not set when a data byte is received. The continuous mode caused by the Listen in Continuous Mode command is released when the Listen auxiliary command is issued or the NAT4882 enters the Listener Idle State (LIDS).

1C Local Unlisten (lun)

The Local Unlisten command generates the local message lun in the form of a pulse. It should be issued when the Controller is in CACS.

(continues)

NAT4882 Interface Registers Chapter 2

Table 2-4. Auxiliary Command Description (continued)

Data Pattern

(Hex)

1D Execute Parallel Poll (rppl)

The Execute Parallel Poll command sets the local message Request Parallel Poll (rpp1). The rpp message is cleared when the NAT4882 enters either Controller Parallel Poll State (CPPS), Controller Idle State (CIDS), or Controller Addressed State (CADS). The transition of the Controller interface function is not guaranteed if the local messages rpp and Go To Standby (gts) are issued simultaneously when the NAT4882 is in Controller Active State (CACS) and Source Generate State (SGNS).

Set IFC (sic & rsc) Clear IFC (~sic & rsc)

These commands generate the local message Request System Control (rsc) and set the local message Send Interface Clear (sic) equal to the value of COM3. These commands should only be issued if the interface is System Controller. To meet the IEEE 488 requirements, you must not issue the Clear IFC command until IFC has been held true for at least 100 µsec.

Set REN (sre & rsc) Clear REN (~sre & rsc)

Description

These commands generate the local message Request System Control (rsc) and set the local message Send Remote Enable (sre) to the value in COM3. These commands should only be issued if the interface is System Controller. To meet IEEE 488 requirements, you must not issue the Set REN command until REN has been held false for at least 100 µsec.

14 Disable System Control (~rsc)

The Disable System Control command clears the local message rsc.

50† Page-In Additional Registers

The Page-In Additional Registers replaces some of the standard µPD7210 registers with new registers. By using this method, you can implement more read/write registers while staying within the eight byte address space of the µPD7210. Issuing the Page-In Additional Registers auxiliary command replaces the SPSR with the Key Status Register (KSR) and the SPMR with the Key Control Register (KCR) at offset 3, the CPTR with the Source/Acceptor Status Register (SASR) at offset 5, the ACR0/ADR with the ISR0/IMR0 at offset 6, and ADR1/EOSR with the BSR/BCR at offset 7. The new registers remain paged-in until any non-DMA register access is made, after which the standard µPD7210 registers are paged back.

(continues)

NAT4882 Programmer Reference Manual 2-40 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Table 2-4. Auxiliary Command Description (continued)

Data Pattern

(Hex)

51† Immediate Holdoff

This command forces the acceptor handshake function to immediately perform an RFD Holdoff when Listener. Issuing this command forces a transition into ANHS where the handshake is held off until a release handshake holdoff is issued.

52† 53†

Reserved Reserved

These commands are reserved for future use and should not be issued by the control program.

54† Clear DET

This command clears the DET bit (ISR1[5]r). Use this command to clear the DET bit when SISB is set.

55† Clear END

This command clears the END bit (ISR1[4]r). Use this command to clear the END bit when SISB is set.

Description

56† Clear DEC

This command clears the DEC bit (ISR1[3]r). Use this command to clear the DEC bit when SISB is set.

57† Clear ERR

This command clears the ERR bit (ISR1[2]r). Use this command to clear the ER bit when SISB is set.

58† Clear SRQI

This command clears the SRQI bit (ISR2[6]r). Use this command to clear the SRQI bit when SISB is set. If SRQ is still asserted when this command is issued, SRQI clears and then sets after one clock cycle. SRQI continues to be set until SRQ is unasserted and the command is issued. The NAT4882A did not have this feature, and SRQI would remain cleared after issuing the command.

59† Clear LOKC

This command clears the LOKC bit (ISR2[2]r). Use this command to clear the LOKC bit when SISB is set.

5A† Clear REMC

This command clears the REMC bit (ISR2[1]r). Use this command to clear the REMC bit when SISB is set.

(continues)

NAT4882 Interface Registers Chapter 2

Table 2-4. Auxiliary Command Description (continued)

Data Pattern

(Hex)

5B† Clear ADSC

This command clears the ADSC bit (ISR2[0]r). Use this command to clear the ADCS bit when SISB is set.

5C† Clear IFCI

This command clears the IFCI bit (ISR0[3]r). Use this command to clear the IFCI bit when SISB is set.

5D† Clear ATNI

This command clears the ATNI bit (ISR0[2]r). Use this command to clear the ATNI bit when SISB is set.

5E† 5F†

Clear SYNC Set SYNC

These commands are used to control the SYNC function by resetting or starting the function. For more information on the SYNC function, refer to Synchronization Detection in Chapter 3.

15† Switch to 9914A Mode

Description

This command puts the interface chip in 9914A compatibility mode.

08† Request Control (rqc)

This command forces the Controller function to enter CADs, where it will wait for ATN to unassert and then enter CACS

0A† Release Control (rlc)

This command forces the Controller function to unassert ATN and enter CIDS.

0B† Untalk (lut)

This command issues the local unt message forcing the Talker function to enter TIDS.

0C† Unlisten (lul)

This command issues the local unl message forcing the Listener function to enter LIDS.

0E† New Byte Available False (nbaf)

If a Talker is interrupted before the byte just stored in the CDOR is sent over the interface, this byte is transmitted as soon as the ATN line returns to the unasserted state when NTNL is set. If, as a result of the interrupt, this byte is no longer required, you can use the nbaf command to suppress transmission.

(continues)

NAT4882 Programmer Reference Manual 2-42 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Table 2-4. Auxiliary Command Description (continued)

Data Pattern

(Hex)

18† 19†

Description

Request rsv True (reqt) Request rsv False (reqf)

These commands are inputs to the IEEE 488.2 Service Request Synchronization circuitry. These commands are used to set and clear the local message rsv. If STBO IE = 0, the commands reqt and reqf are not issued immediately, but are issued on the write of the SPMR following the issuing of the reqt or reqf auxiliary command. If STBO = IE, the commands reqt and reqf are issued immediately.

NAT4882 Interface Registers Chapter 2

Hidden Registers

The hidden registers are loaded through the Auxiliary Mode Register (AUXMR). AUXMR[7-5] or AUXMR[7-4] is loaded with the hidden register number, and AUXMR[4-0] or AUXMR[3-0] is loaded with the data to be transferred to the hidden register. The hidden registers cannot be read. Figure 2-2 shows the five hidden registers and illustrates how they are loaded with data from the AUXMR. All hidden registers are cleared by a Chip Reset auxiliary command or a hardware reset.

Parallel Poll Register (PPR)

Access: 2-location 5 (not affected by the page-in auxiliary command or the Page-In pin) Mode: µPD7210 Control Code: 011 (Binary, bits 7 - 5) Attributes: Write-Only

Accessed through AUXMR

43210

U S P3 P2 P1

Writing to the Parallel Poll Register (PPR) is done via the AUXMR. Writing the binary value 011 into the Control Code (CNT[2-0]) and writing a bit pattern into the command code portion (COM[4-0]) of the AUXMR causes the command code to be written to the PPR. When COM[4-0] is written to the PPR, the bits are named as shown in the PPR. This 5-bit command code determines the manner in which the NAT4882 responds to a Parallel Poll.

When using the remote Parallel Poll Configure (IEEE 488 capability code PP1), do not write to the PPR. The NAT4882 implements remote configuration fully and automatically without software assistance. The hardware recognizes, interprets, and responds to Parallel Poll Configure (PPC), Parallel Poll Unconfigure (PPU), Parallel Poll Enable (PPE), Parallel Poll Disable (PPD), and Identify (IDY) messages. You need only set or clear the individual status (ist) message (using Set/Clear Parallel Poll Flag auxiliary commands) according to pre-established system protocol convention. Writing to the PPR after it is remotely configured corrupts the configuration.

When using the local PPC (capability code PP2), use a valid PPE or PPD message to write to the PPR in advance of the poll. If PP2 (AUXRI[2]w) is clear, the contents written to the PPR will be overwritten if the Controller sends a Parallel Poll command (such as, PPE or PPD while in PACS or PPU), causing the remote configuration to override the local configuration. If PP2 is set, the reception of Parallel Poll commands does not affect the contents of the PPR and the local configuration determines the response during Parallel Polls.

NAT4882 Programmer Reference Manual 2-44 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Bit Mnemonic Description

4w U Unconfigure bit

The U bit determines whether or not the NAT4882 participates in a Parallel Poll. If U = 0, the NAT4882 participates in Parallel Polls and responds in the manner defined by PPR[3] through PPR[0] and by ist. If U = 1, the NAT4882 does not participate in a Parallel Poll.

The U bit is equivalent to the local message lpe* (Local Poll Enable, active low). When U = 0, S and P[3-1] are the same as the bit of the same name in the PPE message, and the I/O write operation to the PPR is the same as the receipt of the PPE message from the GPIB Controller. When U = 1, S and P[3-1] do not carry any meaning, but they should be cleared.

3w S Status Bit Polarity (Sense) bit

The S bit indicates the polarity, or sense, of the NAT4882 local ist message. If S = 1, the status is in phase, meaning that if, during a Parallel Poll response, S = ist, and U = 0, the NAT4882 responds to the Parallel Poll by driving one of the eight GPIB DIO lines low, thus asserting it to a logic one. If S = 1 and ist = 0, the NAT4882 does not assert the DIO line.

If S = 0, the status is in reverse phase, meaning that if, during a Parallel Poll, ist = 0, and U = 0, the NAT4882 responds to the Parallel Poll by driving one of the eight GPIB DIO lines low. If S = 0 and ist = 1, the NAT4882 does not assert the DIO line. Refer to the description of Auxiliary Register B and Clear Parallel Poll Flags/Set Parallel Poll Flags later in this chapter for more information.

2-0w P[3-1] Parallel Poll Response bits 3 through 1

PPR bits 3 through 1, designated P[3-1], contain an encoded version of the Parallel Poll response. P[3-1] indicate which of the eight DIO lines is asserted during a Parallel Poll (equal to N-1). For example, if P[3-1] = 010 (binary), GPIB DIO line DIO3* is driven low (asserted) if the GPIB chip is parallel polled and S = ist.

NAT4882 Interface Registers Chapter 2

Some examples of configuring the Parallel Poll Register are as follows: Written to the AUXMR

7 6 5 4 3 2 1 0___ Result

0 1 1 1 0 0 0 0 Unconfigures PPR. 0 1 1 0 0 0 0 0 0 0 0 0 0 is written to the PPR. If ist = 0, the GPIB chip participates

in a Parallel Poll asserting the DIO1 line. Otherwise, it does not participate.

0 1 1 0 1 0 0 1 0 1 0 0 1 is written to the PPR. If ist = 1, the GPIB chip participates

in a Parallel Poll asserting the DIO2 line. Otherwise, it does not participate.

NAT4882 Programmer Reference Manual 2-46 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Auxiliary Register A (AUXRA)

Access: location 5 ( not affected by the page-in auxiliary command or the Page-In pin) Mode: µPD7210 Control Code: 100 (Binary, bits 7 - 5) Attributes: Write-Only

Accessed through AUXMR

43210

BIN XEOS REOS HLDE HLDA

Writing to Auxiliary Register A (AUXRA) is done via the AUXMR. Writing the binary value 100 into the Control Code (CNT[2-0]) and a bit pattern into the Command Code (COM[4-0]) portion of the AUXMR causes the Command Code to be written to Auxiliary Register A. When the data is written to AUXRA, the bits are denoted by the mnemonics shown in the figure above. This 5-bit code controls the data transfer messages Holdoff and EOS/END. The AUXRA is cleared by a chip reset or a hardware reset.

Bit Mnemonic Description

4w BIN Binary bit

The BIN bit selects the length of the EOS message. If BIN = 1, the End Of String Register (EOSR) is treated as a full 8-bit byte when the NAT4882 checks the GPIB data for End Of String. If BIN = 0, the EOSR is treated as a 7-bit register (for ASCII characters) and only a 7-bit comparison is done with the data on the GPIB.

3w XEOS Transmit END with EOS bit

The XEOS bit permits or prohibits automatic transmission of the GPIB END message at the same time as the EOS message when the NAT4882 is in Talker Active State (TACS). If XEOS = 1 and the byte in the CDOR matches the contents of the EOSR, the EOI line is sent true along with the data.

2w REOS END on EOS Received bit

The REOS bit permits or prohibits setting the END bit (ISR1[4]r) upon receiving the EOS message when the NAT4882 is in Listener Active State (LACS). If REOS = 1 and the byte in the DIR matches the byte in the EOSR, the END bit (ISR1[4]r) is set and the acceptor function treats the EOS character just as if it were received with EOI asserted.

NAT4882 Interface Registers Chapter 2

Bit Mnemonic Description

1-0w HLDE Holdoff on End bit

HLDA Holdoff on All bit

HLDE and HLDA together determine the GPIB data receiving mode. The four possible modes are as follows:

HLDE HLDA Data Receiving Mode

0 0 Normal Handshake mode 0 1 RFD Holdoff on All Data mode 1 0 RFD Holdoff on END mode 1 1 Continuous mode

In Normal Handshake mode, the local message rdy is generated when data is received from the GPIB. When the received data is read from the DIR, rdy is generated in Acceptor Not Ready State (ANRS), the RFD message is transmitted, and the GPIB Handshake continues.

In RFD Holdoff on All Data (HLDA) mode, RFD is not sent true after data is received until the Finish Handshake auxiliary command is issued. Unlike normal Handshake mode, the RFD HLDA mode does not generate the rdy message even if the received data is read through the DIR–that is, the GPIB RFD message is not generated.

In RFD Holdoff on End mode, operation is the same as the RFD HLDA mode, but only when the end of the data block (EOS or END message) is detected–that is, when the END message is received, or if REOS is set and the EOS character is received, or when NLEE is set and the NL character is received. The Finish Handshake auxiliary command releases Handshake Holdoff.

In continuous mode, the rdy message is generated when in ANRS until the end of the data block is detected. A Holdoff is generated at the end of a data block. The Finish Handshake auxiliary command must be issued to release the Holdoff. The continuous mode is useful for monitoring the data block transfer without actually participating in the transfer (no data reception). In Continuous mode, the DI bit (ISR1[0]r) is not set by receiving a data byte.

NAT4882 Programmer Reference Manual 2-48 © National Instruments Corporation

Chapter 2 NAT4882 Interface Registers

Auxiliary Register B (AUXRB)

Access: location 5 (not affected by the page-in auxiliary command or the Page-In pin) Mode: µPD7210 Control Code: 101 (Binary, bits 7 - 5) Attributes: Write-Only

Accessed through AUXMR

43210

ISS INV TRI SPEOI

CPT

ENABLE

Writing to Auxiliary Register B (AUXRB) is done via the AUXMR. Writing the value 101 into the Control Code (CNT[2-0]) and a bit pattern into the Command Code portion (COM[4-0]) of the AUXMR causes the Command Code to be written to AUXRB. When the data is written to AUXRB, the bits are denoted as shown in the figure above. This 5-bit code affects several interface functions, as described in the following paragraphs. The AUXRB is cleared by a chip reset or a hardware reset.

Bit Mnemonic Description

4w ISS Individual Status Select bit

The ISS bit determines the value of the NAT4882 ist. If ISS = 1, ist takes on the value of the NAT4882 Service Request State (SRQS). (The NAT4882 is asserting the GPIB SRQ message when it is in SRQS.) If ISS = 0, ist takes on the value of the NAT4882 Parallel Poll Flag. The Parallel Poll Flag is set and cleared using the Set Parallel Poll Flag and Clear Parallel Poll Flag auxiliary commands.

3w INV Invert bit

The INV bit affects the polarity of the NAT4882 INT pin. If INV = 1, the polarity of the Interrupt (INT) pin on the NAT4882 is active low.

2w TRI Three-State Timing bit

The TRI bit determines the NAT4882 GPIB Source Handshake Timing, T1. TRI can be set to enable high-speed data transfers (T1 ≥ 500 nsec) when tri-state GPIB drivers are used. Setting TRI enables high-speed timing as T1 of the GPIB Source Handshake after transmission of the first data byte. Clearing TRI sets the low-speed timing (T1 ≥ 2 µsec). The T1 delay can be reduced further by setting the USTD bit (AUXRI[3]w) or MSTD bit .

NAT4882 Interface Registers Chapter 2

Bit Mnemonic Description

1w SPEOI Send Serial Poll EOI bit

The SPEOI bit permits or prohibits the transmission of the END message in Serial Poll Active State (SPAS). If SPEOI = 1, EOI is sent true when the NAT4882 is in SPAS and is sourcing an STB. Otherwise, EOI is sent false in SPAS.

0w CPT ENABLE Command Pass Through Enable bit

The CPT ENABLE bit permits or prohibits the detection of undefined GPIB commands and permits or prohibits the setting of the CPT bit (ISR1[7]r) on receipt of an undefined command. If CPT ENABLE = 1 and an undefined command has been received, the DAC message is held and the Handshake stops until the Valid or Non-valid auxiliary command is issued. The undefined command can be read from the CPTR and processed by the software.

Chapter 2 NAT4882 Interface Registers

Auxiliary Register E (AUXRE)

Access: location 5 (not affected by the page-in auxiliary command or the Page-In pin) Mode: µPD7210 Control Code: 1100 (Binary, bits 7 - 4) Attributes: Write-Only

Accessed through AUXMR

3210

DHADT DHADC DHDT DHDC

Writing to Auxiliary Register E (AUXRE) is done via the AUXMR. Writing the binary value 1100 into the Data Lines 7 through 4 and a bit pattern into the lower four bits of the AUXMR (COM[30]) causes the four lowest order bits to be written to AUXRE. The 4-bit code determines how the NAT4882 uses DAC Holdoff. The AUXRE is cleared by a chip reset or a hardware reset.

Bit Mnemonic Description

3w DHADT DAC Holdoff on GET bit

Setting DHADT enables DAC Holdoff when the acceptor handshake function receives the GET command. When this occurs, the CPT bit in ISR1 is set. Clearing DHADT disables DAC Holdoff on GET. Issuing the Valid or the Non-valid auxiliary command releases the Holdoff. With this feature, you are notified via a CPT interrupt that GET was sent regardless of the status of the Listener function.

2w DHADC DAC Holdoff on DCL or SDC bit

Setting DHADC enables DAC Holdoff when the acceptor handshake function receives the DCL or SDC command. When this occurs the CPT bit in ISR1 is set. Clearing DHADC disables DAC Holdoff on DCL or SDC. Issuing the Valid or the Non-valid auxiliary command releases the Holdoff. With this feature, you are notified via a CPT interrupt that DCL or SDC was sent regardless of the status of the Listener function.

1w DHDT DAC Holdoff on DTAS bit

Setting DHDT enables DAC Holdoff when the NAT4882 enters Device Trigger Active State (DTAS). Clearing DHDT disables DAC Holdoff on DTAS. Issuing the Valid or the Non-valid auxiliary command releases the Holdoff.

NAT4882 Interface Registers Chapter 2

Bit Mnemonic Description

0w DHDC DAC Holdoff on DCAS bit

Setting DHDC enables DAC Holdoff when the NAT4882 enters Device Clear Active State (DCAS). Clearing DHDC disables DAC Holdoff on DCAS. Issuing the Valid or the Non-valid auxiliary command releases the Holdoff.

Chapter 2 NAT4882 Interface Registers

Auxiliary Register F (AUXRF)

Access: location 5 (not affected by the page-in auxiliary command or the Page-In pin) Mode: µPD7210 Control Code: 1101 (Binary, bits 7 - 4) Attributes: Write-Only

Accessed through AUXMR

3210

DHATA DHALA DHUNTLDHALL

Writing to Auxiliary Register F (AUXRF) is done via the AUXMR. Writing the binary value 1101 into the Data Lines 7 through 4 and a bit pattern into the lower four bits of the AUXMR (COM[30]) causes the four lowest order bits to be written to AUXRF. The 4-bit code determines how the NAT4882 uses DAC Holdoff. The AUXRF is cleared by a chip reset or a hardware reset.

Bit Mnemonic Description

3w DHATA DAC Holdoff on All Talker Addresses bit

Setting DHATA enables DAC Holdoff when the Acceptor Handshake function receives any primary Talker Address. When this occurs the CPT bit in ISR1 is set. Clearing DHATA disables DAC Holdoff on primary Talker Addresses. Issuing the Valid or the Non-valid auxiliary command releases the Holdoff. With this feature, you are notified via a CPT interrupt that a primary Talker Address was issued.

2w DHALA DAC Holdoff on All Listener Addresses bit

Setting DHALA enables DAC Holdoff when the Acceptor Handshake function receives any primary Listener Address. When this occurs the CPT bit in ISR1 is set. Clearing DHALA disables DAC Holdoff on primary Listener Addresses. Issuing the Valid or the Non-valid auxiliary command releases the Holdoff. With this feature you are notified via a CPT interrupt that a primary Listener Address was issued.

1w DHUNTL DAC Holdoff on the UNT or UNL Command bit

Setting DHUNTL enables DAC Holdoff when the Acceptor Handshake function receives the UNT or UNL command. When this occurs the CPT bit in ISR1 is set. Clearing DHUNTL disables

NAT4882 Interface Registers Chapter 2

Bit Mnemonic Description

DAC Holdoff on UNT and UNL. Issuing the Valid or the Non-valid auxiliary command releases the Holdoff. With this feature, you are notified via a CPT interrupt that UNT or UNL was issued.

0w DHALL DAC Holdoff on All UCG, ACG, and SCG Commands bit

Setting DHALL enables DAC Holdoff when the Acceptor Handshake function receives any UCG, ACG, or SCG command. When this occurs the CPT bit in ISR1 is set. Clearing DHALL disables DAC Holdoff on any UCG, ACG, or SCG command. Issuing the Valid or the Non-valid auxiliary command releases the Holdoff. With this feature, you are notified via a CPT interrupt that a UCG, ACG, or SCG command was issued.

Chapter 2 NAT4882 Interface Registers

Auxiliary Register G (AUXRG)

Access: location 5 (not affected by the page-in auxiliary command or the Page-In pin) Mode: µPD7210 Control Code: 0100 (Binary, bits 7 - 4) Attributes: Write-Only

Accessed through AUXMR

3210

NTNL RPP2 DISTCT CHES

Writing to Auxiliary Register G (AUXRG) is done via the AUXMR. Writing the binary value 0100 into the Data Lines 7 through 4 and a bit pattern into the lower four bits of the AUXMR (COM[3-0]) causes the four lowest order bits to be written to AUXRG. The AUXRG is cleared by a chip reset or a hardware reset.

Bit Mnemonic Description

3w NTNL No Talking When No Listener bit

Setting this bit prevents the chip from sourcing data (talking) when there is no external Listener, modifies the setting of the ERR bit, modifies the way the nba local message is cleared, and changes the EOI generation function. If NTNL is cleared, the NAT4882 Source Handshake State machine performs the following: the Source NRFD is unasserted; the ERR bit is set on TACS&SDYS&DAC&RFD + SIDS&(write CDOR) + (the transition from SDYS to SIDS if the local message nba is cleared upon entering SIDS or STRS); and the send EOI auxiliary command is ignored or forgotten upon exiting TACS. If NTNL = 1, the Source Handshake function will not make the transition from SDYS to STRS unless there is an external Listener (that is, a device on the GPIB is asserting NDAC); the ERR bit is set when the T1 delay has elapsed and TACS&SDYS&EXTDAC&RFD (where EXTDAC refers to some device on the GPIB asserting NDAC); the local nba is cleared upon entering STRS and ~SPAS; and the send EOI auxiliary command is cleared upon entering SDYS or STRS.

2w RPP2 Request Parallel Poll 2 bit

During the execution of a Parallel Poll via the Execute Parallel Poll auxiliary command, the NAT4882 asserts the GPIB lines ATN and EOI (Controller state CPWS) for approximately 2 µsecs (T6) and then latches the state of the DIO lines into the Command Pass

NAT4882 Interface Registers Chapter 2

Bit Mnemonic Description

Through Register. In some situations, such as with bus extenders, it is desirable to extend the amount of time that ATN and EOI are asserted by extending the time value of T6. Setting the RPP2 bit causes a Parallel Poll to execute which does not terminate until the RPP2 bit is cleared via software.

Using this method, the amount of time that ATN and EOI are asserted is controlled by software and can be any value. The result of the Parallel Poll must be read in the CPTR before RPP2 is cleared.

1w DISTCT Disable Automatic Take Control bit

If DISTCT = 0 and control is passed to the NAT4882 by the Take Control GPIB command (TCT), the NAT4882 automatically becomes Controller-In-Charge. In some applications (such as Talker/Listener only configurations) this feature is undesirable. Setting the DISTCT bit disables the NAT4882's ability to automatically take control when another GPIB Controller-In-Charge passes control. However, even if DISTCT is set, the interface chip can still take control by issuing the Request Control auxiliary command. When DISTCT is set the TCT command is considered undefined.

0w CHES Clear Holdoff on End Select bit

CHES determines how long the NAT4882 remembers that it detected an END condition. IF CHES = 0, the NAT4882 remembers the detection of the END condition until the Release Handshake Holdoff auxiliary command is issued. This command causes the NAT4882 holdoff circuitry to treat every data byte as if it was the END message until the Release Handshake auxiliary command is issued. If CHES is set, the NAT4882 remembers the detection of the END condition until the Release Handshake Holdoff auxiliary command is issued or the DIR is read when in the normal Handshake Holdoff mode (that is, HLDE and HLDA cleared). This setting causes the NAT4882 holdoff circuitry to treat every data byte as it appears, with or without END.

Chapter 2 NAT4882 Interface Registers

Auxiliary Register I (AUXRI)

Access: location 5 (not affected by the page-in auxiliary command or the Page-In pin) Mode: µPD7210 Control Code: 1110 (Binary, bits 7 - 4) Attributes: Write-Only

Accessed through AUXMR

3210

USTD PP2 ACC SISB

Writing to Auxiliary Register I (AUXRI) is done via the AUXMR. Writing the binary value 1110 into the Data Lines 7 through 4 and a bit pattern into the lower four bits of the AUXMR (COM[30]) causes the four lowest order bits to be written to AUXRI. The AUXRI is cleared by a chip reset or a hardware reset.

Bit Mnemonic Description

3w USTD Ultra Short T1 Delay bit

USTD sets the value of the T1 delay used by the Source Handshake function for data setup to 350 nsec for the second and subsequent data bytes sent after ATN unasserts. If this bit is cleared, the value of T1 is determined by the TRI bit (AUXRB[2]w). The bit is overridden by the MSTD in the KCR.

TRI

Bit

UST

D Bit

T1 for first

data & all

commands

002 µsec 2 µsec 0 1 1.1 µsec 1.1 µsec 102 µsec 500 nsec 1 1 1.1 µsec 350 nsec

T1 for the second

and remaining data

2w PP2 Parallel Poll 2 bit

If PP2 = 0, the NAT4882 responds to Parallel Polls in the same

manner as the µPD7210–that is, by supporting Parallel Poll functions PP1

and PP2 at the same time. However, a contradiction arises because PP1 requires the interface to be configured by remote GPIB commands and PP2 requires the interface to be

NAT4882 Interface Registers Chapter 2

Bit Mnemonic Description

configured locally and ignore remote GPIB commands. When PP2 is set, the chip ignores remote GPIB commands (that is, PPC & PPU are treated as undefined commands), thus allowing a true implementation of PP2. Also, by setting PP2 and U (PPR[4]w), the chip supports PP0 (no Parallel Poll response).

1w ACC Automatic Carry Cycle bit

Setting ACC enables automatic carry cycles on GPIB DMA transfers. When this bit is set during GPIB DMA reads, the Acceptor Handshake function performs an RFD Holdoff on the last byte read by the DMA Controller–that is, on the byte in which the T/C signal is pulsed during the read. Issuing the Finish Handshake auxiliary command releases the holdoff. If this bit is set during GPIB DMA writes, the source handshake function issues EOI with the last byte written to the CDOR by the DMA Controller–that is, the byte in which the T/C signal is pulsed when written.

Note: When you use the NAT4882 with the Turbo488, do not set

this bit, because the Turbo488 handles Carry Cycles automatically and the T/C pin is normally grounded.

0w SISB Static Interrupt Status Bits bit

Setting SISB changes the ISR0, ISR1, and ISR2 bits (in µPD7210 mode) from being automatically cleared by reads of the corresponding Interrupt Status register to being static bits that remain set until a certain condition is met. Table 2-5 lists the condition for clearing each interrupt status bit when SISB = 1.

Table 2-5. Clear Conditions for SISB Bit

Bit Clear Condition when SISB = 1

CPT pon + read CPTR APT pon + Valid + Non-Valid DET pon + clearDET

END pon + clearEND

DEC pon +clearDEC ERR pon + clearERR

DO pon + ~TACS +~SGNS +nba

DI pon + (finish handshake) * (Holdoff mode) + read DIR

SRQI pon + clearSRQI

(continues)

Chapter 2 NAT4882 Interface Registers

Table 2-5. Clear Conditions for SISB Bit (continued)

Bit Clear Condition when SISB = 1

CO pon + ~CACS + ~SGNS + nba LOKC pon + clear LOKC REMC pon + clearREMC

ADSC pon + clearADSC + ton +lon

IFCI pon + clearIFCI

ATNI pon + clearATNI

Note: Interrupt Status bits STBO, SYNC, and TO are not affected by the SISB bit.

NAT4882 Interface Registers Chapter 2

Auxiliary Register J (AUXRJ)

Access: location 5 (not affected by the page-in auxiliary command or the Page-In pin) Mode: µPD7210 Control Code: 1111 (Binary, bits 7 - 4) Attributes: Write-Only

Accessed through AUXMR

3210

TM3 TM2 TM1 TM0

Writing to Auxiliary Register J (AUXRJ) is done via the AUXMR. Writing the binary value 1111 into the Data Lines 7 through 4 and a bit pattern into the lower four bits of the AUXMR (COM[30]) causes the four lowest order bits to be written to AUXRJ.

Auxiliary Register J is a four-bit register that sets the timeout value of the Timer interrupt. The timeout value can be set between the range of 10 µsec and 134 sec when the NAT4882 clock is 20 MHz. The Timer starts when the Timer Register is written with a nonzero value and sets the TO bit in ISR0 when the timeout value expires. The Timer is cleared when a zero is written to the Timer Register. For more information on the Timer interrupt capability see Interrupt Status Register 0 later in this chapter. The AUXRJ is reset by a hardware or chip reset.

Bit Mnemonic Description

3-0w TM[3-0] Timer bits 3 through 0

Table 2-6 lists the approximate timeout values supported by Auxiliary Register J at 20 MHz. If the NAT4882 uses another clock frequency, the timeout value can be computed with the following formula: time

factor

= (2

* 5)/frequency

Table 2-6. Timeout Values in µPD7210 Mode

TM3-0 Timeout Value (> or =) Factor

0000 Disable 0001 16 µsec 6 0010 32 µsec 7 0011 128 µsec 9 0100 256 µsec 10

(continues)

Chapter 2 NAT4882 Interface Registers

Bit Mnemonic Description

Table 2-6. Timeout Values in µPD7210 Mode (continued)

TM3-0 Timeout Value (> or =) Factor

0101 1 msec 12 0110 4 msec 14 0111 16 msec 16 1000 33 msec 17 1001 131 msec 19 1010 262 msec 20 1011 1 sec 22 1100 4 sec 24 1101 17 sec 26 1110 34 sec 27 1111 134 sec 29

The Timer supports two different types of timeouts depending on the value of the BTO bit. If BTO is cleared, the Timer operates in global mode. In this mode, the Timer starts upon writing a non-zero value to the Timer Register and continues counting until it reaches the timeout value and sets the TO bit.

If BTO is set, the Timer operates in Byte Timeout mode. In this mode, the Timer starts upon writing a non-zero value to the Timer Register and continues counting until it reaches the timeout value. However, reads of the DIR or writes of the CDOR clear the Timer and force it to start counting over. In Byte Timeout mode, if TO is set, it remains set until the Timer Register is written. Further reads of DIR or writes of CDOR have no effect on TO until the Timer Register is written.

NAT4882 Interface Registers Chapter 2

Address Register 0 (ADR0)

Access: location 6 (except immediately after the page-in auxiliary command is issued or if

the Page-In pin is asserted)

Mode: µPD7210 Attributes: Read-Only

76543210R

X DT0 DL0 AD5-0 AD4-0 AD3-0 AD2-0 AD1-0

Address Register 0 (ADR0) reflects the internal GPIB address status of the NAT4882 as configured using the ADMR. In addressing mode 2, ADR0 indicates the address and enable bits for the primary GPIB address of the NAT4882. In dual primary addressing (Modes 1 and 3) ADR0 indicates the NAT4882 major primary GPIB address. Refer to the description of the Address Mode Register earlier in this chapter for information on addressing modes.

Bit Mnemonic Description

7r X Don't care bit 6r DT0 Disable Talker 0 bit

If DT0 is set, the mode 2 primary (or mode 1 and 3 major) Talker is not enabled, and this register will not be compared with GPIB Talker addresses. If DT0 = 0, the NAT4882 responds to a GPIB talk address matching bits AD[5-0 through 1-0].

5r DL0 Disable Listener 0 bit

If DL0 is set, the mode 2 primary (or mode 1 and 3 major) Listener is not enabled, and this register will not be compared with GPIB Listener addresses. If DL0=0, the NAT4882 responds to a GPIB listen address matching bits AD[5-0 through 1-0].

4-0r AD[5-0 – 1-0] NAT4882 GPIB Address bits 5-0 through 1-0

These are the lower 5 bits of the NAT4882 GPIB primary (or major) address. The primary talk address is formed by adding hex 40 to AD[5-0 through 1-0], while the listen address is formed by adding hex 20.

Chapter 2 NAT4882 Interface Registers

Address Register (ADR)

Access: location 6 (except immediately after the page-in auxiliary command is issued or if

the Page-In pin is asserted)

Mode: µPD7210 Attributes: Write-Only

76543210

ARS DT DL AD5 AD4 AD3 AD2 AD1

The Address Register (ADR) loads the internal registers ADR0 and ADR1. Both ADR0 and ADR1 must be loaded for all addressing modes.

Bit Mnemonic Description

7w ARS Address Register Select bit

If ARS = 1, the seven low-order bits of ADR are loaded into internal register ADR1. If ARS = 0, they are loaded into ADR0.

6w DT Disable Talker bit

DT = 1 disables recognition of the GPIB talk address formed from AD5 through AD1 (ADR[4-0]w).

5w DL Disable Listener bit

DL = 1 disables recognition of the GPIB listen address formed from AD5 through AD1 (ADR[4-0]w).

4-0w AD[5-1] NAT4882 GPIB Address bits 5 through 1

These bits specify the five low-order bits of the GPIB address that is to be recognized by the NAT4882. The corresponding GPIB talk address is formed by adding hex 40 to AD[5-1], while the corresponding GPIB listen address is formed by adding hex 20. The value written to AD[5-1] should not be all ones because the corresponding talk and listen addresses would conflict with the GPIB Untalk (UNT) and GPIB Unlisten (UNL) commands.

NAT4882 Interface Registers Chapter 2

Interrupt Status Register 0 (ISR0)

Access: location 6 (immediately after the page-in auxiliary command is issued or if

the Page-In pin is asserted)

Mode: µPD7210 Attributes: Read-Only

Interrupt Mask Register 0 (IMR0)

Access: location 6 (except immediately after the page-in auxiliary command is issued or if

the Page-In pin is asserted)

Mode: µPD7210 Attributes: Write-Only

76543210R

cdba STBO NL EOS IFCI ATNI TO SYNC

GLINT STBO IE NLEE BTO IFCI IE ATNI IE TO IE SYNC

The Interrupt Status Register 0 (ISR0) consists of five Interrupt Status bits and three Internal Status bits. The Interrupt Mask Register 0 (IMR0) consists of six Interrupt Enable bits and two Internal Control bits. If the Interrupt Enable bit is true when the corresponding status condition or event occurs, an interrupt request is generated. Bits in ISR0 are set and cleared regardless of the status of the bits in IMR2. If a condition occurs that requires the NAT4882 to set or clear an Interrupt Status bit in the ISR0 at the same time the ISR2 is being read, the NAT4882 holds off setting or clearing the bit or bits until the read is finished. A hardware reset clears all bits in IMR0 except GLINT, which is set.

Bit Mnemonic Description

7r cdba Command/Data Byte Available local message bit

This bit reflects the status of the local message Command/Data Byte Available. cdba is set on writes to the CDOR and cleared on entrance to STRS, pon, nbaf or the entrance into SIDS when NTNL = 0.

7w GLINT Global Interrupt Enable bit

GLINT provides a Global Interrupt Enable. If this bit is cleared, the NAT4882 does not generate an Interrupt request regardless of the state of the ISR bits and IMR bits. If this bit is set, the NAT4882 can generate interrupts. A hardware reset sets this bit.

Chapter 2 NAT4882 Interface Registers

Bit Mnemonic Description

6r STBO Status Byte Out bit 6w STBO IE Status Byte Out Interrupt Enable bit

STBO is set if it enters SPAS when STBO IE is set, thus causing an interrupt. The control program writes the current STB to the SPMR which will be transmitted to the GPIB as the STB. Writing the SPMR, clears STBO, which is then set upon entering SPAS during the next serial poll. When STBO IE is set, the rsv bit in the SPMR has no effect on the SR function and rsv must be generated via the reqt auxiliary command.

STBO is set by:

STBO IE & SPAS

STBO is cleared by:

pon + (write SPMR) + ~SPAS

Notes

SPAS: GPIB Serial Poll Active State pon: Power On Reset write SPMR: Write the Serial Poll Mode Register

5r NL New Line Receive bit

NL is set when the NAT4882 accepts the ASCII new line character from the GPIB data bus.

NL is set by:

LACS & NL & ACDS

NL is cleared by:

pon + (LACS & ~NL & ACDS)

Notes

LACS: GPIB Listener Active State NL: seven bit ASCII 'new line' character (hex 0A) ACDS: GPIB Accept Data State pon: Power On Reset

5w NLEE New Line End Enable bit

If NLEE = 1, the NAT4882 treats the seven-bit ASCII new line character (0A hex) as an EOS character. The Acceptor Handshake function responds to the acceptance of a new line character as if EOI was sent.

NAT4882 Interface Registers Chapter 2

Bit Mnemonic Description

4r EOS End-Of-String Character bit

The EOS bit indicates that the END bit in ISR1 was set by the acceptance of the End-Of-String character.

EOS is set by:

LACS & EOS & REOS & ACDS

EOS is cleared by:

pon + (LACS & ~EOS & ACDS) + ~REOS

Notes

LACS: GPIB Listener Active State EOS: GPIB End-Of-String message REOS: End on EOS Received bit, AUXRA[2]w ACDS: GPIB Accept Data State pon: Power On Reset

4w BTO Byte Timeout bit

Setting BTO enables Byte Timeouts. For more information on the function of Byte Timeouts, see Auxiliary Register J earlier in this chapter.

3r IFCI IFC Interrupt bit 3w IFCI IE IFC Interrupt Enable bit

IFCI is set on the assertion of the GPIB IFC* line. IFCI is set by:

(IFC & ~SACS) becomes true

IFCI is cleared by:

pon + (read ISR0) & ~SISB + clearIFCI

Notes

IFC: GPIB Interface Clear Signal SACS: GPIB System Control Active State read ISR0: Read the Interrupt Status Register 0 SISB: Static Interrupt Status Bit, AUXRI[0]w pon: Power On Reset clearIFCI: clearIFCI Auxiliary Command issued

Chapter 2 NAT4882 Interface Registers

Bit Mnemonic Description

2r ATNI ATN Interrupt bit 2w ATNI IE ATN Interrupt Enable bit

ATNI is set on the assertion of the GPIB ATN* line. ATNI is set by:

(ATN) becomes true

ATNI is cleared by:

pon + (read ISR0) & ~SISB + clearATNI

Notes

ATN: GPIB Attention Signal read ISR0: Read the Interrupt Status Register 0 SISB: Static Interrupt Status Bit, AUXRI[0]w pon: Power On Reset clearATNI: clearATNI Auxiliary Command issued

1r TO Time-Out bit 1w TO IE Time-Out Interrupt Enable bit

TO reflects the status of the Timer. Once started, the Timer sets the timeout status bit after the amount of time specified in the Timer Register has elapsed (see Auxiliary Register J). An interrupt is generated when TO IE and TO are set. TO is cleared when the Timer Register is written.

0r SYNC GPIB Synchronization bit 0w SYNC IE GPIB Synchronization Interrupt Enable bit

This bit reflects the status of a GPIB handshake line after a transfer. It is set at the completion of a transfer when the GPIB handshake is complete. An interrupt is generated when SYNC IE and SYNC are set. For more information, refer to the Synchronization Detection section in Chapter 3, NAT4882 Programming Considerations.

NAT4882 Interface Registers Chapter 2

Address Register 1 (ADR1)

Access: location 7 (except immediately after the page-in auxiliary command is issued or if

the Page-In pin is asserted)

Mode: µPD7210 Attributes: Read-Only

76543210R

EOI DT1 DL1 AD5-1 AD4-1 AD3-1 AD2-1 AD1-1

Address Register 1 (ADR1) indicates the status of the GPIB address and enable bits for the secondary address of the NAT4882 if mode 2 addressing is used, or the minor primary address of the NAT4882 if dual primary addressing is used (modes 1 and 3). If mode 1 addressing is used and only a single primary address is needed, both the talk and listen addresses must disable in this register. If mode 2 addressing is used, the talk and listen disable bits in this register must match those in ADR0.

Bit Mnemonic Description

7r EOI End Or Identify bit

EOI indicates the value of the GPIB EOI line latched when a data byte is received by the NAT4882 GPIB Acceptor Handshake (AH) function. If EOI = 1, the EOI line was asserted with the received byte. EOI is cleared by issuing the Chip Reset auxiliary command. EOI is updated after each byte is received.

6r DT1 Disable Talker 1 bit

If DT1 is set, the mode 2 secondary (or mode 1 and 3 minor) Talker function is not enabled–that is, the GPIB secondary address (or minor primary talk address) is not compared with this register. If DT1 is cleared, and the NAT4882 received its primary talk address (that is, in TPAS), the secondary address is checked when in mode 2. In mode 1 or 3, the minor talk address is checked.

5r DL1 Disable Listener 1 bit

If DL1 is set, the mode 2 secondary (or mode 1 and 3 minor) Listener function is not enabled–that is, the GPIB secondary address (or minor primary listen address) is not compared with this register. If DL1 is cleared, and the NAT4882 received its primary listen address (that is, in LPAS), the secondary address is checked when in mode 2. In mode 1 or 3, the minor listen address is checked.

Chapter 2 NAT4882 Interface Registers

Bit Mnemonic Description

4-0r AD[5-1 – 1-1] NAT4882 GPIB Address bits 5-1 through 1-1

These are the lower five bits of the NAT4882 secondary or minor address. The secondary address is formed by adding hex 60 to bits AD[5-1 through 1-1]. The minor talk address is formed by adding hex 40 to AD[5-1 through 1-1], while the listen address is formed by adding hex 20.

NAT4882 Interface Registers Chapter 2

End Of String Register (EOSR)

Access: location 7 (except immediately after the page-in auxiliary command is issued or if

the Page-In pin is asserted)

Mode: µPD7210 Attributes: Write-Only

76543210

EOS7 EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOS0

The End Of String Register (EOSR) holds the byte that the NAT4882 uses to detect the end of a GPIB data block transfer. You can place a seven- or eight-bit byte (ASCII or binary) in the EOSR to be used in detecting the end of a block of data. The length of the EOS byte to be used in the comparison is selected by the BIN bit in Auxiliary Register A, AUXRA[4]w.

If the NAT4882 is a Listener and bit REOS of AUXRA is set, the END bit is set in ISR1 whenever the byte in the DIR matches the EOSR. If the NAT4882 is a Talker and bit XEOS of AUXRA is set, the END message (GPIB EOI* line asserted low) is sent along with the data byte whenever the contents of the CDOR matches the EOSR.

Bit Mnemonic Description

7-0w EOS[7-0] End of String bits 7 through 0

Chapter 2 NAT4882 Interface Registers

Bus Status Register (BSR)

Access: location 7 (immediately after the page-in auxiliary command is issued or if

the Page-In Pin is asserted)

Mode: µPD7210 Attributes: Read-Only

Bus Control Register (BCR)

Access: location 7 (immediately after the page-in auxiliary command is issued or if

the Page-In Pin is asserted)

Mode: µPD7210 Attributes: Write-Only Reads of the Bus Status Register (BSR) return the status of the GPIB control lines at the time of the

read. Writing a one to a bit in the Bus Control Register (BCR) asserts the corresponding GPIB control lines. The order of bits in the BCR and BSR are shown below:

76543210

ATN_S DAV_S NDAC_S NRFD_S EOI_S SRQ_S IFC_S REN_S

ATN_C DAV_C NDAC_C NRFD_

EOI_C SRQ_C IFC_C REN_C

Because the chip is either transmitting or receiving a GPIB control line at any particular time, and not doing both simultaneously, setting a bit in the BCR may not automatically assert the corresponding line on the GPIB. If the chip is transmitting a GPIB line when the corresponding bit in the BCR is set, the chip asserts the GPIB line. If the chip is receiving a GPIB line when the corresponding bit in the BCR is set, the GPIB line is not asserted. However, in both these cases, the GPIB signal internal to the interface chip is logically ORed with the value of the BCR bit. Figure 23 illustrates the GPIB input/output hardware configuration.

NAT4882 Interface Registers Chapter 2

Transmit Enable

GPIB Line Out BCR Bit

NDAC

NRFD

SRQ

GPIB Line In

eliminates glitches in

REN & IFC

Figure 2-3. GPIB I/O Hardware Configuration for µPD7210 Mode

Transmit Enable represents the internal signal that is true when the chip is driving a particular GPIB control line. GPIB Line Out represents the internal signal that is true when an interface function within the chip is attempting to assert a GPIB control signal. BCR bit corresponds to the bit in the Bus Control register. GPIB Line In represents the internal GPIB lines that are inputs to the GPIB interface functions and the Bus Status register. The internal signals SRQ, NDAC, and NRFD are monitored by the interface functions even when they are not driven onto the pin. For this reason, the internal value of these signals is ORed with the external value.

Bit Mnemonic Description

7r ATN_S GPIB Attention Status bit 7w ATN_C GPIB Attention Control bit

6r DAV_S GPIB Data Valid Status bit 6w DAV_C GPIB Data Valid Control bit

5r NDAC_S GPIB Not Data Accepted Status bit 5w NDAC_C GPIB Not Data Accepted Control bit

4r NRFD_S GPIB Not Ready For Data Status bit 4w NRFD_C GPIB Not Ready For Data Control bit

3r EOI_S GPIB End or Identify Status bit 3w EOI_C GPIB End or Identify Control bit

2r SRQ_S GPIB Service Request Status bit 2w SRQ_C GPIB Service Request Control bit

1r IFC_S GPIB Interface Clear Status bit 1w IFC_C GPIB Interface Clear Control bit

0r REN_S GPIB Remote Enable Status bit 0w REN_C GPIB Remote Enable Control bit

Chapter 2 NAT4882 Interface Registers

Because the BSR samples the GPIB control lines from the GPIB transceiver and not the actual GPIB bus, the validity of each bit is determined by the direction of each line. Generally, when a signal is an input, its true bus status is reflected in the BSR, while an output signal only reflects the NAT4882 value of that particular line. Under normal GPIB operation, this function should not be too limiting, because the lines that are typically monitored are valid when they are monitored. For example, the SRQ line is valid in the BSR when the NAT4882 is CIC, which is also when the SRQ line will be monitored.

NAT4882 Interface Registers Chapter 2

9914 Mode Registers

The 9914 mode register group consists of 26 registers available when the NAT4882 is in 9914A mode. This set of registers is a compatible superset of those found in the Texas Instruments TMS9914A.

Figure 2-4 shows the register map for the NAT4882 in 9914 mode, and Figure 2-5 shows the 9914 hidden registers. The leftmost column of each register map gives the name of each register in mnemonic form. Following the register names is the register offset, and then a block showing the bits of all of the registers at that offset. On the rightmost column of each register, the map tells whether that register is a read-only or a write-only register. In the cases where there is more than one register at the same offset, the register with the white bitmap normally responds at that offset, and the shaded register responds only after it has been paged-in. In the 9914A mode, all of the shaded registers are at the same offset and there is a separate page-in command for each one. The registers remain paged in until another page-in command is issued or a chip reset occurs.

Key = 9914 Mode Paged Registers

R = Read Register W = Write Register

ISR0 IMR0

ISR1 IMR1

ADSR IMR2 EOSR BCR ACCR

BSR AUXCR

ISR2 ADR

SPSR SPMR

CPTR PPR

7 6 5 4 3 2 1 0

INT0

DMAO

GET

GET IE

REM

GLINT

EOS7

ATN C

CNT2

ATN S

cdba edpa

S8 S8

CPT7

PP8

INT1

DMAI

ERR

ERR IE

LLO

STBO IE

EOS6

DAV C

CNT1

DAV S

STBO

dal

PEND

rsv/RQS

CPT6

PP7

BI IE

UNC

UNC IE

ATN

NLEE

EOS5

NDAC C

CNT0

NDAC S

NL dat

S6 S6

CPT5

PP6

BO IE

APT

APT IE

LPAS

BTO

EOS4

NRFD C

COM4

NRFD S

EOS

S5 S5

CPT4

PP5

END

END IE

DCAS

DCAS IE

TPAS

LLOC IE

EOS3 EOI C COM3

EOI S

LLOC

S4 S4

CPT3

PP4

SPAS

SPAS IE

MA IE

ATNI IE

EOS2

SRQ C

COM2

SRQ S

ATNI

S3 S3

CPT2

PP3

RLC

RLC IE

SRQ

SRQ IE

TO IE

EOS1 IFC C COM1

IFC S

S2 S2

CPT1

PP2

MAC

MAC IE

IFC

IFC IE

ulpa

CIC IE

EOS0

REN C

COM0

REN S

CIC

CPT0

PP1

S1 S1

R W W W W

R W

DIR DOR

DI7

DO7

DI6

DO6

DI5

DO5

DI4

DO4

DI3

DO3

DI2

DO2

DI1

DO1

DI0

DO0

R W

Figure 2-4. 9914 Mode Interface Registers

Chapter 2 NAT4882 Interface Registers

Key W = Write Register

7 6 5 4 3 2 1 0

ACCR CNT2 CNT1 CNT0 COM4 COM3 COM2 COM1 COM0

ACCRA 1 0 0 BIN XEOS REOS 0 0

ACCRB 1 0 1 ISS INV LWC SPEOI ATCT

ACCRE 1 1 0 0 DHADT DHADC 0 0

ACCRF 1 1 0 1 DHATA DHALA DHUNTL DHALL

ACCRI 1 1 1 0 USTD PP1 ACC DMAEN

ACCRJ 1 1 1 1 TM3 TM2 TM1 TM0

Figure 2-5. 9914 Mode Hidden Registers

NAT4882 Interface Registers Chapter 2

Interrupt Status Register 0 (ISR0)

Access: location 0 (if Swap* is unasserted) or location 6 (if Swap* is asserted)

(not affected by a page-in auxiliary command) Mode: TMS9914A Attributes: Read-Only

Bits are cleared when read

Interrupt Mask Register 0 (IMR0)

Access: location 0 (if Swap* is unasserted) or location 6 (if Swap* is asserted)

(not affected by a page-in auxiliary command) Mode: TMS9914A Attributes: Write-Only

76543210R

INT0 INT1 BI BO END SPAS RLC MAC

DMAO DMAI BI IE BO IE END IE SPAS IE RLC IE MAC IE

The Interrupt Status Register 1 (ISR1) is composed of eight Interrupt Status bits. The Interrupt Mask Register 1 (IMR1) is composed of six Interrupt Enable bits that directly correspond to the Interrupt Status bits in ISR1. As a result, ISR1 and IMR1 service six possible interrupt conditions, where each condition has an Interrupt Status bit and an Interrupt Enable bit associated with it. If the Interrupt Enable bit is true when the corresponding status condition or event occurs, a hardware interrupt request is generated. Bits in ISR1 are set and cleared by the NAT4882 regardless of the status of the Interrupt bits in IMR1. If an interrupt condition occurs at the same time ISR1 is being read, the NAT4882 holds off setting the corresponding Status bit until the read has finished.

Bit Mnemonic Description

7r INT0 Interrupt Register 0 Interrupt bit

INT0 is set when an unmasked status bit in Interrupt Status Register 0 is set to a 1.

7w DMAO DMA Output Enable bit

If DMAEN = 0, this bit has no meaning. If DMAEN = 1, setting DMAO enables the NAT4882 to assert the DRQ line when TACS & SGNS & ~cdba. Once asserted, the NAT4882 keeps the DRQ pin asserted until ~[TACS & SGNS & ~cdba].

Chapter 2 NAT4882 Interface Registers

Bit Mnemonic Description

6r INT1 Interrupt Register 1 Interrupt bit

INT1 is set when an unmasked status bit in Interrupt Status Register 1 is set.

6w DMAI DMA Input Enable bit

If DMAEN = 0, this bit has no meaning. If DMAEN = 1, setting DMAI enables the NAT4882 to assert the DRQ line when LACS & ACDS & ~shadow handshaking. Once asserted, the NAT4882 keeps the DRQ pin asserted until the DIR is read.

5r BI Byte In bit 5w BI IE Byte In Interrupt Enable bit

The BI bit indicates that a data byte has been received in the Data In Register. An RFD Holdoff must occur before the next data byte can be accepted. BI is cleared by reading the DIR or reading ISR0. BI is not set if shadow handshaking is on.

BI is set by:

LACS & ACDS & ~shadow handshaking

BI is cleared by:

swrst + (read ISR0) + (read DIR)

Notes

swrst: software reset Auxiliary Command issued LACS: GPIB Listener Active State ACDS: GPIB Accept Data State shadow handshaking: Shadow Handshaking enabled read ISR0: Read the Interrupt Status Register 0 read DIR: Read the Data In Register

4r BO Byte Out bit 4w BO IE Byte Out Interrupt Enable bit

The BO bit indicates that the Data Out Register is available to send a byte over the GPIB. This byte can be either a command if the device is a Controller or data if the device is a Talker. It is set when the device becomes Active Talker or Controller, but will not occur if the DOR has been loaded with a byte that has not been sent (that is, cdba is true). BO sets again after each byte has been sent and the source handshake returns to SGNS. BO is cleared by writing the DOR or reading ISR0.

NAT4882 Interface Registers Chapter 2

Bit Mnemonic Description

BO is set by:

CACS & SGNS & ~cdba + TACS & SGNS & ~cdba

BO is cleared by:

swrst + (read ISR0) + (write DOR)

Notes

swrst: software reset Auxiliary Command issued TACS: GPIB Talker Active State CACS: GPIB Controller Active State SGNS: GPIB Source Generate State cdba: Command/Data Byte Available local message read ISR0: Read the Interrupt Status Register 0 write DOR: Write the Data Out Register

3r END End Received bit 3w END IE End Received Interrupt Enable bit

The END bit is set either when the NAT4882 is a Listener and the GPIB uniline message, END, is received with a data byte from the GPIB Talker, when the data byte in the DIR matches the contents of the End Of String Register (EOSR) and REOS is set, or when the data byte in the DIR matches the ASCII new line character (hex 0A) and NLEE is set. END is always set before the BI bit is set to indicate that the data byte with END was received.

END is set by:

LACS & (EOI + EOS & REOS + NL & NLEE) & ACDS

END is cleared by:

swrst + (read ISR0)

Notes

swrst: software reset Auxiliary Command issued LACS: GPIB Listener Active State EOI: GPIB End Of Identify Signal EOS: GPIB END Of String message NL: ASCII 'new line' message (hex 0A) ACDS: GPIB Accept Data State read ISR0: Read the Interrupt Status Register 0 REOS: END on EOS Received bit, AUXRA[2]w NLEE: New Line End Enable, IMR0[5]w

Chapter 2 NAT4882 Interface Registers

Bit Mnemonic Description

2r SPAS Serial Poll Active State bit 2w SPAS IE Serial Poll Active State Interrupt Enable bit

The SPAS bit indicates that the NAT4882 has requested service and has been serial polled. It is set on the false transition of STRS when the serial poll status byte is sent.

SPAS is set by:

[STRS & SPAS & APRS] becoming false

SPAS is cleared by:

swrst + (read ISR0)

Notes

swrst: software reset Auxiliary Command issued STRS: GPIB Source Transfer State SPAS: GPIB Serial Poll Active State APRS: GPIB Affirmative Poll Response State read ISR0: Read the Interrupt Status Register 0

1r RLC Remote/Local Change bit 1w RLC IE Remote/Local Change Interrupt Enable bit

RLC is set on any change in the REM bit, ADSR[7]r. RLC is set by:

LOCS -> REMS + REMS -> LOCS + LWLS -> RWLS + RWLS -> LWLS

RLC is cleared by:

swrst + (read ISR0)

Notes

swrst: software reset Auxiliary Command issued LOCS: GPIB Local State REMS: GPIB Remote State LWLS: GPIB Local with Lockout State RWLS: GPIB Remote with Lockout State read ISR0: Read the Interrupt Status Register 0

NAT4882 Interface Registers Chapter 2

Bit Mnemonic Description

0r MAC My Address Change bit 0w MAC IE My Address Change Interrupt Enable bit

The MAC bit indicates that a command has been received from the GPIB that has changed the addressed state of the NAT4882. It does not occur if secondary addressing is being used, nor does it indicate that the NAT4882 has been readdressed on its other primary address.

MAC is set by:

ACDS & (MTA & ~TADS & ~APTIE+ OTA & TADS + MLA & ~LADS & ~APTIE + UNL & LADS)

MAC is cleared by:

swrst + (read ISR0)

Notes

swrst: software reset Auxiliary Command issued ACDS: GPIB Accept Data State MTA: GPIB My Talk Address TADS: GPIB Talker Active State OTA: GPIB Other Talk Address MLA: GPIB My Listen Address LADS: GPIB Listen Active State UNL: GPIB Unlisten Message read ISR0: Read the Interrupt Status Register 0

National Instruments NAT4882 NAT4882 Programmer Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

National Instruments Corporate Headquarters

Limited Warranty

Copyright

Trademarks

Contents

Figures

Tables

About This Manual

Organization of This Manual

Conventions Used in This Manual

Related Documents

Customer Communication

Chapter 1 Introduction and General Description

NAT4882 Features

NAT4882 Functional Description

Figure 1-1. NAT4882 Implementation Block Diagram

Figure 1-2. NAT4882 Block Diagram

GPIB Capabilities

Table 1-1. NAT4882 IEEE 488 Interface Capabilities

Interrupt Capabilities

7210 Mode Interrupts

9914 Mode Interrupts

Addressing Schemes

Chapter 2 NAT4882 Interface Registers

Register Description Format

Table 2-1. Clues to Understanding Mnemonics

7210 Mode Registers

Figure 2-1. 7210 Mode Register Map

Figure 2-2. 7210 Mode Hidden Registers

Data In Register (DIR)

Command/Data Out Register (CDOR)

Interrupt Status Register 1 (ISR1)

Interrupt Mask Register 1 (IMR1)

Interrupt Status Register 2 (ISR2)

Interrupt Mask Register 2 (IMR2)

Serial Poll Status Register (SPSR)

Serial Poll Mode Register (SPMR)

Key Status Register (KSR)

Key Control Register (KCR)

Address Status Register (ADSR)

Address Mode Register (ADMR)

Command Pass Through Register (CPTR)

Table 2-2. Multiline GPIB Commands Recognized by the GPIB Chip

Source/Acceptor Status Register (SASR)

Auxiliary Mode Register (AUXMR)

Table 2-3. Auxiliary Command Summary

Table 2-4. Auxiliary Command Description

Hidden Registers

Parallel Poll Register (PPR)

Auxiliary Register A (AUXRA)

Auxiliary Register B (AUXRB)

Auxiliary Register E (AUXRE)

Auxiliary Register F (AUXRF)

Auxiliary Register G (AUXRG)

Auxiliary Register I (AUXRI)

Table 2-5. Clear Conditions for SISB Bit

Auxiliary Register J (AUXRJ)

Address Register 0 (ADR0)

Address Register (ADR)

Interrupt Status Register 0 (ISR0)

Interrupt Mask Register 0 (IMR0)

Address Register 1 (ADR1)

End Of String Register (EOSR)

Bus Status Register (BSR)

Bus Control Register (BCR)

9914 Mode Registers

Figure 2-4. 9914 Mode Interface Registers

Figure 2-5. 9914 Mode Hidden Registers

Interrupt Status Register 0 (ISR0)

Interrupt Mask Register 0 (IMR0)