National Instruments LAB-PC-1200 Programming Manual

DAQ

Lab-PC-1200/AI
Register-Level Programmer Manual

Multifunction I/O Board for AT Bus Computers

Lab-PC-1200/AI RLPM

December 1997 Edition

Part Number 341309A-01

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© Copyright 1997 National Instruments Corporation. All rights reserved.

Important Information

Warranty

The Lab-PC-1200/AI is warranted against defects in materials and workmanship for a period of one year from the date
of shipment, as evidenced by receipts or other documentation. National Instruments will, at its opti on, repair or replace
equipment that proves to be defective during the warranty period. This warranty includes parts and labor.

The media on which you receive National Instrum ent s soft ware are warranted not to fai l to execut e pro gramm ing
instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as evidenced
by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do not
execute programming instructions if National Instrument s receives no tice of s uch defects d uring th e warranty p e riod.
National Instruments does not warrant that the operat ion o f t he soft ware shall be unint errupt ed or error free.

A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside
of the package before any equipment wil l be accepted for warranty work. National Instrume nts will pay the shipping costs
of returning to the owner parts which are covered by warranty.

National Instruments believes that the information in this manual is accurate. The doc ument has been carefully reviewed
for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to
make changes to subsequent editions of this do cu me nt with out p rio r no ti ce to ho ld ers o f t his ed itio n. The read er sh oul d
consult National Instruments if errors are suspected. In no event shal l N ati onal In strum ent s b e liabl e for any dama ges
arising out of or related to this docume nt or th e in form ation con tained in it .

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Product and company names listed are trademarks or trade names of their respective companies.

WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS

National Instruments products are not designed with com po nents and testing in ten ded to ensu re a le vel of reliab ilit y
suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involvin g med ical
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to be a substitute for any form of established process, procedure, or equipment used to monitor or safeguard human health
and safety in medical or clinical treatment.

Contents

About This Manual

Organization of This Manual...........................................................................................ix

Conventions Used in This Manual...................................................................................x

National Instruments Documentation..............................................................................xi

Related Documentation.......................................... ..........................................................xii

Customer Communication...............................................................................................xii

Chapter 1
General Description

General Characteristics....................................................................................................1-1

Board Configuration Overview .......................................................................................1-2

Analog Input Configuration ..............................................................................1-2

Analog Output Configuration (Lab-PC-1200 Only) .........................................1-2

Digital I/O Configuration..................................................................................1-3

Counter Configuration.......................................................................................1-3

Chapter 2
Register Map and Descriptions

Register Map....................................................................................................................2-1

Register Description Overview........................................................................................2-3

Configuration and Status Register Group..........................................................2-4

Command Register 1................................................... ........................2-5

Command Register 2................................................... ........................2-7

Command Register 3................................................... ........................2-9

Command Register 4................................................... ........................2-11

Command Register 5................................................... ........................2-13

Command Register 6................................................... ........................2-15

Status Register 1..................................................................................2-17

Status Register 2..................................................................................2-19

Analog Input Register Group ............................................................................2-20

A/D FIFO Register..............................................................................2-21

A/D FIFO Clear Register....................................................................2-23

Start Convert Register.........................................................................2-23

DMATC Interrupt Clear Register.......................................................2-23

Analog Output Register Group (Lab-PC-1200 Only).......................................2-24

DAC0 Low-Byte, DAC0 High-Byte, DAC1 Low-Byte, and

DAC1 High-Byte Registers..............................................................2-25

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National Instruments Corporation v Lab-PC-1200/AI RLPM

Contents

Chapter 3
Programming

Register Programming Considerations............................................................................3-1

Programming Examples .......................................................... .................................. ......3-1

Initializing the Lab-PC-1200/AI Circuitry...................................................................... 3-3

Programming the Analog Input Circuitry for Single A/D Conversions.......................... 3-4

Programming a DAQ Operation Using Internal Timing.................................................3-8

Programming a DAQ Operation Using External Timing................................................3-13

DAQ Interrupt Programming .......................................................................................... 3-16

82C53 Counter/Timer Register Groups A and B..............................................2-26

Counter A0 Data Register...................................................................2-27

Counter A1 Data Register...................................................................2-27

Counter A2 Data Register...................................................................2-28

Counter A Mode Register...................................................................2-28

Timer Interrupt Clear Register ...........................................................2-29

Counter B0 Data Register...................................................................2-29

Counter B1 Data Register...................................................................2-30

Counter B2 Data Register...................................................................2-30

Counter B Mode Register...................................................................2-31

82C55A Digital I/O Register Group.................................................................2-32

Port A Register ...................................................................................2-33

Port B Register....................................................................................2-33

Port C Register....................................................................................2-34

Digital Control Register......................................................................2-34

Interval Counter Register Group.......................................................................2-35

Interval Counter Data Register........................................................... 2-36

Interval Counter Strobe Register ........................................................ 2-36

Lab-PC-1200/AI Companion Disk ........................................................... ........3-2

Assigning Lab-PC-1200/AI Resources.............................................................3-2

Clearing the Analog Input Circuitry .................................................................3-4

Configuring the Analog Input Circuitry............................................................3-5

Performing Single A/D Conversions ................................................................3-7

Programming Counter A0 and Counter B0....................................................... 3-10

Programming Counter A1................................................................................. 3-11

Programming Counter B1 and the Interval Counter Register........................... 3-11

Triggering the DAQ Operation.........................................................................3-12

Servicing the DAQ Operation ...........................................................................3-12

Programming a DAQ Operation Using EXTCONV*.......................................3-14

Programming a DAQ Operation Using EXTTRIG in Posttrigger Mode..........3-14

Programming a DAQ Operation Using EXTTRIG in Pretrigger Mode........... 3-15

Programming a DAQ Operation Using OUTB1...............................................3-15

Lab-PC-1200/AI RLPM vi

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National Instruments Corporation

DAQ DMA Programming ...............................................................................................3-17

Programming the Analog Output Circuitry (Lab-PC-1200 Only)...................................3-17

Programming the Digital I/O Circuitry............................................................................3-20

Programming the General-Purpose Counter/Timers .......................................................3-21

Chapter 4
Calibration

Storing User-Defined Constants......................................................................................4-1

Calibration DACs ............................................................................................................4-3

Analog Input Calibration .................................................................................................4-4

Analog Output Calibration (Lab-PC-1200 Only)............................................................4-8

Contents

Configuring the Analog Output Circuitry .........................................................3-17

Programming the Update Mode of the Analog Output Circuitry......................3-18

DAC Interrupt Programming.............................................................................3-20

Bipolar Input Calibration Procedure .................................................................4-5

Pregain Offset Coarse Calibration ......................................................4-5

Pregain Offset Fine Calibration ..........................................................4-5

Gain Calibration............................................ .................................. ....4-6

Postgain Offset Calibration.................................................................4-6

Calibration at Higher Gains ................................................................ 4-6

Unipolar Input Calibration Procedure...............................................................4-6

Pregain Offset Calibration ..................................... .............................4-7

Gain Calibration............................................ .................................. ....4-7

Postgain Offset Calibration.................................................................4-7

Bipolar Output Calibration Procedure...............................................................4-8

Gain Calibration............................................ ... .................................. .4-9

Offset Calibration................................................................................4-9

Unipolar Output Calibration Procedure.............................................................4-9

Gain Calibration............................................ ... .................................. .4-10

Offset Calibration................................................................................4-10

EEPROM Map...................................................................................................4-10

Appendix A
Fujitsu MB88341/MB88342 Data Sheet

Appendix B
Xicor X25020 Data Sheet

Appendix C
OKI MSM82C53 Data Sheet

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National Instruments Corporation vii Lab-PC-1200/AI RLPM

Contents

Appendix D
OKI MSM82C55A Data Sheet

Appendix E
Customer Communication

Glossary

Index

Tables

Table 1-1. Analog Input Settings .............................................................................1-2

Table 1-2. Analog Output Settings...........................................................................1-2

Table 2-1. Lab-PC-1200/AI Register Map ...............................................................2-2

Table 3-1. Lab-PC-1200/AI Allowable Resources ..................................................3-2

Table 3-2. Analog Output Voltage Versus Digital Code

(Unipolar Mode, Straight Binary Coding)..............................................3-18

Table 3-3. Analog Output Voltage Versus Digital Code

(Bipolar Mode, Two’s Complement Coding).........................................3-18

Table 4-1. Calibration DAC Characteristics for Analog Input Circuitry................. 4-3

Table 4-2. Calibration DAC Characteristics for Analog Output Circuitry .............. 4-3

Table 4-3. Lab-PC-1200/AI EEPROM Map............................................................4-11

Lab-PC-1200/AI RLPM viii

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National Instruments Corporation

About This Manual

This manual contains information about the internal operation and
programming of the Lab-PC-1200/AI. The Lab-PC-1200 and
Lab-PC-1200AI boards are low-cost multifunction analog, digital, and
timing boards. The Lab-PC-1200/AI is a member of the National
Instruments AT Series of expansion boards for AT/ISA bus computers.
Additionally, the Lab-PC-1200 has two 12-bit DACs with voltage outputs.
These boards are designed for high-performance data acquisition (DAQ)
and control for applications in laboratory testing, production testing, and
industrial process monitoring and control.

This manual assumes you are familiar with the Lab-PC-1200/AI User
Manual. If you will be using National Instruments software with the
Lab-PC-1200/AI, you do not need to read this manual. For information on
the Lab-PC-1200/AI installation, signal connections, and theory of
operation, consult your user manual.

Organization of This Manual

The Lab-PC-1200/AI Register-Level Programmer Manual is organized as
follows:

• Chapter 1, General Description, describes the general characteristics
and gives a configuration overview of the Lab-PC-1200/AI.

• Chapter 2, Register Map and Descriptions, describes in detail th e
address and function of each of the Lab-PC-1200/AI registers.

• Chapter 3, Programming, contains programming instructions for
operating the Lab-PC-1200/AI circuitry, and examples of the
programming steps necessary to execute an operation.

• Chapter 4, Calibration, contains instructions for creating user-defined
calibration constants for the Lab-PC-1200/AI CALDACs.

• Appendix A, Fujitsu MB88341 /MB8834 2 Data Sheet, contains the
manufacturer data sheet for the MB88341/MB88342 R-2R type 8-bit
D/A converter manufactured by Fujitsu Microelectronics, Inc. The
MB88341 D/A converter is used on the Lab-PC-1200/AI.

• Appendix B, Xicor X25020 Data Sheet, contains the manufacturer data
sheet for the X25020 SPI serial EEPROM manufactured by Xicor , Inc.
This EEPROM is used on the Lab-PC-1200/AI.

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National Instruments Corporation ix Lab-PC-1200/AI RLPM

About This Manual

• Appendix C, OKI MSM82C53 Data Sheet, contains the manufacturer
data sheet for the MSM82C53 CMOS programmable interval timer
manufactured by OKI Semiconductor, Inc. This counter/timer is used
on the Lab-PC-1200/AI.

• Appendix D, OKI MSM82C55A Data Sheet, contains the
manufacturer data sheet for the MSM82C55A CMOS programmable
peripheral interface manufactured by OKI Semiconductor, Inc. This
interface is used on the Lab-PC-1200/AI.

• Appendix E, Customer Communication, contains a form you can use
to comment on the product documentation. This appendix also
contains information on how to access technical assistance for your
National Instruments product.

•The Glossary contains an alphabetical list and description of terms
used in this manual, including abbreviations, acronyms, metric
prefixes, mnemonics, and symbols.

•The Index contains an alphabetical list of key terms and topics cov ered
in this manual, including the page where you can find each one.

Conventions Used in This Manual

The following conventions are used in this manual.

<> Angle brackets containing numbers separated by an ellipsis represent a

range of values associated with a bit or signal name—for example,
DBIO<3..0>.

This icon to the left of bold italicized text denotes a note, which alerts you
to important information.

1200 Series 1200 Series refers to both the Lab-PC-1200 and the Lab-PC-1200AI
bold Bold text denotes the names of menus, menu items, dialog boxes, dialog

box buttons or options.

bold italic Bold italic text denotes a note, caution, or warning.
italic Italic text denotes emphasis, a cross reference, or an introduction to a key

concept.

©

Lab-PC-1200/AI RLPM x

National Instruments Corporation

About This Manual

monospace Text in this font denotes text or characters that you should literally enter

from the keyboard, sections of code, programming examples, and syntax
examples. This font is also used for the proper names of disk drives, paths,
directories, programs, subprograms, subroutines, device names, functions,
operations, variables, filenames and extensions, and for statements and
comments taken from programs.

NI-DAQ NI-DAQ is used in this manual to refer to the NI-DAQ driver software,

unless otherwise noted.

PC PC refers to all PC compatible computers with PCI bus, unless otherwise

noted.

SCXI SCXI stands for Signal Conditioning eXtensions for Instrumentation and is

a National Instruments product line designed to perform front-end signal
conditioning for National Instruments plug-in DAQ boards.

National Instruments Documentation

The Lab-PC-1200/AI Register-Level Programmer Manual is one piece of
the documentation set for your DA Q system. You could have any of several
types of manuals, depending on the hardware and software in your system.
Use the different types of manuals you have as follows:

• Getting Started with SCXI—If you are using SCXI, this is the first
manual you should read. It gives an overvie w of the SCXI system and
contains the most commonly needed information for the modules,
chassis, and software.

• Y our SCXI hardware user manuals—If you are using SCXI, read these
manuals next for detailed information about signal connections and
module configuration. They also explain in greater detail how the
module works and contain application hints.

• Your DAQ hardware user manuals—These manuals have detailed
information about the DA Q hardware that plugs into or is connected to
your computer. Use these manuals for hardware installation and
configuration instructions, specification information about your DAQ
hardware, and application hints.

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National Instruments Corporation xi Lab-PC-1200/AI RLPM

About This Manual

• Software manuals—Examples of software manuals you may have are

the LabVIEW or LabWindows/CVI manual sets and the NI-DAQ
manuals. After you set up your hardware system, use either the
LabVIEW, LabWindows/CVI, or NI-DAQ manuals to help you write
your application. If you have a large and complicated system, it is
worthwhile to look through the software manuals before you configure
your hardware.

• Accessory installation guides or manuals—If you are using accessory
products, read the terminal block and cable assembly installation
guides or accessory board user manuals. They explain how to
physically connect the relevant pieces of the system. Consult these
guides when you are making your connections.

• SCXI Chassis Manual—If you are using SCXI, read this manual for
maintenance information on the chassis and installation instructions.

Related Documentation

The following National Instruments document contains information that
you may find helpful as you read this manual:

• Application Note 025, Field Wiring and Noise Considerations for

Analog Signals

The following document also contains information that you may find
helpful as you read this manual:

• Your computer’s technical reference manual

Customer Communication

National Instruments wants to receive your comments on our products
and manuals. We are interested in the applications you develop with our
products, and we want to help if you have problems with them. To make it
easy for you to contact us, this manual contains a comment form for you to
complete. This form is in Appendix E, Customer Communication, at the
end of this manual.

Lab-PC-1200/AI RLPM xii

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National Instruments Corporation

General Description

This chapter describes the general characteristics and gives a configuration
overview of the Lab-PC-1200/AI.

General Characteristics

Thank you for purchasing the Lab-PC-1200/AI, low-cost,
high-performance multifunction analog, digital, and timing boards for
AT/ISA bus computers. The Lab-PC-1200/AI boards have eight analog
input channels that you can configure as eight single-ended or four
differential inputs; a 12-bit successive-approximation ADC; two 12-bit
DACs with voltage outputs; 24 lines of TTL-compatible digital I/O; and
three 16-bit counter/timers for timing I/O. Additionally, the Lab-PC-1200
has two 12-bit DACs with voltage outputs.

The Lab-PC-1200/AI is a member of the National Instruments A T Series of
expansion boards for AT/ISA bus computers. The 1200 Series boards are
completely switchless and jumperless DAQ boards. This allows DMA,
interrupts, and base I/O addresses to be assigned by your system to avoid
resource conflicts with other boards in your system. These boards are
designed for high-performance data acquisition and control for
applications in laboratory testing, production testing, and industrial process
monitoring and control. You can use the TTL-compatible digital I/O lines
for switching external devices such as transistors and solid-state relays, for
reading the status of external digital logic, and for generating interrupts.
You can use the counter/timers to synchronize events, generate pulses, and
measure frequency and time. The Lab-PC-1200/AI, used in conjunction
with the computer, is a versatile, cost-ef fecti ve platform for laboratory test,
measurement, and control.

1

This manual is intended for programming at the register level. Even if you
are an experienced register-level programmer, consider using NI-DAQ or
other National Instruments application software to program the
Lab-PC-1200/AI. If NI-DAQ does not support your operating system, or
you have other reasons to write your own register-level programs, continue
reading this manual.

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National Instruments Corporation 1-1 Lab-PC-1200/AI RLPM

Chapter 1 General Description

Board Configuration Overview

This section is a reference to the Lab-PC-1200/AI configuration options.
You should already have unpacked and installed your Lab-PC-1200/AI.
Refer to your Lab-PC-1200/AI User Manual if you have not already
performed these tasks.

Analog Input Configuration

The Lab-PC-1200/AI is completely software configurable, and at startup,
defaults to the following configuration:

• Referenced single-ended input mode

• ±5 V analog input range

Table 1-1 lists the available analog I/O configurations for the
Lab-PC-1200/AI and shows the default settings.

Table 1-1.

Parameter Configuration

Analog Input Range Bipolar—±5 V (default settings)

Unipolar—0 to 10 V

Analog Input Mode Referenced single-ended (RSE) (default setting)

Nonreferenced single-ended (NRSE)
Differential (DIFF)

The analog input circuitry is software configurable.

Analog Input Settings

Analog Output Configuration (Lab-PC-1200 Only)

At startup, the two channels of analog output of the Lab-PC-1200 default
to the following configuration:

• ±5 V analog input range

T able 1-2 lists the available analog I/O conf igurations for the Lab-PC-1200
and shows the default settings.

Table 1-2.

Parameter Configuration

Analog Output Range Bipolar—±5 V (default settings)

Analog Output Settings

Unipolar—0 to 10 V

Lab-PC-1200/AI RLPM 1-2

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National Instruments Corporation

The analog output circuitry is software configurable.

Digital I/O Configuration

The Lab-PC-1200/AI uses the MSM82C55A PPI, which provides
24 digital lines in the form of three ports—A, B, and C. On power up, all
three ports reset to mode 0 input. Appendix D, OKI MSM82C55A Data

Sheet, has the 82C55A data sheets that you need to program the digital I/O.

Counter Configuration

You can use the MSM82C53 counter/timers for general-purpose
applications, such as pulse and square wave generation, event counting,
and pulse width, time-lapse, and frequency measurement. Appendix C,

OKI MSM82C53 Data Sheet, has the 82C53 data sheet that you need to

program the counters/timers.

Chapter 1 General Description

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National Instruments Corporation 1-3 Lab-PC-1200/AI RLPM

Register Map and Descriptions

This chapter describes in detail the address and function of each of the Lab-PC-1200/AI
registers.

Register Map

T able 2-1 shows the register map for the Lab-PC-1200/AI and lists the register name, address,
type (read-only, write-only, or read-write), and size in bits.

Table 2-1 divides the Lab-PC-1200/AI registers into seven groups. The Configuration and
Status Register Group controls the overall operation of the Lab-PC-1200/AI. The Analog
Input Register Group reads output from the 12-bit successive-approximation ADC and can
initiate conversions. The Analog Output Register Group accesses the two 12-bit D A Cs on the
Lab-PC-1200 only . The two Counter/Timer Register Groups (A and B) access each of the two
onboard 82C53 counter/timer integrated circuits. The Digital I/O Register Group consists of
the four registers of the onboard 82C55A PPI integrated circuit that are used for digital I/O.
The Interval Counter registers are used in single-channel interval-scanning acquisition.

The Lab-PC-1200/AI registers are 8-bit registers. To transfer 16-bit data, you must perform
two consecutive memory readings or writings. F or example, to read the 16-bit A/D con version
result, you must make two consecutive 8-bit readings of the FIFO. The first reading returns
the low byte of the 16-bit data, and the second returns the high byte of the data.

2

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National Instruments Corporation 2-1 Lab-PC-1200/AI RLPM

Chapter 2 Register Map and Descriptions

Table 2-1. Lab-PC-1200/AI Register Map

Register Name

Configuration and Status Register Group

Command Register 1
Command Register 2
Command Register 3
Command Register 4
Command Register 5
Command Register 6
Status Register 1
Status Register 2

Analog Input Register Group

A/D FIFO Register
A/D FIFO Clear Register
CONFIGMEM Register
DMA TC Interrupt Clear Register

Analog Output Register Group

DAC0 Low-Byte Register
DAC1 High-Byte Register
DAC1 Low-Byte Register
DAC1 High-Byte Register

Address

Offset

(Hex)

00
01
02
0F
1C
0E
00

1D

0A

08
03

0A

04
05
06
07

Type Size

Write-only
Write-only
Write-only
Write-only
Write-only
Write-only

Read-only
Read-only

Read-only
Write-only
Write-only
Write-only

Write-only
Write-only
Write-only
Write-only

8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit

8-bit
8-bit
8-bit
8-bit

8-bit
8-bit
8-bit
8-bit

82C53 Counter/Timer Register Group A

Counter A0 Data Register
Counter A1 Data Register
Counter A2 Data Register
Counter A Mode Register
Timer Interrupt Clear Register

82C53 Counter/Timer Register Group B

Counter B0 Data Register
Counter B1 Data Register
Counter B2 Data Register
Counter B Mode Register

Lab-PC-1200/AI RLPM 2-2

14
15
16
17

0C

18

19
1A
1B

Read-Write
Read-Write
Read-Write

Write-only
Write-only

Read-Write
Read-Write
Read-Write

Write-only

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National Instruments Corporation

8-bit
8-bit
8-bit
8-bit
8-bit

8-bit
8-bit
8-bit
8-bit

Chapter 2 Register Map and Descriptions

Table 2-1.

Lab-PC-1200/AI Register Map (Continued)

Register Name

82C55A Digital I/O Register Group

Port A Register
Port B Register
Port C Register
Digital Control Register

Interval Counter Register Group

Interval Counter Data Register
Interval Counter Strobe Register

Register Description Overview

The remainder of this chapter discusses each of the Lab-PC-1200/AI registers in the order
shown in Table 2-1. Each register group is introduced, followed by a detailed bit description
of each register on the Lab-PC-1200/AI. For a detailed bit description of each register
concerning the 82C53 (A or B) chip or the 82C55A chip on the Lab-PC-1200/AI, refer to
Appendix C, OKI MSM82C53 Data Sheet, or Appendix D, OKI MSM82C55A Data Sheet.
The individual register description gives the address, type, word size, and bit map of the
register, followed by a description of each bit.

Address

Offset

(Hex)

10
11
12
13

1E
1F

Type Size

Read-Write
Read-Write
Read-Write

Write-only

Write-only
Write-only

8-bit
8-bit
8-bit
8-bit

8-bit
8-bit

The register bit map shows a diagram of the register with the most significant bit (MSB),
bit 7 for an 8-bit register, shown on the left, and the least significant bit (LSB), bit 0, shown
on the right. A rectangle labeled with the bit name inside its rectangle represents each bit.
An asterisk (*) after the bit name indicates that the bit is inverted (negative logic).

In a few of the registers, several bits are labeled with an X, indicating don’t care bits. When
you read a register, these bits may appear set or cleared but should be ignored because they
have no significance. When you write to a register, these bit locations should always be
written with a 0.

The bit map field for some write-only registers states not applicable, no bits used. Writing to
these registers causes some event to occur on the Lab-PC-1200/AI, such as clearing the
analog input circuitry. The data is ignored when writing to these registers; therefore, any bit
pattern will suffice.

Note

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National Instruments Corporation 2-3 Lab-PC-1200/AI RLPM

Always write a 0 to don’t care bits.

Chapter 2 Register Map and Descriptions

Configuration and Status Register Group

The eight registers of the Configuration and Status Register Group allo w general control and
monitoring of the Lab-PC-1200/AI A/D and D/A circuitry.

Command Register 1 and Command Register 2 contain bits that control the operation modes
of the A/D and D/A circuitry. Command Register 3 enables or disables interrupt operations.
Use Command Register 4 to select the analog input mode and to allow certain DAQ signals
to be externally driven at the I/O connector . Use Command Register 5 for softw are calibration
of the A/D circuitry. Use Command Register 6 to enable and disable interrupt operations and
to configure the A/D and D/A circuitry.

Status Register 1 reports the status of a DAQ operation and the status of analog output during
waveform generation. Status Register 2 reports the status of a D A Q operation and gives access
to the output of the EEPROM.

Upon power up, all of the Command Registers are cleared.
Bit descriptions for the registers in the Configuration and Status Register Group are on the

following pages.

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National Instruments Corporation

Chapter 2 Register Map and Descriptions

Command Register 1

Use Command Register 1 to select the input channel you want to scan, the gain for the analog
input circuitry, the DAQ scanning mode, and the coding used for the output of the ADC.

Address: 00 (hex)
Type: Write-only
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0

SCANEN GAIN2 GAIN1 GAIN0 TWOSCMP MA2 MA1 MA0

Bit Name Description

7 SCANEN Scan Enable—This bit enables or disables

multiple-channel scanning during data acquisition. Set this
bit to scan the analog channels as specified by MA<2..0>
and SE*/DIFF (bit 3 of Command Register 4). Clear this
bit to sample a single analog channel specified by
MA<2..0> and SE*/DIFF during the entire DAQ
operation.

6–4 GAIN<2..0> Gain—These three bits select the gain setting as follows:

GAIN<2..0> Selected Gain

000 1
001 Invalid
010 2
011 5
100 10
101 20
110 50
111 100

3 TWOSCMP Two’s Complement—This bit selects the coding format of

the ADC output. Set this bit to sign-extend the 12-bit data

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Chapter 2 Register Map and Descriptions

2–0 MA<2..0> Multiplexer Address—These three bits select which of

Single-Ended Mode Differential Mode

from the ADC to 16 bits (two’s complement). Clear this bit
to make bits 12 through 15 return 0 (straight binary).

the eight input channels are scanned. The analog input
multiplexers depend on these bits and also on SCANEN,
SCANUP (bit 7 of Command Register 6), and SE*/DIFF.
Input channels are selected as follows:

Selected Analog Input Channels

MA<2..0>

Scan

Disabled/Enabled

Scan

Disabled

000 0 0 0
001 1 0 2
010 2 2 4
011 3 2 6
100 4 4 0
101 5 4 2
110 6 6 4
111 7 6 6

In single-ended mode (SE*/DIFF cleared), if you set
SCANEN and clear SCANUP, analog channels MA<2..0>
through 0 are sampled sequentially. In single-ended
mode (SE*/DIFF cleared), if you set SCANEN and set
SCANUP, analog channels 0 through MA<2..0> are
sampled sequentially. If you clear SCANEN, a single
analog channel specified by MA<2..0> is sampled during
the entire DAQ operation.

Scan

Enabled

In DIFF mode, the number of analog inputs reduces to
four. The single-ended input channels 0 and 1 (pins 3
and 4) become differential input channel 0. The
single-ended input channels 2 and 3 (pins 5 and 6) become
differential input channel 2. There are no odd differential
input channels.

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National Instruments Corporation

Chapter 2 Register Map and Descriptions

Command Register 2

Command Register 2 contains eight bits that control the Lab-PC-1200/AI analog input trigger
modes, analog output update modes, and the coding scheme of the DACs.

Address: 01 (hex)
Type: Write-only
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0

LDAC1 LDAC0 2SDAC1 2SDAC0 TBSEL SWTRIG HWTRIG PRETRIG

Bit Name Description

7 LDAC1 Load DAC1—This bit determines how DAC1 will be

updated. If you set this bit, DAC1 updates its output at
regular intervals as determined by counter A2 or the
EXTUPDATE* signal at the I/O connector. If you clear
this bit, the voltage output of DAC1 is immediately
updated when data is loaded into the DAC1 High-Byte
Register.

6 LDAC0 Load DAC0—This bit determines how DAC0 will be

updated. If you set this bit, DAC0 updates its output at
regular intervals as determined by counter A2 or the
EXTUPDATE* signal at the I/O connector. If you clear
this bit, the voltage output of DAC0 is immediately
updated when data is loaded into the DAC0 High-Byte
Register.

5 2SDAC1 Two’s Complement DAC1—This bit selects the binary

coding scheme used for the DAC1 data. If you set this bit,
a two’s complement binary coding scheme is used for
interpreting the 12-bit data. Two's complement is used
with bipolar output mode. If you clear this bit, a straight
binary coding scheme is used. Straight binary is used with
unipolar output mode.

4 2SDAC0 Two’s Complement DAC0—This bit selects the binary

coding scheme used for the DAC0 data. If you set this bit,
a two’s complement binary coding scheme is used for
interpreting the 12-bit data. Two’s complement is used
with bipolar output mode. If you clear this bit, a straight

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Chapter 2 Register Map and Descriptions

3 TBSEL Time Base Select—This bit selects the clock source for

2 SWTRIG Software Trigger—This bit is a software trigger for a DAQ

1 HWTRIG Hardware Trigger—This bit enables or disables the

binary coding scheme is used. Straight binary is used with
unipolar output mode.

counter A0, the sample interval timer. If you clear this bit,
a 1 MHz clock drives counter A0, and the interval between
samples is the value loaded into counter A0 multiplied by
1 µs. If you set thi s b it , t he ou tpu t of co unt er B0 i s us ed as
the clock source. The timebase for counter B0 is fixed at
2 MHz. The sample in terval is the value loaded in to
counter A0 multiplied by the period of the output signal
from counter B0.

operation. You can trigger a DAQ operation by setting this
bit. The terminal count signal of counter A1 or a cleared
SWTRIG terminates a DAQ process.

posttrigger mode using the EXTTRIG signal at the
I/O connector. If you set this bit, you can use the
EXTTRIG signal to trigger a DAQ operation in place of
SWTRIG. A DAQ process is terminated by a terminal
count signal of counter A1 or by writing to the A/D FIFO
Clear Register. You must clear PRETRIG to use this
mode.

0 PRETRIG Pretrigger—This bit enables or disables the pretrigger

mode using the EXTTRIG signal at the I/O connector. If
you set this bit, you can use the EXTRIG signal at the
I/O connector to terminate a DAQ operation by using
counter A1. Data acquisition is terminated by a terminal
count on A1. You must clear the HWTRIG to use this
mode.

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Chapter 2 Register Map and Descriptions

Command Register 3

The Command Register 3 contains four bits that enable and disable interrupts for a DAQ
operation and for digital I/O.

Address: 02 (hex)
Type: Write-only
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0
0 0 FIFOINTEN ERRINTEN CNTINTEN TCINTEN DIOINTEN DMAEN

Bit Name Description

7, 6 0 Always leave these bits cleared.
5 FIFOINTEN FIFO Interrupt Enable—This bit enables and disables the

generation of an interrupt when an A/D conversion result
is available to be read from the A/D FIFO. If you set
FIFOINTEN, an interrupt is generated whenever the
DAVAIL bit becomes set in Status Register 1. Service this
interrupt by reading the data from the FIFO.

4 ERRINTEN Error Interrupt Enable—This bit enables and disables the

generation of an interrupt when an A/D error condition is
detected. If you set ERRINTEN, an interrupt is generated
whenever the OVERFLOW or OVERRUN bit becomes set
in Status Register 1. Service the interrupt by writing to the
A/D FIFO Clear Register.

3 CNTINTEN Counter Interrupt Enable—This bit enables the counter A2

output or the EXTUPDATE* signal to generate an
interrupt. If you set CNTINTEN, an interrupt occurs
whenever the CNTINT bit becomes set in Status Register

1. Clear this interrupt by writing to the Timer Interrupt
Clear Register. This interrupt allows waveform generation
on the analog output because the same signal that sets the
interrupt also updates the DAC output i f the corresponding
LDAC bit in Command Register 2 is set.

2 TCINTEN DMA Terminal Count Interrupt Enable—This bit enables

generation of an interrupt when a DMA terminal count
pulse is received. If TCINTEN is set, an interrupt request

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Chapter 2 Register Map and Descriptions

1 DIOINTEN DIO Interrupt Enable—This bit enables or disables

0 DMAEN DMA Enable—This bit enables or disables Analog Input

is generated when the DMA controller transfer count
register decrements from 0 to FFFF (hex). The interrupt is
serviced by writing to the DMATC Interrupt Clear
Register.

generation of an interrupt when either Port A or Port B
is ready to transfer data, and an interrupt re quest is
set via PC3 or PC0 of 82C55A. See Appendix D, OKI

MSM82C55A Data Sheet, for details. Clear this interrupt by

clearing PC3 or PC0. If you clear DIOINTEN, the
interrupts from PC3 or PC0 are disabled.

DMA transfers. If DMAEN is set, a DMA request is
generated whenever an A/D conversion result is available.
If DMAEN is cleared, no DMA request will be generated.

See the DAQ DMA Programming section in Chapter 3,

Programming, for more information.

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National Instruments Corporation

Chapter 2 Register Map and Descriptions

Command Register 4

Use this register to select the analog input mode, to enable interval scanning, and to allow the
I/O connector pins to externally drive certain DAQ signals.

Address: 0F (hex)
Type: Write-only
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0
0 0 0 ECLKRCV SE*/DIFF ECLKDRV EOIRCV INTSCAN

Bit Name Description

7–5 0 Always leave these bits cleared.
4 ECLKRCV External Clock Receive—This bit disables or enables the

external signal EXTCONV*. If you set this bit, transitions
on EXTCONV* will not effect data acquisition. If you
clear this bit, a falling edge on EXTCONV* initiates an
A/D conversion if ECLKDRV is cleared.

3 SE*/DIFF

Single-Ended/Differential—This bit, along with bit 0 of
Command Register 6 (RSE*/NRSE), selects one of three
analog input modes of the Lab-PC-1200/AI. You can
select the single-ended mode by clearing this bit and you
can select the differential mode by setting this bit. Refer to
the Lab-PC-1200/AI User Manual for an explanation of the
different modes. The following table illustrates how to
choose the various input modes by using SE*/DIFF and
RSE*/NRSE.

RSE*/NRSE SE*/DIFF Input Mod e

0 0 RSE (reset condition)
1 0 NRSE

X 1 DIFF

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Chapter 2 Register Map and Descriptions

2 ECLKDRV External Clock Drive—When you clear this bit (default

1 EOIRCV External Output Interval Clock Receive—This bit selects

0 INTSCAN Interval Scan—This bit selects the DAQ mode. When

power up), you can drive the EXTCONV* pin at the I/O
connector to cause conversions (if ECLKRCV is also
cleared). When you set this bit, you enable internally timed
conversions and the conversion pulses are driven onto the
EXTCONV* pin for synchronizing channels on SCXI
modules (if used with SCXI).

the clock source for interval scanning. If you clear this bit,
counter B1 drives the interval scanning circuitry. This will
also configure OUTB1 on the I/O connector as an output
signal. If you set this bit, OUTB1 on the I/O connector is
selected as an input signal and allows you to externally
drive the interval scanning circuitry.

you set this bit, the Lab-PC-1200/AI performs interval
data acquisition. If you clear this bit, freerun or controlled
data acquisition occurs. For an explanation of the different
modes, refer to Chapter 4, Theory of Operation, in the
Lab-PC-1200/AI User Manual. Also, this bit selects the
clock source for counter B1 used in interval scanning. If
interval scanning is disabled (INTSCAN = 0), then counter
B1 is available for user applications. You can then drive
CLKB1 externally at the I/O connector. If interval
scanning is enabled (INTSCAN = 1), the clock source of
counter A0 also drives CLKB1. This source can further be
selected by using the TBSEL bit in Command Register 2.

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Chapter 2 Register Map and Descriptions

Command Register 5

Use Command Register 5 for software calibration of the A/D and D/A circuitry, for
interaction with the EEPROM, and for enabling dither.

Address: 1C (hex)
Type: Write-only
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0

EEPROMCS SDATA SCLK CALDACLD DITHEREN WRTPRT* 0 0

Bit Name Description

7 EEPROMCS EEPROM Chip Select—This bit enables and disables the

EEPROM. You can enable the EEPROM for both read and
write operations by setting this bit. You can disable the
EEPROM by clearing this bit. Notice that this bit is
inverted on the Lab-PC-1200/AI to make EEPROMCS* as
explained in Chapter 5, Calibration, in your
Lab-PC-1200/AI User Manual.

6 SDATA Serial Data—This bit is a serial data input for both the

calibration DACs and the EEPROM.

5 SCLK Serial Clock—This bit is a serial clock for both the

calibration DACs and the EEPROM. A low-to-high
transition of this bit clocks data into the EEPROM (during
a write operation) and the calibration DAC. A high-to-low
transition of the bit clocks data out of the EEPROM
(during a read operation).

4CALDACLD

Calibration DAC Load—This bit updates the calibration
DACs. After you load the calibration DAC address and
data, set CALDACLD high to update the selected
CALDAC output signal.

3 DITHEREN Dither Enable—This bit enables or disables the dither

circuitry. When you set this bit, 0.5 LSB of white Gaussian
noise is added to the selected analog input signal. By
enabling dither and using averaging, you can achieve
greater input resolution.

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Chapter 2 Register Map and Descriptions

2 WRTPRT* Write Protect—This bit controls the write protect input

1, 0 0 Always leave these bits cleared.

signal for the EEPROM. When you set this bit, you enable
normal write operations. When you clear this bit, you
disable write operations.

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National Instruments Corporation

Chapter 2 Register Map and Descriptions

Command Register 6

Use Command Register 6 to enable A/D interrupts and to configure the A/D and D/A
circuitry.

Address: 0E (hex)
Type: Write-only
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0

SCANUP DQINTEN HFINTEN 0 DAC1UNI/BI* DAC0UNI/BI* ADCUNI/BI* RSE*/NRSE

Bit Name Description

7 SCANUP Scan Up—This bit selects the orde r in which the analog

input channels are scanned. Clear this bit to select down
counting (highest numbered channel scanned first). Set
this bit to select up counting (channel 0 scanned first).

6 DQINTEN DAQ Interrupt Enable—This bit enables and disables the

end of a DAQ operation interrupt. Set this bit to generate
an interrupt whenever the OUTA1 bit in Status Register 2
becomes set. Service this interrupt by resetting counter
A1. Clear this bit to disable interrupt generation.

5 HFINTEN Half-Full Interrupt Enable—This bit enables and disables

the FIFO half-full interrupt. Set this bit to generate an
interrupt whenever the FIFOHF* bit in Status Register 2
becomes cleared. Service this interrupt by reading data
from the FIFO. Clear this bit to disable interrupt

generation.
4 0 Always leave this bit cleared.
3 DAC1UNI/BI* DAC1 Unipolar/Bipolar—This bit sets the analog voltage

output range for DAC1. Set this bit to configure DAC1 for

a unipolar (0 to +10 V) output voltage range. Clear this bit

to configure DAC1 for a bipolar (–5 to +5 V) output

voltage range.

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Chapter 2 Register Map and Descriptions

2 DAC0UNI/BI* DAC0 Unipolar/Bipolar—This bit sets the analog voltage

1 ADCUNI/BI* ADC Unipolar/Bipolar—This bit sets the analog voltage

0 RSE*/NRSE Referenced Single-Ended/Nonreferenced

output range for DAC0. Set this bit to configure DAC0 for
a unipolar (0 to +10 V) output voltage range. Clear this bit
to configure DAC0 for a bipolar (–5 to +5 V) output
voltage range.

input range for data acquisition. Set this bit to select a
unipolar (0 to +10 V) voltage input range. Clear this bit to
select a bipolar (–5 to +5 V) voltage input range.

Single-Ended—This bit, and bit 3 of Command Register 4
(SE*/DIFF), selects one of three input modes of the
Lab-PC-1200/AI. The status of RSE*/NRSE is only
important with the single-ended analog-input modes. Set
this bit to select the nonreferenced single-ended mode.
Clear this bit to select the referenced single-ended mode.
For an explanation of the three input modes, refer to the
Lab-PC-1200/AI User Manual.

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Chapter 2 Register Map and Descriptions

Status Register 1

Status Register 1 indicates the status of the current DAQ operation and the status of analog
output during waveform generation. These bits indicate if a DAQ operation is in progress or
if data is available, whether any errors have been found, and the analog output interrupt status.

Address: 00 (hex)
Type: Read-only
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0

X EXTGATA0 GATA0 DMATC CNTINT OVERFLOW OVERRUN DAV AIL

Bit Name Description

7 X Don’t care bits.
6 EXTGATA0 External Gate A0—This bit indicates the status of the

external trigger signal (EXTTRIG) during a DAQ

operation in posttrigger mode. If this bit is set, EXTTRIG

has triggered a DAQ operation. Clear this bit by writing to

the A/D FIFO Clear Register.
5 GATA0 Gate A0—This bit indicates the status of the GATEA0

input for counter A0. Use this bit as a busy indicator for

DAQ operations because conversions are enabled as long

as GATEA0 is high and counter A0 is programmed

appropriately. A DAQ operation is terminated when

GATA0 is cleared.
4 DMATC DMA Terminal Count—This bit reflects the status of the

DMA terminal count. If this bit is set and the TCINTEN bit

in Command Register 3 is set, the current interrupt was

generated by a DMA terminal count pulse. This bit is

cleared by writing to the DMATC Interrupt Clear Register.
3 CNTINT Counter Interrupt—This bit reflects the status of the

interrupt caused by counter A2 output or the

EXTUPDATE* signal. A low-to-high transition on

counter A2 output or on EXTUPDATE* sets this bit.

You can ge nerate an interrup t if you set C NTINTEN in

Command Register 3. Clear this bit by writing to the Timer

Interrupt Clear Register.

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Chapter 2 Register Map and Descriptions

2 OVERFLOW Overflow—This bit indicates if an overflow error has

1 OVERRUN Overrun—This bit indicates if an overrun error has

0 DAVAIL Data Available—This bit indicates if conversion output is

occurred. If this bit is cleared, no error was encountered. If
this bit is set, the A/D FIFO has overflowed because the
DAQ servicing operation could not keep up with the
sampling rate.

occurred. If this bit is cleared, no error occurred. This bit
is set if a convert command is issued to the ADC while the
last conversion is still in progress.

available. If this bit is set, the ADC is finished with the last
conversion and the result can be read from the FIFO. This
bit is cleared if the FIFO is empty.

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Chapter 2 Register Map and Descriptions

Status Register 2

Status Register 2 reports the status of a DA Q operation and the FIFO half-full output and gives
access to the output of the EEPROM.

Address: 1D (hex)
Type: Read-only
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0

X X X X X FIFOHF* OUTA1 PROMOUT

Bit Name Description

7–3 X Don’t care bits.
2 FIFOHF* FIFO Half-Full—This bit indicates the status of the FIFO

half-full output. If this bit is low, the FIFO is at least half

full. If this bit is high, the FIFO is less than half full.
1 OUTA1 Output Counter A1—This bit indicates the status of the

output signal of counter A1. If the user sets the counter A1

mode for a terminal count, OUTA1 low indicates counter

A1 has not started counting or that counting is in progress.

OUTA1 high indicates that counter A1 has finished

counting.
0 PROMOUT EEPROM Output—This bit allows access to the serial

output pin of the EEPROM. During calibration

procedures, the software reads the calibration data from

the EEPROM through PROMOUT and writes the data to

the calibration DACs.

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Chapter 2 Register Map and Descriptions

Analog Input Register Group

The three registers making up the Analog Input Register Group control the analog input
circuitry and the FIFO. Reading the FIFO Register returns stored A/D conversion results.
Writing to the Start Convert Register initiates a single A/D conversion. Writing to the A/D
FIFO Clear Register clears the analog input circuitry.

Bit descriptions for the registers of the Analog Input Register Group are on the following
pages.

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National Instruments Corporation

A/D FIFO Register

The 12-bit A/D conversion results are sign-e xtended to 16-bit data in either two’ s complement
or straight binary format and are stored into a 4 Kword-deep A/D FIFO buffer. Two
consecutive 8-bit readings of the A/D FIFO Register return an A/D conversion value stored
in the A/D FIFO. The first reading returns the low byte of the 16-bit value, and the second
reading returns the high byte. The value read is removed from the A/D FIFO, thereby freeing
space for another A/D conversion value to be stored.

The A/D FIFO is empty when all values it contains are read. The DAVAIL bit in Status
Register 1 should be read before the A/D FIFO Register is read. If the A/D FIFO contains one
or more A/D conversion v alues, the DAVAIL bit is set and the A/D FIFO Register can be read
to retrieve a value. If the DAVAIL bit is cleared, the A/D FIFO is empty. Therefore, reading
the A/D FIFO Register returns meaningless information.

The values returned by reading the A/D FIFO Register are available in tw o different binary
formats: straight binary or two’s complement binary. The binary format used is selected by
the TWOSCMP bit in Command Register 1. The bit pattern returned for either format is as
follows.

Address: 0A (hex)
Type: Read-only
Word Size: 8-bit
Bit Map: Straight binary mode

High Byte

Chapter 2 Register Map and Descriptions

7 6 5 4 3 2 1 0
0 0 0 0 D11 D10 D9 D8

Low Byte

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0

Bit Name Description

High Byte
7–4 0 These bits always return 0 in straight binary mode.
3 –0 D<11..8> Data—These bits contain the high byte of the straight

binary result of a 12-bit A/D conversion. Values made up

of D<11..0> range from 0 to +4,095 decimal (0000 to

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Chapter 2 Register Map and Descriptions

0FFF hex). Straight binary mode is useful for unipolar
analog input readings because all values read reflect a
positive polarity input signal.

Low Byte
7–0 D<7..0> Data—These bits contain the low byte of the straight

binary result of a 12-bit A/D conversion. The first of the
two consecutive readings of the A/D FIFO Register returns
this byte.

Bit Map: Two’s complement binary mode
High Byte

7 6 5 4 3 2 1 0

D15 D14 D13 D12 D11 D10 D9 D8

Low Byte

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0

Bit Name Description

High Byte
7–0 D<15..8> Data—These data bits contain the high byte of the 16-bit,

sign-extended two’s complement result of a 12-bit A/D
conversion. Values made up of D<15..0>, therefore, range
from –2,048 to +2,047 decimal (F800 to 07 FF hex). Two’s
complement mode is useful for bipolar analog input
readings because the values read reflect the polarity of the

input signal.
Low Byte
7–0 D<7..0> Data—These data bits contain the low byte of the 16-bit,

sign-extended two’s complement result of a 12-bit A/D

conversion. The first of the two consecutive readings of

A/D FIFO Register returns this by te.

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A/D FIFO Clear Register

Write to this register to reset the ADC FIFO. This operation clears the FIFO, clears the
DAVAIL bit, and sets the FIFOHF* bit. All error bits in Status Register 1 are cleared.

Address: 08 (hex)
Type: Write-only
Word Size: 8-bit
Bit Map: Not applicable, no bits used

Start Convert Register

Write to the Start Convert Register to initiate a single A/D conversion.

Address: 03 (hex)
Type: Write-only
Word Size: 8-bit
Bit Map: Not applicable, no bits used

DMATC Interrupt Clear Register

Chapter 2 Register Map and Descriptions

Writing to the DMA Terminal Count (DMATC) Clear Register clears the interrupt request
asserted when a DMA terminal count pulse is detected.

Address: 0A (hex)
Type: Write-only
Word Size: 8-bit
Bit Map: Not applicable, no bits used

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Chapter 2 Register Map and Descriptions

Analog Output Register Group (Lab-PC-1200 Only)

Use the four registers of the Analog Output Register Group to load the two 12-bit DACs.
DAC0 controls analog output channel 0. DAC1 controls analog output channel 1. Write to
these DACs individually.

Bit descriptions of the registers making up the Analog Output Register Group are on the
following pages.

Note

DACx represents DAC0 and DAC1 registers. LDACx represents LDAC0 and
LDAC1 bits.

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Chapter 2 Register Map and Descriptions

DAC0 Low-Byte, DAC0 High-Byte, DAC1 Low-Byte, and
DAC1 High-Byte Registers

Write to DAC0 Low-Byte and then to DAC0 High-Byte to load DAC0. Write to DAC1
Low-Byte and then to DAC1 High-Byte to load DAC1. If you clear the LDACx bit in
Command Register 2, then the corresponding analog output channel is updated immediately
after you write to the DACx High-Byte register. If you set the LDACx bit, then the
corresponding analog output channel is updated when an active low pulse occurs on the
output of counter A2 or on the EXTUPDATE* line on the I/O connector.

Address: 04 (hex) DAC0 Low Byte

05 (hex) DAC0 High Byte
06 (hex) DAC1 Low Byte
07 (hex) DAC1 High Byte

Type: Write-only (all)
Word Size: 8-bit (all)
Bit Map:

DACxH

7 6 5 4 3 2 1 0

D15 D14 D13 D12 D11 D10 D9 D8

DACxL

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0

Bit Name Description

DACxH
7–4 D<15..12> Data—Zero in straight binary mode, sign extensio n in

two’s complement mode.

3–0 D<11..8> Data—These four bits are loaded into the specified

DAC high byte.
DACxL
7–0 D<7..0> Data—These eight bits are loaded into the specified

DAC low byte should be loaded first, followed by the

corresponding high byte.

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Chapter 2 Register Map and Descriptions

82C53 Counter/Timer Register Groups A and B

The nine registers of the two counter/timer register groups access the two onboard 82C53
counter/timers. Each 82C53 has three counters. For convenience, the two counter/timer
groups and their respective 82C53 integrated circuits ha ve been designated A and B. The three
counters of group A control onboard DAQ timing and waveform generation. You can use the
three counters of group B for general-purpose timing functions.

Each 82C53 has three independent 16-bit counters and one 8-bit Mode Register. The Mode
Register sets the mode of operation for each of the three counters.

Writing to the Timer Interrupt Clear Register clears the interrupt request asserted when a low
pulse is detected on the output of counter A2 or on the EXTUPDATE* line.

Bit descriptions for the registers in the Counter/Timer Register Groups are in the following
pages.

Lab-PC-1200/AI RLPM 2-26

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National Instruments Corporation

Chapter 2 Register Map and Descriptions

Counter A0 Data Register

Use the Counter A0 Data Register to write data and read back the contents of 82C53(A)
counter 0. Counter A0 is the sample interval counter for a DAQ operation.

Address: 14 (hex)
Type: Read-and-write
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0

Bit Name Description

7–0 D<7..0> Data—8-bit counter A0 contents.

Counter A1 Data Register

Use the Counter A1 Data Register to write data and read back the contents of 82C53(A)
counter 1. Counter A1 is the sample counter for a DAQ operation.

Address: 15 (hex)
Type: Read-and-write
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0

Bit Name Description

7–0 D<7..0> Data—8-bit counter A1 contents.

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Chapter 2 Register Map and Descriptions

Counter A2 Data Register

Use the Counter A2 Data Register to write data and read back the contents of 82C53(A)
counter A2. Counter A2 is the DAC update timer for waveform generation.

Address: 16 (hex)
Type: Read-and-write
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0

Bit Name Description

7–0 D<7..0> Data—8-bit counter A2 contents.

Counter A Mode Register

The Counter A Mode Register determines the operation mode for each of the three counters
on the 82C53(A) chip. The Counter A Mode Register selects the counter involved, its
read/write mode, its operation mode (that is, any of the 82C53 six operation modes), and the
counting mode (binary or BCD counting).

The Counter A Mode Register is an 8-bit register . Bit and programming descriptions for each
of these bits are in Appendix C, OKI MSM82C53 Data Sheet.

Address: 17 (hex)
Type: Write-only
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0

SC1 SC0 RL1 RL0 M2 M1 M0 BCD

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National Instruments Corporation

Timer Interrupt Clear Register

Write to the Timer Interrupt Clear Register to clear the interrupt request asserted when a lo w
pulse is detected on the counter A2 output or on EXTUPDATE* line.

Address: 0C (hex)
Type: Write-only
Word Size: 8-bit
Bit Map: Not applicable, no bits used.

Counter B0 Data Register

Use the Counter B0 Data Register to write data and read back the contents of 82C53(B)
counter 0. Counter B0 either supplies the time base clock for counter A0 or is reserved for
external usage.

Address: 18 (hex)
Type: Read-and-write
Word Size: 8-bit
Bit Map:

Chapter 2 Register Map and Descriptions

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0

Bit Name Description

7–0 D<7..0> Data—8-bit counter B0 contents.

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Chapter 2 Register Map and Descriptions

Counter B1 Data Register

Use the Counter B1 Data Register to write data and read back the contents of 82C53(B)
counter 1. Counter B1 is either the interval timer for a DAQ operation or is reserved for
external usage.

Address: 19 (hex)
Type: Read-and-write
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0

Bit Name Description

7–0 D<7..0> Data—8-bit counter B1 contents.

Counter B2 Data Register

Use the Counter B2 Data Register to write data and read back the contents of 82C53(B)
counter 2. Counter B2 is reserved for external usage.

Address: 1A (hex)
Type: Read-and-write
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0

D7 D6 D6 D4 D3 D2 D1 D0

Bit Name Description

7–0 D<7..0> Data—8-bit counter B2 contents.

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National Instruments Corporation

Chapter 2 Register Map and Descriptions

Counter B Mode Register

The Counter B Mode Register determines the operation mode for each of the three counters
on the 82C53(B) chip. The Counter B Mode Register selects the counter involved, its
read/write mode, its operation mode (that is, any of the 82C53 six operation modes), and the
counting mode (binary or BCD counting).

The Counter Mode Register is an 8-bit register. Bit descriptions for each of these bits are in
Appendix C, OKI MSM82C53 Data Sheet.

Address: 1B (hex)
Type: Write-only
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0

SC1 SC0 RL1 RL0 M2 M1 M0 BCD

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Chapter 2 Register Map and Descriptions

82C55A Digital I/O Register Group

The four registers of the Digital I/O register group access the 82C55A peripheral interface.
The 82C55A is a general-purpose peripheral interface containing 24 programmable I/O pins.
These pins represent the three 8-bit I/O ports (A, B, and C) of the 82C55A and the 24 digital
I/O lines on the I/O connector. You can program these ports as two groups of 12 signals or as
three individual 8-bit ports. You can also configure them as either input or output pins. Use
the Digital Control Register to configure the three ports. For further information on the
82C55A, refer to Appendix D, OKI MSM82C55A Data Sheet.

Bit descriptions for the registers in the Digital I/O Register Group are on the following pages.

Lab-PC-1200/AI RLPM 2-32

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National Instruments Corporation

Chapter 2 Register Map and Descriptions

Port A Register

Use the Port A Register to write and to read the eight digital I/O lines constituting port A
on the I/O connector (PA<0..7>). See Appendix D, OKI MSM82C55A Data Sh eet, for
information on how to configure port A for input or output.

Address: 10 (hex)
Type: Read-and-write
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0

Bit Name Description

7–0 D<7..0> Data—8-bit port A data.

Port B Register

Use the Port B Register to write and to read the eight digital I/O lines constituting port B, that
is, PB<0..7>. See Appendix D, OKI MSM82C55A Data Sheet, for information on how to
configure port B for input or output.

Address: 11 (hex)
Type: Read-and-write
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0

Bit Name Description

7–0 D<7..0> Data—8-bit port B data.

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Chapter 2 Register Map and Descriptions

Port C Register

You can use port C as an 8-bit I/O port like port A and port B if neither port A nor port B is
used in handshaking mode. If either port A or port B is configured for mode 1 or mode 2, some
of the bits in port C are used for handshaking signals. See Appendix D, OKI MSM82C55A

Data Sheet, for a description of the individual bits in the Port C Register.

Address: 12 (hex)
Type: Read-and-write
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0

Bit Name Description

7–0 D<7..0> Data—8-bit port C data.

Digital Control Register

You can use the Digital Control Register to configure port A, port B, and port C as inputs or
outputs, and you can select simple mode (basic I/O) or handshaking mode (strobed I/O) for
transfers. See Appendix D, OKI MSM82C55A Data Sheet, for a description of the individual
bits in the Digital Control Register.

Address: 13 (hex)
Type: Write-only
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0

CW7 CW6 CW5 CW4 CW3 CW2 CW1 CW0

Bit Name Description

7–0 CW<7..0> Control Word—8-bit control word.

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Lab-PC-1200/AI RLPM 2-34

National Instruments Corporation

Interval Counter Register Group

Use the 8-bit Interval Counter only in the single-channel interval scanning mode
(SCANEN = 0 and INTSCAN = 1). Refer to the DAQ Operations section in Chapter 4,
Theory of Operation, of your Lab-PC-1200/AI User Manual for an explanation of interval
scanning mode. The Interval Counter consists of two 8-bit registers—the Interval Counter
Data Register and the Interval Counter Strobe Register. Load the Interval Counter Data
Register with the count. Writing to the Interval Counter Strobe Register loads this count into
the Interval Counter . The Interv al Counter decrements with each con v ersion. When the count
reaches 0, the Interval Counter autoinitializes, restoring the original count value.

Bit descriptions for the registers in the Interval Counter Register Group are on the following
pages.

Chapter 2 Register Map and Descriptions

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National Instruments Corporation 2-35 Lab-PC-1200/AI RLPM

Chapter 2 Register Map and Descriptions

Interval Counter Data Register

Load the Interval Counter Data Register with the desired number of samples to be acquired
within a scan interval of a single channel DAQ operation.

Address: 1E (hex)
Type: Write-only
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0

Bit Name Description

7–0 D<7..0> Data—Interval counter count.

Interval Counter Strobe Register

Writing to the Interval Counter Strobe Register strobes the contents of the Interval Counter
Data Register into the Interval Counter. This action arms the Interval Counter, which
decrements with each conversion pulse.

Address: 1F (hex)
Type: Write-only
Word Size: 8-bit
Bit Map:

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1

Bit Name Description

7–0 0 Each of these bits must be 0 for proper operation of the

Lab-PC-1200/AI.

0 1 This bit must be 1 for proper operation of the

Lab-PC-1200/AI.

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National Instruments Corporation

Programming

This chapter contains programming instructions for operating the
Lab-PC-1200/AI circuitry, and examples of the programming steps
necessary to execute an operation. If you are not using NI-DAQ, you must
first initialize your board. The initialization steps are unique for PC and
Macintosh users, so refer to the section pertaining to your platform.

Programming the Lab-PC-1200/AI involves writing to and reading from
registers on the board. Y ou will f ind a listing of these registers in Chapter 2,

Register Map and Descriptions, of this manual.

Register Programming Considerations

The Lab-PC-1200/AI supports 8-bit I/O transfers; thus, all the
read-and-write operations are 8-bit operations. You must do 16-bit
transfers in two consecutive 8-bit operations.

Several write-only registers on the Lab-PC-1200/AI contain bits that
control several independent pieces of the onboard circuitry. In the set or
clear instructions, specific register bits should be set or cleared without
changing the current state of the remaining bits in the register. However,
writing to these registers affects all register bits simultaneously. Because
you cannot read these registers to determine their current status, you should
maintain a software copy of the write-only registers. To change the state of
a single bit without disturbing the remaining bits, set or clear the bit in the
software copy and then write the modified software copy to the register.

3

Programming Examples

The programming examples in this section demonstrate the programming
steps needed to perform several different operations. The instructions are
language independent; that is, they tell you to read or write a given register
or to detect if a given bit is set or cleared, without presenting the actual
code. The information given is not intended to be used without proper
modification in a practical solution.

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National Instruments Corporation 3-1 Lab-PC-1200/AI RLPM

Chapter 3 Programming

Before you can implement any of the examples into a real application, you
must know the base memory address for your board. To process any
interrupts, you must write and install an applicable interrupt service
routine.

Note In this chapter all numbers preceded by 0x are hexadecimal.

Common terms that you will see used in the programming examples are
listed below:

Write (address, data) Generic function call for a I/O space

Write of data to address

Read (address) Generic function call for a I/O space

Read from address

Lab-PC-1200/AI Companion Disk

The companion disk provides code to execute the ISA Plug and Play
algorithm and assign resources to the card. This process is normally
performed by your computer’s operating system, such as Windows 95, but
for programming environments that do not execute the Plug and Play
algorithm, such as MS-DOS, the board will not be operable. The code
provided can be used to execute the Plug and Play algorithm for
environments such as MS-DOS. The code was compiled with Microsoft
Visual C++, version 1.5, as an MS-DOS application.

Assigning Lab-PC-1200/AI Resources

The companion disk code allows you to assign any of the allowable
resources for the base I/O address, interrupt channel, and DMA channel.
T able 3-1 lists the acceptable resources for the Lab-PC-1200/AI board. The
function,
the resources to the board. This function, as written, assigns all boards
interrupt channel 5, DMA channel 3, and base I/O address
0x220 + (0x20 •j), where j is the board number. Thus, the first
Lab-PC-1200/AI board will be assigned base I/O address 0x220, the next
0x240, and so on. This function should be changed accordingly for your
application.

0x100-0x3e0
(in 0x20 increments)

Lab-PC-1200/AI RLPM 3-2

PNPProgramSrom(), located in the file, pnp_util.c, assigns

Table 3-1. Lab-PC-1200/AI Allowable Resources

Base I/O Address IRQ Channels DMA Channels

3, 4, 5, 6, 7, 9 1, 3

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National Instruments Corporation

Initializing the Lab-PC-1200/AI Circuitry

Initializing the Lab-PC-1200/AI circuitry involves two steps—reset and
calibration. The Lab-PC-1200/AI circuitry is reset on power up.
Calibration of the analog input and output circuitry involves reading the
factory-defined calibration constants from the onboard EEPROM and
loading them into the appropriate calibration DACs. For information on
using user-defined calibration constants, refer to Chapter 4, Calibration.

When reset, the Lab-PC-1200/AI is left in the following state:

1. All of the command registers are cleared.

2. All of the interrupts are disabled and cleared.

3. The 82C55A digital I/O is in Mode 0 input.

4. The analog output DACs are reset to 0.0 V (Lab-PC-1200 only).
Calibrating the Lab-PC-1200/AI involves two steps— reading eight

factory-defined calibration constants from the EEPROM and writing each
value to the appropriate CALDAC. Choose the desired factory-defined
calibration constants as explained in Chapter 5, Calibration, of your
Lab-PC-1200/AI User Manual.

Chapter 3 Programming

Use the following sequence of steps to read a single byte from the
EEPROM.

1. Set the EEPROMCS and WRTPRT* bits in Command Register 5.

2. Serially write the READ instruction, 0x03, to the EEPROM to start a
read operation.

3. Serially write the 8-bit address.

4. Serially read one byte of data from the EEPROM.

5. Clear the EEPROMCS and WRTPRT* bits in Command Register 5 to
end the read operation.

Repeat the following two steps eight times to serially write one byte to the
EEPROM.

1. Write a single bit of the 8-bit value, MSB first, by setting or clearing
the SDATA bit in Command Register 5. The SCLK bit in Command
Register 5 should be cleared during this step.

2. Set the SCLK bit in Command Register 5.

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National Instruments Corporation 3-3 Lab-PC-1200/AI RLPM

Chapter 3 Programming

Repeat the following three steps eight times to serially read one byte from
the EEPROM.

1. Set the SCLK bit in Command Register 5.

2. Clear the SCLK bit in Command Register 5.

3. Read a single bit of the 8-bit value, MSB first, by reading the
PROMOUT bit of Status Register 2.

After reading a single calibration constant from the EEPROM, you must
write this value to the appropriate CALDAC. Use the following steps to
write a single byte to a CALDAC.

1. Write the 4-bit address of the desired CALDAC (address 0x3-0xA),
LSB first. CALDACLD should be cleared during this step.

2. Write the 8-bit calibration constant, MSB first.

3. Set the CALDACLD bit in Command Register 5.

4. Clear the CALDACLD bit in Command Register 5.

Repeat the following steps the appropriate number of times to serially write
required bits to the CALDAC.

1. Write a single bit of the value by setting or clearing the SDATA bit in
Command Register 5. SCLK should be cleared during this step.

2. Set the SCLK bit in Command Register 5.

Repeat the calibration operation for each CALDAC to fully calibrate the
Lab-PC-1200/AI.

Programming the Analog Input Circuitry for
Single A/D Conversions

This section explains how to clear the analog input circuitry, how to
configure the analog input circuitry, and how to perform single A/D
conversions.

Clearing the Analog Input Circuitry

Before clearing the analog input circuitry, perform the following steps:

1. Clear SWTRIG in Command Register 2.

2. Ensure that EXTCONV* from the I/O connector does not cause any
conversions.

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Lab-PC-1200/AI RLPM 3-4

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Chapter 3 Programming

3. Ensure that EXTTRIG from the I/O connector does not cause any
conversions.

Clearing the analog input circuitry does not stop a DA Q operation that
was started by the SWTRIG bit in Command Register 2. Therefore,
you should clear this bit before clearing the analog input circuitry.

While clearing the analog input circuitry, do not externally drive the
EXTCONV* pin on the I/O connector or, if you do, drive it high.
Another option is to set the ECLKRCV bit in Command Register 4.
This disables any transitions on the EXTCONV* pin and no unwanted
conversions will occur while you are clearing the analog input
circuitry.

While clearing the analog input circuitry, do not externally drive the
EXTTRIG pin on the I/O connector or, if you do, drive it high. Another
option is to make sure the HWTRIG bit in Command Register 2 is
cleared. This disables any transitions on the EXTTRIG pin and no
unwanted conversions will occur while you are clearing the analog
input circuitry.

The analog input circuitry can be cleared by writing to the A/D FIFO Clear
Register, which leaves the analog input circuitry in the following state:

1. Analog input status bits OVERRUN, OVERFLOW, and DAVAIL are
cleared and FIFOHF* is set.

2. Pending interrupt requests from the analog input circuitry are cleared.

The command registers are not cleared, so you do not necessarily have to
reconfigure the Lab-PC-1200/AI before initiating another DAQ sequence.

Configuring the Analog Input Circuitry

Configure the analog input circuitry after initializing the Lab-PC-1200/AI
and any time the characteristics of the analog input signals change.
Program the appropriate register bits as follows (not necessarily in this
order):

• Select the appropriate input mode (DIFF, NRSE, or RSE).

• Select the input polarity (bipolar or unipolar) and coding of the
resulting conversions (straight binary or two’s complement).

• Select the analog input channels to be scanned and gain.

You determine the input mode by identifying the types of signal sources
that you are using. For more information about determining the input mode,
consult the Lab-PC-1200/AI User Manual. Select the input mode by setting

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National Instruments Corporation 3-5 Lab-PC-1200/AI RLPM

Chapter 3 Programming

or clearing the RSE*/NRSE and SE*/DIFF bits in Command Register 6 and
Command Register 4, respectively.

You determine the input polarity according to the voltage range of the
analog input signal. For more information about determining the input
polarity , consult the Lab-PC-1200/AI User Manual. The conversion coding
should be selected according to the input polarity. Select the input polarity
by setting or clearing the ADCUNI/BI* bit in Command Register 6. Select
the respective coding by setting or clearing the TWOSCMP bit in
Command Register 1.

If you will be performing single-channel data acquisition, select the desired
analog channel and gain by setting or clearing the GAIN<2..0> and
MA<2..0> bits in Command Register 1. You must also clear SCANEN in
Command Register 1. If you will be doing multiple-channel data
acquisition, set MA<2..0> to specify the highest numbered channel in the
scan sequence. Set or clear the SCANUP bit in Command Register 6 for the
desired scanning order. For example, if you set MA<2..0> to 011 (binary)
and clear the SCANUP bit, the following scan sequence is used:

channel 3, channel 2, channel 1, channel 0, channel 3, channel 2, and
so on.

If you set MA<2..0> to 011 (binary) and set the SCANUP bit, the following
scan sequence is used:

channel 0, channel 1, channel 2, channel 3, channel 0, channel 1, and
so on.

Select the analog input channel and gain for multiple-channel data
acquisition in the following order.

1. Set or clear the SCANUP bit for the desired scanning order.

2. Set the gain and the highest channel number in the scan sequence in
Command Register 1. Clear the SCANEN bit during this first write to
Command Register 1.

3. Write to Command Register 1 again, but this time set the SCANEN bit.
This latches the channel number into the scan counter. You must write
all other bits in Command Register 1 as you did in the first write, which
set the gain and highest channel number.

Lab-PC-1200/AI RLPM 3-6

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National Instruments Corporation

Performing Single A/D Conversions

After configuring the analog input circuitry, you can perform single A/D
conversions and then read the conversion result from the A/D FIFO.
Perform the following steps:

1. Set counter A0 so that OUTA0 is high.

2. Initiate a conversion by writing to the Start Convert Register.

3. Read the conversion result from the A/D FIFO.
You must program counter A0 so that OUTA0 is high. You can do this by

writing 0x14 (select counter A0, mode 2) to Counter A Mode Register. This
enables the conversions initiated by writing to the Start Convert Register.

Initiate a conversion by writing to the Start Convert Register. When you
initiate an A/D conversion, the ADC stores the result in the A/D FIFO at
the end of its conversion c ycle (approximately 10 µs later). You can acquire
a specific number of samples by writing to the Start Convert Register that
same number of times. In multiple-channel data acquisition, the hardware
scans the channels as described before with each write to the Start Convert
Register .

Y ou obtain A/D con version results by reading the A/D FIFO Register . First,
you must read the status registers to determine the state of the A/D FIFO.
The useful status bits are OVERR UN, O VERFLOW , and D AVAIL in Status
Register 1 and FIFOHF* in Status Register 2. The DAVAIL bit will be set
if there is at least one conversion result stored in the A/D FIFO. The
DAVAIL bit should become set within a maximum of 12 µs after you
initiate an A/D conversion. If DAVAIL is set, you can follow the Status
Register read by reading the A/D FIFO. If the FIFOHF* bit is cleared, you
can follow the Status Register read with 4,096 consecuti ve readings of the
A/D FIFO. This corresponds to 2,048 samples, since each sample requires
two readings of the A/D FIFO. If either the OVERFLOW or the
OVERR UN bit is set, an error has occurred. You have either lost at least one
conversion by o verflo wing the A/D FIFO, or you have attempted to initiate
a conversion before the previous one has completed.

Chapter 3 Programming

You must read the A/D FIFO twice to obtain the result. Th e first reading
returns the low byte of the 16-bit data, and the second reading returns the
high byte. Reading the A/D FIFO removes the A/D con v ersion result from
the A/D FIFO. If the DAVAIL bit is cleared, then the A/D FIFO is empty
and further reading of the A/D FIFO returns meaningless data.

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National Instruments Corporation 3-7 Lab-PC-1200/AI RLPM

Chapter 3 Programming

Programming a DAQ Operation Using Internal Timing

A sequence of timed A/D conversions is referred to in this manual as a
DAQ operation. The parameters of concern in a DAQ operation are the
sample interval, scan interval, and the total number of samples. A sample
interval indicates the time to elapse between A/D conversions on each
channel in the sequence. The scan interval is the time that elapses between
the channel-scanning cycles. The scan interval is only used in interval
scanning mode. There are four different internal counters that can help you
time these parameters—counter A0, counter A1, counter B0, and
counter B1. There are three different DAQ operation modes—interval
scanning, controlled, and freerun acquisition mode. The Lab-PC-1200/AI
can perform both single-channel data acquisition and multiple-channel data
acquisition.

In a controlled acquisition mode, only one counter is required to time the
sample intervals. In this mode, you can perform a specified number of
conversions, after which the hardware ends the DAQ operation. The
number of conversions in a single DAQ operation in this case is limited to
a 16-bit count (or 65,535 samples). Use counter A0 to time the sample
intervals without any delays. Use counter A1 as the sample counter. Each
sample is taken with the same sample interval. Counter A0 is clocked by a
1 MHz clock. The period of counter A0, or the sample interval, is equal to
the value programmed into counter A0 multiplied by 1µs. The minimum
period that can be selected for counter A0 is 2 µs. The sample interval
period, or Counter A0, must be at least 10 µs to avoid an overrun error.
Choose your sample interval according to the specifications in Chapter 4,
Theory of Operation, of your Lab-PC-1200/AI User Manual, to maintain
12-bit accuracy.

In freerun acquisition mode, only one counter is required for a DAQ
operation. Counter A0 continuously generates the conversion pulses as
long as GATEA0 is held at a high logic level. The software keeps track of
the number of conversions that ha ve occurred and turns off counter A0 after
the required number of conversions hav e been obtained or after some other
user-defined criteria hav e been met. The number of con v ersions in a single
DAQ operation in this case is unl im ited.

In an interval scanning acquisition mode, you need two counters. Use
counter B1 to time the scan interval. Within the scan interval, each
conversion occurs at reg ular sample in tervals timed by counter A0. In
multiple-channel data acquisition, the conversions stop after the sample
counter A1 counts down to 0. In single-channel interval data acquisition,
the conversions stop after the programmed count in the Interval Counter

Lab-PC-1200/AI RLPM 3-8

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Chapter 3 Programming

Register has expired. An interval scanning DAQ operation consists of
back-to-back scan intervals. Counter B1 is clocked by the same timebase
used for counter A0. If the 1 MHz clock is used for the timebase of counter
A0, then the period of counter B1, or the scan interval, is the value
programmed into counter B1 times 1 µs.

Alternatively, a programmable timebase for counter A0 is available by
using counter B0. Counter B0 has a fixed, unalterable 2 MHz clock as its
own timebase. Therefore, its period is the value programmed into counter
B0 multiplied by 500 ns. The minimum period that can be selected for
counter B0 is 1 µs. The period of counter A0, or the sample interval, is then
equal to the period of counter B0 multiplied by the value programmed into
counter A0. The maximum sample interval is approximately 35 minutes.
You can use counter B0 in any DAQ operation as an alternative timebase
for the sample interval.

Programming a DAQ operation requires setting up th e four available
counters, setting up the Interval Counter Register in single-channel interval
scanning mode, and then triggering the DAQ operation. If you are using
counter B0 or counter B1 internally for a DAQ operation, be sure that
GATB0 or GATB1 are not being driven externally through the
I/O connector or are being driven high. Perform the following steps to
program a DAQ operation:

1. Clear the analog input circuitry.

2. Configure the analog input circuitry.

3. Set up the four available counters (and the Interval Counter Register
if necessary).

4. Trigger the operation.

5. Service the operation.

Perform the configuration steps and clear the analog input circuitry
as described in Programming the Analog Input Circuitry for

Single A/D Conversions section of this chapter.

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National Instruments Corporation 3-9 Lab-PC-1200/AI RLPM

Chapter 3 Programming

Programming Counter A0 and Counter B0

You must always program counter A0 for a DAQ operation using internal
timing. A high-to-low transition on OUTA0 (counter A0 output) initiates a
conversion. You can program counter A0 to generate a pulse once every
N µs, where N is the value programmed into counter A0 and the clock input
is a 1 MHz signal. The minimum number that you can use for N is 2. The
sample interval can then be programmed to be between 2 µs and 65,535 µs.
Use the following equation to determine the sample interval:

sample interval = N • 1 µs

Use the following sequence to program counter A0, the sample interval
counter. All writes are 8-bit write operations.

1. Write 0x34 (select counter A0, mode 2) to the Counter A Mode
Register.

2. Write the least significant byte of the sample interval (N) to the
Counter A0 Data Register.

3. Write the most significant byte of the sample interval (N) to the
Counter A0 Data Register.

You can achieve a larger option of sample intervals by using counter B0
along with counter A0. The resulting sample interval is then N

multiplied by 500 ns, where Nb is the value programmed into counter

by N

a

B0 and N
can then be programmed to be between 2 µs and [(65,535)
following equation to determine the sample interval:

is the value programmed into counter A0. The sample interval

a

multiplied

b

2

/2]µs. Use the

sample interval = Na • Nb • 500 ns

Use the following programming sequence to program counter B0 as an
alternative timebase for counter A0. All writes are 8-bit operations.

1. Set the TBSEL bit in Command Register 2.

2. Write 0x36 (select counter B0, mode 3) to the Counter B Mode
Register.

3. Write the least significant byte of the sample interval (N
Counter B0 Data Register.

4. Write the most significant byte of the sample interval (N
Counter B0 Data Register.

Lab-PC-1200/AI RLPM 3-10

) to the

b

) to the

b

©

National Instruments Corporation

Programming Counter A1

You must program counter A1 even if you are planning on doing a freerun
DAQ operation. In a freerun DAQ operation, set the output of counter A1
low to gate counter A0 on and thus allow conversions to occur. The number
of samples you want to acquire in a controlled DAQ operation is equal to
N + 2, where N is the value programmed into counter A1. Therefore the
number of samples can range from 3 to 65,537. Use the following equation
to determine the number of samples:

Use the following sequence to program counter A1. All writes are 8-bit
operations.

1. Write 0x70 (select counter A1, mode 0) to the Counter A Mode
Register. This step sets the output of counter A1 (OUTA1) low.

Chapter 3 Programming

number of samples = N + 2

Note

Continue to steps 2 and 3 only for controlled DAQ operations.

2. Write the least significant byte of the sample count (N) to the
Counter A1 Data Register.

3. Write the most significant byte of the sample count (N) to the
Counter A1 Data Register.

Programming Counter B1 and the Interval Counter Register

If you are doing interval scanning data acquisition, you must program
counter B1. CLKB1 (the clock input of counter B1) is the same as that used
for counter A0 in order to synchronize the individual conversions and the
scan interval. The scan interval is equal to N (the value programmed into
counter B1) multiplied by the clock period used for counter A0. The
scan interval should be longer than the total conversion time. In a
multiple-channel interval DAQ operation, the total conversion time is equal
to the number of channels being scanned, multiplied by the sample interval.
In a single-channel interval DAQ operation, the total conversion time is
equal to the number loaded into the Interval Counter Register, multiplied
by the sample interval.

For single-channel interval scanning data acquisition, the number that you
program into the Interval Counter Register should be smaller than the total
number of desired samples. For example, if you want to acquire 2,000
samples in batches of 100, load the Interval Counter Register with 100 and
the sample counter (counter A1) with 2,000. In this example, 20 scan
intervals are required to convert 2,000 samples. The Interval Counter
Register is an 8-bit register. Therefore, you can convert up to 255 samples

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National Instruments Corporation 3-11 Lab-PC-1200/AI RLPM

Chapter 3 Programming

in a single scan interval. Use the following sequence to program the Interval
Counter Register:

1. Write the desired number of samples of a single channel that will be
acquired during a scan interval to the Interval Counter Data Register.

2. Write 0x01 to the Interval Counter Strobe Register to latch the Interv al
Counter Register.

Use the following sequence to program counter B1 for interval data
acquisition. All of the writes are 8-bit operations.

1. Set the INTSCAN bit in Command Register 4.

2. Clear the EOIRCV bit in Command Register 4.

3. Write 0x74 (select counter B1, mode 2) to the Counter B Mode
Register.

4. Write the least significant byte of the scan interval (N) to the
Counter B1 Data Register.

5. Write the most significant byte of the scan interval (N) to the
Counter B1 Data Register.

Triggering the DAQ Operation

To start the DAQ operation, set the SWTRIG bit in Command Register 2,
which enables counter A0 to start counting. In a freerun DAQ operation
(or in any other type of DAQ operation in which you want to stop the
operation prematurely), you can stop the DAQ operation by clearing the
SWTRIG bit.

Note

In interval DAQ operations, the first scan interval is not synchronized with
counter B1. Therefore you may wish to discard the conversions acquired in
the first scan interval.

Servicing the DAQ Operation

When you start a DAQ operation, you must service the operation by
reading the A/D FIFO Register. You can either read the A/D FIFO every
time a conversion is available or when the A/D FIFO is half full. You
read the A/D FIFO as explained in the section Performing Single A/D
Conversions. You can also use interrupts to service the DAQ operation.
In order to process interrupts, you must install an interrupt handler. See
Programming Options earlier in this chapter for information on installing
interrupt handlers.

Lab-PC-1200/AI RLPM 3-12

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National Instruments Corporation

Chapter 3 Programming

Two error conditions, overflow or overrun, may occur during a DAQ
operation. If these error conditions occur, the OVERFLOW and/or the
OVERRUN bits are set in Status Register 1. Check these bits every time
you read Status Register 1 to check the DAVAIL bit.

An overflow condition occurs if more than 4,096 A/D conversions have
been stored in the A/D FIFO without the A/D FIFO being read; that is, the
A/D FIFO is full and cannot accept any more data. This condition occurs if
the software loop reading the A/D FIFO is not fast enough to keep up with
the A/D conversion rate. When an overflow occurs, at least one A/D
conversion result is lost.

An overrun condition occurs if a second A/D conv ersion is initiated before
the previous conversion is finished. This condition may result in one or
more missing A/D conversions. This condition occurs if the sample interval
is smaller than the conversion time of the ADC, which is 10 µs.

Programming a DAQ Operation Using External Timing

You can use three external timing signals, EXTTRIG, EXTCONV* and
OUTB1, to time a DAQ operation. Use EXTTRIG to initiate a DAQ
operation (posttrigger mode) or to terminate an ongoing DAQ operation
(pretrigger mode). In posttrigger mode, you use EXTTRIG in place of
writing to the SWTRIG bit in Command Register 2. Use the EXTCONV*
signal to time the individual A/D conversions in place of counter A0. If you
are performing an interval-scanning DAQ operation and are timing the
individual A/D conversions using EXTCONV*, you must time the scan
interval through OUTB1 in place of using counter B1. For signal
specifications of these external timing signals, see Chapter 3, Signal
Connections, in the Lab-PC-1200/AI User Manual.

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National Instruments Corporation 3-13 Lab-PC-1200/AI RLPM

Chapter 3 Programming

Programming a DAQ Operation Using EXTCONV*

If you want to use EXTCONV* instead o f co unter A0 for sample-interval
timing, you can follow the same sequence of steps described in

Programming a DAQ Operation Using Internal Timing, except for

programming counters A0 and B0. Replace the steps for programming
counters A0 and B0 with the following sequence.

1. Write 0x34 (select counter A0, mode 2) to the Counter A Mode
Register.

2. Clear the ECLKRCV bit in Command Register 4.

You must set up counter A0 to force OUTA0 high and enable conversions
initiated by EXTCONV*. You also need to ensure that the ECLKRCV bit
in Command Register 4 is cleared to enable EXTCONV*.

Note

After you trigger the DAQ operation, using either SWTRIG or EXTTRIG in
posttrigger mode, the first EXTCONV* pulse may not cause an A/D conversion.
See Chapter 3, Signal Connections, in the Lab-PC-1200/AI User Manual for
specifications regarding EXTCONV*.

Programming a DAQ Operation Using EXTTRIG in Posttrigger Mode

If you want to use EXTTRIG in posttrigger mode instead of SWTRIG
to trigger a DAQ operation, you can follow the same sequence of steps
described in Programming a DAQ Operation Using Internal Timing except
for the section describing triggering of the DAQ operation. Use the
following sequence to trigger a DAQ operation using EXTTRIG:

1. Set the HWTRIG bit in Command Register 2.

2. Trigger a DAQ operation with a rising edge on EXTTRIG.

When you set the HWTRIG bit in Command Register 2, the next rising
edge on EXTTRIG will trigger a DAQ operation. Further transitions on
EXTTRIG do not affect anything. In a freerun DAQ operation (or in a
controlled DAQ operation triggered by EXTTRIG in which you want to
stop the operation prematurely), you can stop conversions by first clearing
the HWTRIG bit in Command Register 2 and then writing to the A/D FIFO
Clear Register. After writing to the A/D FIFO Clear Register, any
remaining data in the FIFO will have been cleared.

Lab-PC-1200/AI RLPM 3-14

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National Instruments Corporation

Chapter 3 Programming

Programming a DAQ Operation Using EXTTRIG in Pretrigger Mode

If you want to use EXTTRIG in a pretrigger mode, you must trigger the
DAQ operation using SWTRIG, and you must program counter A1 as
described in Programming a DAQ Operation Using Internal Timing.
However, the number of samples that you want to occur after the
EXTTRIG trigger is equal to N + 1, where N is the programmed count in
counter A1. The number of samples that can occur after the EXTTRIG
trigger ranges from 3 to 65,536. Use the following sequence to use
EXTTRIG in a pretrigger mode:

1. During configuration of the analog input circuitry, set the PRETRIG
bit in Command Register 2.

2. Clear the analog input circuitry, program the appropriate counters, and
trigger the DAQ operation as described in Programming a DAQ

Operation Using Internal Timing.

3. Gate on counter A1 with a low-to-high transition on EXTTRIG.

The first rising edge on EXTTRIG should occur after you trigger the DAQ
operation using SWTRIG. This rising edge gates on counter A1. The DAQ
operation stops after the programmed count in counter A1 has expired.

Programming a DAQ Operation Using OUTB1

If you want to drive your own interval-scanning pulse on OUTB1 instead
of using counter B1 to time the scan interval, you can follow the same
sequence of steps as described in Programming a DAQ Operation Using

Internal Timing, except for the section describing the programming of

counter B1. Use the following sequence of steps to use OUTB1 in place
of counter B1:

1. Program the Interval Counter Register (if necessary).

2. Set the INTSCAN bit in Command Register 4.

3. Set the EOIRCV bit in Command Register 4.

If you want to externally time the scan interval, you should also externally
time the sample interval through EXTCONV* to synchronize the sample
interval and the scan interval. Refer to Chapter 3, Signal Connections, in
the Lab-PC-1200/AI User Manual for timing specifications.

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National Instruments Corporation 3-15 Lab-PC-1200/AI RLPM

Chapter 3 Programming

DAQ Interrupt Programming

Five different interrupts can be generated by the analog input circuitry, as
follows:

• When a conversion is available to be read from the A/D FIFO

• When the A/D FIFO is half full

• When an error condition (overflow or overrun) is detected

• When a DAQ operation is terminated by counter A1

• When a DMA TC pulse is received
You can enable these five interrupts individually.
Set the FIFOINTEN bit in Command Register 3 to enable interrupt

generation when a conv ersion is av ailable to be read from the A/D FIFO. If
FIFOINTEN is set, an interrupt is generated whenever the DAVAIL bit in
Status Register 1 is set.

Set the HFINTEN bit in Command Register 6 to enable interrupt generation
when the A/D FIFO becomes half full (2,048 samples). If HFINTEN is set,
an interrupt is generated whenever the FIFOHF* bit is cleared in Status
Register 2.

Set the ERRINTEN bit in Command Register 3 to enable interrupt
generation when an error condition is detected. If ERRINTEN is set, an
interrupt is generated whenever either the O VERFLOW or O VERR UN bits
are set in Status Register 1.

Set the DQINTEN bit in Command Register 6 to enable interrupt
generation when a DAQ operation is terminated by counter A1. If
DQINTEN is set, an interrupt is generated whenever OUT A1 is set in Status
Register 2.

Set the TCINTEN bit in Command Register 3 to enable interrupt generation
when a DMA TC is received. If TCINTEN is set, an interrupt is generated
whenever DMA TC is set in Status Register 1.

Lab-PC-1200/AI RLPM 3-16

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National Instruments Corporation

DAQ DMA Programming

You can program the Lab-PC-1200/AI so that the FIFO generates a DMA
request whenever one or more A/D conversions are available in the FIFO.
To use DMA, the AT DMA controller must be properly configured.
Perform the following steps to configure the board.

1. Configure the analog input circuitry.

2. Set the DMAEN bit in Command Register 3.

3. Program the AT DMA controller.

4. Trigger the operation.

The DMA controller automatically transfers data from the AI FIFO into a
buffer in system memory when properly configured.

Programming the Analog Output Circuitry
(Lab-PC-1200 Only)

This section explains how to configure the analog output circuitry and how
to update the analog output voltage.

Chapter 3 Programming

Configuring the Analog Output Circuitry

You must configure the analog output circuitry after initializing the
Lab-PC-1200/AI and anytime the characteristics of the analog output
signals change. Program the appropriate register bits as follows:

1. Select the output polarity (unipolar or bipolar) and the coding of the
digital code (straight binary or two’s complement).

2. Set or clear the DAC1UNI/BI* and DAC0UNI/BI* bits in Command
Register 6 and the 2SD A C1 and 2SD A C0 bits in Command Re gister 2.

If you select a unipolar output polarity, the straight binary coding is
recommended. If you select a bipolar output polarity, the tw o’s complement
coding is recommended.

Use the following formula to calculate the output voltage versus digital
code for a unipolar analog output configuration and straight binary coding.
The digital code is a decimal value ranging from 0 to +4,095.

Code

= 10.0 •

V

out

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National Instruments Corporation 3-17 Lab-PC-1200/AI RLPM

-------------- -

4 096,

Chapter 3 Programming

The following formula calculates the output voltage versus digital code for
a bipolar analog output configuration and two’s complement coding. The
digital code is a decimal value ranging from –2,048 to +2,047.

Code

V

out

= 5.0 •

-------------- -

2048,

Tables 3-1 and 3-2 show the analog output voltage versus the input digital
code in unipolar and bipolar mode, respectively.

Table 3-2.

Analog Output Voltage Versus Digital Code

(Unipolar Mode, Straight Binary Coding)

Digital Code

Voltage OutputDecimal Hex

0 0000 0 V

1 0001 2.4414 mV
2,048 0800 5.0 V
4,095 0FFF 9.9976 V

Table 3-3.

Analog Output Voltage Versus Digital Code

(Bipolar Mode, Two’s Complement Coding)

Digital Code

Voltage OutputDecimal Hex

–2,048 F800 –5.0 V
–1,024 FC00 2.5 V

0 0000 0.0 V
1,024 0400 2.5 V
2,047 07FF 4.9976 V

Programming the Update Mode of the Analog Output Circuitry

The analog output circuitry on the Lab-PC-1200/AI uses double-buffered
DACs. Therefore the output voltages (DAC0OUT and DAC1OUT on the
I/O connector) do not have to be updated immediately with each write to
the DAC Data Registers. You can update the analog output in

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Lab-PC-1200/AI RLPM 3-18

National Instruments Corporation

Chapter 3 Programming

synchronization with counter A2 or the external update timing signal
EXTUPDATE*. This is useful for waveform generation applications
because the timed update pulses eliminate the timing jitter associated with
software writes to the DAC Data Registers.

You can operate the analog output circuitry in three ways—immediate
update, update on OUTA2, or update on EXTUPDATE*.

Use the following sequence to program for immediate update mode:

1. Clear the LDAC1 or LDAC0 bit in Command Register 2.

2. Write the low byte to the DAC0 or DAC1 Low-Byte Register.

3. Write the high byte to the DAC0 or DAC1 High-Byte Register.
The analog output voltage is updated immediately after you write the high

byte to the DAC0 or DAC1 High-Byte Register.
Use the following sequence to program for update on OUT A2 or

EXTUPDATE*.

1. Set the LDAC1 or LDAC0 bit in Command Register 2.

2. Set the CNTINTEN bit in Command Register 3 to enable timer
interrupts.

3. Program counter A2.

4. Service the interrupts for waveform generation.

Y ou must program counter A2 e ven if you are using EXTUPDATE*. If you
are using EXTUPDATE*, you must set OUTA2 high to enable updates
caused by EXTUPDATE*. If you are using counter A2, do not drive
EXTUPDATE* externally or, if you do, drive it high. You can not block
EXTUPDATE* through software. The clock for counter A2 is the same as
that used for counter A0, so you can use a 1 MHz clock or the output of
counter B0 to clock counter A2. The update period is equal to the value
programmed into counter A2 times the period of the clock. You should set
the update period to be longer than the time it takes to write a new value to
the DAC Registers. Use the following sequence to program counter A2.

1. Write 0xB4 (select counter A2, mode 2) to the Counter A Mode
Register.

Note Continue to steps 2 and 3 if you are using counter A2 to update the analog output

circuitry.

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National Instruments Corporation 3-19 Lab-PC-1200/AI RLPM

Chapter 3 Programming

2. Write the least significant byte of the update period to the Counter A2
Data Register.

3. Write the most significant byte of the update period to the Counter A2
Data Register.

The update cycle starts immediately after you write the most significant
byte to the Counter A2 Data Register. If you are using EXTUPD ATE*, the
update cycle starts after setting OUT A2 high and on the first falling edge of
EXTUPDA TE*.

DAC Interrupt Programming

Set the CNTINTEN bit in Command Register 3 to enable interrupt
generation on the rising edge of either OUTA2 or EXTUPDATE*. If
CNTINTEN is set, then an interrupt is generated whenever the CNTINT bit
in Status Register 1 is set.

You service this interrupt by writing a new value to DAC0 or DAC1
Low-Byte and High-Byte Registers. To clear the interrupt, write to the
Timer Interrupt Clear Register. This allows continuous waveform
generation. The DAC output voltage is then updated by a high-to-low
transition on either OUTA2 or EXTUPDATE*.

Programming the Digital I/O Circuitry

Digital I/O on the Lab-PC-1200/AI uses the 82C55A integrated circuit.
Programming the digital I/O circuitry involves setting the mode of the
82C55A by writing to the Digital Control Register and then writing and
reading from the three port registers (port A, port B, and port C). The
various modes of the 82C55A are illustrated in Appendix D, OKI

MSM82C55A Data Sheet. Examples for using the digital I/O circuitry are

in the Lab-PC-1200/AI User Manual.
You can generate interrupts through PC0 and PC3 on the I/O connector.

Enable digital I/O interrupts by setting the DIOINTEN bit in Command
Register 3. There are no status bits associated with the digital I/O interrupts.
You clear this interrupt by clearing PC0 and PC3.

Lab-PC-1200/AI RLPM 3-20

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National Instruments Corporation

Chapter 3 Programming

Programming the General-Purpose Counter/Timers

You can use Counter/Timer Group B of the 82C53 timing circuitry as
general-purpose counters when they are not being used for internal timing.
To program the general-purpose counters, set the mode of the 82C53 by
writing to the Counter B Mode Register, then write and read from the three
data registers (counter B0, counter B1, and counter B2). See Appendix C,

OKI MSM82C53 Data Sheet for information on the various modes of the

82C53. Examples for using the general-purpose counters are given in the
Lab-PC-1200/AI User Manual. You cannot generate interrupts with the
general-purpose counter/timers.

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National Instruments Corporation 3-21 Lab-PC-1200/AI RLPM

Calibration

4

This chapter contains instructions for creating user-defined calibration
constants for the Lab-PC-1200/AI CALDACs. This information is
important if you do not want to use NI-DAQ to create user-defined
calibration constants to be stored in the user areas of the Lab-PC-1200/AI
EEPROM. Since the calibration process is quite complicated, the user is
advised to use NI-DAQ whenever possible. If NI-DAQ does not support
your operating system, only then should you try to write register-level code
to perform calibration. Also, if you accidentally overwrite the factory area,
you will permanently lose factory-calibration information, and may have to
send your unit back to National Instruments for recalibration.

Note

National Instruments is not liable for accidental overwriting of the calibration
EEPROM in the field.

For information concerning writing register-level programs to write to
the CALDACs, refer to Chapter 3, Programming. For information on
calibration equipment requirements, refer to the Lab-PC-1200/AI User
Manual.

Storing User-Defined Constants

You should store only one set of user-defined calibration constants in one
user area. One set of calibration constants consists of twenty constants, six
for CALDACs 3, 4 and 7–10, seven for CALDAC6, and seven for
CALDAC5 (one at each gain setting). Therefore, one set of calibration
constants can calibrate the Lab-PC-1200/AI analog input and analog output
circuitry in either bipolar or unipolar polarity and at all gains.

Store your user-defined calibration constants in the same format as that
shown for the factory-defined calibration constants in Table 4-1. For
example, if you use user area 1, store the calibration constants for
CALDA Cs 3–10 in EEPROM addresses 117–110, then store the seven gain
constants for CALDA C6 in EEPROM locations 109–102, followed by the
seven postgain offset values for each gain in locations 101–94. Table 4-3
shows the Lab-PC-1200/AI EEPROM map.

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National Instruments Corporation 4-1 Lab-PC-1200/AI RLPM

Chapter 4 Calibration

Note that the location for gain 1.25 is provided; however , the corresponding
value is ignored. Also note that within each user area, the AI CALDAC 3
value is the analog input gain calibration constant for the gain at which
the calibration is performed. This value must also be duplicated in the
corresponding location in the GAIN X value in that user area. For example,
if the calibration is performed at gain = 5, then the calibration constant must
be written in both locations 114 and 106 for user area 1. Similarly, the
postgain offset value for that gain must be duplicated in the corresponding
GAIN X value-offset location.

When the Lab-PC-1200/AI is shipped, the contents of factory area for
bipolar mode are copied in all the user areas. Consequently, there will be
constants in the user areas that will be very accurate when the
Lab-PC-1200/AI is used in the bipolar mode for both analog input and
output.

T o sa v e your user -defined calibration constants in the EEPROM, you need
programming instructions for writing to the EEPROM. Use the following
sequence of steps to store a calibration constant to the EEPROM. For
information on user areas in the EEPROM, refer to the EEPROM memory
map at the end of this chapter.

1. Set the EEPROMCS and WRTPRT* bits in Command Register 5.

2. Serially write the WRITE instruction, 0x06, to the EEPROM to enable
a write operation.

3. Clear the EEPROMCS bit in Command Register 5.

4. Set the EEPROMCS bit in Command Register 5.

5. Serially write the WRITE instruction, 0x02, to the EEPROM to start a
write operation.

6. Serially write the 8-bit user area address to the EEPROM.

7. Serially write the 8-bit calibration constant to the EEPROM.

8. Clear the EEPROMCS and WRTPRT* bits in Command Register 5.

Repeat the following two steps eight times to serially write one byte to the
EEPROM.

1. Clear the SCLK bit in Command Register 5. Write a single bit of the
8-bit value, MSB first, by setting or clearing the SDATA bit in
Command Register 5.

2. Set the SCLK bit in Command Register 5.

Lab-PC-1200/AI RLPM 4-2

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National Instruments Corporation

After you store a single calibration constant, you must wait a minimum of
10 ms before accessing the EEPROM again. Alternati vely , you may use the
RDSR (Read status register) instruction of the X25020 and poll the WIP
(write-in-process) bit. If this bit is 1, then the previous write is still in
progress. You must wait until this bit reads 0, then you may proceed with
the next write.

Calibration DACs

There are eight 8-bit calibration DACs (CALDACs) on the
Lab-PC-1200/AI that are used for calibration. These DACs are described
in Tables 4-1 and 4-2 for analog input and output calibration respectively.
The tolerance in both tables is simply the adjustment range divided by 255
(8-bit). In Table 4-1, V
provide during the gain calibration procedure. In Table 4-2, V
the voltage that you write to either DAC0 or DAC1 during the gain
calibration procedure.

Chapter 4 Calibration

refers to the reference voltage value that you

ref

refers to

ref

Table 4-1.

Calibration DAC Characteristics for Analog Input Circuitry

DAC Name Function Adjustment Range To lerance

CALDAC3 Pregain offset, coarse 820 LSBs (gain = 100) 3.2 LSBs
CALDAC4 Pregain offset, fine 8 LSBs (gain =100) 0.04 LSBs
CALDAC5 Postgain offset 82 LSBs 0.32 LSBs
CALDAC6 Gain 2% of V

Table 4-2.

Calibration DAC Characteristics for Analog Output Circuitry

ref

0.008% of V

DAC Name Function Adjustment Range To lerance

CALDAC7 Offset, DAC0 31 LSBs 0.12 LSBs
CALDAC8 Gain, DAC0 2% of V

ref

0.008% of V
CALDAC9 Offset, DAC1 31 LSBs 0.12 LSBs
CALDAC10 Gain, DAC1 2% of V

ref

0.008% of V

ref

ref

ref

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National Instruments Corporation 4-3 Lab-PC-1200/AI RLPM

Chapter 4 Calibration

Analog Input Calibration

To null out error sources, you must calibrate the analog input circuitry by
adjusting the following potential sources of error (not necessarily in this
order):

• Offset error at the input of the instrumentation amplifier.

• Offset error at the input of the ADC.

• Gain error of the analog input circuitry.
Offsets at the input to the instrumentation amplifier contribute

gain-dependent error to the analog input system. This offset is multiplied
by the gain of the instrumentation amplifier. To calibrate this offset, you
must ground the inputs of the instrumentation amplifier, measure the input
at two different gains, and adjust CALDAC3 and CALDAC4 until the
measured offset in LSBs is independent of the gain setting. Calibration of
this pregain offset is done in bipolar mode for both bipolar and unipolar
analog input configurations.

Offset error at the input of the ADC is the total of the voltage offsets
contributed by the circuitry from the output of the instrumentation amplifier
to the ADC input (including the ADC’s own offsets). Offset errors appear
as a voltage added to the input voltage being measured. To calibrate this
offset, you must connect either AGND in bipolar mode or an external
voltage source in unipolar mode to the inputs of the ADC and adjust
CALDAC5 un til the measured voltage is equal to either AGND or
(external voltage source + gain error) respectively.

If the three analog input offset DACs are adjusted in this way, there is no
significant residual offset error , and reading a grounded channel returns, on
average, less than 0.5 LSB regardless of the gain setting.

All the stages up to and including the input of the ADC contribute to the
gain error of the analog input circuitry. With the instrumentation amplifier
set to a gain of 1, the gain of the analog input circuitry is ideally 1. The gain
error is the deviation of the gain from 1 and appears as a multiplication of
the input voltage being measured. T o eliminate this error source, you must
measure the input first with the inputs grounded and then with the inputs
connected to the external voltage source. Then adjust CALD AC6 until the
measured difference between the two voltages is equal to the value of the
external voltage source. After the Lab-PC-1200/AI is calibrated at a gain
of 1, there is only a small residual gain error (±0.5% max) at the other
gains. To reduce this error, calibrate the board at all other gains and for
corresponding values stored in the EEPROM User gain area.

Lab-PC-1200/AI RLPM 4-4

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National Instruments Corporation

In both bipolar and unipolar modes, calibration of postgain offset does not
affect the gain characteristics. However, gain calibration does affect
postgain offset. Therefore, you must perform gain calibration before
postgain calibration.

Perform the calibration procedure for both bipolar and unipolar mode with
dither enabled (by setting the DITHEREN bit in Command Register 5) and
in referenced single-ended mode (clear the RSE*/NRSE bit in Command
Register 6 and the SE*/DIFF bit in Command Register 4). Refer to
Table 4-1 for calibration tolerances.

Bipolar Input Calibration Procedure

If your board is configured for bipolar input, which provides the –5 to +5 V
range, complete the following procedures. This procedure assumes that
ADC readings are in the –2,048 to +2,047 range; that is, you have selected
the two's complement coding scheme.

Because adjusting the gain affects the postgain offset adjustment, you must
calibrate gain before calibrating postgain offset. Also, initialize all of the
CALDACs for an alog input (3, 4, 5, and 6) to 128 before starting the
calibration procedure. This sets each CALDAC at midscale.

Chapter 4 Calibration

Pregain Offset Coarse Calibration

1. Connect ACH0 (pin 1 on the rear panel 50-pin I/O connector) to
AGND (pin 11).

2. Take 1,024 readings from channel 0 at a gain of 1. Take the mean of
these readings and call it mean1.

3. T ake 1,024 readings from channel 0 at a gain of 100. Take the mean of
these readings and call it mean100.

4. Adjust CALDAC3 so that:
|mean1 - mean100| ≤ pregain offset coar se calibration tolerance.

Pregain Offset Fine Calibration

1. Repeat steps 1–3 of the pregain offset coarse procedure.

2. Adjust CALDAC4 so that:
|mean1 - mean100| ≤ pregain offset fine calibration tolerance.

At this point, the pregain offset is nulled out. However, there is a residual
postgain offset remaining.

©

National Instruments Corporation 4-5 Lab-PC-1200/AI RLPM

Chapter 4 Calibration

Gain Calibration

1. T ake 1,024 samples from channel 0 (still connected to AGND) at a gain
of 1. Take the mean and call it postgain_offset.

2. Connect the voltage reference (V
(pin 11). Choose a voltage reference between 3.0 and 4.5 V.

3. Take 1,024 samples from channel 1 at a gain of 1. Take the mean and
call it mean1.

4. Adjust CALDAC6 so that:
|(mean1 - postgain_offset) - • 2,047| ≤ gain calibration

tolerance.

) between ACH1 (pin 2) and A GND

ref

Vref

---------- -

5V

Postgain Offset Calibration

1. T ake 1,024 samples from channel 0 (still connected to AGND) at a gain
of 1. Take the mean and call this postgain_offset.

2. Adjust CALDAC5 so that:
|postgain_offset| ≤ postgain calibration tolerance.

Calibration at Higher Gains

If you have performed gain calibration at a gain of 1 and the gain is changed
to a value not equal to 1 (2, 5, 10, 20, 50, or 100), you will get a maximum
gain error of 0.5%. In addition, the postgain offset will change, so you must
recalibrate both the postgain offset (CALDAC5) as well as gain
(CALDAC6) at that gain. If you perform gain and postgain offset
calibrations at all other gains and store these values in the EEPROM, the
maximum gain error will be 0.02% at all gains. Follow the same steps as
given in the Gain Calibration section, but use a gain not equal to 1.

Note

When you use a gain not equal to 1, remember that the voltage reference (V
multiplied by the gain should be less than 4.5 V.

Unipolar Input Calibration Procedure

If your board is configured for unipolar input, which has an input range of
0 to +10 V, complete the following steps. This procedure assumes that your
ADC readings are in the 0 to 4,095 range; that is, you have selected the
straight binary coding scheme.

In unipolar mode, the offset can be negative and while doing offset
adjustment, all of the acquired samples can be 0 V . This results in incorrect
offset calibration. To correct this problem, initialize CALDAC5 to 0 to

Lab-PC-1200/AI RLPM 4-6

ref

©

National Instruments Corporation

)

Chapter 4 Calibration

create a maximum positive offset. Initialize the other CALDACs (3, 4,
and 6) to 128 as before.

Pregain Offset Calibration

Follow the same steps as in the Bipolar Input Calibration Procedure
section for pregain offset coarse and pregain offset fine calibration.
Remember to configure the analog input for bipolar mode when performing
pregain offset calibration. Reconfigure the analog input for unipolar mode
for gain and postgain offset calibration.

After the pregain offset calibration, there will be a residual positive
postgain offset remaining because the postgain CALDAC is biased to one
extreme.

Gain Calibration

For gain calibration, use the following procedure:

1. T ake 1,024 samples from channel 0 (still connected to AGND) at a gain
of 1. Take the mean and call it postgain_offset.

2. Connect the voltage reference (V
(pin 11). Choose a voltage reference between 8.0 and 9.5 V.

3. Take 1,024 samples from channel 1 at a gain of 1. Take the mean and
call it mean1.

4. Adjust CALDAC6 so that:
|(mean1 - postgain_offset) - • 4,095| ≤ gain calibration

tolerance.

) between ACH1 (pin 2) and A GND

ref

Vref

---------- -

10V

Perform the calibration for gains not equal to 1 as you did for bipolar input.
Remember that the voltage reference (V

) multiplied by the gain used

ref

should be less than 9.5 V.

Postgain Offset Calibration

For postgain offset calibration, use the following procedure:

1. Take 1,024 samples from channel 1 (still connected to V
of 1. Take the mean and call this mean1.

2. Adjust CALDAC5 so that:
|mean1| ≤ postgain calibration tolerance.

©

National Instruments Corporation 4-7 Lab-PC-1200/AI RLPM

) at a gain

ref

Chapter 4 Calibration

Analog Output Calibration (Lab-PC-1200 Only)

To null out error sources that affect the accuracy of the output voltages
generated, you must calibrate the analog output circuitry by adjusting the
following potential sources of error.

• Analog output offset error

• Analog output gain error
Offset error in the analog output circuitry equals the total of the voltage

offsets contributed by each component in the circuitry. This error appears
as a voltage difference between the desired voltage and the actual output
voltage generated and is independent of the D/A v oltage setting. To correct
this offset error, the routine sets the D/A to 0 V and adjusts CALDAC7 or
CALDAC9 (for DAC0 or DAC1 respectively) until the output voltage
is 0 V.

Gain error in the analog output circuitry is the product of the gains
contributed by each component in the circuitry. This error appears as a
voltage difference between the desired voltage and the actual output
voltage generated and is dependent on the D/A voltage setting. To correct
this gain error, the routine sets the D/A to a positive voltage (V
adjusts CALDA C8 or CALD A C10 (for D A C0 or D A C1 respecti vely) until
the output voltage corresponds to V

.

ref

) and

ref

You must calibrate the analog input circuitry before calibrating the analog
output circuitry because the output calibration procedure depends on the
analog input circuitry. Also, for analog output calibration, set the analog
input circuitry calibration to referenced single-ended (RSE), bipolar mode.
Refer to Tables 4-1 and 4-2 for calibration tolerances.

Bipolar Output Calibration Procedure

If your board is configured for bipolar output, which provides the –5 to
+5 V range, complete the following procedure. This procedure assumes
that DAC coding is in the –2,048 to +2,047 range; that is, you have selected
the two's complement coding scheme.

Initialize all of the CALDACs for analog output (7, 8, 9, and 10) to 128
before you start the calibration procedure. This sets each CALDAC at
midscale. Perform gain calibration before offset calibration.

Lab-PC-1200/AI RLPM 4-8

©

National Instruments Corporation

Gain Calibration

Chapter 4 Calibration

1. Write a value (–V

) to DA C0 or DA C1. Choose a value of V

ref

between

ref

3 and 4.5 V.

2. Take 1,024 readings from analog input channel 2 (still connected to
DAC0OUT or DAC1OUT) at a gain of 1. Take the mean and call it
mean_gain_neg_vref.

3. Write the value V

to DAC0 or DAC1.

ref

4. Take 1024 readings from analog input channel 2 at a gain of 1. Take
the mean and call it mean_gain_vref.

5. Adjust CALDAC8 (or CALDAC10) so that:

Vref

|(mean_gain_ref - mean_gain_neg_ref) - • 4095| ≤ gain
calibration tolerance.

---------- -

5V

Offset Calibration

1. Connect DAC0OUT, pin 10, (or DAC1OUT, pin 12) to analog input
channel 2 (pin 3).

2. Write a 0 to DA C0 (or DAC1).

3. Take 1,024 readings from analog input channel 2 at a gain of 1. Take
the mean and call it offset.

4. Adjust CALDAC7 (or CALDAC9) so that:
|offset| ≤ offset calibration tolerance.

Unipolar Output Calibration Procedure

If your board is configured for unipolar output, which provides the 0 to
+10 V range, complete the following procedure. This procedure assumes
that DAC coding is in the 0 to +4,095 range; that is, you have selected the
straight binary coding scheme.

Set analog input to bipolar mode for analog output unipolar offset
calibration. For gain calibration, set the analog input mode to unipolar.
Initialize all of the CALDACs for analog output (7–10) to 128 before
starting the gain calibration procedure. This sets each CALDAC to
mid-scale.

©

National Instruments Corporation 4-9 Lab-PC-1200/AI RLPM

Chapter 4 Calibration

Gain Calibration

1. Write 0 to DAC0 (or DAC1). Choose a value between 8.0 and 9.5 V.

2. Take 1,024 readings from analog input channel 2 (still connected to
DAC0OUT or DAC1OUT) at a gain of 1. Take the mean and call it
mean_gain_zero.

3. Write the value v

to DA C0 or DA C1. Choose a value between 8.0 and

ref

9.5 V.

4. Take 1,024 readings from analog input channel 2 at a gain of 1. Take
the mean and call it mean_gain_v

.

ref

5. Adjust CALDAC8 (or CALDAC10) so that:

Vref

|(mean_gain_v

- mean_gain_zero) - • 4,095| ≤ gain

ref

calibration tolerance.

---------- -

10V

Offset Calibration

1. Connect DAC0OUT, pin 10, (or DAC1OUT, pin 12) to analog input
channel 2 (pin 3).

2. Write a 0 to DA C0 (or DAC1).

3. Take 1,024 readings from analog input channel 2 at a gain of 1. Take
the mean and call it offset.

4. Adjust CALDAC7 (or CALDAC9) so that:
|offset| ≤ offset calibration tolerance.

EEPROM Map

Table 4-3 shows part of the EEPROM map for the Lab-PC-1200/AI.
Locations 180–255 contain information about the Lab-PC-1200/AI that
NI-DAQ uses. These locations are not shown and you should not access
them. The factory bipolar area contains locations 156–179 and the factory
unipolar area contains 132–155. The user areas are in the lower half of the
EEPROM. The pointers from 120–127 are initialized to point to factory
locations. To use user area calibration data, you must set these pointers to
point to the appropriate user area. Notice that if you point the AI bipolar
frame to user area 1, you must also point the corresponding gain and offset
pointers to the user area 1 gain and offset frames respectively.

Note

Lab-PC-1200/AI RLPM 4-10

NI-DAQ uses these pointers to load a set of calibration constants int o the
CALDA C each time you run a function pertaining to the Lab-PC-1200/AI. Hence,
if you use NI-DAQ along with your register-level code, you must assign these
pointers correctly or NI-DAQ will load incorrect values into the CALDACs.

©

National Instruments Corporation

Chapter 4 Calibration

Table 4-3. Lab-PC-1200/AI EEPROM Map

Location Hex Decimal Description

179 00 0 Factory AI CALDAC0 bipolar value
178 00 0 Factory AI CALDAC1 bipolar value
177 00 0 Factory AI CALDAC2 bipolar value
176 00 0 Factory AI CALDAC3 bipolar value
175 00 0 Factory AO CALDAC4 bipolar value
174 00 0 Factory AO CALDAC5 bipolar value
173 00 0 Factory AO CALDAC6 bipolar value
172 00 0 Factory AO CALDAC7 bipolar value
171 00 0 Factory Gain 1 bipolar value-gain
170 00 0 Factory Gain 1.25 bipolar value-gain
169 00 0 Factory Gain 2 bipolar value-gain
168 00 0 Factory Gain 5 bipolar value-gain
167 00 0 Factory Gain 10 bipolar value-gain
166 00 0 Factory Gain 20 bipolar value-gain
165 00 0 Factory Gain 50 bipolar value-gain
164 00 0 Factory Gain 100 bipolar value-gain
163 00 0 Factory Gain 1 bipolar value-offset
162 00 0 Factory Gain 1.25 bipolar value-offset
161 00 0 Factory Gain 2 bipolar value-offset
160 00 0 Factory Gain 5 bipolar value-offset
159 00 0 Factory Gain 10 bipolar value-offset
158 00 0 Factory Gain 20 bipolar value-offset
157 00 0 Factory Gain 50 bipolar value-offset
156 00 0 Factory Gain 100 bipolar value-offset
155 00 0 Factory AI CALDAC0 unipolar value
154 00 0 Factory AI CALDAC1 unipolar value

©

National Instruments Corporation 4-11 Lab-PC-1200/AI RLPM

Chapter 4 Calibration

Table 4-3. Lab-PC-1200/AI EEPROM Map (Continued)

Location Hex Decimal Description

153 00 0 Factory AI CALDAC2 unipolar value
152 00 0 Factory AI CALDAC3 unipolar value
151 00 0 Factory AO CALDAC4 unipolar value
150 00 0 Factory AO CALDAC5 unipolar value
149 00 0 Factory AO CALDAC6 unipolar value
148 00 0 Factory AO CALDAC7 unipolar value
147 00 0 Factory Gain 1 unipolar value-gain
146 00 0 Factory Gain 1.25 unipolar value-gain
145 00 0 Factory Gain 2 unipolar value-gain
144 00 0 Factory Gain 5 unipolar value-gain
143 00 0 Factory Gain 10 unipolar value-gain
142 00 0 Factory Gain 20 unipolar value-gain
141 00 0 Factory Gain 50 unipolar value-gain
140 00 0 Factory Gain 100 unipolar value-gain
139 00 0 Factory Gain 1 unipolar value-offset
138 00 0 Factory Gain 1.25 unipolar value-offset
137 00 0 Factory Gain 2 unipolar value-offset
136 00 0 Factory Gain 5 unipolar value-offset
135 00 0 Factory Gain 10 unipolar value-offset
134 00 0 Factory Gain 20 unipolar value-offset
133 00 0 Factory Gain 50 unipolar value-offset
132 00 0 Factory Gain 100 unipolar value-offset
131 00 0 Not used
130 00 0 Not used
129 00 0 Not used
128 00 0 Not used

©

Lab-PC-1200/AI RLPM 4-12

National Instruments Corporation

Chapter 4 Calibration

Table 4-3. Lab-PC-1200/AI EEPROM Map (Continued)

Location Hex Decimal Description

127 B3 179 Point to AI bipolar frame
126 A3 155 Point to AI unipolar frame
125 AF 175 Point to AO bipolar frame
124 9F 151 Point to AO unipolar frame
123 AB 171 Poin t to bip olar Gain frame
122 9B 147 Point to unipolar Gain frame
121 00 163 Point to bipolar offset frame
120 00 139 Point to unipolar offset frame
119 00 0 Not used
118 00 0 Not used
117 00 0 User 1 AI CALDAC0 value
116 00 0 User 1 AI CALDAC1 value
115 00 0 User 1 AI CALDAC2 value
114 00 0 User 1 AI CALDAC3 value
113 00 0 User 1 AO CALDAC4 value
112 00 0 User 1 AO CALDAC5 value
111 00 0 User 1 AO CALDAC6 value
110 00 0 User 1 AO CALDAC7 value
109 00 0 User 1 Gain 1 value-gain
108 00 0 User 1 Gain 1.25 value-gain
107 00 0 User 1 Gain 2 value-gain
106 00 0 User 1 Gain 5 value-gain
105 00 0 User 1 Gain 10 value-gain
104 00 0 User 1 Gain 20 value-gain
103 00 0 User 1 Gain 50 value-gain
102 00 0 User 1 Gain 100 value-gain

©

National Instruments Corporation 4-13 Lab-PC-1200/AI RLPM

Chapter 4 Calibration

Table 4-3. Lab-PC-1200/AI EEPROM Map (Continued)

Location Hex Decimal Description

101 00 0 User 1 Gain 1 value-offset
100 00 0 User 1 Gain 1.25 value-offset

99 00 0 User 1 Gain 2 v alue-offset
98 00 0 User 1 Gain 5 v alue-offset
97 00 0 User 1 Gain 10 v alue-offset
96 00 0 User 1 Gain 20 v alue-offset
95 00 0 User 1 Gain 50 v alue-offset
94 00 0 User 1 Gain 100 value-offset
93 00 0 Not used
92 00 0 Not used
91 00 0 User 2 AI CALDAC0 value
90 00 0 User 2 AI CALDAC1 value
89 00 0 User 2 AI CALDAC2 value
88 00 0 User 2 AI CALDAC3 value
87 00 0 User 2 AO CALDAC4 value
86 00 0 User 2 AO CALDAC5 value
85 00 0 User 2 AO CALDAC6 value
84 00 0 User 2 AO CALDAC7 value
83 00 0 User 2 Gain 1 v alue-gain
82 00 0 User 2 Gain 1.25 value-gain
81 00 0 User 2 Gain 2 v alue-gain
80 00 0 User 2 Gain 5 v alue-gain
79 00 0 User 2 Gain 10 v alue-gain
78 00 0 User 2 Gain 20 v alue-gain
77 00 0 User 2 Gain 50 v alue-gain
76 00 0 User 2 Gain 100 value-gain

Lab-PC-1200/AI RLPM 4-14

©

National Instruments Corporation

Chapter 4 Calibration

Table 4-3. Lab-PC-1200/AI EEPROM Map (Continued)

Location Hex Decimal Description

75 00 0 User 2 Gain 1 v alue-offset
74 00 0 User 2 Gain 1.25 value-offset
73 00 0 User 2 Gain 2 v alue-offset
72 00 0 User 2 Gain 5 v alue-offset
71 00 0 User 2 Gain 10 v alue-offset
70 00 0 User 2 Gain 20 v alue-offset
69 00 0 User 2 Gain 50 v alue-offset
68 00 0 User 2 Gain 100 value-offset
67 00 0 Not used
66 00 0 Not used
65 00 0 User 3 AI CALDAC0 value
64 00 0 User 3 AI CALDAC1 value
63 00 0 User 3 AI CALDAC2 value
62 00 0 User 3 AI CALDAC3 value
61 00 0 User 3 AO CALDAC4 value
60 00 0 User 3 AO CALDAC5 value
59 00 0 User 3 AO CALDAC6 value
58 00 0 User 3 AO CALDAC7 value
57 00 0 User 3 Gain 1 v alue-gain
56 00 0 User 3 Gain 1.25 value-gain
55 00 0 User 3 Gain 2 v alue-gain
54 00 0 User 3 Gain 5 v alue-gain
53 00 0 User 3 Gain 10 v alue-gain
52 00 0 User 3 Gain 20 v alue-gain
51 00 0 User 3 Gain 50 v alue-gain
50 00 0 User 3 Gain 100 value-gain

©

National Instruments Corporation 4-15 Lab-PC-1200/AI RLPM

Chapter 4 Calibration

Table 4-3. Lab-PC-1200/AI EEPROM Map (Continued)

Location Hex Decimal Description

49 00 0 User 3 Gain 1 v alue-offset
48 00 0 User 3 Gain 1.25 value-offset
47 00 0 User 3 Gain 2 v alue-offset
46 00 0 User 3 Gain 5 v alue-offset
45 00 0 User 3 Gain 10 v alue-offset
44 00 0 User 3 Gain 20 v alue-offset
43 00 0 User 3 Gain 50 v alue-offset
42 00 0 User 3 Gain 100 value-offset
41 00 0 Not used
40 00 0 Not used
39 00 0 User 4 AI CALDAC0 value
38 00 0 User 4 AI CALDAC1 value
37 00 0 User 4 AI CALDAC2 value
36 00 0 User 4 AI CALDAC3 value
35 00 0 User 4 AO CALDAC4 value
34 00 0 User 4 AO CALDAC5 value
33 00 0 User 4 AO CALDAC6 value
32 00 0 User 4 AO CALDAC7 value
31 00 0 User 4 Gain 1 v alue-gain
30 00 0 User 4 Gain 1.25 value-gain
29 00 0 User 4 Gain 2 v alue-gain
28 00 0 User 4 Gain 5 v alue-gain
27 00 0 User 4 Gain 10 v alue-gain
26 00 0 User 4 Gain 20 v alue-gain
25 00 0 User 4 Gain 50 v alue-gain
24 00 0 User 4 Gain 100 value-gain

Lab-PC-1200/AI RLPM 4-16

©

National Instruments Corporation

Chapter 4 Calibration

Table 4-3. Lab-PC-1200/AI EEPROM Map (Continued)

Location Hex Decimal Description

23 00 0 User 4 Gain 1 v alue-offset
22 00 0 User 4 Gain 1.25 value-offset
21 00 0 User 4 Gain 2 v alue-offset
20 00 0 User 4 Gain 5 v alue-offset
19 00 0 User 4 Gain 10 v alue-offset
18 00 0 User 4 Gain 20 value-offset
17 00 0 User 4 Gain 50 value-offset
16 00 0 User 4 Gain 100 value-offset
15 00 0 Not used
14 00 0 Not used
13 00 0 Not used
12 00 0 Not used
11 00 0 Not used
10 00 0 Not used

9 00 0 Not used
8 00 0 Not used
7 00 0 Not used
6 00 0 Not used
5 00 0 Not used
4 00 0 Not used
3 00 0 Not used
2 00 0 Not used
1 00 0 Not used
0 00 0 Not used

©

National Instruments Corporation 4-17 Lab-PC-1200/AI RLPM

Fujitsu MB88341/MB88342

A

Data Sheet

1

This appendix contains the manufacturer data sheet for the
MB88341/MB88342 R-2R type 8-bit D/A converter manufactured by
Fujitsu Microelectronics, Inc. The MB88341 D/A converter is used on the
Lab-PC-1200/AI.

1

Copyright © Fujitsu Microelectronics, Inc. Reprinted with permission of copyright owner. All rights reserved.

Fujitsu Microelectronics, Inc. 1990

©

National Instruments Corporation A-1 Lab-PC-1200/AI RLPM

Linear Products 1990 Data Book

.

Appendix A Fujitsu MB88341/MB88342 Data Sheet

Lab-PC-1200/AI RLPM A-2

©

National Instruments Corporation

Appendix A Fujitsu MB88341/MB88342 Data Sheet

©

National Instruments Corporation A-3 Lab-PC-1200/AI RLPM

Appendix A Fujitsu MB88341/MB88342 Data Sheet

Lab-PC-1200/AI RLPM A-4

©

National Instruments Corporation

Appendix A Fujitsu MB88341/MB88342 Data Sheet

©

National Instruments Corporation A-5 Lab-PC-1200/AI RLPM

Appendix A Fujitsu MB88341/MB88342 Data Sheet

Lab-PC-1200/AI RLPM A-6

©

National Instruments Corporation

Appendix A Fujitsu MB88341/MB88342 Data Sheet

©

National Instruments Corporation A-7 Lab-PC-1200/AI RLPM

Appendix A Fujitsu MB88341/MB88342 Data Sheet

Lab-PC-1200/AI RLPM A-8

©

National Instruments Corporation

Appendix A Fujitsu MB88341/MB88342 Data Sheet

©

National Instruments Corporation A-9 Lab-PC-1200/AI RLPM

Appendix A Fujitsu MB88341/MB88342 Data Sheet

Lab-PC-1200/AI RLPM A-10

©

National Instruments Corporation

Appendix A Fujitsu MB88341/MB88342 Data Sheet

©

National Instruments Corporation A-11 Lab-PC-1200/AI RLPM

Appendix A Fujitsu MB88341/MB88342 Data Sheet

Lab-PC-1200/AI RLPM A-12

©

National Instruments Corporation