National Instruments HPC467064, HPC167064 User Manual
HPC167064/HPC467064 High-Performance microController
with a 16k UV Erasable CMOS EPROM
PRELIMINARY
August 1992
HPC167064/HPC467064 High-Performance
microController with a 16k UV Erasable CMOS EPROM
General Description
The HPC167064 is a member of the HPC family of High
Performance microControllers. Each member of the family
has the same core CPU with a unique memory and I/O
configuration to suit specific applications. The HPC167064
has a 16 kbyte, high-speed, UV-erasable, electrically programmable CMOS EPROM. This is ideally suited for applications where fast turnaround, pattern experimentation, and
code confidentiality are important requirements. The
HPC167064 can serve as a stand-alone emulator for either
the HPC16064 or the HPC16083. Two configuration registers have been added for emulation of the different chips.
The on-chip EPROM replaces the presently available user
ROM space. The on-chip EPROM can be programmed via a
DATA I/O UNISITE. There are security features added to
the chip to implement READ, ENCRYPTED READ, and
WRITE privileges for the on-chip EPROM. These defined
privileges are intended to deter theft, alteration, or unintentional destruction of user code. Each part is fabricated in
National’s advanced microCMOS technology. This process
combined with an advanced architecture provides fast, flexible I/O control, efficient data manipulation, and high speed
computation.
The HPC devices are complete microcomputers on a single
chip. All system timing, internal logic, EPROM, RAM, and
I/O are provided on the chip to produce a cost effective
solution for high performance applications. On-chip functions such as UART, up to eight 16-bit timers with 4 input
capture registers, vectored interrupts, WATCHDOG
and MICROWIRE/PLUS
TM
provide a high level of system
TM
integration. The ability to address up to 64k bytes of external memory enables the HPC to be used in powerful applications typically performed by microprocessors and expensive peripheral chips.
The microCMOS process results in very low current drain
and enables the user to select the optimum speed/power
product for his system. The IDLE and HALT modes provide
further current savings. The HPC167064 is available only in
68-pin LDCC package.
Features
Y
HPC familyÐcore features:
Ð 16-bit architecture, both byte and word operations
Ð 16-bit data bus, ALU, and registers
Ð 64 kbytes of direct memory addressing
Ð FASTÐ200 ns for fastest instruction when using
20.0 MHz clock, 134 ns at 30.0 MHz
Ð High code efficiencyÐmost instructions are single
byte
Ð 16 x 16 multiply and 32 x 16 divide
Ð Eight vectored interrupt sources
Ð Four 16-bit timer/counters with 4 synchronous out-
puts and WATCHDOG logic
Ð MICROWIRE/PLUS serial I/O interface
Ð CMOSÐvery low power with two power save modes:
IDLE and HALT
Y
16 kbytes high speed UV erasable: electrically programmable CMOS EPROM
Y
Stand-alone emulation of HPC16083 and HPC16064
family
Y
EPROM and configuration bytes programmable by
DATA I/O UNISITE with Pinsite Module
Y
Four selectable levels of security to protect on-chip
logic
EPROM contents
Y
UARTÐfull duplex, programmable baud rate
Y
Four additional 16-bit timer/counters with pulse width
modulated outputs
Y
Four input capture registers
Y
52 general purpose I/O lines (memory mapped)
Y
Commercial (0§Ctoa70§C), and military (b55§Cto
a
125§C) temperature ranges for 20.0 MHz, commercial
(0
Ctoa70§C) for 30.0 MHz
§
Block Diagram (HPC167064 with 16k EPROM shown)
Series 32000Éand TRI-STATEÉare registered trademarks of National Semiconductor Corporation.
MICROWIRE/PLUS
UNIX
IBM
É
SunOS
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TM
is a registered trademark of AT & T Bell Laboratories.
É
and PC-ATÉare registered trademarks of International Business Machines Corp.
TM
and WATCHDOGTMare trademarks of National Semiconductor Corporation.
is a trademark of Sun Microsystems.
TL/DD11046
TL/DD/11046– 1
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Total Allowable Source or Sink Current 100 mA
Storage Temperature Range
b
65§Ctoa150§C
Lead Temperature (Soldering, 10 sec.) 300§C
DC Electrical Characteristics
e
V
5.0Vg5% unless otherwise specified, T
CC
otherwise specified, T
e
0§Cto70§C for HPC467064
A
A
eb
V
with Respect to GND
CC
All Other Pins (V
Note:
Absolute maximum ratings indicate limits beyond
CC
a
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
55§Ctoa125§C for HPC167064 and V
CC
e
Symbol Parameter Test Conditions Min Max Units
I
CC
I
CC
I
CC
Supply Current V
1
IDLE Mode Current V
2
HALT Mode Current V
3
e
CC
e
V
CC
e
V
CC
e
CC
e
V
CC
e
V
CC
e
CC
e
V
CC
max, f
max, f
max, f
max, f
max, f
max, f
max, f
2.5V, f
e
30.0 MHz (Note 1) 85 mA
IN
e
20.0 MHz (Note 1) 70 mA
IN
e
2.0 MHz (Note 1) 40 mA
IN
e
30.0 MHz (Note 1) 6.0 mA
IN
e
20.0 MHz, (Note 1) 4.5 mA
IN
e
2.0 MHz, (Note 1) 1 mA
IN
e
0 kHz, (Note 1) 400 mA
IN
e
0 kHz, (Note 1) 100 mA
IN
INPUT VOLTAGE LEVELS FOR SCHMITT TRIGGERED INPUTS RESET, NMI, AND WO; AND ALSO CKI
V
IH1 Logic High 0.9 V
V
IL1 Logic Low 0.1 V
ALL OTHER INPUTS
V
IH2
V
IL2
I
LI1
I
LI2
I
LI3
I
LI4
C
I
C
IO
Logic High 0.7 V
Logic Low * 0.2 V
Input Leakage Current V
Input Leakage Current RDY/HLD, EXUI V
e
0 and V
IN
e
0
IN
Input Leakage Current B12 RESETe0, V
Input Leakage Current EXM V
e
0 and V
IN
e
IN
e
IN
e
IN
VCC(Note 4)
V
CC
VCC(Note 4)
b
0.5 7 mA
g
Input Capacitance (Note 2) 10 pF
I/O Capacitance (Note 2) 20 pF
OUTPUT VOLTAGE LEVELS
V
OH1
V
OL1
V
OH2
V
OL2
V
OH3
V
OL3
V
OH4
V
OL4
V
OH5
V
OL5
V
RAM
I
OZ
Note 1: I
with NMI
Note 2: This is guaranteed by design and not tested.
Note 3: Test duration is 100 ms.
Note 4: The EPROM mode of operation for this device requires high voltage input on pins EXM/V
above the normal specification when driven to voltages greater than V
*See NORMAL RUNNING MODE.
Logic High (CMOS) I
Logic Low (CMOS) I
Port A/B Drive, CK2 I
(A0–A15, B10, B11, B12, B15) I
Other Port Pin Drive, WO (open drain) I
(B0–B9, B13, B14, P0 –P3) I
ST1 and ST2 Drive I
Port A/B Drive (A0–15, B10, B11, B12, B15) I
when used as External Address/Data Bus I
RAM Keep-Alive Voltage (Note 3) 2.5 V
TRI-STATEÉLeakage Current V
,I
,I
CC
1
e
measured with no external drive (IOHand I
CC
CC
2
3
VCC. CKI driven to V
and V
IH1
with rise and fall times less than 10 ns.
IL1
eb
10 mA (Note 2) V
OH
e
10 mA (Note 2)
OH
eb
7 mA 2.4
OH
e
3mA
OL
eb
1.6 mA (except WO) 2.4
OH
e
0.5 mA
OL
eb
6 mA 2.4
OH
e
I
1.6 mA
OL
eb
1 mA 2.4
OH
e
3mA
OL
e
0 and V
IN
e
e
0, IIH,I
OL
CC
IL
a
0.3V.
0 and EXMeVCC). I
e
V
IN
CC
is measured with RESETeGND. I
CC1
, I3, I4, I5, I6 and I7. This will increase the input leakage current
PP
CC
b
2
b
0.5V to 7.0V
0.5V) to (GNDb0.5V)
5.0Vg10% unless
CC
CC
CC
3
* V
CC
g
2 mA
b
50 mA
10 mA
0.1
0.1 V
0.4 V
0.4 V
0.4 V
0.4 V
CC
g
5 mA
is measured
CC3
V
V
V
V
20 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and
e
T
0§Ctoa70§C for HPC467064
A
Symbol and Formula Parameter Min Max Units Notes
f
C
e
t
C1
t
CKIH
t
CKIL
e
t
C
t
WAIT
ClocksTimersMicrowire/PlusExternal HoldUPI Timing
t
DC1C2R
t
DC1C2F
e
f
U
f
MW
e
f
XIN
e
t
XIN
Figures 1
thru5). V
CC
CKI Operating Frequency 2 20 MHz
1/f
C
CKI Clock Period 50 500 ns
CKI High Time 22.5 ns
CKI Low Time 22.5 ns
2/f
C
e
t
C
CPU Timing Cycle 100 ns
CPU Wait State Period 100 ns
Delay of CK2 Rising Edge after CKI Falling Edge 0 55 ns (Note 2)
Delay of CK2 Falling Edge after CKI Falling Edge 0 55 ns (Note 2)
fC/8 External UART Clock Input Frequency 2.5** MHz
External MICROWIRE/PLUS Clock Input Frequency 1.25 MHz
fC/22 External Timer Input Frequency 0.91 MHz
t
C
Pulse Width for Timer Inputs 100 ns
e
5Vg5%*,T
eb
55§Ctoa125§C for HPC167064 and V
A
CC
e
5Vg10%,
t
UWS
t
UWH
t
UWV
e
t
SALE
t
HWP
t
HAE
t
HAD
e
t
BF
e
t
BE
t
UAS
t
UAH
t
RPW
t
OE
t
OD
t
DRDY
t
WDW
t
UDS
t
UDH
t
UDH
t
A
*See NORMAL RUNNING MODE.
**This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2
clock.
e
Note: C
Note 1: These AC Characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (t
Note 2: Do not design with this parameter unless CKI is driven with an active signal. When using a passive crystal circuit, its stability is not guaranteed if either CKI
or CKO is connected to any external logic other than the passive components of the crystal circuit.
Note 3: t
occurs later, t
Note 4: WS
with one wait state programmed.
Note 5: Due to emulation restrictionsÐactual limits will be better.
Note 6: Due to tester limitationsÐactual limits will be better.
40 pF.
L
and t
CKIR
CKIL
is spec’d for case with HLD falling edge occurring at the latest time can be accepted during the present CPU cycle being executed. If HLD falling edge
HAE
may be as long as (3t
HAE
e
t
WAIT
a
*/4 t
C
e
a
t
10 HLD Pulse Width 110 ns
C
e
a
t
100 HLDA Falling Edge after HLD Falling Edge 200 ns (Note 3)
C
e
a
*/4 t
85 HLDA Rising Edge after HLD Rising Edge 160 ns
C
a
(/2 t
66 Bus Float after HLDA Falling Edge 116 ns (Note 5)
C
a
(/2 t
66 Bus Enable after HLDA
C
(HPC467064) Input Data Hold after Rising Edge of UWR 20 ns
(HPC167064) 25* ns
) on CKI input less than 2.5 ns.
c
(number of pre-programmed wait states). Minimum and maximum values are calculated at maximum operating frequency, t
MICROWIRE Setup TimeÐMaster 100
MICROWIRE Setup TimeÐSlave 20
MICROWIRE Hold TimeÐMaster 20
MICROWIRE Hold TimeÐSlave 50
MICROWIRE Output Valid TimeÐMaster 50
MICROWIRE Output Valid TimeÐSlave 150
40 HLD Falling Edge before ALE Rising Edge 115 ns
Rising Edge 116 ns (Note 5)
Address Setup Time to Falling Edge of URD 10 ns
Address Hold Time from Rising Edge of URD 10 ns
URD Pulse Width 100 ns
URD Falling Edge to Output Data Valid 0 60 ns
Rising Edge of URD to Output Data Invalid 5 45 ns (Note 6)
RDRDY Delay from Rising Edge of URD 70 ns
UWR Pulse Width 40 ns
Input Data Valid before Rising Edge of UWR 10 ns
WRRDY Delay from Rising Edge of UWR 70 ns
a
C
4WSa72t
a
100) depending on the following CPU instruction cycles, its wait states and ready input.
C
ns
ns
ns
e
c
20.00 MHz,
3
20 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and
e
T
0§Ctoa70§C for HPC467064 (Continued)
A
Symbol and Formula Parameter Min Max Units Notes
t
DC1ALER
t
DC1ALEF
t
DC2ALER
t
DC2ALEF
e
t
LL
e
t
ST
Address CyclesRead CyclesWrite Cycles
Ready
Input
t
VP
t
ARR
t
ACC
t
RD
t
RW
t
DR
t
RDA
t
ARW
t
WW
t
V
t
HW
t
DAR
t
RWR
e
e
e
e
e
e
e
Figures 1
thru5.) V
CC
Delay from CKI Rising Edge to ALE Rising Edge 0 35 ns (Notes 1, 2)
Delay from CKI Rising Edge to ALE Falling Edge 0 35 ns (Notes 1, 2)
e
a
(/4 t
20 Delay from CK2 Rising Edge to ALE Rising Edge 45 ns
C
e
a
(/4 t
20 Delay from CK2 Falling Edge to ALE Falling Edge 45 ns
C
b
(/2 t
9 ALE Pulse Width 41 ns
C
b
(/4 t
7 Setup of Address Valid before ALE Falling Edge 18 ns
C
b
(/4 t
5 Hold of Address Valid after ALE Falling Edge 20 ns
C
e
b
(/4 t
5 ALE Falling Edge to RD Falling Edge 20 ns
C
e
aWSb
e
e
(/2 t
e
e
(/2 t
(/2 t
*/4 t
*/4 t
(/4 t
t
C
t
C
(/2 t
C
(/4 t
t
C
C
C
55 Data Input Valid after Address Output Valid 145 ns
aWSb
65 Data Input Valid after RD Falling Edge 85 ns
aWSb
C
b
b
C
C
aWSb
C
C
10 RD Pulse Width 140 ns
15 Hold of Data Input Valid after RD Rising Edge 0 60 ns
15 Bus Enable after RD Rising Edge 85 ns
b
5 ALE Falling Edge to WR Falling Edge 45 ns
aWSb
15 WR Pulse Width 160 ns
5 Data Output Valid before WR Rising Edge 145 ns
b
5 Hold of Data Valid after WR Rising Edge 20 ns
aWSb
50 Falling Edge of ALE to Falling Edge of RDY 75 ns
RDY Pulse Width 100 ns
(Continued)
e
5Vg5%*,T
eb
55§Ctoa125§C for HPC167064 and V
A
CC
e
5Vg10%,
4
30 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and
Symbol and Formula Parameter Min Max Units Notes
f
C
e
t
C1
t
CKIH
t
CKIL
e
2/f
t
C
e
t
WAIT
ClocksTimersMicrowire/PlusExternal HoldUPI TimingAddress Cycles
t
DC1C2R
t
DC1C2F
e
f
fC/8 External UART Clock Input Frequency 3.75** MHz
U
f
MW
e
f
XIN
e
t
XIN
Figures 1
thru5). V
CC
CKI Operating Frequency 2 30 MHz
1/f
C
CKI Clock Period 33 500 ns
CKI High Time 22.5 ns
CKI Low Time 22.5 ns
C
t
C
CPU Timing Cycle 66 ns
CPU Wait State Period 66 ns
Delay of CK2 Rising Edge after CKI Falling Edge 0 55 ns (Note 2)
Delay of CK2 Falling Edge after CKI Falling Edge 0 55 ns (Note 2)
External MICROWIRE/PLUS Clock Input Frequency 1.875 MHz
fC/22 External Timer Input Frequency 1.364 MHz
t
C
Pulse Width for Timer Inputs 66 ns
e
5Vg10%, T
e
0§Ctoa70§C for HPC467064.
A
t
UWS
t
UWH
t
UWV
t
SALE
t
HWP
e
t
HAE
t
HAD
e
t
BF
e
t
BE
t
UAS
t
UAH
t
RPW
t
OE
t
OD
t
DRDY
t
WDW
t
UDS
t
UDH
t
A
t
DC1ALER
t
DC1ALEF
t
DC2ALER
t
DC2ALEF
e
t
LL
e
t
ST
e
t
VP
MICROWIRE Setup TimeÐMaster 100
MICROWIRE Setup TimeÐSlave 20
MICROWIRE Hold TimeÐMaster 20
MICROWIRE Hold TimeÐSlave 50
MICROWIRE Output Valid TimeÐMaster 50
MICROWIRE Output Valid TimeÐSlave 150
e
a
*/4 t
40 HLD Falling Edge before ALE Rising Edge 90 ns
C
e
a
t
10 HLD Pulse Width 76 ns
C
a
t
85 HLDA Falling Edge after HLD Falling Edge 151 ns (Note 3)
C
e
a
*/4 t
85 HLDA
C
a
(/2 t
66 Bus Float after HLDA Falling Edge 99 ns (Note 5)
C
a
(/2 t
66 Bus Enable after HLDA Rising Edge 99 ns (Note 5)
C
Rising Edge after HLD Rising Edge 135 ns
Address Setup Time to Falling Edge of URD 10 ns
Address Hold Time from Rising Edge of URD 10 ns
URD Pulse Width 100 ns
URD Falling Edge to Output Data Valid 0 60 ns
Rising Edge of URD to Output Data Invalid 5 45 ns (Note 6)
RDRDY Delay from Rising Edge of URD 70 ns
UWR Pulse Width 40 ns
Input Data Valid before Rising Edge of UWR 10 ns
Input Data Hold after Rising Edge of UWR 20 ns
WRRDY Delay from Rising Edge of UWR 70 ns
Delay from CKI Rising Edge to ALE Rising Edge 0 35 ns (Notes 1, 2)
Delay from CKI Rising Edge to ALE Falling Edge 0 35 ns (Notes 1, 2)
e
a
(/4 t
20 Delay from CK2 Rising Edge to ALE Rising Edge 37 ns
C
e
a
(/4 t
20 Delay from CK2 Falling Edge to ALE Falling Edge 37 ns
C
b
(/2 t
9 ALE Pulse Width 24 ns
C
b
(/4 t
7 Setup of Address Valid before ALE Falling Edge 9 ns
C
b
(/4 t
5 Hold of Address Valid after ALE Falling Edge 11 ns
C
ns
ns
ns
5
30 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and
Figures 1
thru5). V
(Continued)
e
CC
5Vg10%, T
e
0§Ctoa70§C for HPC467064. (Continued)
A
Symbol and Formula Parameter Min Max Units Notes
e
t
ARR
t
ACC
t
RD
t
RW
Read CyclesWrite Cycles
t
DR
t
RDA
t
ARW
t
WW
e
t
V
t
HW
t
DAR
t
RWR
Input
Ready
**This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2
clock.
e
Note: C
Note 1: These AC Characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (t
Note 2: Do not design with this parameter unless CKI is driven with an active signal. When using a passive crystal circuit, its stability is not guaranteed if either CKI
or CKO is connected to any external logic other than the passive components of the crystal circuit.
Note 3: t
occurs later, t
Note 4: WS
with one wait state programmed.
Note 5: Due to emulation restrictionsÐactual limits will be better.
Note 6: Due to tester limitationsÐactual limits will be better.
40 pF.
L
and t
CKIR
CKIL
is spec’d for case with HLD falling edge occurring at the latest time can be accepted during the present CPU cycle being executed. If HLD falling edge
HAE
may be as long as (3t
HAE
e
t
WAIT
b
(/4 t
5 ALE Falling Edge to RD Falling Edge 12 ns
C
e
aWSb
t
C
e
(/2 t
C
e
(/2 t
e
*/4 t
C
e
t
C
e
(/2 t
e
*/4 t
(/2 t
C
e
(/4 t
e
(/4 t
e
t
C
) on CKI input less than 2.5 ns.
c
(number of pre-programmed wait states). Minimum and maximum values are calculated at maximum operating frequency, t
32 Data Input Valid after Address Output Valid 100 ns
aWSb
C
b
b
C
C
aWSb
C
C
39 Data Input Valid after RD Falling Edge 60 ns
aWSb
14 RD Pulse Width 85 ns
15 Hold of Data Input Valid after RD Rising Edge 0 35 ns
15 Bus Enable after RD Rising Edge 51 ns
b
5 ALE Falling Edge to WR Falling Edge 28 ns
aWSb
15 WR Pulse Width 101 ns
5 Data Output Valid before WR Rising Edge 94 ns
b
10 Hold of Data Valid after WR Rising Edge 7 ns
aWSb
50 Falling Edge of ALE to Falling Edge of RDY 33 ns
RDY Pulse Width 66 ns
a
C
4WSa72t
a
100) depending on the following CPU instruction cycles, its wait states and ready input.
C
e
c
30.00 MHz,
CKI Input Signal Characteristics
FIGURE 1. CKI Input Signal
Rise/Fall Time
TL/DD/11046– 2
Duty Cycle
TL/DD/11046– 3
6
CKI Input Signal Characteristics
Note: AC testing inputs are driven at VIHfor logic ‘‘1’’ and VILfor a logic ‘‘0’’. Output timing measurements are made at VCC/2 for both logic ‘‘1’’ and logic ‘‘0’’.
FIGURE 2. Input and Output for AC Tests
TL/DD/11046– 4
Timing Waveforms
TL/DD/11046– 5
FIGURE 3. CK1, CK2, ALE Timing Diagram
TL/DD/11046– 6
FIGURE 4. Write Cycle
7
Timing Waveforms (Continued)
TL/DD/11046– 7
FIGURE 5. Read Cycle
TL/DD/11046– 8
FIGURE 6. Ready Mode Timing
FIGURE 7. Hold Mode Timing
8
TL/DD/11046– 9
Timing Waveforms (Continued)
FIGURE 8. MICROWIRE Setup/Hold Timing
TL/DD/11046– 10
FIGURE 9. UPI Read Timing
FIGURE 10. UPI Write Timing
TL/DD/11046– 11
TL/DD/11046– 12
9
Functional Modes of Operation
There are two primary functional modes of operation for the
HPC167064.
EPROM Mode
#
Normal Running Mode
#
EPROM MODE
In the EPROM mode, the HPC167064 is configured to ‘‘approximately emulate’’ a standard NMC27C256 EPROM.
Some dissimilarities do exist. The most significant one is
that HPC167064 contains only 16 kbytes of programmable
memory, rather than the 32 kbytes in 27C256. An
HPC167064 in the EPROM mode can be programmed with
a Data I/O machine.
Given below is the list of functions that can be performed by
the user in the EPROM mode.
Programming
#
CAUTION: Exceeding 14V on pin 1 (VPP) will damage the
HPC167064.
Initially, and after each erasure, all bits of the HPC
EPROM are in the ‘‘1’’ state. Data is introduced by selectively programming ‘‘0s’’ into the desired bit locations.
Although only ‘‘0s’’ will be programmed, both ‘‘1s’’ and
‘‘0s’’ can be presented in the data word. The only way to
change a ‘‘0’’ to a ‘‘1’’ is by ultraviolet light erasure.
Program/verify EPROM registers
#
To read data (verify) during the programming process,
V
must be at 13V. When reading data after the pro-
PP
gramming process, V
Program/verify ECON registers
#
There are two configuration registers ECON6 and
ECON7 to emulate different family members and also to
enable/disable different features in the chip. These registers are not mapped in the EPROM user space. These
bytes must be programmed through a pointer register
ECONA.
To prevent unintentional programming, the ECON6, 7
registers must be programmed with the assistance of this
pointer register. ECONA, and externally presented address, both identify the same ECON register may be programmed.
NORMAL RUNNING MODE
In this mode, the HPC167064 executes user software in the
normal manner. By default, its arcitecture imitates that of
the HPC16064. It may be configured to emulate the
HPC16083. The addressable memory map will be exactly as
for the HPC16083. The WATCHDOG function monitors addresses accordingly. Thus, the HPC167064 can be used as
a stand-alone emulator for both HPC16064 and HPC16083.
Within this mode, the on-chip EPROM cell acts as read only
memory. Each memory fetch is 16-bits wide. The
HPC167064 operates to 20 MHz with 1 wait state for the onchip memory.
can be either 13V or at VCC.
PP
The HPC167064 emulates the HPC16064 and HPC16083,
except as described here.
The value of EXM is latched on the rising edge of
#
RESET
. Thus, the user may not switch from ROMed to
ROMless operation or vice-versa, without another
RESET
pulse.
The security logic can be used to control access to the
#
on-chip EPROM. This feature is unique to the
HPC167064. There is no corresponding mode of operation on the HPC16064 or the HPC16083.
Specific inputs are allowed to be driven at high voltage
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(13V) to configure the device for programming. These
high voltage inputs are unique to the HPC167064. The
same inputs cannot be driven to high voltage on the
HPC16064 and HPC16083 without damage to the part.
The Port D input structure on this device is slightly differ-
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ent from the masked ROM HPC16083 and HPC16064.
V
min and V
IH2
ROM HPC16083 and HPC16064. There is a V
requirement for this device equal to V
is also a V
GND-0.05V. The V
the masked ROM devices is the Absolute Maximum Ratings of V
CC
The D.C. Electrical Characteristics and A.C. Electrical
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Characteristics for the HPC167064, where T
a
to
125§C, are guaranteed over a reduced operating
voltage range of V
masked ROM devices that it simulates which is V
g
10%. These characteristics for the HPC467064, where
eb
T
0§Ctoa70§C, are guaranteed over the masked
A
ROM operating voltage range which is V
In addition to the reduced operating voltage range for the
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HPC167064, the A.C. timing parameter t
to be a mimimum value of 25 ns. The masked ROM devices require a mimimum t
parameter for the HPC467064 is required to be the same
max are the same as for the masked
IL2
a
0.05V. There
min requirement for this device equal to
IL2
a
max and V
IH2
0.5V and GND-0.5V respectively.
g
5%. This is different from the
CC
UDH
CC
min requirement for
IL2
A
g
CC
is required
UDH
0f 20 ns. This A.C. timing
IH2
eb
10%.
max
55§C
as the masked ROM devices.
HPC167064 EPROM SECURITY
The HPC167064 includes security logic to provide READ
and WRITE protection of the on-chip EPROM. These defined privileges are intended to deter theft, alteration, or unintentional destruction of user code. Two bits are used to
define four levels of security on the HPC167064 to control
access to on-chip EPROM.
Security Level 3
This is the default configuration of an erased HPC167064.
READ and WRITE accesses to the on-chip EPROM or
ECON registers may be accomplished without constraint in
EPROM mode. READ accesses to the on-chip EPROM may
be accomplished without constraint in NORMAL RUNNING
mode.
CC
10
Functional Modes of Operation (Continued)
Security Level 2
This security level prevents programming of the on-chip
EPROM or the ECON registers thereby providing WRITE
protection. Read accesses to the on-chip EPROM or ECON
registers may be accomplished without constraint in
EPROM. Read accesses to the on-chip EPROM may be
accomplished without constraint in NORMAL RUNNING
mode.
Security Level 1
This security level prevents programming of the on-chip
EPROM or ECON registersÐthereby providing registers
write protection. Read accesses to the on-chip ECON-registers may be accomplished without constraint in EPROM
mode. Read accesses to the on-chip EPROM will produce
ENCRYPTED data in EPROM. READ accesses to the onchip EPROM, during NORMAL RUNNING mode, are subject to Runtime Memory Protection. Under Runtime Memory Protection, only instruction opcodes stored within the
on-chip EPROM are allowed to access the EPROM as operand. If any other instruction opcode attempts to use the
contents of EPROM as an operand, it will receive the hex
value ‘‘FF’’. The Runtime Memory Protection feature is designed to prevent hostile software, running from external
memory or on-chip RAM, from reading secured EPROM
data. Transfers of control into, or out of the on-chip EPROM
(such as jump or branch) are not affected by Runtime Memory Protection. Interrupt vector fetches from EPROM proceed normally, and are not affected by Runtime Memory
Protection.
Security Level 0
This security level prevents programming of the on-chip
EPROM or ECON registers, thereby providing write protection. Read accesses to the on-chip ECON registers may be
accomplished without constraint in EPROM mode. READ
accesses to the on-chip EPROM are NOT ALLOWED in
EPROM mode. Such accesses will return data value ‘‘FF’’
hex. Runtime Memory Protection is enforced as in security
level 1.
These four levels of security help ensure that the user
EPROM code is not tampered with in a test fixture and that
code executing from RAM or external memory does not
dump the user algorithm.
Erasure Characteristics
The erasure characteristics of the HPC167064 are such that
erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (Ð). It
should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000Ж4000Рrange.
After programming, opaque labels should be placed over
the HPC167064’s window to prevent unintentional erasure.
Covering the window will also prevent temporary functional
failure due to the generation of photo currents.
The recommended erasure procedure for the HPC167064 is
exposure to short wave ultraviolet light which has a wavelength of 2537 Angstroms (Ð). The integrated dose (i.e., UV
c
intensity
of 30W-sec/cm
The HPC167064 should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. The erasure time table shows the minimum HPC167064 erasure
time for various light intensities.
exposure time) for erasure should be a minimum
2
.
An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one inch.
The erasure time increases as the square of the distance. (If
distance is doubled the erasure time increases by a factor of
4.) Lamps lose intensity as they age. When a lamp is
changed, the distance has changed or the lamp has aged,
the system should be checked to make certain full erasure
is occurring.
Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete
erasure was the problem.
Minimum HPC167064 Erasure Time
Light Intensity Erasure Time
(Micro-Watts/cm
15,000 36
10,000 50
2
) (Minutes)
Memory Map of the HPC167064
The HPC167064 has 256 bytes of on-chip user RAM and
chip registers located at address 0000 –01FF that is always
enabled, and 256 bytes of on-chip RAM located at 0200 –
02FF that can be enabled or disabled. It has 8 kbytes of onchip EPROM located at address 0E000 – 0FFFF that is always enabled and 8 kbytes of EPROM located at address
0C000–0DFFF that can be enabled or disabled.
The ECON6 contains two bits ROM0 and RAM0. When
these bits are ‘‘1’’ (erased default), full 16 kbytes of ROM
and 512 bytes of RAM are enabled. Programming a ‘‘0’’ to
these bits disables the lower 8k for the EPROM and upper
256 bytes for the RAM. The ECON registers are only accessible to the user during EPROM mode.
Address In Address In Other
EPROM Mode HPC Modes
7FFF Operation
4000 FFFF
3FFF
2000 E000
1FFF DFFF
0000 C000
11
–
Enabled or
Disabled by
config logic
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