National Instruments E Series User Manual

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DAQ E Series

E Series User Manual

February 2007 370503K-01

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Important Information

Warranty

The E Series devices are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.

The media on which you receive National Instruments software are warranted not to fail to execute programming instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do not execute programming instruc tions if National Instruments receives notice of such defects during the warranty period. National Instruments does not warrant that the operation of the software shall be uninterrupted or error free.

A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work. National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty.

National Instruments believes that the information in this document is accurate. The document has been carefully reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition. The reader should consult National Instruments if errors are suspected. In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it.

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(1) NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL OF RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT INJURY TO A HUMAN.

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Compliance

Compliance with FCC/Canada Radio Frequency Interference Regulations

Determining FCC Class

The Federal Communications Commission (FCC) has rules to protect wireless communications from interference. The FCC places digital electronics into two classes. These classes are known as Class A (for use in industrial commercial locations only) or Class B (for use in residential or commercial locations). All National Instruments (NI) products are FCC Class A products.

Depending on where it is operated, this Class A product could be subject to restrictions in the FCC rules. (In Canada, the Department of Communications (DOC), of Industry Canada, regulates wireless interference in much the same way.) Digital electronics emit weak signals during normal operation that can affect radio, television, or other wireless products.

All Class A products display a simple warning statement of one paragraph in length regarding interference and undesired operation. The FCC rules have restrictions regarding the locations where FCC Class A products can be operated.

Consult the FCC Web site at

FCC/DOC Warnings

This equipment generates and uses radio frequency energy and, if not installed and used in strict accordance with the instructions in this manual and the CE marking Declaration of Conformity*, may cause interference to radio and television reception. Classification requirements are the same for the Federal Communications Commission (FCC) and the Canadian Department of Communications (DOC).

Changes or modifications not expressly approved by NI could void the user’s authority to operate the equipment under the FCC Rules.

Class A

Federal Communications Commission

This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user is required to correct the interference at their own expense.

www.fcc.gov for more information.

Canadian Department of Communications

This Class A digital apparatus meets all requirements of the Canadian InterferenceCausing Equipment Regulations. Cet appareil numérique de la classe A respecte toutes les exigences du Règlement sur le matériel brouilleur du Canada.

Compliance with EU Directives

Users in the European Union (EU) should refer to the Declaration of Conformity (DoC) for information* pertaining to the CE marking. Refer to the Declaration of Conformity (DoC) for this product for any additional regulatory compliance information. To obtain the DoC for this product, visit and click the appropriate link in the Certification column.

* The CE marking Declaration of Conformity contains important supplementary information and instructions for the user or

installer.

ni.com/certification, search by model number or product line,

About This Manual

Conventions ...................................................................................................................xv

Related Documentation..................................................................................................xvi

NI-DAQ for Windows.....................................................................................xvi

NI-DAQmx for Linux......................................................................................xvi

NI-DAQmx Base.............................................................................................xvii

LabVIEW ........................................................................................................xvii

LabWindows/CVI............................................................................................xviii

Measurement Studio........................................................................................xviii

ANSI C without NI Application Software ......................................................xix

.NET Languages without NI Application Software ........................................xix

Device Documentation and Specifications......................................................xx

Training Courses .............................................................................................xx

Technical Support on the Web ........................................................................xx

Chapter 1 DAQ System Overview

DAQ Hardware ..............................................................................................................1-2

DAQ-STC........................................................................................................1-3

Calibration Circuitry........................................................................................1-3

Internal or Self-Calibration ...............................................................1-4

External Calibration ..........................................................................1-4

Signal Conditioning .......................................................................................................1-4

Sensors and Transducers .................................................................................1-4

Signal Conditioning Options ...........................................................................1-5

SCXI..................................................................................................1-5

SCC ...................................................................................................1-6

5B Series ...........................................................................................1-6

Cables and Accessories..................................................................................................1-6

Using Accessories with Devices .....................................................................1-7

Custom Cabling ...............................................................................................1-9

Programming Devices in Software ................................................................................1-10

I/O Connector Signal Descriptions ................................................................................1-11

Terminal Name Equivalents ..........................................................................................1-14

+5 V Power Source ........................................................................................................1-16

Contents

Chapter 2 Analog Input

Analog Input Circuitry .................................................................................................. 2-1

Input Polarity and Range ............................................................................................... 2-2

Analog Input Terminal Configuration........................................................................... 2-5

Dither............................................................................................................................. 2-8

Multichannel Scanning Considerations ......................................................................... 2-9

Analog Input Triggering................................................................................................ 2-14

Connecting Analog Input Signals.................................................................................. 2-20

Mux ................................................................................................................. 2-1

Instrumentation Amplifier (NI-PGIA) ............................................................ 2-2

A/D Converter................................................................................................. 2-2

AI FIFO........................................................................................................... 2-2

Analog Trigger................................................................................................ 2-2

AI Timing Signals........................................................................................... 2-2

Use Low Impedance Sources.......................................................................... 2-10

Use Short High-Quality Cabling.....................................................................2-11

Carefully Choose the Channel Scanning Order ..............................................2-11

Avoid Switching from a Large to a Small Input Range ................... 2-11

Insert Grounded Channel between Signal Channels ........................ 2-11

Minimize Voltage Step between Adjacent Channels ....................... 2-12

Avoid Scanning Faster than Necessary........................................................... 2-12

Example 1 ......................................................................................... 2-12

Example 2 ......................................................................................... 2-13

AI Data Acquisition Methods .........................................................................2-13

Software-Timed Acquisitions........................................................... 2-13

Hardware-Timed Acquisitions ......................................................... 2-13

AI Start Trigger Signal.................................................................................... 2-15

Using a Digital Source...................................................................... 2-15

Using an Analog Source ................................................................... 2-15

Outputting the AI Start Trigger Signal ........................................................... 2-16

AI Reference Trigger Signal ........................................................................... 2-16

Using a Digital Source...................................................................... 2-18

Using an Analog Source ................................................................... 2-18

Outputting the AI Reference Trigger Signal .................................... 2-18

AI Pause Trigger Signal.................................................................................. 2-19

Using a Digital Source...................................................................... 2-19

Using an Analog Source ................................................................... 2-19

Types of Signal Sources.................................................................................. 2-22

Floating Signal Sources .................................................................... 2-22

Ground-Referenced Signal Sources.................................................. 2-22

E Series User Manual viii ni.com

Contents

Differential Connection Considerations ........................................................................2-22

Differential Connections for Ground-Referenced Signal Sources ..................2-23

Common-Mode Signal Rejection Considerations.............................2-24

Differential Connections for Non-Referenced or

Floating Signal Sources................................................................................2-24

Single-Ended Connection Considerations .....................................................................2-26

Common-Mode Signal Rejection Considerations ...........................................2-26

Single-Ended Connections for Floating Signal Sources

(RSE Configuration).....................................................................................2-27

Single-Ended Connections for Grounded Signal Sources

(NRSE Configuration)..................................................................................2-27

Field Wiring Considerations..........................................................................................2-28

Configuring AI Modes in Software ...............................................................................2-29

Traditional NI-DAQ (Legacy).........................................................................2-29

NI-DAQmx......................................................................................................2-29

Analog Input Timing Signals.........................................................................................2-30

AI Start Trigger Signal ....................................................................................2-32

Using a Digital Source ......................................................................2-33

Using an Analog Source ...................................................................2-33

Outputting the AI Start Trigger Signal .............................................2-33

AI Reference Trigger Signal ...........................................................................2-34

Using a Digital Source ......................................................................2-35

Using an Analog Source ...................................................................2-36

Outputting the AI Reference Trigger Signal.....................................2-36

AI Pause Trigger Signal ..................................................................................2-36

Using a Digital Source ......................................................................2-36

Using an Analog Source ...................................................................2-37

AI Sample Clock Signal ..................................................................................2-37

Using an Internal Source...................................................................2-37

Using an External Source..................................................................2-37

Outputting the AI Sample Clock Signal ...........................................2-38

Other Timing Requirements..............................................................2-39

AI Sample Clock Timebase Signal..................................................................2-40

AI Convert Clock Signal .................................................................................2-41

Using an Internal Source...................................................................2-41

Using an External Source..................................................................2-42

Outputting the AI Convert Clock Signal...........................................2-42

Using a Delay from Sample Clock to Convert Clock.......................2-43

Other Timing Requirements..............................................................2-43

AI Convert Clock Timebase Signal.................................................................2-45

Master Timebase Signal ..................................................................................2-45

AI Hold Complete Event Signal......................................................................2-46

External Strobe Signal.....................................................................................2-46

Getting Started with AI Applications in Software.........................................................2-47

Contents

Chapter 3 Analog Output

Analog Output Circuitry................................................................................................ 3-1

DACs............................................................................................................... 3-1

DAC FIFO....................................................................................................... 3-1

AO Sample Clock ........................................................................................... 3-2

Polarity and Reference Selection .................................................................... 3-2

Reference Selection ....................................................................................................... 3-2

Polarity Selection........................................................................................................... 3-3

Reglitch Selection.......................................................................................................... 3-3

Minimizing Glitches on the Output Signal.................................................................... 3-3

AO Data Generation Methods ....................................................................................... 3-4

Software-Timed Generations .......................................................................... 3-4

Hardware-Timed Generations......................................................................... 3-4

Analog Output Triggering .............................................................................................3-5

AO Start Trigger Signal .................................................................................. 3-6

AO Pause Trigger Signal ................................................................................ 3-7

Connecting Analog Output Signals ............................................................................... 3-8

Waveform Generation Timing Signals.......................................................................... 3-9

AO Start Trigger Signal .................................................................................. 3-9

AO Pause Trigger Signal ................................................................................3-10

AO Sample Clock Signal ................................................................................ 3-11

AO Sample Clock Timebase Signal................................................................ 3-13

Master Timebase Signal.................................................................................. 3-14

Getting Started with AO Applications in Software....................................................... 3-15

Buffered ............................................................................................ 3-4

Non-Buffered.................................................................................... 3-5

Using a Digital Source...................................................................... 3-6

Using an Analog Source ................................................................... 3-6

Outputting the AO Start Trigger Signal ...........................................3-6

Using a Digital Source...................................................................... 3-7

Using an Analog Source ................................................................... 3-7

Using a Digital Source...................................................................... 3-9

Using an Analog Source ................................................................... 3-10

Outputting the AO Start Trigger Signal ...........................................3-10

Using a Digital Source...................................................................... 3-10

Using an Analog Source ................................................................... 3-11

Using an Internal Source .................................................................. 3-11

Using an External Source ................................................................. 3-11

Outputting the AO Sample Clock Signal ......................................... 3-12

Other Timing Requirements ............................................................. 3-12

E Series User Manual x ni.com

Chapter 4 Digital I/O

Extended Digital I/O......................................................................................................4-2

Power-On States of the PFI and DIO Lines...................................................................4-9

Connecting Digital I/O Signals......................................................................................4-9

Getting Started with DIO Applications in Software......................................................4-10

Chapter 5 Counters

Counter Triggering ........................................................................................................5-1

Counter Timing Signals.................................................................................................5-2

Getting Started with Counter Applications in Software ................................................5-10

Contents

Port 3 Signal Assignments...............................................................................4-2

Power-On State................................................................................................4-3

Changing DIO Power-On State to Pulled Low .................................4-3

Timing Specifications......................................................................................4-4

Mode 1 Input Timing.......................................................................................4-6

Mode 1 Output Timing....................................................................................4-7

Mode 2 Bidirectional Timing ..........................................................................4-8

Start Trigger.....................................................................................................5-1

Pause Trigger...................................................................................................5-2

Counter 0 Source Signal..................................................................................5-3

Counter 0 Gate Signal .....................................................................................5-4

Counter 0 Internal Output Signal ....................................................................5-5

CTR 0 OUT Pin ................................................................................5-6

Counter 0 Up/Down Signal .............................................................................5-6

Counter 1 Source Signal..................................................................................5-6

Counter 1 Gate Signal .....................................................................................5-7

Counter 1 Internal Output Signal ....................................................................5-8

Counter 1 Up/Down Signal .............................................................................5-9

Frequency Output Signal.................................................................................5-9

Master Timebase Signal ..................................................................................5-9

Chapter 6 Programmable Function Interfaces (PFI)

Inputs .............................................................................................................................6-1

Outputs...........................................................................................................................6-1

Contents

Chapter 7 Digital Routing

Timing Signal Routing .................................................................................................. 7-1

Connecting Timing Signals ...........................................................................................7-4

Routing Signals in Software.......................................................................................... 7-5

Chapter 8 Real-Time System Integration Bus (RTSI)

RTSI Triggers................................................................................................................ 8-1

PCI E Series Devices ...................................................................................... 8-1

PXI E Series Devices ...................................................................................... 8-2

Device and RTSI Clocks ............................................................................................... 8-4

Synchronizing Multiple Devices ................................................................................... 8-4

Chapter 9 Bus Interface

MITE and DAQPnP ...................................................................................................... 9-1

Using PXI with CompactPCI ........................................................................................ 9-1

Data Transfer Methods .................................................................................................. 9-2

Direct Memory Access (DMA)....................................................................... 9-2

Interrupt Request (IRQ) .................................................................................. 9-2

Programmed I/O.............................................................................................. 9-2

Changing Data Transfer Methods between DMA and IRQ............................ 9-3

Chapter 10 Triggering

Triggering with a Digital Source................................................................................... 10-1

Triggering with an Analog Source ................................................................................ 10-2

PFI 0/AI START TRIG Pin ............................................................................ 10-3

Analog Input Channel ..................................................................................... 10-3

Analog Trigger Actions .................................................................................. 10-3

Analog Trigger Types.................................................................................................... 10-4

Level Triggering ............................................................................................. 10-4

Level Triggering with Hysteresis.................................................................... 10-5

Window Triggering......................................................................................... 10-5

Analog Trigger Accuracy ..............................................................................................10-6

Appendix A Device-Specific Information

E Series User Manual xii ni.com

Appendix B I/O Connector Pinouts

Appendix C Troubleshooting

Appendix D Technical Support and Professional Services

Glossary

Index

Contents

About This Manual

The E Series User Manual contains information about using the National Instruments E Series and several B Series data acquisition (DAQ) devices with NI-DAQ 8.0 or later. E Series devices feature up to 64 analog input (AI) channels, two counters, eight or 32 lines of digital input/output (DIO), and up to two analog output (AO) channels. The B Series devices discussed in this document are similar to E Series devices, but do not support SCXI, RTSI, or referenced single-ended AI mode.

Conventions

The following conventions are used in this manual:

<> Angle brackets indicate function keys. Angle brackets that contain numbers

separated by an ellipsis represent a range of values associated with a bit or signal name—for example, P0.<3..0>.

» The » symbol leads you through nested menu items and dialog box options

to a final action. The sequence File»Page Setup»Options directs you to pull down the File menu, select the Page Setup item, and select Options from the last dialog box.

This icon denotes a note, which alerts you to important information.

This icon denotes a caution, which advises you of precautions to take to avoid injury, data loss, or a system crash. When this symbol is marked on the product, refer to the Read Me First: Safety and Radio-Frequency Interference document shipped with the product for precautions to take.

bold Bold text denotes items that you must select or click in the software, such

as menu items and dialog box options. Bold text also denotes parameter names.

italic Italic text denotes variables, emphasis, a cross-reference, or an introduction

to a key concept. Italic text also denotes text that is a placeholder for a word or value that you must supply.

monospace Text in this font denotes text or characters you should enter from the

keyboard, the proper names of disk drives, paths, directories, programs, functions, filenames, and extensions.

About This Manual

monospace italic

Platform Text in this font denotes a specific platform and indicates that the text

Italic text in this font denotes text that is a placeholder for a word or value that you must supply.

following it applies only to that platform.

Figure 1-1. DAQ System Overview

DAQ Hardware

DAQ hardware digitizes signals, performs D/A conversions to generate analog output signals, and measures and controls digital I/O signals.

E Series User Manual 1-2 ni.com

DAQ-STC

Chapter 1 DAQ System Overview

E Series devices use the National Instruments DAQ system timing controller (DAQ-STC) for time-related functions. The DAQ-STC consists of the following timing groups.

• AI—Two 24-bit, two 16-bit counters

• AO—Three 24-bit, one 16-bit counter

• General-purpose counter/timer functions —Two 24-bit counters

You can independently configure the groups for timing resolutions of 50 ns or 10 μs. With the DAQ-STC, you can interconnect a wide variety of internal timing signals to other internal blocks. The interconnection scheme is flexible and completely software-configurable.

The DAQ-STC offers PFI lines to import external timing and trigger signals or to export internally generated clocks and triggers. The DAQ-STC also supports buffered operations, such as buffered waveform acquisition, buffered waveform generation, and buffered period measurement. It also supports numerous non-buffered operations, such as single pulse or pulse train generation, digital input, and digital output.

Calibration Circuitry

Calibration is the process of making adjustments to a measurement device to reduce errors associated with measurements. Without calibration, the measurement results of your device will drift over time and temperature. Calibration adjusts for these changes to improve measurement accuracy and ensure that your product meets its required specifications.

DAQ devices have high precision analog circuits that must be adjusted to obtain optimum accuracy in your measurements. Calibration determines what adjustments these analog circuits should make to the device measurements. During calibration, the value of a known, high precision measurement source is compared to the value your device acquires or generates. The adjustment values needed to minimize the difference between the known and measured values are stored in the EEPROM of the device as calibration constants. Before performing a measurement, these constants are read out of the EEPROM and are used to adjust the calibration hardware on the device. NI-DAQ determines when this is necessary and does it automatically. If you are not using NI-DAQ, you must load these values yourself.

You can calibrate E Series devices using either internal calibration or external calibration.

Chapter 1 DAQ System Overview

Internal or Self-Calibration

Self-calibration is a process to adjust the device relative to a highly accurate and stable internal reference on the device. Self-calibration is similar to the auto-calibration or auto-zero found on some instruments. You should perform a self-calibration whenever environmental conditions, such as ambient temperature, change significantly. To perform self-calibration, use the self-calibrate function or VI that is included with your driver software. Self-calibration requires no external connections.

External Calibration

External calibration is a process to adjust the device relative to a traceable, high precision calibration standard. The accuracy specifications of your device change depending on how long it has been since your last external calibration. National Instruments recommends that you calibrate your device at least as often as the intervals listed in the accuracy specifications.

For a detailed calibration procedure for E Series devices (and B Series devices such as the NI 6013, NI 6014, NI 6015, and NI 6016) using NI-DAQmx, refer to the E/S/M/B Series Calibration Procedure for NI-DAQmx. For a detailed calibration procedure for B/E Series devices using Traditional NI-DAQ (Legacy), refer to the E Series Calibration

Procedure. These documents can be found by selecting Manual Calibration Procedures at

ni.com/calibration.

Signal Conditioning

Many sensors and transducers require signal conditioning before a computer-based measurement system can effectively and accurately acquire the signal. The front-end signal conditioning system can include functions such as signal amplification, attenuation, filtering, electrical isolation, simultaneous sampling, and multiplexing. In addition, many transducers require excitation currents or voltages, bridge completion, linearization, or high amplification for proper and accurate operation. Therefore, most computer-based measurement systems include some form of signal conditioning in addition to plug-in data acquisition DAQ devices.

Sensors and Transducers

Sensors can generate electrical signals to measure physical phenomena, such as temperature, force, sound, or light. Some commonly used sensors are strain gauges, thermocouples, thermistors, angular encoders, linear encoders, and resistance temperature detectors (RTDs).

E Series User Manual 1-4 ni.com

To measure signals from these various transducers, you must convert them into a form that a DAQ device can accept. For example, the output voltage of most thermocouples is very small and susceptible to noise. Therefore, you may need to amplify or filter the thermocouple output before digitizing it. The manipulation of signals to prepare them for digitizing is called signal conditioning.

For more information about sensors, refer to the following documents.

• For general information about sensors, visit

• If you are using LabVIEW, refer to the LabVIEW Help by selecting Help»Search the LabVIEW Help in LabVIEW, and then navigate to the Taking Measurements book on the Contents tab.

• If you are using other application software, refer to Common Sensors in the NI-DAQmx Help, which you can access from Start»All Programs»National Instruments»NI-DAQ»NI-DAQmx Help, or the LabVIEW 8.x Help.

Signal Conditioning Options

SCXI

SCXI is a front-end signal conditioning and switching system for various measurement devices, including E Series devices. An SCXI system consists of a rugged chassis that houses shielded signal conditioning modules that amplify, filter, isolate, and multiplex analog signals from thermocouples or other transducers. SCXI is designed for large measurement systems or systems requiring high-speed acquisition.

Chapter 1 DAQ System Overview

ni.com/sensors.

System features include:

• Modular architecture—Choose your measurement technology

• Expandability—Expand your system to 3,072 channels

• Integration—Combine analog input, analog output, digital I/O, and switching into a single, unified platform

• High bandwidth—Acquire signals at an aggregate rate of up to 333 kHz

• Connectivity—Select from SCXI modules with thermocouple connectors or terminal blocks

Chapter 1 DAQ System Overview

SCC

SCC is a front-end signal conditioning system for E Series plug-in data acquisition devices. A SCC system consists of a shielded carrier that holds up to 20 single or dual-channel SCC modules for conditioning thermocouples and other transducers. SCC is designed for small measurement systems where you need only a few channels of each signal type, or for portable applications. SCC systems also offer the most comprehensive and flexible signal connectivity options.

System features include:

• Modular architecture—Select your measurement technology on a

• Small-channel systems—Condition up to 16 analog input and eight

• Low-profile/portable—Integrates well with other laptop computer

• High bandwidth—Acquire signals at rates up to 1.25 MHz

• Connectivity—Incorporates panelette technology to offer custom

per-channel basis

digital I/O lines

measurement technologies

connectivity to thermocouple, BNC, LEMO Spec connectors

™

(B Series), and MIL

5B Series

5B is a front-end signal conditioning system for plug-in data acquisition devices. A 5B system consists of eight or 16 single-channel modules that plug into a backplane for conditioning thermocouples and other analog signals. National Instruments offers a complete line of 5B modules, carriers, backplanes, and accessories.

Note For more information about SCXI, SCC, and 5B series products, refer to ni.com/

signalconditioning

Cables and Accessories

NI offers a variety of products to use with E Series devices, such as:

• Cables and cable assemblies, shielded and ribbon

• Connector blocks, shielded and unshielded 50- and 68-pin screw terminals

• RTSI bus cables

E Series User Manual 1-6 ni.com

Chapter 1 DAQ System Overview

• SCXI modules and accessories for isolating, amplifying, exciting, and multiplexing signals for relays and analog output; with SCXI you can condition and acquire up to 3,072 channels

• Low-channel-count signal conditioning modules, devices, and accessories, including conditioning for strain gauges and RTDs, simultaneous sample-and-hold circuitry, and relays

For more specific information about these products, refer to

Using Accessories with Devices

Complete the following steps to choose a cable to connect an E Series device and an accessory:

1. Select an E Series device.

2. Using Table 1-1 or Table 1-2 as a guide, determine which accessories are appropriate for that device. Select an accessory. Table 1-3 provides descriptions for E Series device accessories.

3. Using Table 1-1 or Table 1-2 as a guide, determine which cable is required to connect your selected device and accessory.

Table 1-1. 68-Pin and DAQCard E Series Accessories and Recommended Cables

TBX-68, CB-68LP,

CB-68LPR, DAQ Signal

Accessory, CA-1000, BNC-2110, BNC-2111, BNC-2120, BNC-2090,

Device

68-pin E Series (except DAQCard)

SH6868EP (shielded) R6868 (unshielded)

Acessories and Recommended Cables

SCB-68

Connects directly to the device (PXI only

TB-2705

)

ni.com.

E Series DAQCards: NI 6024E, NI 6036E, NI 6062E

SHC6868EP/M (shielded) RC6868 (unshielded

)

—

Chapter 1 DAQ System Overview

Table 1-2. 100-Pin E Series Accessories and Recommended Cables

TBX-68,

CB-68LP, CB-68LPR, DAQ Signal

Accessory,

CA-1000,

BNC-2110, BNC-2111, BNC-2120, BNC-2090,

Device

SCB-68

Acessories and Recommended Cables

TBX-68,

CB-68LP,

CB-68LPR,

CA-1000,

BNC-2115

SCB-68

SCB-100

100-pin E Series with 64 AI channels: NI 6071E, NI 6031E, NI 6033E

100-pin E Series with 16 AI channels and 32 DIO lines: NI PCI-6025E

SH1006868 (shielded); splits into two 68-pin connectors; these accessories are used with the first 68-pin connector

Table 1-3. E Series DAQ Accessories Overview

SH1006868 (shielded); splits into two 68-pin connectors; these accessories are used with the second 68-pin connector

SH100100 (shielded)

Accessory Description

SCXI Signal Conditioning High-channel-count signal conditioning platform

SCC Modular Signal Conditioning Single or dual-channel signal conditioning modules

AMUX-64T, 5B, SSR, ER, and

External signal conditioning accessories

SC-204x Signal Conditioning

BNC-2110 BNC accessory for 68-pin E Series devices

E Series User Manual 1-8 ni.com

Chapter 1 DAQ System Overview

Table 1-3. E Series DAQ Accessories Overview (Continued)

Accessory Description

BNC-2111 BNC accessory for 68- or 100-pin E Series devices

BNC-2115 BNC accessory for extended I/O on 100-pin E Series

devices

BNC-2120 BNC accessory with function generator

(for 68-pin E Series devices)

BNC-2090 Rack-mountable BNC accessory (for 68-pin E Series

devices)

CA-1000 enclosure Configurable connectivity enclosure

TB-2705 Latching screw terminal block for PXI E Series modules

SCB-100 100-pin, shielded screw terminal block with breadboard

areas

SCB-68 68-pin, shielded screw terminal block with breadboard

areas

TBX-68 68-pin, DIN rail-mountable screw terminal block

CB-68LP, CB-68LPR 68-pin, low-cost screw terminal block

Signal Source and Demo Accessory DAQ signal accessory to demo and test analog, digital,

and counter/timer functions

Custom Cabling

NI offers a variety of cables and accessories to help you prototype your application or to use if you frequently change device interconnections.

However, if you want to develop your own cable, adhere to the following guidelines for best results.

• Use shielded twisted-pair wires for each differential AI pair. Connect the shield for each signal pair to the ground reference at the source.

• Route the analog lines separately from the digital lines.

• When using a cable shield, use separate shields for the analog and digital halves of the cable. Failure to do so results in noise coupling into the analog signals from transient digital signals.

Mating connectors and a back-shell kit for making custom 68-pin cables are available from NI. For more information about the 68- and 100-pin

Chapter 1 DAQ System Overview

connectors used for DAQ devices, refer to the KnowledgeBase document, Specifications and Manufacturers for Board Mating Connectors.

Programming Devices in Software

National Instruments measurement devices are packaged with NI-DAQ driver software, an extensive library of functions and VIs you can call from your application software, such as LabVIEW or LabWindows/CVI, to program all the features of your NI measurement devices. Driver software has an application programming interface (API), which is a library of VIs, functions, classes, attributes, and properties for creating applications for your device.

NI-DAQ includes two NI-DAQ drivers, Traditional NI-DAQ (Legacy) and NI-DAQmx. Each driver has its own API, hardware configuration, and software configuration. Refer to the DAQ Getting Started Guide for more information about the two drivers.

Traditional NI-DAQ (Legacy) and NI-DAQmx each include a collection of programming examples to help you get started developing an application. You can modify example code and save it in an application. You can use examples to develop a new application or add example code to an existing application.

To locate LabVIEW and LabWindows/CVI examples, open the National Instruments Example Finder:

• In LabVIEW, select Help»Find Examples.

• In LabWindows/CVI, select Help»NI Example Finder.

Measurement Studio, Visual Basic, and ANSI C examples are in the following directories:

• NI-DAQmx examples for Measurement Studio-supported languages are in the following directories:

– MeasurementStudio\VCNET\Examples\NI-DAQ

– MeasurementStudio\DotNET\Examples\NI-DAQ

• Traditional NI-DAQ (Legacy) examples for Visual Basic are in the following two directories:

–

NI-DAQ\Examples\Visual Basic with Measurement

Studio

for use with Measurement Studio

E Series User Manual 1-10 ni.com

directory contains a link to the ActiveX control examples

Chapter 1 DAQ System Overview

– NI-DAQ\Examples\VBasic directory contains the examples not

associated with Measurement Studio

• NI-DAQmx examples for ANSI C are in the

DAQmx ANSI C Dev

I/O Connector Signal Descriptions

Table 1-4 describes the signals found on the I/O connectors. For a summary of the I/O signals by device family, refer to the specifications document for your device. Refer to Appendix A, Device-Specific Information, for the I/O pinout for your device.

Table 1-4. I/O Connector Signal Descriptions

Signal Name Reference Direction Description

AI GND — — AI Ground—These pins are the reference point for

AI <0..15> AI GND Input AI Channels 0 through 15—You can configure each

AI <16..63> AI GND Input AI Channels 16 through 63

single-ended AI measurements in RSE mode and the bias current return point for DIFF measurements. All three ground references—AI GND, AO GND, and D GND—are connected on the device.

channel pair, AI <i, i+8> (i = 0..7), as either one differential input or two single-ended inputs.

(NI PCI-6031E/6033E/6071E only)—Each channel pair, AI <i, i +8> (i = 16..23, 32..39, 48..55), can be configured as either one differential input or two single-ended inputs.

AI SENSE — Input AI Sense—This pin is the reference node for AI <0..15> in

AI SENSE 2 — Input AI Sense 2—This pin is the reference node for

AO 0 AO GND Output Analog Channel 0 Output—This pin supplies the voltage

AO 1 AO GND Output Analog Channel 1 Output—This pin supplies the voltage

AO GND — — AO Ground—The AO voltages are referenced to these

NRSE mode.

AI <16..63> in NRSE mode.

output of AO channel 0.

output of AO channel 1.

pins. All three ground references—AI GND, AO GND, and D GND—are connected on the device.

Chapter 1 DAQ System Overview

Table 1-4. I/O Connector Signal Descriptions (Continued)

Signal Name Reference Direction Description

D GND — — Digital Ground—These pins supply the reference for the

digital signals at the I/O connector as well as the +5 VDC supply. All three ground references—AI GND, AO GND, and D GND—are connected on the device.

P0.<0..7> D GND Input or

AO EXT REF AO GND Input External Reference—This is the external reference input

P1.<0..7> D GND Input or

P2.<0..7> D GND Input or

P3.<0..7> D GND Input or

+5 V D GND Output +5 V Power Source—These pins provide +5 V power.

AI HOLD COMP D GND Output AI Hold Complete Event Signal—When enabled, this

EXT STROBE D GND Output External Strobe Signal—You can toggle this output with

PFI 0/AI START TRIG

D GND Input PFI 0—As an input, this pin is a programmable function

Output

Output AI Start Trigger Signal—As an output, this pin is the

Digital I/O Signals—You can individually configure each signal as an input or output. P0.6 and P0.7 can also control the up/down signal of Counters 0 and 1, respectively.

for the AO circuitry.

NI 6025E only—Port 1 bidirectional digital data lines for the 82C55A programmable peripheral interface. P1.7 is the most significant bit (MSB). P1.0 is the least significant bit (LSB).

NI 6025E only—Port 2 bidirectional digital data lines for the 82C55A programmable peripheral interface. P2.7 is the MSB. P2.0 is the LSB.

NI 6025E only—Port 3 bidirectional digital data lines for the 82C55A programmable peripheral interface. P3.7 is the MSB. P3.0 is the LSB.

signal pulses once for each A/D conversion in sampling mode. The low-to-high edge indicates when the input signal can be removed from the input or switched to another signal.

software controls to latch signals or trigger events on external devices. This functionality is not available in LabVIEW or NI-DAQ. EXT STROBE is used for controlling SCXI chassis, and it is not a general-purpose signal. If you want to use or control this signal, you must perform register-level programming.

interface (PFI).

ai/StartTrigger signal. In post-trigger DAQ sequences, a low-to-high transition indicates the initiation of the acquisition sequence. In applications with pre-trigger samples, a low-to-high transition indicates the initiation of the pre-trigger samples.

E Series User Manual 1-12 ni.com

Chapter 1 DAQ System Overview

Table 1-4. I/O Connector Signal Descriptions (Continued)

Signal Name Reference Direction Description

PFI 1/AI REF TRIG, PFI 1

D GND Input PFI 1—As an input, this pin is a PFI.

Output AI Reference Trigger Signal—As an output, this pin is

the ai/ReferenceTrigger signal. In applications with pre-trigger samples, a low-to-high transition indicates the initiation of the post-trigger samples. AI Reference Trigger is not used in applications with post-trigger samples.

PFI 2/AI CONV CLK

PFI 3/CTR 1 SRC D GND Input PFI 3—As an input, this pin is a PFI.

PFI 4/CTR 1 GATE

CTR 1 OUT D GND Input CTR 1 OUT—As an input, this pin can be used to route

PFI 5/AO SAMP CLK

PFI 6/AO START TRIG

D GND Input PFI 2—As an input, this pin is a PFI.

Output AI Convert Clock Signal—As an output, this pin is the

ai/ConvertClock signal. A high-to-low edge on AI CONV indicates that an A/D conversion is occurring.

Output Counter 1 Source Signal—As an output, this pin is the

Ctr1Source signal. This signal reflects the actual source connected to the general-purpose Counter 1.

D GND Input PFI 4—As an input, this pin is a PFI.

Output Counter 1 Gate Signal—As an output, this pin is the

Ctr1Gate signal. This signal reflects the actual gate signal connected to the general-purpose Counter 1.

signals directly to the RTSI bus.

Output Counter 1 Output Signal—As an output, this pin emits

the Ctr1InternalOutput signal.

D GND Input PFI 5—As an input, this pin is a PFI.

Output AO Sample Clock Signal—As an output, this pin is the

ao/SampleClock signal. A high-to-low edge on AO SAMP indicates that the AO primary group is being updated.

D GND Input PFI 6—As an input, this pin is a PFI.

Output AO Start Trigger Signal—As an output, this pin is the

ao/StartTrigger signal. In timed AO sequences, a low-to-high transition indicates the initiation of the waveform generation.

PFI 7/AI SAMP CLK

D GND Input PFI 7—As an input, this pin is a PFI.

Output AI Sample Clock Signal—As an output, this pin is the

ai/SampleClock signal. This pin pulses once at the start of each AI sample in the interval sample. A low-to-high transition indicates the start of the sample.

Chapter 1 DAQ System Overview

Table 1-4. I/O Connector Signal Descriptions (Continued)

Signal Name Reference Direction Description

PFI 8/CTR 0 SRC D GND Input PFI 8—As an input, this pin is a PFI.

Output Counter 0 Source Signal—As an output, this pin is the

PFI 9/CTR 0 GATE

CTR 1 OUT D GND Input Counter 1 Output Signal—As an input, this pin can be

FREQ OUT/USER <1..2>

D GND Input PFI 9—As an input, this pin is a PFI.

Output Counter 0 Gate Signal—As an output, this pin is the

Output As an output, this pin emits the Ctr0InternalOutput signal.

D GND Output Frequency Output Signal—This output is from the

I/O User <1..2>—On BNC devices, these signals connect

Ctr0Source signal. This signal reflects the actual source connected to the general-purpose Counter 0.

Ctr0Gate signal. This signal reflects the actual gate signal connected to the general-purpose Counter 0.

used to route signals directly to the RTSI bus.

frequency generator.

directly from a screw terminal to a BNC. For example, if you connect CTR 0 OUT to the USER 1 screw terminal with a wire, the Ctr0Out signal also is driven to the User 1 BNC.

Terminal Name Equivalents

With NI-DAQmx, National Instruments has revised its terminal names so they are easier to understand and more consistent among National Instruments hardware and software products. The revised terminal names used in this document are usually similar to the names they replace. Refer to Table 1-5 for a list of Traditional NI-DAQ (Legacy) terminal names and their NI-DAQmx equivalents.

Table 1-5. Terminal Name Equivalents

Traditional NI-DAQ (Legacy) NI-DAQmx

ACH# AI #

ACH# + AI # +

ACH# – AI # –

ACHGND AI GND

ACK# PFI #

E Series User Manual 1-14 ni.com

Chapter 1 DAQ System Overview

Table 1-5. Terminal Name Equivalents (Continued)

Traditional NI-DAQ (Legacy) NI-DAQmx

AIGND AI GND

AISENSE AI SENSE

AISENSE2 AI SENSE 2

AOGND AO G ND

CONVERT* AI CONV CLK or AI CONV

DAC0OUT AO 0

DAC1OUT AO 1

DGND D GND

DIO_# P0.#

DIO# P0.#

DIOA#, DIOB#, DIOC#... P0.#, P1.#, P2.#...

EXTREF AO EXT REF or EXT REF

EXT_STROBE EXT STROBE

EXT_TRIG EXT TRIG

EXT_CONV EXT CONV

FREQ_OUT FREQ OUT or F OUT

GPCTR0_GATE CTR 0 GATE

GPCTR0_OUT CTR 0 OUT

GPCTR0_SOURCE CTR 0 SOURCE or CTR 0 SRC

GPCTR1_GATE CTR 1 GATE

GPCTR1_OUT CTR 1 OUT

GPCTR1_SOURCE CTR 1 SOURCE or CTR 1 SRC

PA#, PB#, PC#... P0.#, P1.#, P2.#...

PFI# PFI #

PFI_# PFI #

PCLK# PFI #

Chapter 1 DAQ System Overview

Table 1-5. Terminal Name Equivalents (Continued)

Traditional NI-DAQ (Legacy) NI-DAQmx

REQ# PFI #

SCANCLK AI HOLD COMP or AI HOLD

SISOURCE AI Sample Clock Timebase

STARTSCAN AI SAMP CLK or AI SAMP

STOPTRIG# PFI #

TRIG1 AI START TRIG or AI START

TRIG2 AI REF TRIG or REF TRIG

UISOURCE AO Sample Clock Timebase

UPDATE AO SAMP C LK or AO SAMP

WFTRIG AO START T RIG or AO START

+5 V Power Source

The +5 V pins on the I/O connector supply +5 V power on the plug-in cards or from an internal step-down voltage regulator on DAQPads. You can use these pins, referenced to D GND, to power external circuitry. A self-resetting fuse protects the supply from overcurrent conditions. The fuse resets automatically within a few seconds after the overcurrent condition is removed.

Power rating (most devices): +4.65 to +5.25 VDC at 1 A.

To find your device power rating, refer to the specifications document for your device.

Caution Never connect these +5 V power pins to analog or digital ground or to any other

voltage source on the E Series device or any other device. Doing so can damage the device and the computer. NI is not liable for damage resulting from such a connection.

E Series User Manual 1-16 ni.com

Analog Input

Figure 2-1 shows the analog input circuitry of E Series devices.

AI+ AI+

Mux

AI– AI–

Mux

E Series AI signals include the following signals: AI <0..15>, AI SENSE, and AI GND. The NI 6031E/6033E/6071E devices include AI <16..63> and AI SENSE 2 in addition to the previous list of signals. The type of input signal source and the configuration of the AI channels being used determine how you connect these AI signals to the E Series devices. This chapter provides an overview of the different types of signal sources and AI configuration modes.

NI-PGIA NI-PGIA

ADC ADC

Analog Analog

Trigger Trigger

Figure 2-1. Analog Input Circuitry Block Diagram

AI FIFO AI FIFO

AI Timing Signals AI Timing Signals

AI Data AI Data

Analog Input Circuitry

Mux

Each E Series device has one analog-to-digital converter (ADC). The multiplexer (mux) routes one AI channel at a time to the ADC through the NI-PGIA. The mux also gives you the ability to use three different analog input terminal configuration. For more information, refer to the Analog

Input Terminal Configuration section.

Chapter 2 Analog Input

Instrumentation Amplifier (NI-PGIA)

The NI programmable gain instrumentation amplifier (NI-PGIA) is a measurement and instrument class amplifier that guarantees minimum settling times at all gains. The NI-PGIA can amplify or attenuate an AI signal to ensure that you use the maximum resolution of the ADC.

E Series devices use the NI-PGIA to deliver full 16- and 12-bit accuracy when sampling multiple channels at high gains and fast rates. E Series devices can sample channels in any order at the maximum conversion rate, and you can individually program each channel with a different input polarity and range, as discussed in the Input Polarity and Range section.

A/D Converter

The analog-to-digital converter (ADC) digitizes the AI signal by converting the analog voltage into a digital number.

AI FIFO

A large first-in-first-out (FIFO) buffer holds data during A/D conversions to ensure that no data is lost. E Series devices can handle multiple A/D conversion operations with DMA, interrupts, or programmed I/O.

Analog Trigger

Refer to the Analog Input Triggering section for information about the trigger circuitry of E Series devices.

AI Timing Signals

Refer to the Analog Input Timing Signals section for information about the analog input timing signals available on E Series devices.

Input Polarity and Range

You can individually program the input range of each AI channel on your E Series device. Input range refers to the set of input voltages that an analog input channel can digitize with the specified accuracy.

The input range affects the resolution of the E Series device for an AI channel. Resolution refers to the voltage of one ADC code. For example, a 16-bit ADC converts analog inputs into one of 65,536 (= 2 one of 65,536 possible digital values. These values are spread fairly evenly

E Series User Manual 2-2 ni.com

) codes that is

Chapter 2 Analog Input

across the input range. So, for an input range of 0 to 10 V, the voltage of each code of a 16-bit ADC is

10 V 0 V–

--------------------------- 153 μ V=

Some E Series devices support both unipolar and bipolar input ranges. A unipolar input range means that the input voltage range is between 0 and V

, where V

ref

that the input voltage range is between –V

is a positive reference voltage. A bipolar input range means

ref

and V

ref

The NI-PGIA applies a different gain setting to the AI signal depending on the input range. Gain refers to the factor by which the NI-PGIA multiplies (amplifies) the input signal before sending it to the ADC. For example, for the input range 0 to 100 mV, the NI-PGIA applies a gain of 100 to the signal; for an input range of 0 to 5 V, the NI-PGIA applies a gain of 2.

Choose an input range that matches the expected input range of your signal. A large input range can accommodate a large signal variation, but reduces the voltage resolution. Choosing a smaller input range improves the voltage resolution, but may result in the input signal going out of range.

For more information about programming these settings, refer to the NI-DAQmx Help or the LabVIEW 8.x Help.

Tables 2-1, 2-2, and 2-3 show the input ranges and resolutions supported by each E Series device.

Table 2-1. Input Ranges for NI 6020E, NI 6040E, NI 6052E, NI 6062E, and NI 6070E/6071E

Input Range Gain Polarity

0 to +10 V

0 to +5 V

0 to +2V

0 to +1 V

0 to +500 mV

0 to +200 mV

0 to +100 mV

100

NI 6020E NI 6040E NI 6052E NI 6062E

Unipolar 2.44 mV

1.22 mV

488 μV

244 μV

122 μV

48.8 μV

24.4 μV

2.44 mV

1.22 mV

488 μV

244 μV

122 μV

48.8 μV

24.4 μV

Precision

153 μV

76.3 μV

30.5 μV

15.3 μV

7.63 μV

3.05 μV

1.53 μV

2.44 mV

1.22 mV

488 μV

244 μV

122 μV

48.8 μV

24.4 μV

NI 6070E/

6071E

2.44 mV

1.22 mV

488 μV

244 μV

122 μV

48.8 μV

24.4 μV

Chapter 2 Analog Input

Table 2-1. Input Ranges for NI 6020E, NI 6040E, NI 6052E, NI 6062E, and NI 6070E/6071E (Continued)

Precision

Input Range Gain Polarity

–10 to +10 V

–5 to +5 V

–2.5 to +2.5 V

–1 to +1 V

–500 to +500 mV

–250 to +250 mV

–100 to +100 mV

–50 to +50 mV

0.5

100

Bipolar 4.88 mV

NI 6020E NI 6040E NI 6052E NI 6062E

2.44 mV

1.22 mV

488 μV

244 μV

122 μV

48.8 μV

24.4 μV

4.88 mV

2.44 mV

1.22 mV

488 μV

244 μV

122 μV

48.8 μV

24.4 μV

305 μV

153 μV

76.3 μV

30.5 μV

15.3 μV

7.63 μV

3.05 μV

1.53 μV

4.88 mV

2.44 mV

1.22 mV

488 μV

244 μV

122 μV

48.8 μV

24.4 μV

Table 2-2. Input Ranges for NI 6011E and NI 6030E/6031E/6032E/6033E

Precision

NI 6030E/6030E/

Input Range Gain Polarity

0 to +10 V

0 to +5 V

0 to +2 V

0 to +1 V

0 to +500 mV

0 to +200 mV

0 to +100 mV

100

Unipolar 153 μV

NI 6011E

76.3 μV

—

15.3 μV

—

1.53 μV

6032E/6033E

153 μV

76.3 μV

30.5 μV

15.3 μV

7.63 μV

3.05 μV

1.53 mV

NI 6070E/

6071E

4.88 mV

2.44 mV

1.22 mV

488 μV

244 μV

122 μV

48.8 μV

24.4 μV

–10 to +10 V

–5 to +5 V

–2 to +2 V

–1 to +1 V

–500 to +500 mV

–200 to +200 mV

–100 to +100 mV

E Series User Manual 2-4 ni.com

100

Bipolar 305 μV

153 μV

30.5 μV

3.05 μV

—

305 μV

153 μV

61.0 μV

30.5 μV

15.3 μV

6.10 μV

3.05 μV

Chapter 2 Analog Input

Note You can calibrate NI 6011E and NI 6030E/6031E/6032E/6033E circuitry for either

unipolar or bipolar polarity. If you mix unipolar and bipolar channels in the scan list and you are using NI-DAQ, NI-DAQ loads the calibration constants appropriate to the polarity for which AI channel 0 is configured.

Table 2-3. Input Ranges for NI 6023E/6024E/6025E and NI 6034E/6035E/6036E

Resolution

Input Range Gain

–10 to +10 V 0.5 4.88 mV 305 μV

–5 to +5 V 1 2.44 mV 153 μV

–500 to +500 mV 10 244 μV 15.3 μV

–50 to +50 mV 100 24.4 μV 1.53 μV

NI 6023E/6024E/6025E NI 6034E/6035E/6036E

Analog Input Terminal Configuration

To be flexible enough to interface with various signal sources, E Series devices have three different terminal configurations, also referred to as input modes: Non-Referenced Single-Ended (NRSE) input, Referenced Single-Ended (RSE) input, and differential (DIFF) input. Table 2-4 describes the three input configurations.

Table 2-4. Analog Input Terminal Configuration

AI Terminal Configuration Description

DIFF A channel configured in DIFF mode uses two AI lines.

One line connects to the positive input of the device programmable gain instrumentation amplifier (PGIA), and the other connects to the negative input of the PGIA.

RSE A channel configured in RSE mode uses one AI line, which

connects to the positive input of the PGIA. The negative input of the PGIA is internally tied to AI ground (AI GND).

NRSE A channel configured in NRSE mode uses one AI line, which

connects to the positive input of the PGIA. The negative input of the PGIA connects to the AI sense (AI SENSE) input.

Refer to the Connecting Analog Input Signals section for more information about using these input configurations.

Chapter 2 Analog Input

The single-ended input configurations provide up to 16 channels (64 channels on the NI 6031E, NI 6033E, and NI 6071E). The DIFF input configuration provides up to eight channels (32 channels on the NI 6031E, NI 6033E, and NI 6071E). Input modes are programmed on a per channel basis for multi-mode scanning. For example, you can configure the circuitry to scan 12 channels—four differentially-configured channels and eight single-ended channels.

With each input mode configuration, you use the PGIA in a different way. The PGIA applies gain and common-mode voltage rejection and presents high-input impedance to the AI signals connected to the device. Signals are routed to the positive and negative inputs of the PGIA through input multiplexers on the device. The PGIA converts two input signals to a new signal by taking the difference between the two input signals and multiplying the difference by the gain setting of the amplifier. The amplifier output voltage is referenced to the ground for the device. The device A/D converter (ADC) measures this output voltage when it performs A/D conversions. Figure 2-2 shows a diagram of the PGIA.

Instrumentation

in+

Amplifier

] × Gain

in–

Measured

Voltage

–

PGIA

in–

–

Vm = [V

in+

– V

Figure 2-2. E Series PGIA

E Series User Manual 2-6 ni.com

Chapter 2 Analog Input

Table 2-5 shows how signals are routed to the NI-PGIA.

Table 2-5. NI-PGIA Signal

AI Terminal Configuration

RSE AI <0..15> AI GND

NRSE AI <0..15> AI SENSE

DIFF AI <0..7> AI <8..15>

Reference all signals to ground either at the source or at the DAQ device. If you have a floating source, reference the signal to ground by using RSE mode or DIFF mode with bias resistors. Refer to the Differential

Connections for Non-Referenced or Floating Signal Sources section for

more information. If you have a grounded source, do not reference the signal to AI GND. You can avoid this reference by using DIFF or NRSE input modes.

Caution Exceeding the DIFF and common-mode input ranges distorts the input signals.

Exceeding the maximum input voltage rating can damage the device and the computer. NI is not liable for any damage resulting from such signal connections. The maximum input voltage ratings are listed in the specifications document for each E Series family.

(NI 6031E, NI 6033E, and NI 6071E Only) For these extended AI devices, the AI

signals are AI <0..63>, AI SENSE, AI SENSE 2, and AI GND. In single-ended mode, signals connected to AI <0..63> are routed to the positive input of the PGIA. In differential mode, signals connected to AI <0..7, 16..23, 32..39, 48..55> are routed to the positive input of the PGIA, and signals connected to AI <8..15, 24..31, 40..47, 56..63> are routed to the negative input of the PGIA.

Signals Routed to the

Positive Input of the

NI-PGIA

Signals Routed to the Negative Input of the

NI-PGIA

(NI 6013/6014 Only) These devices do not support RSE mode. To measure

single-ended signals relative to AI GND, connect AI SENSE to AI GND on your accessory and use NRSE mode.

Chapter 2 Analog Input

Dither

With 12-bit E Series devices, you can improve resolution by enabling the Gaussian dither generator and averaging acquired samples. Dithering is a feature on all 12-bit E Series devices. When you enable dithering, you add approximately 0.5 LSB converted by the ADC. This addition is useful for applications involving averaging to increase device resolution, as in calibration or spectral analysis. In such applications, noise modulation decreases and differential linearity improves with the addition of dithering. When taking DC measurements, such as when checking device calibration, enable dithering and average about 1,000 points for a single reading. This process removes the effects of quantization and reduces measurement noise, resulting in improved resolution. For high-speed applications not involving averaging or spectral analysis, you may want to disable dithering to reduce noise. The software enables and disables the dithering circuitry.

Figure 2-3 illustrates the effect of dithering on signal acquisition. Graph A shows a small (±4 LSB) sine wave acquired with dithering off. The ADC quantization is clearly visible. Graph B shows 50 such acquisitions averaged together; quantization is still plainly visible. Graph C shows the sine wave acquired with dithering on. There is a considerable amount of visible noise, but averaging about 50 such acquisitions, as shown in graph D, eliminates both the added noise and the effects of quantization. Dithering has the effect of forcing quantization noise to become a zero-mean random variable rather than a deterministic function of the input signal.

of white Gaussian noise to the signal to be

rms

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Chapter 2 Analog Input

LSBs

6.0

4.0

2.0

0.0

–2.0

–4.0

–6.0

0 100 200 300 400 500

a. Dither Disabled; No Averaging

LSBs

6.0

4.0

2.0

0.0

–2.0

–4.0

–6.0

0 100 200 300 400 500

c. Dither Enabled; No Averaging

LSBs

6.0

4.0

2.0

0.0

–2.0

–4.0

–6.0

0 100 200 300 400 500

b. Dither Disabled; Average of 50 Acquisitions

LSBs

6.0

4.0

2.0

0.0

–2.0

–4.0

–6.0

0 100 200 300 400 500

d. Dither Enabled; Average of 50 Acquisitions

Figure 2-3. Dither

Dither cannot be disabled on devices with 16-bit ADCs.

Multichannel Scanning Considerations

E Series devices can scan multiple channels at high rates and digitize the signals accurately. However, you should consider several issues when designing your measurement system to ensure the high accuracy of your measurements.

In multichannel scanning applications, accuracy is affected by settling time. When your E Series device switches from one AI channel to another AI channel, the device configures the NI-PGIA with the input range of the new channel. The NI-PGIA then amplifies the input signal with the gain and polarity for the new input range. Settling time refers to the time it takes the NI-PGIA to amplify the input signal to the desired accuracy before it is sampled by the ADC. The specification document for your DAQ device shows its settling time.

Chapter 2 Analog Input

E Series devices are designed to have fast settling times. Several factors can increase the settling time, which decreases the accuracy of your measurements. To ensure fast settling times, you should (in order of importance):

• Use Low Impedance Sources

• Use Short High-Quality Cabling

• Carefully Choose the Channel Scanning Order

• Avoid Scanning Faster than Necessary

All E Series devices can acquire data in the interval-scanning mode, which fully accommodates multichannel acquisition in both round-robin and pseudo-simultaneous fashions. In multichannel scanning mode, the maximum conversion rate of the device is distributed among the number of channels scanned. With the addition of external signal conditioners, such as the SCXI-1140 or the SC-2040, you can perform true simultaneous sample-and-hold acquisition of eight channels.

Use Low Impedance Sources

To ensure fast settling times, your signal sources should have an impedances of <1 kΩ. The settling time specifications for your device assume a 1 kΩ source. Large source impedances increase the settling time of the PGIA, and so decrease the accuracy at fast scanning rates.

Settling times increase when scanning high-impedance signals due to a phenomenon called charge injection. Multiplexers contain switches, usually made of switched capacitors. When one of the channels, for example channel 0, is selected in a multiplexer, those capacitors accumulate charge. When the next channel, for example channel 1, is selected, the accumulated charge leaks backward through that channel. If the output impedance of the source connected to channel 1 is high enough, the resulting reading of channel 1 can partially reflect the voltage on channel 0. This is referred to as ghosting, or crosstalk.

If your source impedance is high, you can decrease the scan rate to allow the PGIA more time to settle. Another option is to use a voltage follower circuit external to your DAQ device to decrease the impedance seen by the DAQ device. Refer to the KnowledgeBase document, How Do I Create a Buffer to Decrease the Source Impedance of My Analog Input Signal?, for more information.

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Use Short High-Quality Cabling

Using short high-quality cables can decrease several effects that decrease accuracy including crosstalk, transmission line effects, and noise. The capacitance of the cable can also effectively increase the settling time.

National Instruments recommends using individually shielded, twisted-pair wires that are 2 m or less to connect AI signals to the device. Refer to the Connecting Analog Input Signals section for more information.

Carefully Choose the Channel Scanning Order

Avoid Switching from a Large to a Small Input Range

Switching from a channel with a large input range to a channel with a small input range can greatly increase the settling time.

Suppose a 4 V signal is connected to channel 0 and a 1 mV signal is connected to channel 1. The input range for channel 0 is 0–10 V and the input range of channel 1 is 0–100 mV.

When the multiplexer switches from channel 0 to channel 1, the input to the PGIA switches from 4 V to 1 mV. The approximately 4 V step from 4 V to 1 mV is 4,000% of the new full-scale range. For a 12-bit device to settle within 0.012% (120 ppm or 1/2 LSB) of the 100 mV full-scale range on channel 1, the input circuitry must settle to within 0.0003% (3 ppm or 1/80 LSB) of the 4 V step. Some devices can take as long as 100 μs for the circuitry to settle this much.

Chapter 2 Analog Input

To avoid this effect, you should arrange your channel scanning order so that transitions from large to small input ranges are infrequent. Another useful technique is to insert a grounded channel between signal channels.

In general, you do not need this extra settling time when the PGIA is switching from a small input range to a larger input range.

Insert Grounded Channel between Signal Channels

Another technique to improve settling time is to connect an input channel to ground. Then insert this channel in the scan list between two of your signal channels. The input range of the grounded channel should match the input range of the signal after the grounded channel in the scan list.

Consider again the example above where a 4 V signal is connected to channel 0 and a 1 mV signal is connected to channel 1. The input range for channel 0 is 0–10 V and the input range of channel 1 is 0–100 mV.

Chapter 2 Analog Input

Connect channel 2 to AI GND (or you can use the internal ground signal; refer to Internal Channels for E Series Devices in the NI-DAQmx Help or the LabVIEW 8.x Help. Set the input range of channel 2 to 0–100 mV to match channel 1. Then scan channels in the order: 0, 2, 1.

Inserting a grounded channel between signal channels improves settling time because the NI-PGIA adjusts to the new input range setting faster when the input is grounded.

Minimize Voltage Step between Adjacent Channels

When scanning between channels, the settling time increases when the voltage step is larger between channels. This is true even if all channels being scanned have the same input range. If you know the expected input range of your signals, you can group signals with similar expected ranges together in your scan list.

For example, suppose all channels in a system use a –5 to 5 V input range. The signals on channels 0, 2, and 4 vary between 4.3 V and 5 V. The signals on channels 1, 3, and 5 vary between –4 V and 0 V. Scanning channels in the order 0, 2, 4, 1, 3, 5 will produce more accurate results than scanning channels in the order 0, 1, 2, 3, 4, 5.

Avoid Scanning Faster than Necessary

Designing your system to scan at slower speeds gives the PGIA more time to settle to a more accurate level. Consider the following examples.

Example 1

Averaging many AI samples can increase the accuracy of the reading by decreasing noise effects. In general, the more points you average, the more accurate the final result will be. However, you may choose to decrease the number of points you average and slow down the scanning rate.

Suppose you want to sample 10 channels over a period of 20 ms and average the results. You could acquire 500 points from each channel at a scan rate of 250 kS/s. Another method would be to acquire 1,000 points from each channel at a scan rate of 500 kS/s. Both methods take the same amount of time. Doubling the number of samples averaged (from 500 to 1,000) decreases the effect of noise by a factor of 1.4 (the square root of 2). However, doubling the number of samples (in this example) decreases the time the PGIA has to settle from 4 μs to 2 μs. In some cases, the slower scan rate system returns more accurate results.

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Example 2

If the time relationship between channels is not critical, you can sample from the same channel multiple times and scan less frequently. For example, suppose an application requires averaging 100 points from channel 0 and averaging 100 points from channel 1. You could alternate reading between channels

that is, read one point from channel 0, then one point from channel 1, and so on. You also could read all 100 points from channel 0 and then read 100 points from channel 1. The second method switches between channels much less often and is affected much less by settling time.

AI Data Acquisition Methods

When performing analog input measurements, there are several different data acquisition methods available. You can either perform software-timed or hardware-timed acquisitions. hardware-timed acquisitions can be buffered or non-buffered.

Software-Timed Acquisitions

With a software-timed acquisition, software controls the rate of the acquisition. Software sends a separate command to the hardware to initiate each ADC conversion. In NI-DAQmx, software-timed acquisitions are referred to as having On Demand timing. software-timed acquisitions are also referred to as immediate or static acquisitions and are typically used for reading a single point of data.

Chapter 2 Analog Input

Hardware-Timed Acquisitions

With hardware-timed acquisitions, a digital hardware signal controls the rate of the acquisition. This signal can be generated internally on your device or provided externally.

Hardware-timed acquisitions have several advantages over software-timed acquisitions:

• The time between samples can be much shorter.

• The timing between samples can be deterministic.

Hardware-timed acquisitions can use hardware triggering.

Hardware-timed operations can be buffered or non-buffered. A buffer is a temporary storage in the computer memory where acquired samples are stored.

Chapter 2 Analog Input

Buffered

In a buffered acquisition, data is moved from the DAQ device onboard FIFO memory to a PC buffer using DMA or interrupts before it is transferred to ADE memory. Buffered acquisitions typically allow for much faster transfer rates than non-buffered acquisitions because data is moved in large blocks, rather than one point at a time. For more information, refer to the Data Transfer Methods section of Chapter 9, Bus

Interface.

One property of buffered I/O operations is the sample mode. The sample mode can be either finite or continuous.

Finite sample mode acquisition refers to the acquisitions of a specific, predetermined number of data samples. Once the specified number of samples has been collected into the buffer, the acquisition stops. If you use a reference trigger, you must use finite sample mode.

Continuous acquisition refers to the acquisition of an unspecified number of samples. Instead of acquiring a set number of data samples and stopping, a continuous acquisition continues until you stop the operation. A continuous acquisition is also referred to as double-buffered or circular-buffered acquisition.

If data cannot be transferred across the bus fast enough, the data in the FIFO will be overwritten and an error will be generated. With continuous operations, if the user program does not read data out of the PC buffer fast enough to keep up with the data transfer, the buffer could reach an overflow condition, causing an error to be generated.

Non-Buffered

In non-buffered acquisitions, data is read directly from the FIFO on the device. Typically, hardware-timed non-buffered operations are used to read single samples with good latency and known time increments between them.

Analog Input Triggering

Analog input supports three different triggering actions: start, reference, and pause. An analog or digital hardware trigger can initiate these actions. All E Series devices support digital triggering, and some also support analog triggering. Refer to Chapter 10, Triggering, for more information on analog and digital triggering. Refer to Appendix A, Device-Specific

Information, to find your device triggering options.

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AI Start Trigger Signal

You can use the AI Start Trigger (ai/StartTrigger) signal to begin a measurement acquisition. A measurement acquisition consists of one or more samples. If you do not use triggers, you begin a measurement with a software command. Once the acquisition begins, you can configure the acquisition to stop when one of the following conditions apply:

• When a certain number of points are sampled (in finite mode)

• After a hardware reference trigger (in finite mode)

• With a software command (in continuous mode)

Using a Digital Source

To use ai/StartTrigger with a digital source, specify a source and an edge. The source can be an external signal connected to any PFI or RTSI <0..6> pin. The source can also be one of several internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

Also, specify whether the measurement acquisition begins on the rising edge or falling edge of the ai/StartTrigger signal.

Chapter 2 Analog Input

Figure 2-4 shows the timing requirements of the ai/StartTrigger source.

Rising-Edge

Polar ity

Falling-Edge

Polar ity

tw = 10 ns minimum

Figure 2-4. ai/StartTrigger Source Timing Requirements

Using an Analog Source

When you use an analog trigger source, the acquisition begins on the first rising edge of the Analog Comparison Event signal. Refer to the Triggering

with an Analog Source section of Chapter 10, Triggering, for more

information on analog trigger sources.

Chapter 2 Analog Input

Outputting the AI Start Trigger Signal

You can configure the PFI 0/AI START TRIG pin to output the ai/StartTrigger signal. The output pin reflects the ai/StartTrigger signal regardless of what signal you specify as its source.

The output is an active high pulse. Figure 2-5 shows the timing behavior of the PFI 0/AI START TRIG pin configured as an output.

Figure 2-5. PFI 0/AI START TRIG Timing Behavior

The PFI 0/AI START TRIG pin is configured as an input by default.

When acquisitions use a start trigger without a reference trigger, they are posttrigger acquisitions because data is acquired only after the trigger. The device also uses ai/StartTrigger to initiate pretrigger DAQ operations. In most pretrigger applications, a software trigger generates ai/StartTrigger. Refer to the AI Reference Trigger Signal section for a complete description of the use of ai/StartTrigger and ai/ReferenceTrigger in a pretrigger DAQ operation.

tw = 50 to 100 ns

AI Reference Trigger Signal

You can use the AI Reference Trigger (ai/ReferenceTrigger) signal to stop a measurement acquisition. In Traditional NI-DAQ (Legacy), a reference trigger is referred to as a stop trigger. To use a reference trigger, specify a buffer of finite size and a number of pretrigger samples (samples that occur before the reference trigger). The desired number of posttrigger samples (samples that occur after the reference trigger) is the buffer size minus the number of pretrigger samples.

Once the acquisition begins, the DAQ device writes samples to the buffer. After the DAQ device captures the specified number of pretrigger samples, the DAQ device begins to look for the reference trigger condition. If the reference trigger condition occurs before the DAQ device captures the specified number of pretrigger samples, the DAQ device ignores the condition.

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Chapter 2 Analog Input

If the buffer becomes full, the DAQ device continuously discards the oldest samples in the buffer to make space for the next sample. You can access this data (with some limitations) before the DAQ device discards it. Refer to the KnowledgeBase document, Can a Pretriggered Acquisition be Continuous?, for more information.

When the reference trigger occurs, the DAQ device continues to write samples to the buffer until the buffer contains the desired number of posttrigger samples. Figure 2-6 shows the final buffer.

Reference Trigger

Pre-Trigger Samples

Figure 2-6. Reference Trigger Final Buffer

Post-Trigger Samples

Complete Buffer

Chapter 2 Analog Input

Using a Digital Source

To use ai/ReferenceTrigger with a digital source, specify a source and an edge. The source can be an external signal connected to any PFI or RTSI <0..6> pin. The source can also be one of several internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

Also, specify whether the measurement acquisition stops on the rising edge or falling edge of the ai/ReferenceTrigger signal.

Figure 2-7 shows the timing requirements of the ai/ReferenceTrigger source.

Rising-Edge

Polarity

Falling-Edge

Polarity

tw = 10 ns minimum

Figure 2-7. ai/ReferenceTrigger Source Timing Requirements

Using an Analog Source

When you use an analog trigger source, the acquisition stops on the first rising edge of the Analog Comparison Event signal. Refer to the Triggering

with an Analog Source section of Chapter 10, Triggering, for more

information on analog trigger sources.

Outputting the AI Reference Trigger Signal

You can configure the PFI 1/AI REF TRIG pin to output the ai/ReferenceTrigger signal. The output pin reflects the ai/ReferenceTrigger signal regardless of what signal you specify as its source.

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The output is an active high pulse. Figure 2-8 shows the timing behavior of the PFI 1/AI REF TRIG pin configured as an output.

The PFI 1/AI REF TRIG pin is configured as an input by default.

AI Pause Trigger Signal

You can use the AI Pause Trigger (ai/PauseTrigger) signal to pause and resume a measurement acquisition. This signal is not available as an output.

Chapter 2 Analog Input

tw = 50 to 100 ns

Figure 2-8. PFI 1/AI REF TRIG Timing Behavior

Using a Digital Source

To use ai/PauseTrigger, specify a source and a polarity. The source can be an external signal connected to any PFI or RTSI <0..6> pin. The source can also be one of several other internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

Also, specify whether the measurement sample is paused when ai/PauseTrigger is at a logic high or low level.

Using an Analog Source

When you use an analog trigger source, the internal sample clock pauses when the Analog Comparison Event signal is low and resumes when the signal goes high (or vice versa). Refer to the Triggering with an Analog

Source section of Chapter 10, Triggering, for more information on analog

trigger sources.

Note Pause triggers are only sensitive to the level of the source, not the edge.

Chapter 2 Analog Input

Connecting Analog Input Signals

The following sections discuss the types of signal sources, specify the use of single-ended and DIFF measurements, and provide recommendations for measuring both floating and ground-referenced signal sources.

Table 2-6 summarizes the recommended input configuration for both types of signal sources.

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Table 2-6. Recommended Input Configurations

Signal Source Type

Floating Signal Sources

(Not Connect To Building

Ground-Referenced Signal

Ground)

Chapter 2 Analog Input

Sources

Input

Differential (DIFF)

Single-Ended— Ground Referenced (RSE)

Examples

• Ungrounded thermocouples

• Signal conditioning with isolated outputs

• Battery devices

+ –

AI +

AI –

AI GND

–

ext

AI GND

–

Examples

• Plug-in instruments with non-isolated outputs

+ –

NOT RECOMMENDED

+ –

Ground-loop losses, Vg, are added

AI +

AI –

+ V

to measured signal.

AI GND

–

AI GND

–

Single-Ended— Non-Referenced (NRSE)

–

AI SENSE

ext

AI GND

–

AI GND

+ –

AI SENSE

AI GND

–

Refer to the Analog Input Terminal Configuration section for descriptions of the input modes.

Chapter 2 Analog Input

Types of Signal Sources

When configuring the input channels and making signal connections, first determine whether the signal sources are floating or ground-referenced.

Floating Signal Sources

A floating signal source is not connected to the building ground system, but has an isolated ground-reference point. Some examples of floating signal sources are outputs of transformers, thermocouples, battery-powered devices, optical isolators, and isolation amplifiers. An instrument or device that has an isolated output is a floating signal source. You must connect the ground reference of a floating signal to the AI ground of the device to establish a local or onboard reference for the signal. Otherwise, the measured input signal varies as the source floats outside the common-mode input range.

Ground-Referenced Signal Sources

A ground-referenced signal source is connected to the building system ground, so it is already connected to a common ground point with respect to the device, assuming that the computer is plugged into the same power system as the source. Non-isolated outputs of instruments and devices that plug into the building power system fall into this category.

The difference in ground potential between two instruments connected to the same building power system is typically between 1 and 100 mV, but the difference can be much higher if power distribution circuits are improperly connected. If a grounded signal source is incorrectly measured, this difference can appear as measurement error. Follow the connection instructions for grounded signal sources to eliminate this ground potential difference from the measured signal.

Differential Connection Considerations

A DIFF connection is one in which the AI signal has its own reference signal or signal return path. These connections are available when the selected channel is configured in DIFF input mode. The input signal is connected to the positive input of the PGIA, and its reference signal, or return, is connected to the negative input of the PGIA.

When you configure a channel for DIFF input, each signal uses two multiplexer inputs one for the signal and one for its reference signal.

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Chapter 2 Analog Input

Therefore, half as many DIFF channel pairs are available compared to individual channels.

Use DIFF input connections for any channel that meets any of the following conditions:

• The input signal is low-level (less than 1 V).

• The leads connecting the signal to the device are greater than 3 m (10 ft.).

• The input signal requires a separate ground-reference point or return signal.

• The signal leads travel through noisy environments.

DIFF signal connections reduce noise pickup and increase common-mode noise rejection. DIFF signal connections also allow input signals to float within the common-mode limits of the PGIA.

Differential Connections for Ground-Referenced Signal Sources

Figure 2-9 shows how to connect a ground-referenced signal source to a channel on the device configured in DIFF mode.

Ground-

Referenced

Signal

Source

Common-

Mode

Noise and

Ground

Potential

I/O Connector

–

AI –

–

Input Multiplexers

AI SENSE

AI GND

E Series Device Configured in DIFF Mode

Instrumentation

Amplifier

PGIA

–

Measured

Voltage

–

Figure 2-9. Differential Connections for Ground-Referenced Signal Sources

Chapter 2 Analog Input

With this type of connection, the PGIA rejects both the common-mode noise in the signal and the ground potential difference between the signal source and the device ground, shown as V

in this figure.

Common-Mode Signal Rejection Considerations

Ground-referenced signal sources with differential connections to the device are referenced to some ground point with respect to the device. In this case, the PGIA can reject any voltage caused by ground potential differences between the signal source and the device. In addition, with DIFF input connections, the PGIA can reject common-mode noise pickup in the leads connecting the signal sources to the device. The PGIA can reject common-mode signals as long as AI + and AI – (input signals) are both within ±11 V of AI GND.

Differential Connections for Non-Referenced or Floating Signal Sources

Figure 2-10 shows how to connect a floating signal source to a channel configured in DIFF mode.

AI +

Bias Resistors (see text)

Bias

Current

Return

Paths

I/O Connector

–

AI –

Input Multiplexers

AI SENSE

AI GND

E Series Device Configured in DIFF Mode

Instrumentation

PGIA

–

Amplifier

Measured

Voltage

–

Ground-

Referenced

Signal

Source

Figure 2-10. Connecting a Floating Signal Source to a DIFF Mode Channel

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Chapter 2 Analog Input

The previous figure shows two bias resistors connected in parallel with the signal leads of a floating signal source. If you do not use the resistors and the source is truly floating, the source is not likely to remain within the common-mode signal range of the PGIA. The PGIA then saturates, causing erroneous readings.

You must reference the source to AI GND. The easiest way to make this reference is to connect the positive side of the signal to the positive input of the PGIA and connect the negative side of the signal to AI GND as well as to the negative input of the PGIA, without using resistors. This connection works well for DC-coupled sources with low source impedance (less than 100 Ω).

However, for larger source impedances, this connection leaves the DIFF signal path significantly off balance. Noise that couples electrostatically onto the positive line does not couple onto the negative line because it is connected to ground. Hence, this noise appears as a DIFF-mode signal instead of a common-mode signal, and the PGIA does not reject it. In this case, instead of directly connecting the negative line to AI GND, connect the negative line to AI GND through a resistor that is about 100 times the equivalent source impedance. The resistor puts the signal path nearly in balance, so that about the same amount of noise couples onto both connections, yielding better rejection of electrostatically coupled noise. This configuration does not load down the source (other than the very high input impedance of the PGIA).

You can fully balance the signal path by connecting another resistor of the same value between the positive input and AI GND, as shown in this figure. This fully balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination (sum) of the two resistors. If, for example, the source impedance is 2 kΩ and each of the two resistors is 100 kΩ, the resistors load down the source with 200 kΩ and produce a –1% gain error.

Both inputs of the PGIA require a DC path to ground in order for the PGIA to work. If the source is AC coupled (capacitively coupled), the PGIA needs a resistor between the positive input and AI GND. If the source has low-impedance, choose a resistor that is large enough not to significantly load the source but small enough not to produce significant input offset voltage as a result of input bias current (typically 100 kΩ to 1 MΩ). In this case, connect the negative input directly to AI GND. If the source has high output impedance, balance the signal path as previously described using the same value resistor on both the positive and negative inputs; be aware that there is some gain error from loading down the source.

Chapter 2 Analog Input

Single-Ended Connection Considerations

A single-ended connection is one in which the device AI signal is referenced to a ground that it can share with other input signals. The input signal connects to the positive input of the PGIA, and the ground connects to the negative input of the PGIA.

When every channel is configured for single-ended input, up to 64 AI channels are available.

You can use single-ended input connections for any input signal that meets the following conditions:

• The input signal is high-level (greater than 1 V).

• The leads connecting the signal to the device are less than 10 ft. (3 m).

• The input signal can share a common reference point with other signals.

DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions.

Using the DAQ Assistant, you can configure the channels for RSE or NRSE input modes. RSE mode is used for floating signal sources; in this case, the device provides the reference ground point for the external signal. NRSE input mode is used for ground-referenced signal sources; in this case, the external signal supplies its own reference ground point and the device should not supply one. Refer to the DAQ Assistant Help for more information about the DAQ Assistant.

In the single-ended modes, more electrostatic and magnetic noise couples into the signal connections than in DIFF configurations. The coupling is the result of differences in the signal path. Magnetic coupling is proportional to the area between the two signal conductors. Electrical coupling is a function of how much the electric field differs between the two conductors.

With this type of connection, the PGIA rejects both the common-mode noise in the signal and the ground potential difference between the signal source and the device ground, shown as V

in Figure 2-11.

Common-Mode Signal Rejection Considerations

Ground-referenced signal sources with single-ended connections to a device are referenced to some ground point with respect to the device. In this case, the PGIA can reject any voltage caused by ground potential differences between the signal source and the device.

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Single-Ended Connections for Floating Signal Sources (RSE Configuration)

Figure 2-11 shows how to connect a floating signal source to a channel configured for RSE mode.

Programmable Gain

Floating

Signal

Source

–

I/O Connector

Input Multiplexers

AI SENSE

AIGND

Selected Channel in RSE Configuration

Instrumentation

Amplifier

PGIA

–

Chapter 2 Analog Input

Measured

Voltage

–

Figure 2-11. Single-Ended Connections for Floating Signal Sources

(RSE Configuration)

Single-Ended Connections for Grounded Signal Sources (NRSE Configuration)

To measure a grounded signal source with a single-ended configuration, you must configure your device in the NRSE input configuration. Connect the signal to the positive input of the PGIA, and connect the signal local ground reference to the negative input of the PGIA. The ground point of the signal, therefore, connects to the AI SENSE pin, as shown in Figure 2-12. Any potential difference between the device ground and the signal ground appears as a common-mode signal at both the positive and negative inputs of the PGIA, and this difference is rejected by the amplifier. If the input circuitry of a device were referenced to ground, as it is in the RSE input configuration, this difference in ground potentials would appear as an error in the measured voltage.

Chapter 2 Analog Input

I/O Connector

AI <0..15>

Ground-

Referenced

Signal

Source

Common-

Mode Noise

and Ground

Potential

–

Figure 2-12. Single-Ended Connections for Grounded Signal Sources

Field Wiring Considerations

Environmental noise can seriously affect the measurement accuracy of the device if you do not take proper care when running signal wires between signal sources and the device. The following recommendations apply mainly to AI signal routing to the device, although they also apply to signal routing in general.

Minimize noise pickup and maximize measurement accuracy by taking the following precautions:

• Use DIFF AI connections to reject common-mode noise.

• Use individually shielded, twisted-pair wires to connect AI signals to the device. With this type of wire, the signals attached to the positive and negative input channels are twisted together and then covered with a shield. You then connect this shield only at one point to the signal source ground. This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference.

Instrumentation

Amplifier

Input Multiplexers

AI SENSE

AI GND

E Series Device Configured in NRSE Mode

PGIA

–

(NRSE Configuration)

Measured

Voltage

–

Refer to the NI Developer Zone document, Field Wiring and Noise Considerations for Analog Signals, for more information.

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Configuring AI Modes in Software

You can program channels on an E Series device to acquire in different modes, but once a channel mode is specified, it cannot be reused for another mode. For example, to configure AI 0 for DIFF mode and AI 1 for RSE mode, configure AI 0 and AI 8 in DIFF mode and AI 1 and AI GND in RSE mode. In this configuration, AI 8 is not used in a single-ended configuration.

Traditional NI-DAQ (Legacy)

To enable multi-mode scanning in LabVIEW using Traditional NI-DAQ (Legacy), use the coupling & input config control of the AI Config VI. This input has a one-to-one correspondence with the channels control of the VI. You must list all channels either individually or in groups of channels with the same input configuration. For example, if you want AI 0 to be differential, and AI 1 and AI 2 to be RSE, Figure 2-13 demonstrates how to program this configuration in LabVIEW.

Chapter 2 Analog Input

Figure 2-13. AI Config VI

To enable multi-mode scanning using NI-DAQ functions, call the

AI_Configure

function for each channel.

NI-DAQmx

To enable multi-mode scanning in LabVIEW using NI-DAQmx, use the

NI-DAQmx Create Virtual Channel.vi of the NI-DAQmx API. You

must use a new VI for each channel or group of channels configured in a different input mode. In Figure 2-14, channel 0 is configured in differential mode, and channel 1 is configured in RSE mode.

Chapter 2 Analog Input

Figure 2-14. NI-DAQmx Create Virtual Channel.vi

Analog Input Timing Signals

In order to provide all of the timing functionality described throughout this section, the DAQ-STC provides an extremely powerful and flexible timing engine. Figure 2-15 summarizes all of the clock routing and timing options provided by the analog input timing engine.

RTSI 7

20 MHz

Timebase

Master

Timebase

Onboard

Clock

PFI 0–9,

RTSI 0–6

200

ai/SampleClock

Timebase

ai/ConvertClock

Timebase

Ctr0InternalOutput

Onboard

Clock

Divisor

Onboard

Clock

Divisor

PFI 0–9,

RTSI 0–6

PFI 0–9,

RTSI 0–6

Ctr0InternalOutput

ai/SampleClock

ai/Convert

Clock

Figure 2-15. Analog Input Timing Engine Clock Routing and Timing Options.

E Series devices use the ai/SampleClock and ai/ConvertClock signals to perform interval sampling. As Figure 2-16 shows, ai/SampleClock controls the sample period, which is determined by the following equation:

1/sample period = sample rate

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Chapter 2 Analog Input

Channel 0

Channel 1

Convert Period

Sample Period

Figure 2-16. Interval Sample

The ai/ConvertClock signal controls the convert period, which is determined by the following equation:

1/convert period = convert rate

NI-DAQmx chooses the default convert rate to allow for the maximum settling time between conversions. Typically, this rate is the sampling rate for the task multiplied by the number of channels in the task.

The sampling rate is the fastest you can acquire data on the device and still achieve accurate results. For example, if an E Series device has a sampling rate of 200 kS/s, this sampling rate is aggregate one channel at 200 kS/s or two channels at 100 kS/s per channel illustrates the relationship.

An acquisition with posttrigger data allows you to view data that is acquired after a trigger event is received. A typical posttrigger DAQ sequence is shown in Figure 2-17. The sample counter is loaded with the specified number of posttrigger samples, in this example, five. The value decrements with each pulse on ai/SampleClock, until the value reaches zero and all desired samples have been acquired.

ai/StartTrigger

ai/SampleClock

ai/ConvertClock

Sample Counter

Figure 2-17. Typical Posttrigger Acquisition

13042

Chapter 2 Analog Input

ai/StartTrigger

An acquisition with pretrigger data allows you to view data that is acquired before the trigger of interest, in addition to data acquired after the trigger. Figure 2-18 shows a typical pretrigger DAQ sequence. The ai/StartTrigger signal can be either a hardware or software signal. If ai/StartTrigger is set up to be a software start trigger, an output pulse appears on the AI START TRIG line when the acquisition begins. When the ai/StartTrigger pulse occurs, the sample counter is loaded with the number of pretrigger samples, in this example, four. The value decrements with each pulse on ai/SampleClock, until the value reaches zero. The sample counter is then loaded with the number of posttrigger samples, in this example, three.

ai/Reference Trigger

ai/SampleClock

Sample Counter

If an ai/ReferenceTrigger pulse occurs before the specified number of pretrigger samples are acquired, the trigger pulse is ignored. Otherwise, when the ai/ReferenceTrigger pulse occurs, the sample counter value decrements until the specified number of posttrigger samples have been acquired. Refer to the Analog Input Triggering section for more information about start and reference triggers.

AI Start Trigger Signal

• When a certain number of points are sampled (in finite mode)

• After a hardware reference trigger (in finite mode)

• With a software command (in continuous mode)

Don't Care

01231 0222

Figure 2-18. Typical Pretrigger Acquisition

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Chapter 2 Analog Input

Using a Digital Source

Also, specify whether the measurement acquisition begins on the rising edge or falling edge of the ai/StartTrigger signal.

Figure 2-19 shows the timing requirements of the ai/StartTrigger source.

Rising-Edge

Polar ity

Falling-Edge

Polar ity

tw = 10 ns minimum

Figure 2-19. ai/StartTrigger Timing Requirements

Using an Analog Source

When you use an analog trigger source, the acquisition begins on the first rising edge of the Analog Comparison Event signal. Refer to Chapter 10,

Triggering, for more information on analog triggering.

Outputting the AI Start Trigger Signal

You can configure the PFI 0/AI START TRIG pin to output the ai/StartTrigger signal. The output pin reflects the ai/StartTrigger signal regardless of what signal you specify as its source.

Chapter 2 Analog Input

The output is an active high pulse. Figure 2-20 shows the timing behavior of the PFI 0/AI START TRIG pin configured as an output.

tw = 50 to 100 ns

Figure 2-20. PFI 0/AI START TRIG Timing Behavior

The PFI 0/AI START TRIG pin is configured as an input by default.

AI Reference Trigger Signal

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Chapter 2 Analog Input

When the reference trigger occurs, the DAQ device continues to write samples to the buffer until the buffer contains the desired number of posttrigger samples. Figure 2-21 shows the final buffer.

Reference Trigger

Pre-Trigger Samples

Complete Buffer

Figure 2-21. Reference Trigger Final Buffer

Post-Trigger Samples

Using a Digital Source

Also, specify whether the measurement acquisition stops on the rising edge or falling edge of the ai/ReferenceTrigger signal.

Figure 2-22 shows the timing requirements of the ai/ReferenceTrigger source.

Rising-Edge

Polar ity

Falling-Edge

Polar ity

tw = 10 ns minimum

Figure 2-22. ai/ReferenceTrigger Source Timing Requirements

Chapter 2 Analog Input

Using an Analog Source

When you use an analog trigger source, the acquisition stops on the first rising edge of the Analog Comparison Event signal. Refer to Chapter 10,

Triggering, for more information on analog triggering.

Outputting the AI Reference Trigger Signal

You can configure the PFI 1/AI REF TRIG pin to output the ai/ReferenceTrigger signal. The output pin reflects the ai/ReferenceTrigger signal regardless of what signal you specify as its source.

The output is an active high pulse. Figure 2-23 shows the timing behavior of the PFI 1/AI REF TRIG pin configured as an output.

tw = 50 to 100 ns

Figure 2-23. PFI 1/AI REF TRIG Timing Behavior

The PFI 1/AI REF TRIG pin is configured as an input by default.

AI Pause Trigger Signal

You can use the AI Pause Trigger (ai/PauseTrigger) signal to pause and resume a measurement acquisition. This signal is not available as an output.

Using a Digital Source

Also, specify whether the measurement sample is paused when ai/PauseTrigger is at a logic high or low level.

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Using an Analog Source

Note Pause triggers are only sensitive to the level of the source, not the edge.

AI Sample Clock Signal

You can use the AI Sample Clock (ai/SampleClock) signal to initiate a set of measurements. Your E Series device samples the AI signals of every channel in the scan list once for every ai/SampleClock. A measurement acquisition consists of one or more samples.

The source of the ai/SampleClock signal can be internal or external. You specify whether the measurement sample begins on the rising edge or falling edge of the ai/SampleClock signal.

Using an Internal Source

By default, ai/SampleClock is created internally by dividing down the ai/SampleClockTimebase. Refer to the AI Sample Clock Timebase Signal section for more information.

Chapter 2 Analog Input

Several other internal signals can be routed to the sample clock. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

Using an External Source

You can use a signal connected to any PFI or RTSI <0..6> pin as the source of ai/SampleClock. Figure 2-24 shows the timing requirements of the ai/SampleClock source.

Chapter 2 Analog Input

Rising-Edge

Polar ity

Falling-Edge

Polar ity

tw = 10 ns minimum

Figure 2-24. ai/SampleClock Timing Requirements

Outputting the AI Sample Clock Signal

You can configure the PFI 7/AI SAMP CLK pin to output the ai/SampleClock signal. The output pin reflects the ai/SampleClock signal regardless of what signal you specify as its source.

You specify the output to have one of two behaviors. With the pulse behavior, your DAQ device briefly pulses the PFI 7/AI SAMP CLK pin once for every occurrence of ai/SampleClock.

With level behavior, your DAQ device drives PFI 7/AI SAMP CLK high during the entire sample. The device drives the pin high in response to the ai/StartTrigger signal. The device drives the pin low in response to the last ai/ConvertClock of the sample.

Figures 2-25 and 2-26 show the timing of pulse and level behavior of the PFI 7/AI SAMP CLK pin.

ai/SampleClock

tw = 50 to 100 ns

a. Pulse Behavior

Figure 2-25. ai/SampleClock Input

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Chapter 2 Analog Input

ai/StartTrigger

ai/ConvertClock

ai/SampleClock

= 10 ns minimum t

off

b. Level Behavior. Two Conversions per Sample.

Figure 2-26. ai/SampleClock Output

off

The PFI 7/AI SAMP CLK pin is configured as an input by default.

Other Timing Requirements

A counter on your device internally generates ai/SampleClock unless you select some external source. The ai/StartTrigger signal starts this counter. It is stopped automatically by hardware once a finite acquisition completes or manually through software. When using an internally generated ai/SampleClock, you can also specify a configurable delay from the ai/StartTrigger to the first ai/SampleClock pulse. By default, this delay is two ticks of the ai/SampleClockTimebase signal. When using an externally generated ai/SampleClock in NI-DAQmx, you must ensure the clock signal is matched with respect to the timing requirements of the ai/ConvertClock signal. Failure to do so may result in ai/SampleClock pulses that are masked off and acquisitions with erratic sampling intervals. Refer to the AI

Convert Clock Signal section for more information about the timing

requirements between ai/ConvertClock and ai/SampleClock.

Chapter 2 Analog Input

Figure 2-27 shows the relationship of the ai/SampleClock signal to the ai/StartTrigger signal.

ai/SampleClockTimebase

ai/StartTrigger

ai/SampleClock

Figure 2-27. ai/SampleClock and ai/StartTrigger

AI Sample Clock Timebase Signal

Any PFI can externally input the AI Sample Clock Timebase (ai/SampleClockTimebase) signal, which is not available as an output on the I/O connector. The ai/SampleClockTimebase is divided down to provide the Onboard Clock source for the ai/SampleClock. You can configure the polarity selection for ai/SampleClockTimebase as either rising or falling edge.

Delay

From

Start

Trigger

The maximum allowed frequency is 20 MHz, with a minimum pulse width of 23 ns high or low. There is no minimum frequency limitation.

The 20MHzTimebase or the 100kHzTimebase generates ai/SampleClockTimebase unless you select some external source. Figure 2-28 shows the timing requirements for ai/SampleClockTimebase.

tp = 50 ns minimum

= 23 ns minimum

Figure 2-28. ai/SampleClockTimebase Timing Requirements

E Series User Manual 2-40 ni.com

AI Convert Clock Signal

You can use the AI Convert Clock (ai/ConvertClock) signal to initiate a single A/D conversion on a single channel. A sample (controlled by the AI Sample Clock) consists of one or more conversions.

You specify either an internal or external signal as the source of ai/ConvertClock. You also specify whether the measurement sample begins on the rising edge or falling edge of the ai/ConvertClock signal.

By default, NI-DAQmx will choose a conversion rate so the pulses are evenly spaced throughout the sample. This allows for the maximum settling time between conversions. To approximate simultaneous sampling, you can manually increase the conversion rate. By default, Traditional NI-DAQ (Legacy) chooses the fastest conversion rate possible for the device with 10 μs of delay added between each conversion to allow the channel to some time settle.

Caution Setting the conversion rate higher than the maximum rate specified for your

device will result in errors.

Using an Internal Source

One of the following internal signals can drive ai/ConvertClock:

• CTR 0 OUT (the output of Counter 0)

• AI Convert Clock Timebase (divided down)

Chapter 2 Analog Input

The AI Convert Clock Timebase is driven by either the AI Sample Clock Timebase or the Master Timebase. A programmable internal counter then divides down the AI Convert Clock Timebase to generate ai/ConvertClock. The counter is started by the ai/SampleClock signal and continues to count down and reload itself until the sample is finished. It then reloads itself in preparation for the next ai/SampleClock pulse.

Several other internal signals can be routed to convert clock timebase through RTSI. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

Chapter 2 Analog Input

Using an External Source

You can use a signal connected to any PFI or RTSI <0..6> pin as the source of ai/ConvertClock. Figure 2-29 shows the timing requirements of the ai/ConvertClock source.

Rising-Edge

Polar ity

Falling-Edge

Polar ity

= 10 ns minimum

Figure 2-29. ai/ConvertClock Source Timing Requirements

Outputting the AI Convert Clock Signal

You can configure the PFI 2/AI CONV CLK pin to output the ai/ConvertClock signal. The output pin reflects the ai/ConvertClock signal regardless of what signal you specify as its source.

Figure 2-30 shows the timing of behavior of the PFI 2/AI CONV CLK pin configured as an output.

tw = 50 to 150 ns

Figure 2-30. PFI 2/AI CONV CLK Timing Behavior

The PFI 2/AI CONV CLK pin is configured as an input by default.

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Chapter 2 Analog Input

Using a Delay from Sample Clock to Convert Clock

When using an internally generated ai/ConvertClock, you can also specify a configurable delay from the ai/SampleClock to the first ai/ConvertClock pulse within the sample. By default, this delay is two ticks of the ai/ConvertClockTimebase signal.

Figure 2-31 shows the relationship of the ai/SampleClock signal to the ai/ConvertClock signal.

ai/ConvertClockTimebase

ai/SampleClock

ai/ConvertClock

Delay

Convert

From

Sample

Period

Clock

Figure 2-31. ai/SampleClock and ai/ConvertClock

Other Timing Requirements

The sample and conversion level timing of the DAQ-STC work such that clock signals are gated off unless the proper timing requirements are met. For example, the device ignores both the ai/SampleClock and ai/ConvertClock until it receives a valid ai/StartTrigger signal. Once the device recognizes an ai/SampleClock pulse, it ignores subsequent ai/SampleClock pulses until it receives the correct number of ai/ConvertClock pulses.

Similarly, the device ignores all ai/ConvertClock pulses until it recognizes an ai/SampleClock pulse. Once the device receives the correct number of ai/ConvertClock pulses, it ignores subsequent ai/ConvertClock pulses until it receives another ai/SampleClock. Figure 2-32 shows timing sequences for a four-channel acquisition and demonstrate proper and improper sequencing of the ai/SampleClock and ai/ConvertClock signals.

Chapter 2 Analog Input

ai/SampleClock

ai/ConvertClock

ai/SampleClock

ai/ConvertClock

12 3

Sample Clock too fast for Convert Clock. Sample Clock pulses are gated off.

12 3

Convert Clock too fast for Sample Clock. Convert Clock pulses are gated off.

ai/SampleClock

ai/ConvertClock

123

Improperly matched Sample Clock and Convert Clock. Leads to aperiodic sampling.

ai/SampleClock

ai/ConvertClock

12 3

Properly matched Sample Clock and Convert Clock.

Figure 2-32. ai/SampleClock and ai/ConvertClock Signals

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AI Convert Clock Timebase Signal

Either the ai/SampleClockTimebase or the MasterTimebase signal can serve as the source of the AI Convert Clock Timebase signal (ai/ConvertClockTimebase), which is not available as an output on the I/O connector. The ai/ConvertClockTimebase is divided down to provide the Onboard Clock source for the ai/ConvertClock.

Master Timebase Signal

The Master Timebase (MasterTimebase) signal, or Onboard Clock, is the timebase from which all other internally generated clocks and timebases on the board are derived. It controls the timing for the analog input, analog output, and counter subsystems. It is available as an output on the I/O connector, but you must use one or more counters to do so.

The maximum allowed frequency for the MasterTimebase is 20 MHz, with a minimum pulse width of 23 ns high or low. There is no minimum frequency limitation.

The two possible sources for the MasterTimebase signal are the internal 20MHzTimebase signal or an external signal through RTSI 7. Typically the 20MHzTimebase signal is used as the MasterTimebase unless you wish to synchronize multiple devices, in which case, you should use RTSI 7. Refer to Chapter 8, Real-Time System Integration Bus (RTSI), for more information about which signals are available through RTSI.

Chapter 2 Analog Input

Figure 2-33 shows the timing requirements for MasterTimebase.

tp = 50 ns minimum

= 23 ns minimum

Figure 2-33. MasterTimebase Timing Requirements

Chapter 2 Analog Input

AI Hold Complete Event Signal

AI Hold Complete Event (ai/HoldCompleteEvent) is an output-only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A/D conversion begins. The polarity of this output is software-selectable, but is typically configured so that a low-to-high leading edge can clock external AI multiplexers indicating when the input signal has been sampled and can be removed. This signal has a 400 to 500 ns pulse width and is software-enabled. Figure 2-34 shows the timing for ai/HoldCompleteEvent.

ai/ConvertClock

ai/HoldCompleteEvent

External Strobe Signal

External Strobe is an output-only signal on the EXT STROBE pin that generates either a single pulse or a sequence of eight pulses in the hardware-strobe mode. An external device can use this signal to latch signals or to trigger events. In the single-pulse mode, software controls the level of External Strobe. A 10 ms and a 1.2 μs clock are available for generating a sequence of eight pulses in the hardware-strobe mode. Figure 2-35 shows the timing for the hardware-strobe mode External Strobe signal.

= 50 to 100 ns

= 400 to 500 ns

Figure 2-34. ai/HoldCompleteEvent Timing

wtw

tw = 600 ns or 5 μs

Figure 2-35. External Strobe Timing

Note

External Strobe is used for signal conditioning with SCXI and is not available for

use with NI-DAQmx.

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Chapter 2 Analog Input

Getting Started with AI Applications in Software

You can use the E Series device in the following analog input applications:

• Single-Point Analog Input

• Finite Analog Input

• Continuous Analog Input

You can perform these applications through DMA, interrupt, or programmed I/O data transfer mechanisms. Some of the applications also use start, reference, and pause triggers.

For more information about programming analog input applications and triggers in software, refer to the NI-DAQmx Help or the LabVIEW 8.x Help.

Analog Output

Figure 3-1 shows the analog output circuitry of E Series devices.

AO 0

AO 1

Many E Series boards have analog output functionality. E Series boards that support analog output have two AO channels that are controlled by a single clock and are capable of waveform generation. Refer to Appendix A,

Device-Specific Information, for specific information about the capabilities

of your device.

Analog Output Circuitry

DACs

Digital-to-analog converters (DACs) convert digital codes to analog voltages.

DAC0

AO FIFO

DAC1

Polarity Select Reference Select

Figure 3-1. Analog Output Block Diagram

AO Data

AO Sample Clock

DAC FIFO

The DAC FIFO enables analog output waveform generation. It is a first-in-first-out (FIFO) memory buffer between the computer and the DACs that allows you to download all the points of a waveform to your board without host computer interaction.

Chapter 3 Analog Output

AO Sample Clock

The DAC reads a sample from the FIFO with every cycle of the AO Sample Clock signal and generates the AO voltage.

Polarity and Reference Selection

Polarity and reference selection allow you to set the AO range. Refer to Table 3-1 to set the range for your device. Refer to the Polarity Selection and the Reference Selection sections for more information.

Table 3-1. Polarity and Reference Range

AO Range Polarity Select Reference Select

±10 V Bipolar Internal

0–10 V Unipolar Internal

±EXT REF Bipolar AO External Reference Signal

0–EXT REF Unipolar AO External Reference Signal

To generate the AO External Reference signal, drive an analog voltage on the AO EXT REF pin.

Note Not all E Series devices have every polarity and reference select option. For

example, devices such as the NI 6013/6014 and NI 6015/6016 are bipolar only with an internal reference. Refer to the specifications document for your device for more information about range-setting options.

Reference Selection

(NI 6020E, NI PXI-6040E, NI 6052E, NI 6062E, NI 6070E/6071E, and PCI-MIO-16E-4 Devices Only)

internal reference of 10 V or to the external reference signal connected to the external reference (AO EXT REF) pin on the I/O connector. This signal applied to EXT REF should be within ±11 V. You do not need to configure both channels for the same mode.

E Series User Manual 3-2 ni.com

You can connect each DAC to the device

Polarity Selection

(NI 6020E, NI PXI-6030E, NI PCI-6031E, NI PXI-6040E, NI 6052E, PCI-MIO-16E-4, and PCI-MIO-16XE-10 Devices Only)

each AO channel for either unipolar or bipolar output. All other E Series devices are configured for bipolar output only. A unipolar configuration has a range of 0 to V range of –V used by the DACs in the AO circuitry and can be either the +10 V onboard reference or for supported devices, an externally supplied reference within ±11 V. You do not need to configure both channels for the same range.

Selecting a bipolar range for a particular DAC means that any data written to that DAC is interpreted as two’s complement format. In two’s complement format, data values written to the AO channel can be either positive or negative. If you select unipolar range, data is interpreted in straight binary format. In straight binary mode, data values written to the AO channel range must be positive.

Reglitch Selection

to +V

ref

Chapter 3 Analog Output

With these devices, you can configure

at the analog output. A bipolar configuration has a

ref

at the analog output. V

ref

is the voltage reference

ref

(NI 6052E and NI 6070E/6071E Devices Only) In normal operation, a DAC

output glitches whenever it is updated with a new value. The glitch energy differs from code to code and appears as distortion in the frequency spectrum. Each analog output contains a reglitch circuit that generates uniform glitch energy at every code rather than large glitches at the major code transitions. This uniform glitch energy appears as a multiple of the update rate in the frequency spectrum. Notice that this reglitch circuit does not eliminate the glitches; it only makes them more uniform in size. Reglitching is normally disabled at startup and the software can independently enable each channel.

Minimizing Glitches on the Output Signal

When you use a DAC to generate a waveform, you may observe glitches on the output signal. These glitches are normal; when a DAC switches from one voltage to another, it produces glitches due to released charges. The largest glitches occur when the most significant bit (MSB) of the DACcode switches. You can build a lowpass deglitching filter to remove some of these glitches, depending on the frequency and nature of the output signal. Visit

ni.com/support for more information about minimizing glitches.

Chapter 3 Analog Output

AO Data Generation Methods

When performing an analog output operation, there are several different data generation methods available. You can either perform software-timed or hardware-timed generations. Hardware-timed generations can be non-buffered or buffered.

Software-Timed Generations

With a software-timed generation, software controls the rate at which data is generated. Software sends a separate command to the hardware to initiate each DAC conversion. In NI-DAQmx, software-timed generations are referred to as On Demand timing. software-timed generations are also referred to as immediate or static operations. They are typically used for writing a single value out, such as a constant DC voltage.

Hardware-Timed Generations

With a hardware-timed generation, a digital hardware signal controls the rate of the generation. This signal can be generated internally on your device or provided externally.

Hardware-timed generations have several advantages over software-timed generations:

• The time between samples can be much shorter.

• The timing between samples can be deterministic.

• Hardware-timed generations can use hardware triggering.

Hardware-timed operations can be buffered or non-buffered. A buffer is a temporary storage in computer memory for acquired or to-be-generated samples.

Buffered

In a buffered generation, data is moved from a PC buffer to the DAQ device onboard FIFO using DMA or interrupts before it is written to the DACs one sample at a time. Buffered generations typically allow for much faster transfer rates than non-buffered generations because data is moved in large blocks, rather than one point at a time. Refer to Chapter 9, Bus Interface, for more information on data transfer methods.

One property of buffered I/O operations is the sample mode. The sample mode can be either finite or continuous.

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Chapter 3 Analog Output

Finite sample mode generation refers to the generation of a specific, predetermined number of data samples. Once the specified number of samples has been written out, the generation stops.

Continuous generation refers to the generation of an unspecified number of samples. Instead of generating a set number of data samples and stopping, a continuous generation continues until you stop the operation. There are several different methods of continuous generation that control what data is written. These methods are regeneration, FIFO regeneration, and non-regeneration modes.

Regeneration is the repetition of the data that is already in the buffer. Standard regeneration is when data from the PC buffer is continually downloaded to the FIFO to be written out. New data can be written to the PC buffer at any time without disrupting the output.

With FIFO regeneration, the entire buffer is downloaded to the FIFO and regenerated from there. Once the data is downloaded, new data cannot be written to the FIFO. To use FIFO regeneration, the entire buffer must fit within the FIFO size. The advantage of using FIFO regeneration is that it does not require communication with the main host memory once the operation is started, thereby preventing any problems that may occur due to excessive bus traffic.

With non-regeneration, old data will not be repeated. New data must be continually written to the buffer. If the program does not write new data to the buffer at a fast enough rate to keep up with the generation, the buffer will underflow and cause an error.

Non-Buffered

In hardware-timed non-buffered generations, data is written directly to the FIFO on the device. Typically, hardware-timed non-buffered operations are used to write single samples with known time increments between them and good latency.

Analog Output Triggering

Analog output supports two different triggering actions: start and pause. An analog or digital hardware trigger can initiate these actions. All E Series devices support digital triggering, and some also support analog triggering. Refer to Appendix A, Device-Specific Information, to find your device triggering options.

Chapter 3 Analog Output

AO Start Trigger Signal

You can use the AO Start Trigger (ao/StartTrigger) signal to initiate a waveform generation. If you do not use triggers, you begin a generation with a software command.

Using a Digital Source

To use ao/StartTrigger, specify a source and an edge. The source can be an external signal connected to any PFI or RTSI <0..6> pin. The source can also be one of several internal signal on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

Figure 3-2 shows the timing requirements of the ao/StartTrigger digital source.

Rising-Edge

Polarity

Falling-Edge

Polarity

tw = 10 ns minimum

Figure 3-2. ao/StartTrigger Digital Source Timing Requirements

Using an Analog Source

When you use an analog trigger source, the waveform generation begins on the first rising edge of the Analog Comparison Event signal. Refer to Chapter 10, Triggering, for more information on analog triggering.

Outputting the AO Start Trigger Signal

You can configure the PFI 6/AO START TRIG pin to output the ao/StartTrigger signal. The output pin reflects the ao/StartTrigger signal regardless of what signal you specify as its source.

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The output is an active high pulse. Figure 3-3 shows the timing behavior of the PFI 6/AO START TRIG pin configured as an output.

The PFI 6/AO START TRIG pin is configured as an input by default.

AO Pause Trigger Signal

You can use the AO Pause trigger signal (ao/PauseTrigger) to mask off samples in a DAQ sequence. That is, when ao/PauseTrigger is active, no samples occur.

The ao/PauseTrigger does not stop a sample that is in progress. The pause does not take effect until the beginning of the next sample. This signal is not available as an output.

Chapter 3 Analog Output

tw = 25 to 50 ns

Figure 3-3. PFI 6/AO START TRIG Timing Behavior

Using a Digital Source

To use ao/PauseTrigger, specify a source and a polarity. The source can be an external signal connected to any PFI or RTSI <0..6> pin. The source can also be one of several other internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

Also, specify whether the samples are paused when ao/PauseTrigger is at a logic high or low level.

Using an Analog Source

When you use an analog trigger source, the samples are paused when the Analog Comparison Event signal is at a high level. Refer to Chapter 10,

Triggering, for more information on analog triggering.

Chapter 3 Analog Output

Connecting Analog Output Signals

The AO signals are AO 0, AO 1, and AO GND. AO 0 is the voltage output signal for AO channel 0. AO 1 is the voltage output signal for AO channel 1.

AO GND is the ground reference signal for both AO channels and the external reference signal. Figure 3-4 shows how to make AO connections to the device.

Load

I/O Connector

V OUT

AO 0

–

AO GND

–

AO 1

Channel 0

Channel 1

Analog Output Channels

E Series Device

Figure 3-4. Analog Output Connections

Note

Not all E Series devices use the external reference signal. Refer to the specifications

document for your device.

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Waveform Generation Timing Signals

There is one AO Sample Clock that causes all AO channels to update simultaneously. Figure 3-5 summarizes the timing and routing options provided by the analog output timing engine.

Chapter 3 Analog Output

RTSI 7

20 MHz

Timebase

Master

Timebase

Onboard

Clock

AO Start Trigger Signal

You can use the AO Start Trigger (ao/StartTrigger) signal to initiate a waveform generation. If you do not use triggers, you begin a generation with a software command.

Using a Digital Source

Figure 3-6 shows the timing requirements of the ao/StartTrigger digital source.

RTSI 0 –6

200

PFI 0–9,

Ctr1InternalOutput

ao/SampleClock

Timebase

Onboard

Clock

Divisor

PFI 0–9,

RTSI 0–6

Figure 3-5. Analog Output Timing Engine

ao/SampleClock

Rising-Edge

Polarity

Falling-Edge

Polarity

tw = 10 ns minimum

Figure 3-6. ao/StartTrigger Digital Source Timing Requirements

Chapter 3 Analog Output

Using an Analog Source

Outputting the AO Start Trigger Signal

You can configure the PFI 6/AO START TRIG pin to output the ao/StartTrigger signal. The output pin reflects the ao/StartTrigger signal regardless of what signal you specify as its source.

The output is an active high pulse. Figure 3-7 shows the timing behavior of the PFI 6/AO START TRIG pin configured as an output.

tw = 25 to 50 ns

Figure 3-7. PFI 6/AO START TRIG Timing Behavior

The PFI 6/AO START TRIG pin is configured as an input by default.

AO Pause Trigger Signal

You can use the AO Pause trigger signal (ao/PauseTrigger) to mask off samples in a DAQ sequence. That is, when ao/PauseTrigger is active, no samples occur.

The ao/PauseTrigger does not stop a sample that is in progress. The pause does not take effect until the beginning of the next sample. This signal is not available as an output.

Using a Digital Source

To use ao/Pause Trigger, specify a source and a polarity. The source can be an external signal connected to any PFI or RTSI <0..6> pin. The source can also be one of several other internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

Also, specify whether the samples are paused when ao/PauseTrigger is at a logic high or low level.

E Series User Manual 3-10 ni.com

Using an Analog Source

When you use an analog trigger source, the samples are paused when the Analog Comparison Event signal is at a high level. Refer to Chapter 10,

Triggering, for more information on analog triggering.

AO Sample Clock Signal

You can use the AO Sample Clock (ao/SampleClock) signal to initiate AO samples. Each sample updates the outputs of all the DACs.

The source of the ao/SampleClock signal can be internal or external. You can specify whether the DAC update begins on the rising edge or falling edge of the ao/SampleClock signal.

Using an Internal Source

By default, ao/SampleClock is created internally by dividing down the ao/SampleClockTimebase.

Several other internal signals can be routed to the sample clock. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.

Chapter 3 Analog Output

Using an External Source

You can use a signal connected to any PFI or RTSI <0..6> pin as the source of ao/SampleClock. Figure 3-8 shows the timing requirements of the ao/SampleClock source.

Rising-Edge

Polarity

Falling-Edge

Polarity

tw = 10 ns minimum

Figure 3-8. ao/SampleClock Source Timing Requirements

Chapter 3 Analog Output

Outputting the AO Sample Clock Signal

You can configure the PFI 5/AO SAMP CLK pin to output the ao/SampleClock signal. The output pin reflects the ao/SampleClock signal regardless of what signal you specify as its source.

The output is an active high pulse. Figure 3-9 shows the timing behavior of the PFI 5/AO SAMP CLK pin configured as an output.

tw = 50 to 75 ns

Figure 3-9. PFI 5/AO SAMP CLK Timing Behavior

The PFI 5/AO SAMP CLK is configured as an input by default.

Other Timing Requirements

A counter on your device internally generates ao/SampleClock unless you select some external source. The ao/StartTrigger signal starts this counter. It is stopped automatically by hardware once a finite acquisition completes or manually through software. When using an internally generated ao/SampleClock in NI-DAQmx, you can also specify a configurable delay from the ao/StartTrigger to the first ao/SampleClock pulse. By default, this delay is two ticks of the ao/SampleClockTimebase signal.

E Series User Manual 3-12 ni.com

Figure 3-10 shows the relationship of the ao/SampleClock signal to the ao/StartTrigger signal.

ao/SampleClockTimebase

ao/StartTrigger

ao/SampleClock

Figure 3-10. ao/SampleClock and ao/StartTrigger

AO Sample Clock Timebase Signal

You can select any PFI or RTSI pin as well as many other internal signals as the AO Sample Clock Timebase (ao/SampleClockTimebase) signal. This signal is not available as an output on the I/O connector. The ao/SampleClockTimebase is divided down to provide the Onboard Clock source for the ao/SampleClock. You specify whether the samples begin on the rising or falling edge of ao/SampleClockTimebase.

Chapter 3 Analog Output

Delay

From Start

Trigger

You might use the ao/SampleClockTimebase signal if you want to use an external sample clock signal, but need to divide the signal down. If you want to use an external sample clock signal, but do not need to divide the signal, then you should use the ao/SampleClock signal rather than the ao/SampleClockTimebase. If you do not specify an external sample clock timebase, NI-DAQ uses the Onboard Clock.

Chapter 3 Analog Output

Figure 3-11 shows the timing requirements for the ao/SampleClockTimebase signal.

tp = 50 ns minimum

= 23 ns minimum

Figure 3-11. ao/SampleClockTimebase Signal Timing Requirements

The maximum allowed frequency is 20 MHz, with a minimum pulse width of 10 ns high or low. There is no minimum frequency.

Unless you select an external source, either the 20MHzTimebase or 100kHzTimebase generates the ao/SampleClockTimebase signal.

Master Timebase Signal

The maximum allowed frequency for the MasterTimebase is 20 MHz, with a minimum pulse width of 23 ns high or low. There is no minimum frequency limitation.

E Series User Manual 3-14 ni.com

Chapter 3 Analog Output

Figure 3-12 shows the timing requirements for MasterTimebase.

tp = 50 ns minimum

= 23 ns minimum

Figure 3-12. MasterTimebase Timing Requirements

Getting Started with AO Applications in Software

You can use the E Series device in the following analog output applications:

• Single-Point Generation

• Finite Generation

• Continuous Generation

• Waveform Generation

You can perform these generations through DMA, interrupt, or programmed I/O data transfer mechanisms. Some of the applications also use start triggers and pause triggers.

Note For more information about programming analog output applications and triggers in

software, refer to the NI-DAQmx Help or the LabVIEW 8.x Help.

Digital I/O

Figure 4-1 shows the DIO circuitry of the E Series device.

Data Out

Protection

Output Enable

Data In

Protection

Output Enable

Data In

Figure 4-1. DIO Circuitry Block Diagram

E Series devices contain eight lines of DIO (P0.<0..7>) for general-purpose use. You can individually configure each line with software for either input

Chapter 4 Digital I/O

or output. At system startup and reset, the DIO ports are all high-impedance.

The hardware up/down control for general-purpose Counters 0 and 1 are connected onboard to P0.6 and P0.7, respectively. Thus, you can use P0.6 and P0.7 to control the general-purpose counters. The up/down control signals, Counter 0 Up/Down and Counter 1 Up/Down, are input-only and do not affect the operation of the DIO lines. Refer to Chapter 5, Counters, for more information on counters.

(NI 6016 and NI 6025E Devices Only) The NI 6016 and NI 6025E use an

82C55A programmable peripheral interface to provide additional lines of digital I/O that represent three 8-bit ports. Refer to the Extended Digital I/O section for more information.

Extended Digital I/O

(NI 6016 and NI 6025E Devices Only) The NI 6016 and NI 6025E use an

82C55A programmable peripheral interface (PPI) to provide an additional 24 lines of DIO that represent three 8-bit ports: P1, P2, and P3. The 82C55A has three modes of operation: simple I/O (mode 0), strobed I/O (mode 1), and bidirectional I/O (mode 2). In modes 1 and 2, the three ports are divided into two groups: group A and group B. Each group has eight data bits, plus control and status bits from Port 3 (P3). Modes 1 and 2 use handshaking signals from the computer to synchronize data transfers. NI-DAQmx does not currently support mode 2.

The Example Finder contains examples for programming the 82C55A in both Traditional NI-DAQ (Legacy) and NI-DAQmx. To locate the examples, use the keywords

8255 or handshaking.

Port 3 Signal Assignments

(NI 6016 and NI 6025E Devices Only) The signals assigned to port 3 depend on

how the 82C55A is configured. In mode 0, or no handshaking configuration, port 3 is configured as two 4-bit I/O ports. In modes 1 and 2, or handshaking configuration, port 3 is used for status and handshaking signals with any leftover lines available for general-purpose I/O. Table 4-1 summarizes the port 3 signal assignments for each configuration. You can also use ports 1 and 2 in different modes; Table 4-1 does not show every possible combination.

Note Table 4-1 shows both the port 3 signal assignments and the terminology correlation

between different documentation sources. The 82C55A terminology refers to the different

E Series User Manual 4-2 ni.com

82C55A configurations as modes, whereas NI-DAQ, LabWindows/CVI, and LabVIEW documentation refers to them as handshaking and no handshaking.

Table 4-1. Configuration Terminology and Signal Assignments

Configuration Terminology Signal Assignments

National

NI 6016 or

NI 6025E

Mode 0 (Basic I/O)

Mode 1 (Strobed Input)

Mode 1 (Strobed Output)

Mode 2 (Bidirectional Bus)

Indicates that the signal is active low.

Denotes port 1 handshaking signals.

Denotes port 2 handshaking signals.

Instruments

Software

No Handshaking

Handshaking I/O I/O IBF1STB*1INTR1STB*2IBFB2INTR

Handshaking OBF*1ACK*1I/O I/O INTR1ACK*2OBF

Handshaking OBF*1ACK*1IBF1STB*1INTR1I/O I/O I/O

P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0

I/O I/O I/O I/O I/O I/O I/O I/O

Chapter 4 Digital I/O

INTR

Power-On State

(NI 6016 and NI 6025E Devices Only) The NI 6016 and NI 6025E contain bias

resistors that control the state of the DIO lines, P1.<0..7>, P2.<0..7>, P3.<0..7>. At power-on, each DIO line is configured as an input and pulled high.

You can change the power-on state of individual lines from pulled high to pulled low by adding your own external resistors.

Changing DIO Power-On State to Pulled Low

Each DIO line is pulled to Vcc (approximately +5 VDC) with a 100 kΩ resistor. To pull a specific line low, add a pull-down resistor (R the line and ground so the maximum value on the line is 0.4 VDC. The DIO lines provide a maximum of 2.5 mA at 3.7 V in the high state. Using the largest possible resistor ensures that you do not use more current than necessary to perform the pull-down task.

Ensure the value of the resistor is not so large that leakage current from the DIO line, along with the current from the 100 kΩ pull-up resistor, drives the

) between

Chapter 4 Digital I/O

voltage across the pull-down resistor above a TTL-low level of 0.4 VDC. Figure 4-2 shows the DIO configuration for high DIO power-on state.

100 k

+5 V

GND

Digital I/O Line

Device

82C55

Figure 4-2. DIO Configuration for High DIO Power-On State

The following steps show how to calculate the value of RL needed to achieve a TTL-low power-on state for a single DIO line.

Using the following formula, calculate the largest possible load to maintain a logic low level of 0.4 V and supply the maximum driving current:

V = I × R

→ RL = V/I

where:

V = 0.4 V Voltage across R

I = 46 μA (4.6 V across the 100 kΩ pull-up resistor) + 10 μA (10 μA maximum leakage current)

Therefore:

= 7.1 kΩ (0.4 V/56 μA)

This resistor value, 7.1 kΩ, provides a maximum of 0.4 V on the DIO line at power-on. You can substitute smaller resistor values to lower the voltage or to provide a margin for V

variations and other factors.

Timing Specifications

(NI 6016 and NI 6025E Devices Only) This section lists the timing

specifications for handshaking with the P3.<0..7> lines. The handshaking lines STB* and IBF synchronize input transfers. The handshaking lines OBF* and ACK* synchronize output transfers. Table 4-2 describes signals appearing in the handshaking diagrams.

E Series User Manual 4-4 ni.com

Chapter 4 Digital I/O

Table 4-2. Signal Descriptions

Name Type Description

STB* Input Strobe input—A low signal on this handshaking line

loads data into the input latch.

IBF Output Input buffer full—A high signal on this handshaking

line indicates that data has been loaded into the input latch. A low signal indicates the device is ready for more data. This is an input acknowledge signal.

ACK* Input Acknowledge input—A low signal on this

handshaking line indicates that the data written to the port has been accepted. This signal is a response from the external device indicating that it has received the data from your DIO device.

OBF* Output Output buffer full—A low signal on this handshaking

line indicates that data has been written to the port.

INTR Output Interrupt request—This signal becomes high when

the 82C55A requests service during a data transfer. You must set the appropriate interrupt enable bits to generate this signal.

RD* Internal Read—This signal is the read signal generated from

the control lines of the computer I/O expansion bus.

WR* Internal Write—This signal is the write signal generated from

the control lines of the computer I/O expansion bus.

DATA Bidirectional Data lines at the specified port—For output mode,

this signal indicates the availability of data on the data line. For input mode, this signal indicates when the data on the data lines should be valid.

National Instruments E Series User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

E Series User Manual

Support

Worldwide Technical Support and Product Information

National Instruments Corporate Headquarters

Worldwide Offices

Important Information

Warranty

Copyright

Trademarks

Patents

WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS

Contents

About This Manual

Figure 1-1. DAQ System Overview

DAQ Hardware

DAQ-STC

Calibration Circuitry

Internal or Self-Calibration

External Calibration

Signal Conditioning

Sensors and Transducers

Signal Conditioning Options

SCXI

5B Series

Cables and Accessories

Using Accessories with Devices

Table 1-1. 68-Pin and DAQCard E Series Accessories and Recommended Cables

Table 1-2. 100-Pin E Series Accessories and Recommended Cables

Table 1-3. E Series DAQ Accessories Overview

Custom Cabling

Programming Devices in Software

I/O Connector Signal Descriptions

Table 1-4. I/O Connector Signal Descriptions

Terminal Name Equivalents

Table 1-5. Terminal Name Equivalents

+5 V Power Source

Figure 2-1. Analog Input Circuitry Block Diagram

Analog Input Circuitry

Instrumentation Amplifier (NI-PGIA)

A/D Converter

AI FIFO

Analog Trigger

AI Timing Signals

Input Polarity and Range

Table 2-1. Input Ranges for NI 6020E, NI 6040E, NI 6052E, NI 6062E, and NI 6070E/6071E

Table 2-2. Input Ranges for NI 6011E and NI 6030E/6031E/6032E/6033E

Table 2-3. Input Ranges for NI 6023E/6024E/6025E and NI 6034E/6035E/6036E

Analog Input Terminal Configuration

Table 2-4. Analog Input Terminal Configuration

Figure 2-2. E Series PGIA

Table 2-5. NI-PGIA Signal

Dither

Figure 2-3. Dither

Multichannel Scanning Considerations

Use Low Impedance Sources

Use Short High-Quality Cabling

Carefully Choose the Channel Scanning Order

Avoid Switching from a Large to a Small Input Range

Insert Grounded Channel between Signal Channels

Minimize Voltage Step between Adjacent Channels

Avoid Scanning Faster than Necessary

Example 1

Example 2

AI Data Acquisition Methods

Software-Timed Acquisitions

Hardware-Timed Acquisitions

Analog Input Triggering

AI Start Trigger Signal

Using a Digital Source

Figure 2-4. ai/StartTrigger Source Timing Requirements

Using an Analog Source

Outputting the AI Start Trigger Signal

Figure 2-5. PFI 0/AI START TRIG Timing Behavior

AI Reference Trigger Signal

Figure 2-6. Reference Trigger Final Buffer

Using a Digital Source