National Instruments DP8400 User Manual

The DP8400 Family of
Memory Interface Circuits

The DP8400 Family of Memory Interface Circuits AN-302

National Semiconductor
Application Note 302
Charles Carinalli
Mike Evans
February 1986

INTRODUCTION

The rapid development in dynamic random access memory
(DRAM) chip storage capability, coupled with significant
component cost reductions, has allowed designers to build
large memory arrays with high performance specifications.
However, the development of memory arrays continues to
have a common set of problems generated by the complex
timing and refresh requirements of DRAMs. These include:
how to quickly drive the memories to take advantage of their
speed, minimization of board space required by the support
circuitry and the need for error detection and correction.
Unfortunately, these problems must be addressed with each
new system design. Full system solutions will vary greatly,
depending on the DRAM array size, memory speed, and the
processor.

This application note introduces a complete family of DRAM
support circuits that provides a straightforward solution to
the above problems while allowing a high degree of flexibili­ty in application with little or no performance penalty. The
DP8400 family (Table I) includes DRAM controllers, error
detection/correction circuits, octal address buffers and sys­tem control circuits. The LSI blocks are designed with flex­ible interfaces, making application possible with all existing
DRAMs including the recently announced 1 Mbit devices.
Additionally, interface is easy to all popular microprocessors
with memory word widths possible from 8 to 80 bits.

TABLE I. DP8400 Family Members

DP8400-2, 16 and 32 Bit Error
DP8402A Checker/Correctors

DP8408A, DP8409A, DRAM Controller/Drivers
DP8417, DP8418,
DP8419, DP8428, DP8429

DP8420, DP84244 DRAM Buffer Drivers

DP84XX2 Microprocessor

Interface Circuits

FULL FUNCTION DRAM CONTROLLER

The heart of any DRAM array design is the controller func­tion. Previous LSI controllers supplied a minimum function
of address multiplexing with an on-board refresh counter.
This required external delay line timing and logic to control
memory access, additional logic to perform memory refresh,
and external drivers to drive the capacitive memory array.
The complete solution results in significant access delay in
relation to DRAM speeds and skews in output sequencing,
as well as a large component count.

A previous LSI solution brought much of this logic on-chip.
However, it is limited in application to certain microproces­sors and has the disadvantage of all access timing originat­ing from an external clock, whose phase uncertainty gener­ates a delay in actually knowing when an access has start­ed.

The DP8409A multi-mode dynamic RAM controller/driver
was the first controller to resolve all of these problems. This
Schottky bipolar device provides the flexibility of external
access control, along with automatic access timing genera­tion, without the need for an external timing generator clock.
In addition, on-board capacitive drivers allow direct drive for
over 88 DRAMs. With the simple addition of refresh clocks,
the circuit can perform hidden refresh automatically. It is the
DP8409A design that has been used as the spring board for
a whole family of controllers with faster speed performance
while maintaining maximum pin upgrade compatibility.

All Control On-Chip

Figure 1

is a block diagram of the DP8409A. the ADS input
strobes the parallel memory address into the row latches
R0–8, the column latches C0– 8, and bank select B0 and
B1. The nine output drivers may be multiplexed between the
row or column input latches, or the 9-bit on-chip refresh
counter. One of four RAS
cess cycle by setting the bank select inputs B0 or B1. All
four RAS
or automatic control is available on-chip for the CAS
while an on-chip buffer is provided to minimize skew associ­ated with WE

All DRAM address and control outputs on the DP8409A can
directly drive in excess of 500 pF, or the equivalent of 88
DRAMs (4 banks of 22 DRAMs). All output drivers are
closely matched, significantly reducing output skew. Each
output stage has symmetrical high and low logic level drive
capability, insuring matched rise and fall time characteris­tics.

Flexibility and Upgradability to 256k or 1 Mbit DRAMs

The 9 multiplexed address outputs and 9-bit internal refresh
counter of the DP8409A direct addressing capability for
256k DRAMs. Careful design of memory boards, using 64k
DRAMs with the DP8409A, insures direct upgradability to
256k DRAMs. This can be done by simply allowing for board
address extension by two bits and designing the ninth ad­dress trace (Q8) of the DP8409A to connect to pin 1 of the
DRAMs (A8). This is, in general, a non-connected pin in
64ks and the ninth address in 256ks. All that need be done
is to remove the 64ks and replace them with 256ks, thereby
increasing the memory on the same board bya4to1ratio.
The resulting development cost saving can be significant.

Although the new 1 Mbit DRAMs require the larger 18 pin
package, which will require a memory board redesign, up­grading the controller portion of the board may need no
redesign when converting from the DP8409A or DP8419 to
the new DP8429 1 Mbit DRAM controller driver.

Three mode pins (M0, M1 and M2) offer externally select­able modes of operation, a key reason for the DP8409A’s
application flexibility (Table II). The operational modes are
divided between external and automatic memory control.

outputs are active during refresh. Either external

output generation.

outputs is selected during an ac-

output,

C

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S.A.

TL/F/5012

Indicates that there is a 3
kX pull-up resistor on
these outputs when they
are disabled.

FIGURE 1. DP8409A Block Diagram

TL/F/5012– 1

TABLE II. DP8409A Mode Select Options

Mode

(RFSH

M2

M1 M0 Mode of Operation Conditions

)

0 0 0 0 Externally Controlled Refresh RF I/OeEOC

1 0 0 1 Auto RefreshÐForced RF I/OeRefresh Request (RFRQ)

2 0 1 0 Internal Auto Burst Refresh RF I/OeEOC

3a 0 1 1 All RAS Auto Write RF I/OeEOC

3b 0 1 1 Externally Controlled All RAS Access All RAS Active

4 1 0 0 Externally Controlled Access

5 1 0 1 Auto Access, Slow t

6 1 1 0 Auto Access, Fast t

, Hidden Refresh

RAH

RAH

7 1 1 1 Set End of Count

Modes 0, 3b, and 4 provide full control of access and re­fresh for systems with external memory controllers or for
special purpose applications. Here all timing can be directly
controlled by the external system as shown in

Figure 2

.

Modes 1, 5 and 6 provide on-chip automatic access se­quencing with hidden refresh capability. A graphic example
of the automatic access modes of the DP8409A is shown in

Figure 3

. All DRAM access timing and control is generated

from one input strobe, RASIN

; no external clock is required.
On-chip delays insure proper address and control sequenc­ing once the valid parallel address is presented to the fall­through input latches of the DP8409A. When the RASIN
transitions high-to-low, the decoded RAS output transitions
low, strobing the row address into the DRAM array. An on­chip delay automatically generates a guaranteed selectable
(mode 5 or 6) row address hold time. At this point, the

DP8409A switches the address outputs from the row latch
to the column latch. Then another on-chip delay generates
a guaranteed column address set-up time before CAS
that the CAS

output automatically strobes the column ad­dress into the DRAM array. Read or write cycles are con­trolled by the system through independent control of the WE
buffer that is provided on-chip to minimize delay skewing.
The automatic access mode makes the dynamic RAM ap­pear static with respect to access timing. In this mode, only
one signal, RASIN

, is needed after valid parallel addresses
are presented to the DP8409A to initiate proper access se­quencing. Access timing (RASIN

to CAS), with full output
loading of 88 DRAMs in the auto access mode, is deter­mined by the dash number given on the DP8409A data
sheet. All performance characteristics are specified over the
full operating temperature and supply ranges.

2

,so

Drams may be 16k, 64k or 256k

For 4 banks, can drive 16 data

a

bits

6 check bits for ECC.

For 2 banks, can drive 32 data

a

bits

7 check bits for ECC.

For 1 bank, can drive 64 data

a

bits

8 check bits for ECC.

*These outputs may need damping

resistors to prevent overshoot,
undershoot at memories.

FIGURE 2. Typical Application of DP8409A Using External Control and Refresh in Modes 0 and 4

TL/F/5012– 2

FIGURE 3. This figure demonstrates the automatic accessing capability of the DP8409A. Only one strobing edge,

TL/F/5012– 3

RASIN

, is required for generation of all DRAM access timing signals. This is accomplished with on-chip

delay generators, eliminating the need for external delay lines. No access timing clock is necessary.

3

Refreshing

The DP8409A also provdes hidden refresh capability while
in one of the automatic access modes (

Figure 4

). In this
mode, it will automatically perform a refresh without the sys­tem being interrupted. To do this, the DP8409A requires two
clock signals, refresh clock (RFCK) which defines the re­fresh period (usually 16 ms), and RAS

generator clock

(RGCK), which is typically the microprocessor clock.

Highest priority is given to hidden refreshing through use of
level sensing of RFCK. A refresh cycle begins when RFCK
transitions to a high level. If during the time RFCK is high the
DP8409A is deselected (CS

in the high state) and the proc­essor is accessing another portion of the system such as
another memory segment, or ROM, or a peripheral, then a
hidden refresh is performed. When a read or write cycle is
initiated by the processor, the RASIN
transitions low. With CS

high, this causes the present state

input on the DP8409A

of the internal refresh counter to be placed on the address
outputs, followed by the four RAS

outputs transitioning low,
strobing the refresh address into the DRAM array. When the
cycle ends, RASIN

will terminate, thus forcing the RAS out­puts back to their inactive state and ending the hidden re­fresh. The refresh counter is then incremented and another
microprocssor cycle can begin immediately. However, to
save power, the DP8409A will allow only one hidden refresh
to occur during a given RFCK cycle.

In the event that a hidden refresh does not occur, the
DP8409A must force a refresh before the RFCK’s next
positive-going transition.Thesystem is notified afterthenega­tive-going RFCK transition that a hidden refresh has not oc-

curred, via the refresh request output (RF I/O pin). The sys­tem acknowledges the request for a forced refresh by set­ting M2 (refresh) low on the DP8409A and preventing fur­ther access to the DP8409A. The DP8409A then uses
RGCK to generate an automatic forced refresh. The refresh
request pin then returns to the inactive state, and the
DP8409A allows the processor to take full system control
after the forced refresh has been completed.

OCTAL MEMORY DRIVERS

For those applications where the memory array is extremely
large or the controller design is unique to a particular appli­cation requirement, specialized high capacitive load ad­dress and control buffers are required. However, like any
other element in a DRAM system, selection of the improper
driver can have significant impact on system performance.

In the past, this function has been performed using Schottky
logic family circuits such as the DM74S240 octal inverter or
the DM74S244 octal buffer. The output stages of these de­vices have good drive capability, but their performance with
heavy capacitive loads is not ideal for DRAM arrays. The
key disadvantage of these devices is their non-symmetrical
rise and fall time characteristics and their long propagation
delays with heavy load capacitance. The former is a result
of impedance mismatch in the upper and lower output
stages. The latter stems from process capability and circuit
design techniques not tailored to the DRAM application.
The combined result of all these factors is increased output
skew in address and control lines when these devices are
used as buffers.

FIGURE 4. Hidden and Forced Refresh Timing of the DP8409A

4

TL/F/5012– 4

Two new devices are now available for this application. The
DP84240 is pin and function compatible with the
DM74S240. The DP84244 is likewise compatible with the
DM74S244. However, this is where the similarity between
the devices ends. Both the DP84240 and the DP84244
have been designed specifically to drive DRAM arrays.

ure 5

shows a typical application of the DP84244, used in

Fig-

conjunction with the DP8409A, to drive a very large memory
array.

Figures 6a, 6b

show some typical performance curves for
these circuits. Note that, at over 500 pF, the propagation
delay through these drivers is on the order of 15 ns. This
delay includes propagation delay and rise or fall time. Even

*Resistor required depends on DRAM load. See AN-305

‘‘Precautions to Take When Driving Memories.’’

with this high speed, chip power dissipation is still main­tained at a reasonable level as demonstrated by the graphs
shown in

Figures 7a, 7b

of power versus frequency.

The DP84240 and the DP84244 are fabricated on a high
performance oxide-isolated Schottky bipolar process. Spe­cial circuit techiques have been used to minimize internal
delays and skews. Additionally, both rise and fall time char­acteristics track closely as a function of load capacitance.
This has been accomplished through impedance matching
of the upper and lower output stages. The result of these
characteristics is a substantial reduction of skew in both the
address and control lines to the DRAM array.

FIGURE 5. The DP84244 Used as a Buffer in a Large Memory Array (greater than 88 DRAMs) Controlled by the DP8409A

TL/F/5012– 5

FIGURE 6a. t

Measured to 2.7V on Output vs. C

PLH

TL/F/5012– 6

L

FIGURE 6b. t

Measured to 0.8V on Output vs. C

PHL

TL/F/5012– 7

L

5