National Instruments 6612 User Manual
NI 6612
User Manual
NI 6612 User Manual
November 2013
374008B-01
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Contents
About This Manual
Related Documentation .................................................................................................... xiii
Chapter 1
Introduction
Installation ........................................................................................................................ 1-1
Accessories and Cables .................................................................................................... 1-1
Chapter 2
Digital I/O
Digital Input Data Acquisition Methods .......................................................................... 2-3
Software-Timed Acquisitions ................................................................................... 2-3
Hardware-Timed Acquisitions ................................................................................. 2-3
Digital Input Triggering.................................................................................................... 2-4
Digital Waveform Acquisition ......................................................................................... 2-5
DI Sample Clock Signal ........................................................................................... 2-5
Routing DI Sample Clock to an Output Terminal ............................................ 2-6
Other Timing Requirements ............................................................................. 2-6
DI Sample Clock Timebase Signal........................................................................... 2-6
DI Start Trigger Signal ..................................................................................... 2-7
Retriggerable DI ............................................................................................... 2-7
Using a Digital Source...................................................................................... 2-8
Routing DI Start Trigger to an Output Terminal .............................................. 2-8
DI Reference Trigger Signal..................................................................................... 2-8
Using a Digital Source...................................................................................... 2-9
Routing DI Reference Trigger Signal to an Output Terminal .......................... 2-9
DI Pause Trigger Signal ........................................................................................... 2-9
Using a Digital Source...................................................................................... 2-10
Routing DI Pause Trigger Signal to an Output Terminal ................................. 2-10
Digital Output Data Generation Methods ......................................................................... 2-10
Software-Timed Generations.................................................................................... 2-10
Hardware-Timed Generations .................................................................................. 2-11
Digital Output Triggering ................................................................................................. 2-12
Digital Waveform Generation .......................................................................................... 2-12
DO Sample Clock Signal.......................................................................................... 2-13
Routing DO Sample Clock to an Output Terminal .......................................... 2-13
Other Timing Requirements ............................................................................. 2-13
DO Sample Clock Timebase Signal ......................................................................... 2-13
DO Start Trigger Signal............................................................................................ 2-14
Retriggerable DO.............................................................................................. 2-14
Using a Digital Start Trigger ............................................................................ 2-14
Routing DO Start Trigger Signal to an Output Terminal ................................. 2-14
© National Instruments | vii
Contents
DO Pause Trigger Signal .......................................................................................... 2-15
Using a Digital Pause Trigger...........................................................................2-15
Routing DO Pause Trigger Signal to an Output Terminal................................ 2-15
I/O Protection....................................................................................................................2-16
DI Change Detection ........................................................................................................2-16
DI Change Detection Applications ........................................................................... 2-17
Digital Filtering.................................................................................................................2-17
Connecting Digital I/O Signals ......................................................................................... 2-20
Getting Started with DIO Applications in Software ......................................................... 2-21
Signal Integrity Considerations ........................................................................................ 2-22
Chapter 3
Counters
Counter Input Applications............................................................................................... 3-2
Edge Counting .......................................................................................................... 3-2
Channel Settings ............................................................................................... 3-2
Timing Settings................................................................................................. 3-3
Trigger Settings................................................................................................. 3-4
Other Settings ................................................................................................... 3-6
Exporting a Terminal Count Signal ..................................................................3-6
Cascading Counters ..........................................................................................3-6
Pulse Measurement ................................................................................................... 3-6
Create Channel.................................................................................................. 3-7
Channel Settings ............................................................................................... 3-7
Timing Settings................................................................................................. 3-8
Trigger Settings................................................................................................. 3-9
Other Settings ................................................................................................... 3-10
Semi-Period Measurement........................................................................................ 3-10
Settings.............................................................................................................. 3-10
Frequency Measurement........................................................................................... 3-11
Frequency Measurement Considerations.......................................................... 3-11
Frequency Measurement Methods.................................................................... 3-12
Period Measurement .................................................................................................3-19
Pulse-Width Measurement........................................................................................ 3-19
Channel Settings ............................................................................................... 3-20
Timing Settings................................................................................................. 3-20
Trigger Settings................................................................................................. 3-21
Other Settings ................................................................................................... 3-22
Two-Edge Separation ............................................................................................... 3-22
Channel Settings ............................................................................................... 3-23
Timing Settings................................................................................................. 3-23
Trigger Settings................................................................................................. 3-24
Other Settings ................................................................................................... 3-25
viii | ni.com
NI 6612 User Manual
Quadrature and Two-Pulse Encoder Overview ........................................................ 3-25
Quadrature Encoders ........................................................................................ 3-25
Two-Pulse Encoders ......................................................................................... 3-27
Angular Position Measurement ................................................................................ 3-27
Create Channel ................................................................................................. 3-27
Channel Settings ............................................................................................... 3-27
Timing Settings................................................................................................. 3-28
Trigger Settings ................................................................................................ 3-29
Other Settings ................................................................................................... 3-29
Linear Position Measurement ................................................................................... 3-29
Counter Output Applications ............................................................................................ 3-29
Generating a Series of One or More Pulses.............................................................. 3-30
Create Channel ................................................................................................. 3-30
Channel Settings ............................................................................................... 3-31
Timing Settings................................................................................................. 3-31
Triggering Setting............................................................................................. 3-31
Generating a Waveform with Constant Frequency and Duty Cycle ........................ 3-32
Create Channel ................................................................................................. 3-32
Channel Settings ............................................................................................... 3-33
Timing Settings................................................................................................. 3-33
Triggering Setting............................................................................................. 3-33
Generating a Waveform with Variable Frequency and Duty Cycle......................... 3-34
Create Channel ................................................................................................. 3-34
Channel Settings ............................................................................................... 3-35
Timing Settings................................................................................................. 3-35
Triggering Settings ........................................................................................... 3-35
Buffer Considerations....................................................................................... 3-35
Generating Complex Digital Waveform or Timing Pattern ..................................... 3-36
Create Channel ................................................................................................. 3-36
Channel Settings ............................................................................................... 3-36
Timing Settings................................................................................................. 3-37
Triggering Setting............................................................................................. 3-37
Buffer Considerations....................................................................................... 3-37
Other Features........................................................................................................... 3-37
Frequency Division........................................................................................... 3-37
Frequency Generator ................................................................................................ 3-38
Chapter 4
PFI
Using PFI Terminals as Timing Input Signals ................................................................. 4-2
Exporting Timing Output Signals Using PFI Terminals.................................................. 4-2
Using PFI Terminals as Static Digital I/Os ...................................................................... 4-3
Using PFI Terminals to Digital Detection Events ............................................................ 4-3
Connecting PFI Input Signals........................................................................................... 4-3
PFI Filters ......................................................................................................................... 4-3
© National Instruments | ix
Contents
I/O Protection....................................................................................................................4-5
Signal Integrity Considerations ........................................................................................ 4-5
Chapter 5
Counter Signal Routing and Clock Generation
Clock Routing ...................................................................................................................5-1
100 MHz Timebase................................................................................................... 5-2
20 MHz Timebase..................................................................................................... 5-2
100 kHz Timebase .................................................................................................... 5-2
External Reference Clock ......................................................................................... 5-2
10 MHz Reference Clock ......................................................................................... 5-3
PXIe_CLK100 (NI PXIe-6612 Only)....................................................................... 5-3
PXIe_SYNC100 (NI PXIe-6612 Only) .................................................................... 5-3
PXI_CLK10 (NI PXIe-6612 Only)........................................................................... 5-3
Default Routing.................................................................................................................5-3
Routing Options ................................................................................................................ 5-5
Matching Routing Terminology .......................................................................................5-5
Synchronizing Multiple Devices ...................................................................................... 5-6
PXI Express Devices ................................................................................................ 5-6
PCI Express Devices................................................................................................. 5-7
Real-Time System Integration (RTSI).............................................................................. 5-7
Using RTSI as Outputs ............................................................................................. 5-8
Using RTSI Terminals as Timing Input Signals....................................................... 5-8
RTSI Filters............................................................................................................... 5-9
PXI Trigger Signals (NI PXIe-6612 Only)....................................................................... 5-9
PXI_Trigger<0..7>.................................................................................................... 5-9
PXI_STAR................................................................................................................ 5-9
PXIe-DSTAR<A..C>................................................................................................ 5-10
Chapter 6
Bus Interface
Data Transfer Methods ..................................................................................................... 6-1
PCI Express/PXI Express Device Data Transfer Methods....................................... 6-1
PXI Express Considerations .............................................................................................6-2
PXI Express Clock and Trigger Signals ................................................................... 6-2
PXI Express .............................................................................................................. 6-2
Chapter 7
Calibration
Appendix A
Pinout and Signal Descriptions
x | ni.com
Appendix B
Technical Support and Professional Services
NI 6612 User Manual
© National Instruments | xi
About This Manual
This manual describes the electrical and mechanical aspects of the NI 6612 devices, and contains
information about device operation and programming.
Related Documentation
The following documents contain information that you may find helpful as you read this manual:
• Read Me First: Safety and Electromagnetic Compatibility—Lists precautions to take to
avoid possible injury, data loss, or a system crash.
• DAQ Getting Started guides—Explain installation of the NI-DAQ driver software and the
DAQ device, and how to confirm that the device is operating properly.
• NI 6612 Specifications—Contains specifications specific to the NI 6612.
• NI-DAQmx Help—Contains API overviews, general information about measurement
concepts, key NI-DAQmx concepts, and common applications that are applicable to all
programming environments.
NI-DAQmx is the software you use to communicate with and control your DAQ device.
Select Start»All Programs»National Instruments»NI-DAQ»NI-DAQmx Help.
• Measurement & Automation Explorer Help—Contains information about configuring and
testing supported NI devices using Measurement & Automation Explorer (MAX) for
NI-DAQmx. For more information, select Help»Help Topics»NI-DAQmx»MAX Help
for NI-DAQmx.
Note You can download these documents at ni.com/manuals, unless stated
otherwise.
© National Instruments | xiii
1
Introduction
This chapter describes the NI PCIe/PXIe-6612, lists what you need to get started, and describes
optional equipment. If you have not already installed the device, refer to the DAQ Getting
Started documents.
The NI 6612 is a timing and digital I/O device that offers eight 32-bit counter channels and up
to 32 lines of individually configurable, TTL/CMOS-compatible digital I/O.
The counter/timer channels have many measurement and generation modes, such as event
counting, time measurement, frequency measurement, encoder position measurement, pulse
generation, and square-wave generation.
Installation
Before installing your DAQ device, you must install the software you plan to use with the device.
1. Installing application software—Refer to the installation instructions that accompany
your software.
2. Installing NI-DAQmx—The DAQ Getting Started documents contain step-by-step
instructions for installing software and hardware, configuring channels and tasks, and
getting started developing an application.
3. Installing the hardware—The DAQ Getting Started documents describe how to install
PCI Express and PXI Express devices, as well as accessories and cables.
Accessories and Cables
Caution This NI product must be operated with shielded cables and accessories to
ensure compliance with the Electromagnetic Compatibility (EMC) requirements
defined in the Specifications section of this document. Do not use unshielded cables
or accessories unless they are installed in a shielded enclosure with properly designed
and shielded input/output ports and connected to the NI product using a shielded
cable. If unshielded cables or accessories are not properly installed and shielded, the
EMC specifications for the product are no longer guaranteed.
© National Instruments | 1-1
Chapter 1 Introduction
Table 1-1 provides a list of accessories and cables available for use with the NI 6612.
Table 1-1. Accessories and Cables
Accessory Description
SH68-68-D1 Shielded 68-conductor cable
R6868 Unshielded 68-conductor flat ribbon cable
BNC-2121 BNC connector block with built-in test features
CA-1000 Configurable connector accessory
SCB-68A Shielded screw connector block
TBX-68 Unshielded DIN-rail connector block
CB-68LP Unshielded low-cost screw connector block
CB-68LPR Unshielded low-cost screw connector block
(NI PXIe-6612 only) TB-2715 Front-mount terminal block
1-2 | ni.com
2
Digital I/O
The NI 6612 contains 40 Programmable Function Interface (PFI) signals. These PFI signals can
function as either timing input, timing output, or DIO signals. This chapter describes the DIO
functionality. Refer to Chapter 4, PFI, for information on using the PFI lines as timing input or
output signals.
The 40 PFI signals are grouped into a 32-bit Port 0 and an 8-bit Port 1. When a terminal is used
for digital I/O, it is called Px.y, where x is the port number and y is the line number. For example,
P1.3 refers to Port 1, Line 3. When a terminal is used for timing input or output, it is called PFI x,
where x is a number between 0 and 39 representing the PFI line number. The same physical pin
has two different names depending on whether it is used for digital I/O (Px.y) or timing I/O
(PFI x). For example, the digital I/O line P1.3 is the same physical pin as the timing I/O signal
PFI 35. Refer to Appendix A, Pinout and Signal Descriptions, for a complete pinout.
The DIO features supported on Port 0 and Port 1 are listed in Table 2-1.
Table 2-1. DIO Features on Ports 0 and 1
Port 0 Port 1
32 lines of DIO 8 lines of DIO
Direction and function of each terminal individually controllable
Static digital input and output
DI change detection trigger/interrupt
High-speed digital waveform acquisition —
High-speed digital waveform generation —
© National Instruments | 2-1
Chapter 2 Digital I/O
x
DO.x Direction Control
Static DI
DI Change
Detection
I/O Protection
Weak Pull-Down
P1.x
Static DO
Buffer
Filter
CI
Figures 2-1 and 2-2 show the circuitry of a DIO line on Port 0 and Port 1 respectively. Each DIO
line is similar.
Figure 2-1. Digital I/O Circuitry on Port 0
DO Waveform
Generation FIFO
DO Sample Clock
Static DO
Buffer
DO.x Direction Control
CI
I/O Protection
P0.
DI Sample Clock
In both Figures 2-1 and 2-2, CI represents additional input capacitance. This capacitance
provides some filtering and slew-rate control benefits. However, the capacitance also limits the
maximum input frequency.
CI is populated on all the lines except for the default counter source input pins. CI is not
populated on the default source input pins in order to allow the measurement of higher speed
input signals. Table 2-2 lists the lines that do not populate CI. You must use the lines in Table 2-2
when measuring inputs frequencies above 25 MHz. For more information, refer to the NI 6612
Specifications.
Static DI
DI Waveform
Measurement
FIFO
DI Change
Detection
Filter
Figure 2-2. Digital I/O Circuitry on Port 1
Weak Pull-Down
2-2 | ni.com
NI 6612 User Manual
Table 2-2. Lines Without a Populated CI
Port 0 Port 1
PFI 11 / P0.11 PFI 35 / P1.3
PFI 15 / P0.15 PFI 39 / P1.7
PFI 19 / P0.19 —
PFI 23 / P0.23 —
PFI 27 / P0.27 —
PFI 31 / P0.31 —
For voltage input and output levels and the current drive levels of the DIO lines, refer to the
NI 6612 Specifications.
Digital Input Data Acquisition Methods
When performing digital input measurements, you either can perform software-timed or
hardware-timed acquisitions.
Software-Timed Acquisitions
With a software-timed acquisition, software controls the rate of the acquisition. Software sends
a separate command to the hardware to initiate each acquisition. In NI-DAQmx, software-timed
acquisitions are referred to as having on-demand timing. Software-timed acquisitions are also
referred to as immediate or static acquisitions and are typically used for reading a single sample
of data.
Each of the DIO lines can be used as a static DI or DO line. You can use static DIO lines to
monitor or control digital signals. Each DIO can be individually configured as a digital input
(DI) or digital output (DO).
All samples of static DI lines and updates of static DO lines are software-timed.
Hardware-Timed Acquisitions
With hardware-timed acquisitions, a digital hardware signal (di/SampleClock) controls the rate
of the acquisition. This signal can be generated internally on your device or provided externally.
Hardware-timed acquisitions have several advantages over software-timed acquisitions.
• The time between samples can be much shorter.
• The timing between samples is deterministic.
• Hardware-timed acquisitions can use hardware triggering.
© National Instruments | 2-3
Chapter 2 Digital I/O
Hardware-timed operations can be buffered or hardware-timed single point. A buffer is a
temporary storage in computer memory for to-be-transferred samples.
• Buffered—Data is moved from the DAQ device’s onboard FIFO memory to a PC buffer
using DMA before it is transferred to application memory. Buffered acquisitions typically
allow for much faster transfer rates than non-buffered acquisitions because data is moved
in large blocks, rather than one point at a time.
One property of buffered I/O operations is the sample mode. The sample mode can be either
finite or continuous:
– Finite sample mode acquisition refers to the acquisition of a specific, predetermined
number of data samples. After the specified number of samples has been read in, the
acquisition stops. If you use a reference trigger, you must use finite sample mode.
– Continuous acquisition refers to the acquisition of an unspecified number of samples.
Instead of acquiring a set number of data samples and stopping, a continuous
acquisition continues until you stop the operation. Continuous acquisition is also
referred to as double-buffered or circular-buffered acquisition.
If data cannot be transferred across the bus fast enough, the FIFO becomes full. New
acquisitions will overwrite data in the FIFO before it can be transferred to host
memory. The device generates an error in this case. With continuous operations, if the
user program does not read data out of the PC buffer fast enough to keep up with the
data transfer, the buffer could reach an overflow condition, causing an error to be
generated.
• Hardware-timed single point (HWTSP)—Typically, HWTSP operations are used to read
single samples at known time intervals. While buffered operations are optimized for high
throughput, HWTSP operations are optimized for low latency and low jitter. In addition,
HWTSP can notify software if it falls behind hardware. These features make HWTSP ideal
for real time control applications. HWTSP operations, in conjunction with the wait for next
sample clock function, provide tight synchronization between the software layer and the
hardware layer.
Refer to the document, NI-DAQmx Hardware-Timed Single Point Lateness Checking, for
more information. To access this document, go to
daqhwtsp.
ni.com/info and enter the Info Code
Digital Input Triggering
Digital input supports three different triggering actions:
• Start trigger
• Reference trigger
• Pause trigger
Refer to the DI Start Trigger Signal, DI Reference Trigger Signal, and DI Pause Trigger Signal
sections for information about these triggers.
2-4 | ni.com
NI 6612 User Manual
PFI, RTSI, PXI_Trigger
PXI_STA R
20 MHz Timebase
100 kHz Timebase
PXI_CLK10
Programmable
Clock
Divider
DI Sample Clock
Timebase
PFI, RTSI, PXI_Trigger
PXI_STA R
Ctr n Internal Output
DI Sample Clock
100 MHz Timebase
DSTAR <A..B>
DSTAR <A..B>
Digital Waveform Acquisition
Figure 2-3 summarizes all of the timing options provided by the digital input timing engine.
Figure 2-3. Digital Input Timing Options
You can acquire digital waveforms on the Port 0 DIO lines. The DI waveform acquisition FIFO
stores the digital samples. The NI 6612 has a DMA controller dedicated to moving data from the
DI waveform acquisition FIFO to system memory. The device samples the DIO lines on each
rising or falling edge of a clock signal, DI Sample Clock.
You can configure each DIO line to be an output, a static input, or a digital waveform acquisition
input.
The following digital input timing signals are featured:
• DI Sample Clock Signal*
• DI Sample Clock Timebase Signal
• DI Start Trigger Signal*
• DI Reference Trigger Signal*
• DI Pause Trigger Signal*
Signals with an * support digital filtering. Refer to the PFI Filters section of Chapter 4, PFI, for
more information.
DI Sample Clock Signal
The device uses the DI Sample Clock (di/SampleClock) signal to sample the Port 0 terminals
and store the result in the DI waveform acquisition FIFO.
By default, the programmable clock divider drives DI Sample Clock (see Figure 2-3). You can
route many signals to DI Sample Clock. To view the complete list of possible routes, see the
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Chapter 2 Digital I/O
DI Sample Clock Timebase
DI Start Trigger
DI Sample Clock
Delay
from
Start
Trigger
Device Routes tab in MAX. Refer to Device Routing in MAX in the NI-DAQmx Help or the
LabVIEW Help for more information.
If the NI 6612 receives a DI Sample Clock when the FIFO is full, it reports an overflow error to
the host software.
You can sample data on the rising or falling edge of DI Sample Clock.
Routing DI Sample Clock to an Output Terminal
You can route DI Sample Clock out to any PFI <0..39> terminal. The PFI circuitry inverts the
polarity of DI Sample Clock before driving the PFI terminal.
Other Timing Requirements
The NI 6612 only acquires data during an acquisition. The device ignores DI Sample Clock
when a measurement acquisition is not in progress. During a measurement acquisition, you can
cause the device to ignore DI Sample Clock using the DI Pause Trigger signal.
The DI timing engine on the device internally generates DI Sample Clock unless you select some
external source. DI Start Trigger starts this timing engine and either software or hardware can
stop it after a finite acquisition completes. When using the DI timing engine, you also can specify
a configurable delay from DI Start Trigger to the first DI Sample Clock pulse.
By default, this delay is set to two ticks of the DI Sample Clock Timebase signal.
Figure 2-4. DI Sample Clock and DI Start Trigger
DI Sample Clock Timebase Signal
By default, the NI 6612 routes the onboard 100 MHz timebase to DI Sample Clock Timebase.
You can route many signals to DI Sample Clock Timebase. To view the complete list of possible
routes, see the Device Routes tab in MAX. Refer to Device Routing in MAX in the NI-DAQmx
Help or the LabVIEW Help for more information.
DI Sample Clock Timebase is not available as an output on the I/O connector. DI Sample Clock
Timebase is divided down to provide one of the possible sources for DI Sample Clock. The
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DI Start Trigger
DI Sample Clock
polarity selection for DI Sample Clock Timebase can be configured as either rising—or
falling—edge except for the 100 MHz Timebase or 20 MHz Timebase.
The DI Sample Clock Timebase may be used if an external sample clock signal is required, but
the signal needs to be divided down. If an external sample clock signal is required, but there is
no need to divide the signal, then the DI Sample Clock should be used instead of the DI Sample
Clock Timebase.
DI Start Trigger Signal
Use the DI Start Trigger (di/StartTrigger) signal to begin a measurement acquisition. A
measurement acquisition consists of one or more samples. If triggers are not used, a
measurement acquisition can be initiated with a software command. After the acquisition begins,
configure the acquisition to stop:
• When a certain number of points are sampled (in finite mode)
• After a hardware reference trigger (in finite mode)
• With a software command (in continuous mode)
An acquisition that uses a start trigger (but not a reference trigger) is sometimes referred to as a
posttriggered acquisition.
Retriggerable DI
The DI Start Trigger can also be configured to be retriggerable. The timing engine generates
samples and converts clocks for the configured acquisition in response to each pulse on an
DI Start Trigger signal.
The timing engine ignores the DI Start Trigger signal while the clock generation is in progress.
After the clock generation is finished, the timing engine waits for another Start Trigger to begin
another clock generation. Figure 2-5 shows a retriggerable DI of four samples.
Reference triggers are not retriggerable.
Figure 2-5. Retriggerable DI
Note Waveform information from LabVIEW does not reflect the delay between
triggers. They are treated as a continuous acquisition with constant t0 and dt
information.
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Chapter 2 Digital I/O
Using a Digital Source
To use DI Start Trigger with a digital source, specify a source and an edge. You can route many
signals to DI Start Trigger. To view the complete list of possible routes, see the Device Routes
tab in MAX. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW Help for
more information.
You also can specify whether the measurement acquisition begins on the rising- or falling-edge
of DI Start Trigger.
Routing DI Start Trigger to an Output Terminal
You can route DI Start Trigger out to any PFI <0..39>, RTSI <0..7>, PXI_Trig <0..7>, or
PXIe-DSTARC terminal. The output is an active high pulse. All PFI terminals are configured as
inputs by default.
The device also uses DI Start Trigger to initiate pretriggered DAQ operations. In most
pretriggered applications, a software trigger generates DI Start Trigger. Refer to the
DI Reference Trigger Signal section for a complete description of the use of DI Start Trigger and
DI Reference Trigger in a pretriggered acquisition operation.
DI Reference Trigger Signal
Use the DI Reference Trigger (di/ReferenceTrigger) signal to stop a measurement acquisition.
To use a reference trigger, specify a buffer of finite size and a number of pretrigger samples
(samples that occur before the reference trigger). The number of posttrigger samples (samples
that occur after the reference trigger) desired is the buffer size minus the number of pretrigger
samples.
After the acquisition begins, the device writes samples to the buffer. After the device captures
the specified number of pretrigger samples, it begins to look for the reference trigger condition.
If the reference trigger condition occurs before the device captures the specified number of
pretrigger samples, it ignores the condition.
If the buffer becomes full, the device continuously discards the oldest samples in the buffer to
make space for the next sample. This data can be accessed (with some limitations) before the
device discards it. Refer to the KnowledgeBase document, Can a Pretriggered Acquisition be
Continuous?, for more information. To access this KnowledgeBase, go to
enter the Info Code
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ni.com/info and
NI 6612 User Manual
Reference Trigger
Pretrigger Samples
Complete Buffer
Posttrigger Samples
When the reference trigger occurs, the device continues to write samples to the buffer until the
buffer contains the number of posttrigger samples desired. Figure 2-6 shows the final buffer.
Figure 2-6. Reference Trigger Final Buffer
Using a Digital Source
To use DI Reference Trigger with a digital source, specify a source and an edge. You can route
many signals to DI Reference Trigger. To view the complete list of possible routes, see the
Device Routes tab in MAX. Refer to Device Routing in MAX in the NI-DAQmx Help or the
LabVIEW Help for more information.
You also can specify whether the measurement acquisition stops on the rising- or falling-edge of
DI Reference Trigger.
Routing DI Reference Trigger Signal to an Output Terminal
DI Reference Trigger can be routed out to any PFI <0..39>, RTSI <0..7>, PXI_Trig <0..7>, or
PXIe-DSTARC terminal. All PFI terminals are configured as inputs by default.
DI Pause Trigger Signal
The DI Pause Trigger (di/PauseTrigger) signal can be used to pause and resume a measurement
acquisition. The internal sample clock pauses while the external trigger signal is active and
resumes when the signal is inactive. The active level of the pause trigger can be programmed to
be high or low, as shown in Figure 2-7. In the figure, T represents the period, and A represents
the unknown time between the clock pulse and the posttrigger.
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Chapter 2 Digital I/O
Figure 2-7. Halt (Internal Clock) and Free Running (External Clock)
DI Sample Clock
DI Pause Trigger
DI External Sample Clock
DI Sample Clock
DI Pause Trigger
A
T
Halt. Used on Internal Clock
Free Running. Used on External Clock
T – A
Using a Digital Source
To use DI Pause Trigger, specify a source and a polarity. You can route many signals to DI Pause
Trigger. To view the complete list of possible routes, see the Device Routes tab in MAX. Refer
to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW Help for more information.
Routing DI Pause Trigger Signal to an Output Terminal
DI Pause Trigger can be routed out to any RTSI <0..7>, PXI_Trig <0..7>, PFI <0..39>,
PXI_STAR, or PXIe-DSTARC terminal.
Note Pause triggers are only sensitive to the level of the source, not the edge.
Digital Output Data Generation Methods
When performing a digital waveform operation, either software-timed or hardware-timed
generations can be performed.
Software-Timed Generations
With a software-timed generation, software controls the rate at which data is generated. Software
sends a separate command to the hardware to initiate each update. In NI-DAQmx,
software-timed generations are referred to as on-demand timing. Software-timed generations are
also referred to as immediate or static operations. They are typically used for writing a single
value out, such as a constant digital value.
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NI 6612 User Manual
Hardware-Timed Generations
With a hardware-timed generation, a digital hardware signal controls the rate of the generation.
This signal can be generated internally on your device or provided externally.
Hardware-timed generations have several advantages over software-timed generations:
• The time between samples can be much shorter.
• The timing between samples can be deterministic.
• Hardware-timed acquisitions can use hardware triggering.
Hardware-timed operations can be buffered or hardware-timed single point (HWTSP). A buffer
is a temporary storage in computer memory for to-be-transferred samples.
• Hardware-timed single point (HWTSP)—Typically, HWTSP operations are used to
write single samples at known time intervals. While buffered operations are optimized for
high throughput, HWTSP operations are optimized for low latency and low jitter. In
addition, HWTSP can notify software if it falls behind hardware. These features make
HWTSP ideal for real time control applications. HWTSP operations, in conjunction with
the wait for next sample clock function, provide tight synchronization between the software
layer and the hardware layer. Refer to the document, NI-DAQmx Hardware-Timed Single
Point Lateness Checking, for more information. To access this document, go to
and enter the Info Code daqhwtsp.
info
• Buffered—In a buffered generation, data is moved from a PC buffer to the device’s
onboard FIFO using DMA before it is written to the output lines one sample at a time.
Buffered generation typically allow for much faster transfer rates than non-buffered
acquisitions because data is moved in large blocks, rather than one point at a time.
One property of buffered I/O operations is the sample mode. The sample mode can be either
finite or continuous:
– Finite sample mode generation refers to the generation of a specific, predetermined
number of data samples. After the specified number of samples has been written out,
the generation stops.
– Continuous generation refers to the generation of an unspecified number of samples.
Instead of generating a set number of data samples and stopping, a continuous
generation continues until you stop the operation. There are several different methods
of continuous generation that control what data is written. These methods are
regeneration, FIFO regeneration, and non-regeneration modes:
• Regeneration is the repetition of the data that is already in the buffer. Standard
regeneration is when data from the PC buffer is continually downloaded to the
FIFO to be written out. New data can be written to the PC buffer at any time
without disrupting the output. Use the NI-DAQmx write property regenMode to
allow (or not allow) regeneration. The NI-DAQmx default is to allow
regeneration.
• With non-regeneration, old data is not repeated. New data must be continually written
to the buffer. If the program does not write new data to the buffer at a fast enough rate
to keep up with the generation, the buffer underflows and causes an error.
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© National Instruments | 2-11
Chapter 2 Digital I/O
• With FIFO regeneration, the entire buffer is downloaded to the FIFO and
regenerated from there. After the data is downloaded, new data cannot be written
to the FIFO. To use FIFO regeneration, the entire buffer must fit within the FIFO
size. The advantage of using FIFO regeneration is that it does not require
communication with the main host memory after the operation is started, thereby
preventing any problems that may occur due to excessive bus traffic. Use the
NI-DAQmx DO channel property, UseOnlyOnBoardMemory to enable or
disable FIFO regeneration.
Digital Output Triggering
Digital output supports two different triggering actions:
• Start trigger
• Pause trigger
A digital trigger can initiate these actions. Refer to the DO Start Trigger Signal and DO Pause
Trigger Signal sections for more information about these triggering actions.
Digital Waveform Generation
Digital waveforms can be generated on the Port 0 DIO lines. The DO waveform generation FIFO
stores the digital samples. NI 6612 has a DMA controller dedicated to moving data from the
system memory to the DO waveform generation FIFO. The device moves samples from the
FIFO to the DIO terminals on each rising—or falling—edge of a clock signal, DO Sample
Clock. Each DIO signal is configurable to be an input, a static output, or a digital waveform
generation output.
The FIFO supports a retransmit mode. In the retransmit mode, after all the samples in the FIFO
have been clocked out, the FIFO begins outputting all of the samples again in the same order.
For example, if the FIFO contains five samples, the pattern generated consists of sample #1, #2,
#3, #4, #5, #1, #2, #3, #4, #5, #1, and so on.
The following DO (waveform generation) timing signals are featured:
• DO Sample Clock Signal*
• DO Sample Clock Timebase Signal
• DO Start Trigger Signal*
• DO Pause Trigger Signal*
Signals with an * support digital filtering. Refer to the PFI Filters section of Chapter 4, PFI, for
more information.
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NI 6612 User Manual
DO Sample Clock Signal
The device uses the DO Sample Clock (do/SampleClock) signal to update the DO terminals with
the next sample from the DO waveform generation FIFO. If the device receives a DO Sample
Clock when the FIFO is empty, it reports an underflow error to the host software.
By default, the NI 6612 routes the divided down DO Sample Clock Timebase to DO Sample
Clock. You can route many other signals to DO Sample Clock. To view the complete list of
possible routes, see the Device Routes tab in MAX. Refer to Device Routing in MAX in the
NI-DAQmx Help or the LabVIEW Help for more information.
Routing DO Sample Clock to an Output Terminal
DO Sample Clock can be routed out to any PFI <0..39>, RTSI <0..7>, PXI_Trig <0..7>, or
PXIe-DSTARC terminal.
Other Timing Requirements
The DO timing engine internally generates DO Sample Clock unless configured to an external
source. DO Start Trigger starts the timing engine and either the software or hardware can stop it
after a finite generation completes. When using the DO timing engine, a configurable delay can
be configured from DO Start Trigger to the first DO Sample Clock pulse. By default, this delay
is two ticks of DO Sample Clock Timebase. Figure 2-8 shows the relationship of DO Sample
Clock to DO Start Trigger.
Figure 2-8. DO Sample Clock and DO Start Trigger
DO Sample Clock Timebase
DO Start Trigger
DO Sample Clock
Delay
from
Start
Trigger
DO Sample Clock Timebase Signal
The DO Sample Clock Timebase (do/SampleClockTimebase) signal is divided down to provide
a source for DO Sample Clock. By default, the NI 6612 routes the onboard 100 MHz timebase
to the DO Sample Clock Timebase. You can route many signals to DO Sample Clock Timebase.
To view the complete list of possible routes, see the Device Routes tab in MAX. Refer to Device
Routing in MAX in the NI-DAQmx Help or the LabVIEW Help for more information.
DO Sample Clock Timebase is not available as an output on the I/O connector.
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Chapter 2 Digital I/O
DO Start Trigger
DO Sample Clock
You might use DO Sample Clock Timebase if you want to use an external sample clock signal,
but need to divide the signal down. If you want to use an external sample clock signal but do not
need to divide the signal, then you should use DO Sample Clock rather than DO Sample Clock
Timebase.
DO Start Trigger Signal
Use the DO Start Trigger (do/StartTrigger) signal to initiate a waveform generation. If you do
not use triggers, you can begin a generation with a software command.
Retriggerable DO
The DO Start Trigger can also be configured to be retriggerable. The timing engine will generate
the sample clocks for the configured generation in response to each pulse on a DO Start Trigger
signal.
The timing engine ignores the DO Start Trigger signal while the clock generation is in progress.
After the clock generation is finished, the timing engine waits for another start trigger to begin
another clock generation. Figure 2-9 shows a retriggerable DO of four samples.
Figure 2-9. Retriggerable DO
Using a Digital Start Trigger
To use DO Start Trigger, specify a source and an edge. You can route many signals to DO Start
Trigger Signal. To view the complete list of possible routes, see the Device Routes tab in MAX.
Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW Help for more
information.
Waveform generation can be specified to begin either on the rising- or falling-edge of DO Start
Trigger.
Routing DO Start Trigger Signal to an Output Terminal
DO Start Trigger can be routed out to any RTSI <0..7>, PFI <0..39>, PXI_Trig <0..7>, or
PXIe-DSTARC terminal. The output is an active high pulse. PFI terminals are configured as
inputs by default.
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NI 6612 User Manual
Pause Trigger
Sample Clock
Pause Trigger
Sample Clock
DO Pause Trigger Signal
Use the DO Pause Trigger (do/PauseTrigger) signal to mask off samples in a DAQ sequence.
That is, when DO Pause Trigger is active, no samples occur.
DO Pause Trigger does not stop a sample that is in progress. The pause does not take effect until
the beginning of the next sample.
When generating digital output signals, the generation pauses as soon as the pause trigger is
asserted. If the sample clock source is the onboard clock, the generation resumes as soon as the
pause trigger is deasserted, as shown in Figure 2-10.
Figure 2-10. DO Pause Trigger with the Onboard Clock Source
When using any signal other than the onboard clock as the source of your sample clock, the
generation resumes as soon as the pause trigger is deasserted and another edge of the sample
clock is received, as shown in Figure 2-11.
Figure 2-11. DO Pause Trigger with Other Signal Sources
Using a Digital Pause Trigger
To use DO Pause Trigger, specify a source and a polarity. You can route many signals to DO
Pause Trigger. To view the complete list of possible routes, see the Device Routes tab in MAX.
Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW Help for more
information.
Routing DO Pause Trigger Signal to an Output Terminal
DO Pause Trigger can be routed out to any RTSI <0..7>, PXI_Trig <0..7>, PFI <0..39>, or
PXIe-DSTARC terminal.
© National Instruments | 2-15
Chapter 2 Digital I/O
I/O Protection
Each DIO and PFI signal has limited protection against overvoltage, undervoltage, and
overcurrent conditions as well as ESD events. Avoid these fault conditions by following these
guidelines:
• When configuring a PFI or DIO line as an output, do not connect it to any external signal
source, ground, or power supply.
• When configuring a PFI or DIO line as an output, understand the current requirements of
the load connected to these signals. Do not exceed the specified current output limits of the
DAQ device. NI has several signal conditioning solutions for digital applications requiring
high current drive.
• When configuring a PFI or DIO line as an input, do not drive the line with voltages outside
of its normal operating range.
• Treat the DAQ device as you would treat any static sensitive device. Always properly
ground yourself and the equipment when handling the DAQ device or connecting to it.
DI Change Detection
The device can be configured to detect changes in the DIO signals, which includes Port 0 and
Port 1. Figure 2-12 shows a block diagram of the DIO change detection circuitry.
Figure 2-12. DI Change Detection
P0.0
P1.7
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Synch
Synch
Enable
Enable
Change Detection Event
Enable
Enable
NI 6612 User Manual
The DIO change detection circuitry can be enabled to detect rising edges, falling edges, or either
edge individually on each DIO line. The device synchronizes each DI signal to the 100 MHz
Timebase, and then sends the signal to the change detectors. The circuitry ORs the output of all
enabled change detectors from every DI signal. The result of this OR is the Change Detection
Event signal.
Change detection performs bus correlation by considering all changes within a 50 ns window
one change detection event. This keeps signals on the same bus synchronized in samples and
prevents overruns.
The Change Detection Event signal can do the following:
• Drive any RTSI<0..7>, PXI_Trig<0..7>, PFI<0..39>, or PXI_STAR signal
• Drive the DO Sample Clock or DI Sample Clock
• Generate an interrupt
The Change Detection Event signal also can be used to detect changes on digital output events.
DI Change Detection Applications
The DIO change detection circuitry can interrupt a user program when one of several DIO
signals changes state.
You also can use the output of the DIO change detection circuitry to trigger a DI or counter
acquisition on the logical OR of several digital signals. By routing the Change Detection Event
signal to a counter, the relative time between bus changes can be captured.
The Change Detection Event signal can be used to trigger DO or counter generations.
Digital Filtering
A programmable debouncing filter can be enabled on each digital line on Port 0. When the filters
are enabled, the device samples the input on each rising edge of a filter clock. The device divides
down the onboard 100 MHz or 100 kHz clocks to generate the filter clock. The following is an
example of low-to-high transitions of the input signal. High-to-low transitions work similarly.
Assume that an input terminal has been low for a long time. The input terminal then changes
from low-to-high, but glitches several times. When the filter clock has sampled the signal high
on two consecutive edges and the signal remained stable in between, the low-to-high transition
is propagated to the rest of the circuit.
© National Instruments | 2-17
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