National Instruments 3.21E+04 User Manual

AT-MIO/AI E Series

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User Manual

Multifunction I/O Boards for the PC AT

May 1996 Edition

Part Number 320517E-01

 Copyright 1994, 1996 National Instruments Corporation. All Rights Reserved.

Internet Support

GPIB: [e-mail]
DAQ: [e-mail]
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LabWindows: [e-mail]
HiQ: [e-mail]

E-mail: [e-mail]
FTP Site: ftp.natinst.com
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BBS France: 1 48 65 15 59

FaxBack Support

[phone]

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National Instruments Corporate Headquarters

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Important Information

Warranty

Copyright

Trademarks

The AT-MIO/AI E Series boards are warranted against defects in materials and workmanship for a period of one year
from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option,
repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and
labor.

The media on which you receive National Instruments software are warranted not to fail to execute programming
instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as evidenced
by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do
not execute programming instructions if National Instruments receives notice of such defects during the warranty
period. National Instruments does not warrant that the operation of the software shall be uninterrupted or error free.

A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside
of the package before any equipment will be accepted for warranty work. National Instruments will pay the shipping
costs of returning to the owner parts which are covered by warranty.

National Instruments believes that the information in this manual is accurate. The document has been carefully
reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments
reserves the right to make changes to subsequent editions of this document without prior notice to holders of this
edition. The reader should consult National Instruments if errors are suspected. In no event shall National
Instruments be liable for any damages arising out of or related to this document or the information contained in it.

XCEPT AS SPECIFIED HEREIN

E

SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE

C

USTOMER’S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL

I

NSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER
WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS, OR INCIDENTAL OR
CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY THEREOF

Instruments will apply regardless of the form of action, whether in contract or tort, including negligence. Any action
against National Instruments must be brought within one year after the cause of action accrues. National Instruments
shall not be liable for any delay in performance due to causes beyond its reasonable control. The warranty provided
herein does not cover damages, defects, malfunctions, or service failures caused by owner’s failure to follow the
National Instruments installation, operation, or maintenance instructions; owner’s modification of the product;
owner’s abuse, misuse, or negligent acts; and power failure or surges, fire, flood, accident, actions of third parties, or
other events outside reasonable control.

Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or
mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole or
in part, without the prior written consent of National Instruments Corporation.

LabVIEW, NI-DAQ, RTSI, DAQCard, DAQPad, DAQ-PnP, DAQ-STC, NI-PGIA, and SCXI are
trademarks of National Instruments Corporation.

Product and company names listed are trademarks or trade names of their respective companies.

, N

ATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR IMPLIED, AND

. N

ATIONAL INSTRUMENTS

. This limitation of the liability of National

.

WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS

National Instruments products are not designed with components and testing intended to ensure a level of reliability
suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving
medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the
part of the user or application designer. Any use or application of National Instruments products for or involving
medical or clinical treatment must be performed by properly trained and qualified medical personnel, and all
traditional medical safeguards, equipment, and procedures that are appropriate in the particular situation to prevent
serious injury or death should always continue to be used when National Instruments products are being used.
National Instruments products are NOT intended to be a substitute for any form of established process, procedure, or
equipment used to monitor or safeguard human health and safety in medical or clinical treatment.

About This Manual

Organization of This Manual ........................................................................................xi

Conventions Used in This Manual ................................................................................xii

National Instruments Documentation ...........................................................................xiii

Related Documentation .................................................................................................xiv

Customer Communication ............................................................................................xiv

Chapter 1
Introduction

About the AT E Series ..................................................................................................1-1

What You Need to Get Started ......................................................................................1-2

Software Programming Choices ...................................................................................1-3

LabVIEW and LabWindows/CVI Application Software ...............................1-3

NI-DAQ Driver Software ...............................................................................1-3

Register-Level Programming ..........................................................................1-5

Optional Equipment ......................................................................................................1-5

Custom Cabling .............................................................................................................1-6

Unpacking .....................................................................................................................1-7

Table

of

Contents

Chapter 2
Installation and Configuration

Software Installation .....................................................................................................2-1

Hardware Installation ....................................................................................................2-1

Board Configuration ......................................................................................................2-2

Bus Interface ...................................................................................................2-2

Plug and Play ....................................................................................2-3

Switchless Data Acquisition .............................................................2-3

Base I/O Address Selection ..............................................................2-3

DMA Channel Selection ..................................................................2-3

Interrupt Channel Selection ..............................................................2-4

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Table of Contents

Chapter 3
Hardware Overview

Analog Input .................................................................................................................3-6

Input Mode ..................................................................................................... 3-6

Input Polarity and Input Range ...................................................................... 3-7

Dither .............................................................................................................. 3-11

Multiple-Channel Scanning Considerations ..................................................3-12

Analog Output ..............................................................................................................3-14

Analog Output Reference Selection ............................................................... 3-14

Analog Output Polarity Selection ..................................................................3-14

Analog Output Reglitch Selection .................................................................3-15

Analog Trigger .............................................................................................................3-15

Digital I/O ..................................................................................................................... 3-19

Timing Signal Routing .................................................................................................3-19

Programmable Function Inputs ...................................................................... 3-20

Board and RTSI Clocks .................................................................................3-21

RTSI Triggers ................................................................................................. 3-21

Chapter 4
Signal Connections

I/O Connector ............................................................................................................... 4-1

I/O Connector Signal Descriptions ................................................................4-5

Analog Input Signal Connections ................................................................................. 4-16

Types of Signal Sources ............................................................................................... 4-18

Floating Signal Sources .................................................................................. 4-18

Ground-Referenced Signal Sources ............................................................... 4-18

Input Configurations ..................................................................................................... 4-18

Differential Connection Considerations (DIFF Input Configuration) ........... 4-20

Single-Ended Connection Considerations ...................................................... 4-24

Common-Mode Signal Rejection Considerations .......................................... 4-26

Analog Output Signal Connections .............................................................................. 4-27

Digital I/O Signal Connections .................................................................................... 4-28

Considerations for Selecting Input Ranges ...................................... 3-10

Differential Connections for Ground-Referenced

Signal Sources ................................................................................4-21

Differential Connections for Nonreferenced or Floating

Signal Sources ................................................................................4-22

Single-Ended Connections for Floating Signal Sources

(RSE Configuration) ...................................................................... 4-25

Single-Ended Connections for Grounded Signal Sources

(NRSE Configuration) ...................................................................4-25

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Table of Contents

Power Connections ........................................................................................................4-30

Timing Connections ......................................................................................................4-30

Programmable Function Input Connections ...................................................4-31

Data Acquisition Timing Connections ...........................................................4-32

SCANCLK Signal ............................................................................4-33

EXTSTROBE* Signal ......................................................................4-33

TRIG1 Signal ...................................................................................4-34

TRIG2 Signal ...................................................................................4-36

STARTSCAN Signal .......................................................................4-37

CONVERT* Signal ..........................................................................4-39

AIGATE Signal ................................................................................4-41

SISOURCE Signal ...........................................................................4-41

Waveform Generation Timing Connections ...................................................4-42

WFTRIG Signal ...............................................................................4-42

UPDATE* Signal .............................................................................4-43

UISOURCE Signal ...........................................................................4-45

General-Purpose Timing Signal Connections ................................................4-46

GPCTR0_SOURCE Signal ..............................................................4-46

GPCTR0_GATE Signal ...................................................................4-47

GPCTR0_OUT Signal ......................................................................4-47

GPCTR0_UP_DOWN Signal ..........................................................4-48

GPCTR1_SOURCE Signal ..............................................................4-48

GPCTR1_GATE Signal ...................................................................4-49

GPCTR1_OUT Signal ......................................................................4-50

GPCTR1_UP_DOWN Signal ..........................................................4-51

FREQ_OUT Signal ..........................................................................4-52

Timing Specifications for Digital I/O Ports A, B, and C ................................4-53

Mode 1 Input Timing .......................................................................4-55

Mode 1 Output Timing .....................................................................4-56

Mode 2 Bidirectional Timing ...........................................................4-57

Field Wiring Considerations .........................................................................................4-58

Chapter 5
Calibration

Loading Calibration Constants ......................................................................................5-1

Self-Calibration .............................................................................................................5-2

External Calibration ......................................................................................................5-2

Other Considerations .....................................................................................................5-3

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Table of Contents

Appendix A
Specifications

AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 ................................................ A-1

AT-MIO-16E-10 and AT-MIO-16DE-10 ....................................................................A-11

AT-MIO-16XE-10 and AT-AI-16XE-10 ..................................................................... A-19

AT-MIO-16XE-50 ........................................................................................................ A-26

Appendix B
Optional Cable Connector Descriptions

Appendix C
Common Questions

Appendix D
Customer Communication

Glossary

Index

Figures

Figure 1-1. The Relationship between the Programming Environment,

NI-DAQ, and Your Hardware ............................................................... 1-4

Figure 3-1. AT-MIO-16E-1 and AT-MIO-16E-2 Block Diagram ............................. 3-1

Figure 3-2. AT-MIO-64E-3 Block Diagram ..............................................................3-2

Figure 3-3. AT-MIO-16E-10 and AT-MIO-16DE-10 Block Diagram ...................... 3-3

Figure 3-4. AT-MIO-16XE-10 Block Diagram ......................................................... 3-4

Figure 3-5. AT-AI-16XE-10 Block Diagram ............................................................. 3-5

Figure 3-6. AT-MIO-16XE-50 Block Diagram ......................................................... 3-6

Figure 3-7. Dither ....................................................................................................... 3-12

Figure 3-8. Analog Trigger Block Diagram ............................................................... 3-16

Figure 3-9. Below-Low-Level Analog Triggering Mode .......................................... 3-17

Figure 3-10. Above-High-Level Analog Triggering Mode .........................................3-17

Figure 3-11. Inside-Region Analog Triggering Mode ................................................. 3-17

Figure 3-12. High-Hysteresis Analog Triggering Mode .............................................. 3-18

Figure 3-13. Low-Hysteresis Analog Triggering Mode ..............................................3-18

Figure 3-14. CONVERT* Signal Routing ...................................................................3-20

Figure 3-15. RTSI Bus Signal Connection ..................................................................3-22

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Table of Contents

Figure 4-1. I/O Connector Pin Assignment for the AT-MIO-16E-1,

AT-MIO-16E-2, AT-MIO-16E-10, AT-MIO-16XE-10,

AT-AI-16XE-10, and AT-MIO-16XE-50 ..............................................4-2

Figure 4-2. I/O Connector Pin Assignment for the AT-MIO-64E-3 ..........................4-3

Figure 4-3. I/O Connector Pin Assignment for the AT-MIO-16DE-10 .....................4-4

Figure 4-4. AT E Series PGIA ....................................................................................4-17

Figure 4-5. Summary of Analog Input Connections ..................................................4-19

Figure 4-6. Differential Input Connections for Ground-Referenced Signals .............4-21

Figure 4-7. Differential Input Connections for Nonreferenced Signals .....................4-22

Figure 4-8. Single-Ended Input Connections for Nonreferenced or

Floating Signals ......................................................................................4-25

Figure 4-9. Single-Ended Input Connections for Ground-Referenced Signal ............4-26

Figure 4-10. Analog Output Connections .....................................................................4-28

Figure 4-11. Digital I/O Connections ...........................................................................4-29

Figure 4-12. Timing I/O Connections ..........................................................................4-31

Figure 4-13. Typical Posttriggered Acquisition ...........................................................4-32

Figure 4-14. Typical Pretriggered Acquisition .............................................................4-33

Figure 4-15. SCANCLK Signal Timing .......................................................................4-33

Figure 4-16. EXTSTROBE* Signal Timing ................................................................4-34

Figure 4-17. TRIG1 Input Signal Timing .....................................................................4-35

Figure 4-18. TRIG1 Output Signal Timing ..................................................................4-35

Figure 4-19. TRIG2 Input Signal Timing .....................................................................4-36

Figure 4-20. TRIG2 Output Signal Timing ..................................................................4-37

Figure 4-21. STARTSCAN Input Signal Timing .........................................................4-38

Figure 4-22. STARTSCAN Output Signal Timing ......................................................4-38

Figure 4-23. CONVERT* Input Signal Timing ...........................................................4-40

Figure 4-24. CONVERT* Output Signal Timing .........................................................4-40

Figure 4-25. SISOURCE Signal Timing ......................................................................4-42

Figure 4-26. WFTRIG Input Signal Timing .................................................................4-43

Figure 4-27. WFTRIG Output Signal Timing ..............................................................4-43

Figure 4-28. UPDATE* Input Signal Timing ..............................................................4-44

Figure 4-29. UPDATE* Output Signal Timing ............................................................4-44

Figure 4-30. UISOURCE Signal Timing ......................................................................4-45

Figure 4-31. GPCTR0_SOURCE Signal Timing .........................................................4-46

Figure 4-32. GPCTR0_GATE Signal Timing in Edge-Detection Mode .....................4-47

Figure 4-33. GPCTR0_OUT Signal Timing ................................................................4-48

Figure 4-34. GPCTR1_SOURCE Signal Timing .........................................................4-49

Figure 4-35. GPCTR1_GATE Signal Timing in Edge-Detection Mode .....................4-50

Figure 4-36. GPCTR1_OUT Signal Timing ................................................................4-50

Figure 4-37. GPCTR Timing Summary .......................................................................4-51

Figure 4-38. Mode 1 Input Timing ...............................................................................4-55

Figure 4-39. Mode 1 Output Timing ............................................................................4-56

Figure 4-40. Mode 2 Bidirectional Timing ...................................................................4-57

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National Instruments Corporation ix AT-MIO/AI E Series User Manual

Table of Contents

Figure B-1. 68-Pin MIO Connector Pin Assignments ................................................ B-2

Figure B-2. 68-Pin DIO Connector Pin Assignments ................................................B-3

Figure B-3. 68-Pin Extended Analog Input Connector Pin Assignments .................. B-4

Figure B-4. 50-Pin MIO Connector Pin Assignments ................................................ B-5

Figure B-5. 50-Pin DIO Connector Pin Assignments ................................................B-6

Figure B-6. 50-Pin Extended Analog Input Connector Pin Assignments .................. B-7

Tables

Table 2-1. PC AT I/O Address Map .........................................................................2-4

Table 2-2. PC AT Interrupt Assignment Map ..........................................................2-6

Table 2-3. PC AT 16-bit DMA Channel Assignment Map ...................................... 2-7

Table 3-1. Available Input Configurations for the AT E Series ...............................3-7

Table 3-2. Actual Range and Measurement Precision .............................................. 3-8

Table 3-3. Actual Range and Measurement Precision, AT-MIO-16XE-10,

Table 4-1. I/O Signal Summary, AT-MIO-16E-1, AT-MIO-16E-2, and

Table 4-2. I/O Signal Summary, AT-MIO-16E-10 and AT-MIO-16DE-10 ............ 4-10

Table 4-3. I/O Signal Summary, AT-MIO-16XE-10 and AT-AI-16XE-10 ............. 4-12

Table 4-4. I/O Signal Summary, AT-MIO-16XE-50 ...............................................4-14

Table 4-5. Port C Signal Assignments ...................................................................... 4-53

AT-AI-16XE-10, and AT-MIO-16XE-50 ............................................. 3-10

AT-MIO-64E-3 ..................................................................................... 4-8

AT-MIO/AI E Series User Manual x

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National Instruments Corporation

About

About

This

This

Manual

Manual

This manual describes the electrical and mechanical aspects of each
board in the AT E Series product line and contains information
concerning their operation and programming. Unless otherwise noted,
text applies to all boards in the AT E Series.

The AT E Series includes the following boards:

• AT-MIO-16E-1

• AT-MIO-16E-2

• AT-MIO-64E-3

• AT-MIO-16E-10

• AT-MIO-16DE-10

• AT-MIO-16XE-10

• AT-AI-16XE-10

• AT-MIO-16XE-50
The AT E Series boards are high-performance multifunction analog,

digital, and timing I/O boards for the PC AT series computers.
Supported functions include analog input, analog output, digital I/O,
and timing I/O.

Organization of This Manual

The AT-MIO/AI E Series User Manual is organized as follows:

• Chapter 1, Introduction, describes the AT E Series boards, lists
what you need to get started, describes the optional software and
optional equipment, and explains how to unpack your AT E Series
board.

• Chapter 2, Installation and Configuration, explains how to install
and configure your AT E Series board.

• Chapter 3, Hardware Overview, presents an overview of the
hardware functions on your AT E Series board.

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National Instruments Corporation xi AT-MIO/AI E Series User Manual

About This Manual

• Chapter 4, Signal Connections, describes how to make input and
output signal connections to your AT E Series board via the board
I/O connector.

• Chapter 5, Calibration, discusses the calibration procedures for
your AT E Series board.

• Appendix A, Specifications, lists the specifications of each board in
the AT E Series.

• Appendix B, Optional Cable Connector Descriptions, describes the
connectors on the optional cables for the AT E Series boards.

• Appendix C, Common Questions, contains a list of commonly asked
questions and their answers relating to usage and special features
of your AT E Series board.

• Appendix D, Customer Communication, contains forms you can use
to request help from National Instruments or to comment on our
products.

• The Glossary contains an alphabetical list and description of terms
used in this manual, including acronyms, abbreviations, metric
prefixes, mnemonics, and symbols.

• The Index alphabetically lists topics covered in this manual,
including the page where you can find the topic.

Conventions Used in This Manual

The following conventions are used in this manual.

bold Bold text denotes parameters.
bold italic Bold italic text denotes a note, caution, or warning.
italic Italic text denotes emphasis on a specific board in the AT E Series or on

other important information, a cross reference, or an introduction to a
key concept.

NI-DAQ NI-DAQ refers to the NI-DAQ software for PC compatibles unless

otherwise noted.
PC PC refers to the PC AT series computers.
SCXI SCXI stands for Signal Conditioning eXtensions for Instrumentation

and is a National Instruments product line designed to perform

front-end signal conditioning for National Instruments plug-in DAQ

boards.

AT-MIO/AI E Series User Manual xii

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National Instruments Corporation

♦ The ♦ indicates that the text following it applies only to specific

AT E Series boards.

<> Angle brackets containing numbers separated by an ellipsis represent a

range of values associated with a bit, port, or signal name (for example,
ACH<0..7> stands for ACH0 through ACH7).

Abbreviations, acronyms, metric prefixes, mnemonics, symbols, and
terms are listed in the Glossary at the end of this manual.

National Instruments Documentation

The AT-MIO/AI E Series User Manual is one piece of the documentation
set for your DAQ system. You could have any of several types of
manuals depending on the hardware and software in your system. Use
the manuals you have as follows:

• Getting Started with SCXI—If you are using SCXI, this is the first
manual you should read. It gives an overview of the SCXI system
and contains the most commonly needed information for the
modules, chassis, and software.

• Your SCXI hardware user manuals—If you are using SCXI, read
these manuals next for detailed information about signal
connections and module configuration. They also explain in
greater detail how the module works and contain application hints.

• Your DAQ hardware user manuals—These manuals have detailed
information about the DAQ hardware that plugs into or is
connected to your computer. Use these manuals for hardware
installation and configuration instructions, specification
information about your DAQ hardware, and application hints.

• Software documentation—Examples of software documentation
you may have are the LabVIEW and LabWindows/CVI
documentation sets and the NI-DAQ documentation. After you set
up your hardware system, use either the application software
(LabVIEW or LabWindows/CVI) or the NI-DAQ documentation to
help you write your application. If you have a large and
complicated system, it is worthwhile to look through the software
documentation before you configure your hardware.

• Accessory installation guides or manuals—If you are using
accessory products, read the terminal block and cable assembly
installation guides. They explain how to physically connect the

About This Manual

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National Instruments Corporation xiii AT-MIO/AI E Series User Manual

About This Manual

relevant pieces of the system. Consult these guides when you are
making your connections.

• SCXI chassis manuals—If you are using SCXI, read these manuals
for maintenance information on the chassis and installation
instructions.

Related Documentation

The following National Instruments document contains information
you may find helpful:

• Application Note 025, Field Wiring and Noise Considerations for

Analog Signals

Customer Communication

National Instruments wants to receive your comments on our products
and manuals. We are interested in the applications you develop with
our products, and we want to help if you have problems with them. To
make it easy for you to contact us, this manual contains comment and
configuration forms for you to complete. These forms are in
Appendix D, Customer Communication, at the end of this manual.

AT-MIO/AI E Series User Manual xiv

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National Instruments Corporation

Introduction

This chapter describes the AT E Series boards, lists what you need to
get started, describes the optional software and optional equipment, and
explains how to unpack your AT E Series board.

About the AT E Series

Thank you for buying a National Instruments AT E Series board. The
AT E Series boards are the first completely Plug and Play-compatible
multifunction analog, digital, and timing I/O boards for the PC AT and
compatible computers. This family of boards features 12-bit and 16-bit
ADCs with 16 and 64 analog inputs, 12-bit and 16-bit DACs with
voltage outputs, eight and 32 lines of TTL-compatible digital I/O, and
two 24-bit counter/timers for timing I/O. Because the AT E Series
boards have no DIP switches, jumpers, or potentiometers, they are
easily configured and calibrated using software.

Chapter

1

The AT E Series boards are the first completely switchless and
jumperless data acquisition boards. This feature is made possible by the
National Instruments DAQ-PnP bus interface chip that connects the
board to the AT I/O bus. The DAQ-PnP implements the Plug and Play
ISA Specification so that the DMA, interrupts, and base I/O addresses
are all software configurable. This allows you to easily change the
AT E Series board configuration without having to remove the board
from your computer. The DAQ-STC makes possible such applications
as buffered pulse generation, equivalent time sampling, and seamlessly
changing the sampling rate.

The AT E Series boards use the National Instruments DAQ-STC
system timing controller for time-related functions. The DAQ-STC
consists of three timing groups that control analog input, analog output,
and general-purpose counter/timer functions. These groups include a
total of seven 24-bit and three 16-bit counters and a maximum timing
resolution of 50 ns.

A common problem with DAQ boards is that you cannot easily
synchronize several measurement functions to a common trigger or

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National Instruments Corporation 1-1 AT-MIO/AI E Series User Manual

Chapter 1 Introduction

timing event. The AT E Series boards have the Real-Time System
Integration (RTSI) bus to solve this problem. The RTSI bus consists of
our RTSI bus interface and a ribbon cable to route timing and trigger
signals between several functions on as many as five DAQ boards in
your PC.

The AT E Series boards can interface to an SCXI system so that you can
acquire over 3,000 analog signals from thermocouples, RTDs, strain
gauges, voltage sources, and current sources. You can also acquire or
generate digital signals for communication and control. SCXI is the
instrumentation front end for plug-in DAQ boards.

Detailed specifications of the AT E Series boards are in Appendix A,
Specifications.

What You Need to Get Started

To set up and use your AT E Series board, you will need the following:
❏ One of the following boards:

AT-MIO-16E-1
AT-MIO-16E-2
AT-MIO-64E-3
AT-MIO-16E-10
AT-MIO-16DE-10
AT-MIO-16XE-10
AT-AI-16XE-10
AT-MIO-16XE-50

❏ AT-MIO/AI E Series User Manual
❏ One of the following software packages and documentation

NI-DAQ for PC compatibles
LabVIEW
LabWindows/CVI

❏ Your computer

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National Instruments Corporation

Software Programming Choices

There are several options to choose from when programming your
National Instruments DAQ and SCXI hardware. You can use
LabVIEW, LabWindows/CVI, NI-DAQ, or register-level
programming.

LabVIEW and LabWindows/CVI Application Software

LabVIEW and LabWindows/CVI are innovative program development
software packages for data acquisition and control applications.
LabVIEW uses graphical programming, whereas LabWindows/CVI
enhances traditional programming languages. Both packages include
extensive libraries for data acquisition, instrument control, data
analysis, and graphical data presentation.

LabVIEW features interactive graphics, a state-of-the-art user
interface, and a powerful graphical programming language. The
LabVIEW Data Acquisition VI Library, a series of VIs for using
LabVIEW with National Instruments DAQ hardware, is included with
LabVIEW. The LabVIEW Data Acquisition VI Library is functionally
equivalent to the NI-DAQ software.

Chapter 1 Introduction

LabWindows/CVI features interactive graphics, a state-of-the-art user
interface, and uses the ANSI standard C programming language. The
LabWindows/CVI Data Acquisition Library, a series of functions for
using LabWindows/CVI with National Instruments DAQ hardware, is
included with the NI-DAQ software kit. The LabWindows/CVI Data
Acquisition library is functionally equivalent to the NI-DAQ software.

Using LabVIEW or LabWindows/CVI software will greatly reduce the
development time for your data acquisition and control application.

NI-DAQ Driver Software

The NI-DAQ driver software is included at no charge with all National
Instruments DAQ hardware. NI-DAQ is not packaged with signal
conditioning or accessory products. NI-DAQ has an extensive library of
functions that you can call from your application programming
environment. These functions include routines for analog input (A/D
conversion), buffered data acquisition (high-speed A/D conversion),
analog output (D/A conversion), waveform generation (timed D/A
conversion), digital I/O, counter/timer operations, SCXI, RTSI,
calibration, messaging, and acquiring data to extended memory.



National Instruments Corporation 1-3 AT-MIO/AI E Series User Manual

Chapter 1 Introduction

NI-DAQ has both high-level DAQ I/O functions for maximum ease of
use and low-level DAQ I/O functions for maximum flexibility and
performance. Examples of high-level functions are streaming data to
disk or acquiring a certain number of data points. An example of a
low-level function is writing directly to registers on the DAQ device.
NI-DAQ does not sacrifice the performance of National Instruments
DAQ devices because it lets multiple devices operate at their peak
performance.

NI-DAQ also internally addresses many of the complex issues between
the computer and the DAQ hardware such as programming interrupts
and DMA controllers. NI-DAQ maintains a consistent software
interface among its different versions so that you can change platforms
with minimal modifications to your code. Whether you are using
conventional programming languages, LabVIEW, or
LabWindows/CVI, your application uses the NI-DAQ driver software,
as illustrated in Figure 1-1.

Conventional

Programming

Environment

(PC, Macintosh, or

Sun SPARCstation)

DAQ or

SCXI Hardware

LabVIEW
(PC, Macintosh, or
Sun SPARCstation)

NI-DAQ

Driver Software

LabWindows/CVI

(PC or

Sun SPARCstation)

Personal

Computer

or

Workstation

Figure 1-1. The Relationship between the Programming Environment, NI-DAQ, and

Your Hardware

AT-MIO/AI E Series User Manual 1-4



National Instruments Corporation

You can use your AT E Series board, together with other PC, AT,
EISA, DAQCard, and DAQPad Series DAQ and SCXI hardware, with
NI-DAQ software for PC compatibles.

Register-Level Programming

The final option for programming any National Instruments DAQ
hardware is to write register-level software. Writing register-level
programming software can be very time-consuming and inefficient and
is not recommended for most users.

Even if you are an experienced register-level programmer, consider
using NI-DAQ, LabVIEW, or LabWindows/CVI to program your
National Instruments DAQ hardware. Using the NI-DAQ, LabVIEW, or
LabWindows/CVI software is as easy and as flexible as register-level
programming and can save weeks of development time.

Optional Equipment

National Instruments offers a variety of products to use with your
AT E Series board, including cables, connector blocks, and other
accessories, as follows:

• Cables and cable assemblies, shielded and ribbon

• Connector blocks, shielded and unshielded 50, 68, and 100-pin
screw terminals

• Real Time System Integration (RTSI) bus cables

• Signal condition eXtension for instrumentation (SCXI) modules
and accessories for isolating, amplifying, exciting, and
multiplexing signals for relays and analog output. With SCXI you
can condition and acquire up to 3072 channels.

• Low channel count signal conditioning modules, boards, and
accessories, including conditioning for strain gauges and RTDs,
simultaneous sample and hold, and relays

Chapter 1 Introduction

For more specific information about these products, refer to your
National Instruments catalogue or call the office nearest you.



National Instruments Corporation 1-5 AT-MIO/AI E Series User Manual

Chapter 1 Introduction

Custom Cabling

National Instruments offers cables and accessories for you to prototype
your application or to use if you frequently change board
interconnections.

If you want to develop your own cable, however, the following
guidelines may be useful:

• For the analog input signals, shielded twisted-pair wires for each

• You should route the analog lines separately from the digital lines.

• When using a cable shield, use separate shields for the analog and

The following list gives recommended part numbers for connectors that
mate to the I/O connector on your AT E Series board.

♦ AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-16E-10,

♦ AT-MIO-64E-3 and AT-MIO-16DE-10

analog input pair yield the best results, assuming that you use
differential inputs. Tie the shield for each signal pair to the ground
reference at the source.

digital halves of the cable. Failure to do so results in noise coupling
into the analog signals from transient digital signals.

Mating connectors and a backshell kit for making custom 68-pin
cables are available from National Instruments (part number
776832-01)

AT-MIO-16XE-10, AT-AI-16XE-10, and the AT-MIO-16XE-50
Honda 68-position, solder cup, female connector (part number

PCS-E68FS)
Honda backshell (part number PCS-E68LKPA)

AMP 100-position IDC male connector (part number 1-750913-9)
AMP backshell, .50 max O.D. cable (part number 749081-1)
AMP backshell, .55 max O.D. cable, (part number 749854-1)

AT-MIO/AI E Series User Manual 1-6



National Instruments Corporation

Unpacking

Chapter 1 Introduction

Your AT E Series board is shipped in an antistatic package to prevent
electrostatic damage to the board. Electrostatic discharge can damage
several components on the board. To avoid such damage in handling
the board, take the following precautions:

• Ground yourself via a grounding strap or by holding a grounded
object.

• Touch the antistatic package to a metal part of your computer
chassis before removing the board from the package.

• Remove the board from the package and inspect the board for loose
components or any other sign of damage. Notify National
Instruments if the board appears damaged in any way. Do not
install a damaged board into your computer.

• Never touch the exposed pins of connectors.



National Instruments Corporation 1-7 AT-MIO/AI E Series User Manual

Installation and

Chapter

Configuration

This chapter explains how to install and configure your AT E Series
board.

Software Installation

You may need to install your software before you install your
AT E Series board. Refer to the appropriate release notes indicated
below for specific instructions on the software installation sequence.

If you are using NI-DAQ, refer to the NI-DAQ User Manual for PC
Compatibles Version 4.9.0 Release Notes. Find the installation section
for your operating system and follow the instructions given there.

If you are using LabVIEW, refer to your LabVIEW release notes. After
you have installed LabVIEW, refer to the NI-DAQ release notes and
follow the instructions given there for your operating system and
LabVIEW.

If you are using LabWindows/CVI, refer to your LabWindows/CVI
release notes. After you have installed LabWindows/CVI, refer to your
NI-DAQ release notes and follow the instructions given there for your
operating system and LabWindows/CVI.

2

If you are a register-level programmer, refer to the AT-MIO E Series
Register-Level Programmer Manual and the DAQ-STC Technical
Reference Manual for software configuration information.

Hardware Installation

You can install an AT E Series board in any available expansion slot
in your PC. However, to achieve best noise performance, you should
leave as much room as possible between the AT E Series board and
other boards and hardware. The following are general installation
instructions, but consult your PC user manual or technical reference
manual for specific instructions and warnings.



National Instruments Corporation 2-1 AT-MIO/AI E Series User Manual

Chapter 2 Installation and Configuration

1. Write down the AT E Series board serial number in the AT E Series
Hardware and Software Configuration Form in Appendix D at the
back of this manual. You will need this serial number when you
install and configure your software.

2. Turn off and unplug your computer.

3. Remove the top cover or access port to the I/O channel.

4. Remove the expansion slot cover on the back panel of the
computer.

5. Insert the AT E Series board into an EISA or 16-bit ISA slot. It
may be a tight fit, but do not force the board into place.

6. Screw the mounting bracket of the AT E Series board to the back
panel rail of the computer.

7. Check the installation.

8. Replace the cover.

9. Plug in and turn on your computer.

The AT E Series board is installed. You are now ready to install and
configure your software.

Board Configuration

Due to the DAQ-PnP features, the AT E Series boards are completely
software configurable. Two types of configuration must be performed
on the AT E Series boards—bus-related configuration and data
acquisition-related configuration. Bus-related configuration includes
setting the base I/O address, DMA channels, and interrupt channels.
Data acquisition-related configuration, explained in the next chapter,
includes such settings as analog input polarity and range, analog output
reference source, and other settings. For more information about data
acquisition-related configuration, refer to your NI-DAQ user manual.

Bus Interface

The AT E Series boards work in either a Plug and Play mode or a
switchless mode. These modes dictate how the base I/O address, DMA
channels, and interrupt channels are determined and assigned to the
board.

AT-MIO/AI E Series User Manual 2-2



National Instruments Corporation

Chapter 2 Installation and Configuration

Plug and Play

The AT E Series boards are fully compatible with the industry-standard
Plug and Play ISA specification. A Plug and Play system arbitrates and
assigns resources through software, freeing you from manually setting
switches and jumpers. These resources include the board base I/O
address, DMA channels, and interrupt channels. Each AT E Series
board is configured at the factory to request these resources from the
Plug and Play Configuration Manager.

The Configuration Manager receives all of the resource requests at start
up, compares the available resources to those requested, and assigns the
available resources as efficiently as possible to the Plug and Play
boards. Application software can query the Configuration Manager to
determine the resources assigned to each board without your
involvement. The Plug and Play software is installed as a device driver
or as an integral component of the computer BIOS.

Switchless Data Acquisition

You can use an AT E Series board in a non-Plug and Play system as a
switchless DAQ board. A non-Plug and Play system is a system in
which the Configuration Manager has not been installed and which does
not contain any non-National Instruments Plug and Play products. You
use a configuration utility to enter the base address, DMA, and interrupt
selections, and the application software assigns them to the board.

Note: Avoid resource conflicts with non-National Instruments boards. For

example, do not configure two boards for the same base address.

Base I/O Address Selection

The AT E Series boards can be configured to use base addresses in the
range of 20 to FFE0 hex. Each AT E Series board occupies 32 bytes of
address space and must be located on a 32-byte boundary. Therefore,
valid addresses include 100, 120, 140, ..., 3C0, 3E0 hex. This selection
is software configured and does not require you to manually change any
settings on the board.

DMA Channel Selection

The AT E Series boards can achieve high transfer rates by using up to
three 16-bit DMA channels. You can use these DMA channels for data
transfers with the analog input, analog output, and general-purpose
counter sections of the board. The AT E Series boards can use only



National Instruments Corporation 2-3 AT-MIO/AI E Series User Manual

Chapter 2 Installation and Configuration

16-bit DMA channels, which correspond to channels 5, 6, and 7 in an
ISA computer and channels 0, 1, 2, 3, 5, 6, and 7 in an EISA computer.
These selections are all software configured and do not require you to
manually change any settings on the board.

Interrupt Channel Selection

The AT E Series boards can increase bus efficiency by using an
interrupt channel. You can use an interrupt channel for event
notification without the use of polling techniques. AT E Series boards
can use interrupt channels 3, 4, 5, 7, 10, 11, 12, and 15. These selections
are all software configured and do not require you to manually change
any settings on the board. The following tables provide information
concerning possible conflicts when configuring your AT E Series
board.

Table 2-1. PC AT I/O Address Map

I/O Address Range (Hex)

100 to 1EF

1F0 to 1F8 IBM PC AT Fixed Disk

200 to 20F PC and PC AT Game Controller, reserved

210 to 213 PC-DIO-24 – default

218 to 21F —

220 to 23F Previous generation of AT-MIO boards – default

240 to 25F AT-DIO-32F – default

260 to 27F Lab-PC/PC+ – default

278 to 28F AT Parallel Printer Port 2 (LPT2)

279 Reserved for Plug and Play operation

280 to 29F WD EtherCard+ – default

2A0 to 2BF —

2E2 to 2F7 —

2F8 to 2FF PC, AT Serial Port 2 (COM2)

—

Device

AT-MIO/AI E Series User Manual 2-4



National Instruments Corporation

Chapter 2 Installation and Configuration

Table 2-1. PC AT I/O Address Map (Continued)

I/O Address Range (Hex)

300 to 30F

310 to 31F —

320 to 32F ICM PC/XT Fixed Disk Controller

330 to 35F —

360 to 363 PC Network (low address)

364 to 367 Reserved

368 to 36B PC Network (high address)

36C to 36F Reserved

370 to 366 PC, AT Parallel Printer Port 1 (LPT1)

380 to 38C SDLC Communications

380 to 389 Bisynchronous (BSC) Communications (alternate)

390 to 393 Cluster Adapter 0

394 to 39F —

3A0 to 3A9 BSC Communications (primary)

3Com EtherLink – default

Device

3AA to 3AF —

3B0 to 3BF Monochrome Display/Parallel Printer Adapter 0

3C0 to 3CF Enhanced Graphics Adapter, VGA

3D0 to 3DF Color/Graphics Monitor Adapter, VGA

3E0 to 3EF —

3F0 to 3F7 Diskette Controller

3F8 to 3FF Serial Port 1 (COM1)

A79 Reserved for Plug and Play operation



National Instruments Corporation 2-5 AT-MIO/AI E Series User Manual

Chapter 2 Installation and Configuration

Table 2-2. PC AT Interrupt Assignment Map

IRQ

15

14 Fixed Disk Controller

13 Coprocessor

12 AT-DIO-32F – default

11 AT-DIO-32F – default

10 AT-MIO-16 – default

9 PC Network – default

8 Real Time Clock

7 Parallel Port 1 (LPT1)

6 Diskette Drive Controller

5 Parallel Port 2 (LPT2)

4 Serial Port 1 (COM1)

Available

PC Network Alternate – default

Fixed Disk and Diskette Drive Controller

PC-DIO-24 – default
Lab-PC/PC+ – default

BSC, BSC Alternate

Device

3 Serial Port 2 (COM2)

2 IRQ 8-15 Chain (from interrupt controller 2)

1 Keyboard Controller Output Buffer Full

0 Timer Channel 0 Output

AT-MIO/AI E Series User Manual 2-6

BSC, BSC Alternate
Cluster (primary)
PC Network, PC Network Alternate
WD EtherCard+ – default
3Com EtherLink – default



National Instruments Corporation

Chapter 2 Installation and Configuration

Table 2-3. PC AT 16-bit DMA Channel Assignment Map

Channel

7

6 AT-MIO-16 series – default

5 AT-DIO-32F – default

4 Cascade for DMA Controller #1 (channels 0 through 3)

AT-MIO-16 series – default

AT-DIO-32F – default

Device

Note: EISA computers also have channels 0–3 available as 16-bit DMA

channels.



National Instruments Corporation 2-7 AT-MIO/AI E Series User Manual

Chapter

Hardware Overview

This chapter presents an overview of the hardware functions on your
AT E Series board.

Figure 3-1 shows the block diagram for the AT-MIO-16E-1 and
AT-MIO-16E-2

Dither

Circuitry

Calibration

DACs

+

NI-PGIA
Gain
Amplifier
–

3

Trigger

Counter/

Timing I/O

Digital I/O

Voltage

REF

(8)

Analog
Muxes

(8)

Calibration

Mux

DACs

2

Trigger

PFI / Trigger

Timing

Digital I/O (8)

Trigger Level

I/O Connector

Mux Mode
Selection
Switches

Analog
Trigger

Circuitry

Sampling
Converter

Configuration

Memory

Analog Input

Timing/Control

DAQ - STC

Analog Output
Timing/Control

AO Control

12-Bit

A/D

AI Control

DMA/
Interrupt
Request

Bus

Interface

RTSI Bus

Interface

ADC
FIFO

Data (16)

IRQ
DMA

Analog

Input

Control

DAQ-STC

Bus

Interface

Analog
Output
Control

Transceivers

EEPROM

EEPROM

Control

DAQ-PnP

8255

DIO

Control

Data

3

DMA

Interface

Plug

and

Play

Bus

Interface

8

3

AT – I/O Channel

DAC0

DAC1

6

DAC

FIFO

Calibration

DACs

Data (16)

RTSI Bus

Figure 3-1. AT-MIO-16E-1 and AT-MIO-16E-2 Block Diagram



National Instruments Corporation 3-1 AT-MIO/AI E Series User Manual

Chapter 3 Hardware Overview

Figure 3-2 shows the block diagram for the AT-MIO-64E-3.

Voltage

REF

(32)

Analog
Muxes

(32)

Calibration

Mux

DACs

2

Trigger

PFI / Trigger

Timing

Digital I/O (8)

DAC0

DAC1

Trigger Level

I/O Connector

Mux Mode
Selection
Switches

Analog
Trigger

Circuitry

6

Dither

Circuitry

Calibration

DACs

+

NI-PGIA
Gain
Amplifier
–

DAC
FIFO

Calibration

DACs

3

12-Bit

Trigger

Counter/

Timing I/O

Digital I/O

Sampling
Converter

Configuration

Memory

Analog Input

Timing/Control

DAQ - STC

Analog Output
Timing/Control

AO Control

Data (16)

A/D

AI Control

DMA/
Interrupt
Request

Bus

Interface

RTSI Bus

Interface

ADC
FIFO

RTSI Bus

Figure 3-2. AT-MIO-64E-3 Block Diagram

Data (16)

IRQ
DMA

Analog

Input

Control

DAQ-STC

Bus

Interface

Analog
Output
Control

Data

Transceivers

EEPROM

EEPROM

Control

DAQ-PnP

8255

DIO

Control

DMA

Interface

Plug
and
Play

Bus

Interface

8

3

AT – I/O Channel

AT-MIO/AI E Series User Manual 3-2



National Instruments Corporation

Chapter 3 Hardware Overview

Figure 3-3 shows the block diagram for the AT-MIO-16E-10 and
AT-MIO-16DE-10.

Voltage

REF

(8)

Analog
Muxes

(8)

Calibration

Mux

PFI / Trigger

PA (8)
PB (8)
PC (8)

Timing

Digital I/O (8)

8255

DIO
Port

DAC0

DAC1

I/O Connector

Mux Mode
Selection
Switches

Dither

Circuitry

AT-MIO-16DE-10 ONLY

Data (8)

6

Calibration

DACs

4

+

NI-PGIA
Gain
Amplifier
–

Calibration

DACs

Trigger

Counter/

Timing I/O

Digital I/O

Sampling

Converter

Configuration

Memory

Analog Input

Timing/Control

DAQ - STC

Analog Output

Timing/Control

AO Control

Data (16)

12-Bit

A/D

ADC
FIFO

AI Control

DMA/
Interrupt
Request

Bus

Interface

RTSI Bus

Interface

RTSI Bus

Data (16)

IRQ
DMA

Analog

Input

Control

DAQ-STC

Bus

Interface

Analog
Output
Control

Data

Transceivers

EEPROM

EEPROM

Control

DAQ-PnP

8255

DIO

Control

DMA

Interface

Plug

and

Play

Bus

Interface

Figure 3-3. AT-MIO-16E-10 and AT-MIO-16DE-10 Block Diagram

8

3

AT – I/O Channel

The primary differences between the AT-MIO-16E-10 and the
AT-MIO-16DE-10 are in the 8255 DIO port, which is not present on the
AT-MIO-16E-10, and the I/O connector.



National Instruments Corporation 3-3 AT-MIO/AI E Series User Manual

Chapter 3 Hardware Overview

Voltage

REF

(8)

Analog
Muxes

(8)

Calibration

Trigger Level

DACs

Trigger

PFI / Trigger

Timing

I/O Connector

Digital I/O (8)

Figure 3-4 shows a block diagram for the AT-MIO-16XE-10.

REF

Calibration

DACs

3

Mux Mode
Selection
Switches

Mux

2

Analog
Trigger
Circuitry

+

Programmable
Gain
Amplifier
–

Trigger

Counter/

Timing I/O

Digital I/O

2

Sampling
Converter

Configuration

Memory

Analog Input

Timing/Control

DAQ - STC

Analog Output

Timing/Control

AO Control

Buffer

16-Bit

AI Control

DMA/
Interrupt
Request

Bus

Interface

RTSI Bus

Interface

ADC

FIFO

Data (16)

IRQ

DMA

A/D

Analog

Input

Control

DAQ-STC

Bus

Interface

Analog
Output

Control

Transceivers

EEPROM

EEPROM

Control

DAQ-PnP

8255

DIO

Control

Data

DMA

Interface

Plug

and
Play

Bus

Interface

8

7

AT – I/O Channel

DAC0

DAC1

DAC

FIFO

Calibration

4

DACs

Data (16)

RTSI Bus

Figure 3-4. AT-MIO-16XE-10 Block Diagram

AT-MIO/AI E Series User Manual 3-4



National Instruments Corporation

Voltage

REF

(8)

Analog
Muxes

(8)

Calibration

Mux

Trigger Level

DACs

2

Trigger

PFI / Trigger

Timing

I/O Connector

Digital I/O (8)

Chapter 3 Hardware Overview

Figure 3-5 shows a block diagram for the AT-AI-16XE-10.

REF

2

Sampling
Converter

Configuration

Memory

Analog Input

Timing/Control

DAQ - STC

Analog Output

Timing/Control

Buffer

16-Bit

AI Control

DMA/
Interrupt
Request

Bus

Interface

RTSI Bus

Interface

ADC

FIFO

Data (16)

IRQ

DMA

A/D

Analog

Input

Control

DAQ-STC

Bus

Interface

Analog
Output

Control

Data (16)

Transceivers

EEPROM

EEPROM

Control

DAQ-PnP

8255

DIO

Control

Data

DMA

Interface

Plug

and
Play

Bus

Interface

Mux Mode
Selection
Switches

Analog
Trigger
Circuitry

Calibration

DACs

+

Programmable
Gain
Amplifier
–

3

Trigger

Counter/

Timing I/O

Digital I/O

8

7

AT – I/O Channel

RTSI Bus

Figure 3-5. AT-AI-16XE-10 Block Diagram



National Instruments Corporation 3-5 AT-MIO/AI E Series User Manual

Chapter 3 Hardware Overview

Figure 3-6 shows a block diagram for the AT-MIO-16XE-50.

Voltage

REF

(8)

Analog
Muxes

(8)

Calibration

Mux

PFI / Trigger

Timing

I/O Connector

Digital I/O (8)

DAC0

DAC1

Mux Mode
Selection
Switches

4

Calibration

DACs

+

Programmable
Gain
Amplifier
–

Calibration

DACs

3

Trigger

Counter/

Timing I/O

Digital I/O

Sampling
Converter

Configuration

Memory

Analog Input

Timing/Control

DAQ - STC

Analog Output
Timing/Control

AO Control

Data (16)

16-Bit

A/D

2

ADC
FIFO

AI Control

DMA/
Interrupt
Request

Bus

Interface

RTSI Bus

Interface

RTSI Bus

Figure 3-6. AT-MIO-16XE-50 Block Diagram

Data (16)

IRQ
DMA

Analog

Input

Control

DAQ-STC

Bus

Interface

Analog
Output
Control

Transceivers

EEPROM

EEPROM

Control

DAQ-PnP

8255

DIO

Control

Data

DMA

Interface

Plug

and

Play

Bus

Interface

8

3

AT – I/O Channel

Analog Input

The analog input section of each AT E Series board is software
configurable. You can select different analog input configurations
through application software designed to control the AT E Series
boards. The following sections describe in detail each of the analog
input categories.

Input Mode

The AT E Series boards have three different input modes—
nonreferenced single-ended (NRSE) input, referenced single-ended
(RSE) input, and differential (DIFF) input. The single-ended input
configurations use up to 16 channels (64 channels on the
AT-MIO-64E-3). The DIFF input configuration uses up to eight
channels (32 channels on the AT-MIO-64E-3). Input modes are

AT-MIO/AI E Series User Manual 3-6



National Instruments Corporation

Chapter 3 Hardware Overview

programmed on a per channel basis for multimode scanning. For
example, you can configure the circuitry to scan 12 channels—four
differentially configured channels and eight single-ended channels.
Table 3-1 describes the three input configurations.

Table 3-1. Available Input Configurations for the AT E Series

Configuration

DIFF

A channel configured in DIFF mode uses two analog

Description

channel input lines. One line connects to the positive
input of the board programmable gain
instrumentation amplifier (PGIA), and the other
connects to the negative input of the PGIA.

RSE A channel configured in RSE mode uses one analog

channel input line, which connects to the positive
input of the PGIA. The negative input of the PGIA
is internally tied to analog input ground (AIGND).

NRSE A channel configured in NRSE mode uses one

analog channel input line, which connects to the
positive input of the PGIA. The negative input of the
PGIA connects to the analog input sense (AISENSE)
input.

For more information about the three types of input configuration, refer
to the Analog Input Signal Connections section in Chapter 4, Signal
Connections, which contains diagrams showing the signal paths for the
three configurations.

Input Polarity and Input Range

♦ AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-64E-3,

AT-MIO-16E-10, and AT-MIO-16DE-10
These boards have two input polarities—unipolar and bipolar.

Unipolar input means that the input voltage range is between 0 and
V

, where V

ref

means that the input voltage range is between -V
+V

/2. The AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-64E-3,

ref

AT-MIO-16E-10, and AT-MIO-16DE-10 have a unipolar input
range of 10 V (0 to 10 V) and a bipolar input range of 10 V (±5 V).



National Instruments Corporation 3-7 AT-MIO/AI E Series User Manual

is a positive reference voltage. Bipolar input

ref

ref

/2

and

Chapter 3 Hardware Overview

You can program polarity and range settings on a per channel basis
so that you can configure each input channel uniquely.

The software-programmable gain on these boards increases their
overall flexibility by matching the input signal ranges to those that
the ADC can accommodate. The AT-MIO-16E-1, AT-MIO-16E-2,
AT-MIO-64E-3, AT-MIO-16E-10, and AT-MIO-16DE-10 have
gains of 0.5, 1, 2, 5, 10, 20, 50, and 100 and are suited for a wide
variety of signal levels. With the proper gain setting, you can use
the full resolution of the ADC to measure the input signal.
Table 3-2 shows the overall input range and precision according to
the input range configuration and gain used.

Table 3-2. Actual Range and Measurement Precision

Range

Gain Actual Input Range Precision

Configuration

0 to +10 V

1.0

2.0

5.0

10.0

20.0

50.0

100.0

-5 to +5 V 0.5

1.0

2.0

5.0

10.0

20.0

50.0

100.0

1

The value of 1 LSB of the 12-bit ADC; that is, the voltage

0 to +10 V

0 to +5 V
0 to +2 V

0 to +1 V
0 to +500 mV
0 to +200 mV
0 to +100 mV

-10 to +10 V

-5 to +5 V

-2.5 to +2.5 V

-1 to +1 V

-500 to +500 mV

-250 to +250 mV

-100 to +100 mV

-50 to +50 mV

2.44 mV

1.22 mV

488.28 µV

244.14 µV

122.07 µV

48.83 µV

24.41 µV

4.88 mV

2.44 mV

1.22 mV

488.28 µV

244.14 µV

122.07 µV

48.83 µV

24.41 µV

increment corresponding to a change of one count in the ADC
12-bit count.

Note: See Appendix A, Specifications, for absolute maximum

ratings.

1

AT-MIO/AI E Series User Manual 3-8

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National Instruments Corporation

Chapter 3 Hardware Overview

♦ AT-MIO-16XE-10, AT-AI-16XE-10, AT-MIO-16XE-50

These boards have two input polarities—unipolar and bipolar.
Unipolar input means that the input voltage range is between 0 and
V

, where V

ref

means that the input voltage range is between -V

is a positive reference voltage. Bipolar input

ref

ref

and +V
AT-MIO-16XE-10, AT-AI-16XE-10, and AT-MIO-16XE-50 have
a unipolar input range of 10 V (0 to 10 V) and a bipolar input range
of 20 V (±10 V). You can program polarity and range settings on
a per channel basis so that you can configure each input channel
uniquely.

Note: You can calibrate your AT-MIO-16XE-10, AT-AI-16XE-10, and

AT-MIO-16XE-50 analog input circuitry for either a unipolar or bipolar
polarity. If you mix unipolar and bipolar channels in your scan list and you
are using NI-DAQ, then NI-DAQ will load the calibration constants
appropriate to the polarity for which analog input channel 0 is configured.

The software-programmable gain on these boards increases their
overall flexibility by matching the input signal ranges to those that
the ADC can accommodate. The AT-MIO-16XE-10 and
AT-AI-16XE-10 have gains of 1, 2, 5, 10, 20, 50, and 100 and the
AT-MIO-16XE-50 has gains of 1, 2, 10, and 100. These gains are
suited for a wide variety of signal levels. With the proper gain
setting, you can use the full resolution of the ADC to measure the
input signal. Table 3-3 shows the overall input range and precision
according to the input range configuration and gain used.

ref

. The



National Instruments Corporation 3-9 AT-MIO/AI E Series User Manual

Chapter 3 Hardware Overview

Table 3-3. Actual Range and Measurement Precision, AT-MIO-16XE-10,

Range

AT-AI-16XE-10, and AT-MIO-16XE-50

Gain Actual Input Range Precision

Configuration

0 to +10 V

1.0

2.0

5.0

10.0

20.0

50.0

2

2
2

100.0

-10 to +10 V 1.0

2.0

2

5.0

10.0

2

20.0

2

50.0

100.0

1

The value of 1 LSB of the 16-bit ADC; that is, the voltage

0 to +10 V

0 to +5 V
0 to +2 V

0 to +1 V
0 to +500 mV
0 to +200 mV

0 to 100 mV

-10 to +10 V

-5 to +5 V

-2 to +2 V

-1 to +1 V

-500 to +500 mV

-200 to +200 mV

-100 to +100 mV

152.59 µV

76.29 µV

30.52 µV

15.26 µV

7.63µV

3.05 µV

1.53 µV

305.18 µV

152.59 µV

61.04 µV

30.52 µV

15.26 µV

6.10 µV

3.05 µV

increment corresponding to a change of one count in the ADC
16-bit count.

2

AT-MIO-16XE-10 and AT-AI-16XE-10 only

1

Note: See Appendix A, Specifications, for absolute maximum

ratings.

Considerations for Selecting Input Ranges

Which input polarity and range you select depends on the expected
range of the incoming signal. A large input range can accommodate a
large signal variation but reduces the voltage resolution. Choosing a
smaller input range improves the voltage resolution but may result in
the input signal going out of range. For best results, you should match
the input range as closely as possible to the expected range of the input
signal. For example, if you are certain the input signal will not be
negative (below 0 V), unipolar input polarity is best. However, if the
signal is negative or equal to zero, inaccurate readings will occur if you
use unipolar input polarity.

AT-MIO/AI E Series User Manual 3-10

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National Instruments Corporation

Dither

Chapter 3 Hardware Overview

When you enable dither, you add approximately 0.5 LSB rms of white
Gaussian noise to the signal to be converted by the ADC. This addition
is useful for applications involving averaging to increase the resolution
of your AT E Series board, as in calibration or spectral analysis. In
such applications, noise modulation is decreased and differential
linearity is improved by the addition of the dither. When taking DC
measurements, such as when checking the board calibration, you should
enable dither and average about 1,000 points to take a single reading.
This process removes the effects of quantization and reduces
measurement noise, resulting in improved resolution. For high-speed
applications not involving averaging or spectral analysis, you may want
to disable the dither to reduce noise. You enable and disable the dither
circuitry through software.

Figure 3-7 illustrates the effect of dither on signal acquisition.
Figure 3-7a shows a small (±4 LSB) sine wave acquired with dither off.
The quantization of the ADC is clearly visible. Figure 3-7b shows what
happens when 50 such acquisitions are averaged together; quantization
is still plainly visible. In Figure 3-7c, the sine wave is acquired with
dither on. There is a considerable amount of noise visible. But
averaging about 50 such acquisitions, as shown in Figure 3-7d,
eliminates both the added noise and the effects of quantization. Dither
has the effect of forcing quantization noise to become a zero-mean
random variable rather than a deterministic function of the input signal.



National Instruments Corporation 3-11 AT-MIO/AI E Series User Manual

Chapter 3 Hardware Overview

LSBs

LSBs

6.0

6.0

4.0

4.0

2.0

2.0

0.0

0.0

-2.0

-2.0

-4.0

-4.0

-6.0

-6.0
100 200 300 4000 500

100 200 300 4000 500

a. Dither disabled; no averaging b. Dither disabled; average of 50 acquisitions

LSBs

LSBs

6.0

6.0

4.0

4.0

2.0

2.0

0.0

0.0

-2.0

-2.0

-4.0

-4.0

-6.0

-6.0
100 200 300 4000 500

100 200 300 4000 500

c. Dither enabled; no averaging

LSBs

LSBs

6.0

6.0

4.0

4.0

2.0

2.0

0.0

0.0

-2.0

-2.0

-4.0

-4.0

-6.0

-6.0

LSBs

LSBs

6.0

6.0

4.0

4.0

2.0

2.0

0.0

0.0

-2.0

-2.0

-4.0

-4.0

-6.0

-6.0

100 200 300 4000 500

100 200 300 4000 500

100 200 300 4000 500

100 200 300 4000 500

d. Dither enabled; average of 50 acquisitions

Figure 3-7. Dither

You cannot disable dither on the AT-MIO-16XE-10, AT-AI-16XE-10,
or AT-MIO-16XE-50. This is because the resolution of the ADC is so
fine that the ADC and the PGIA inherently produce almost 0.5 LSB rms
of noise. This is equivalent to having a dither circuit that is always
enabled.

Multiple-Channel Scanning Considerations

All of the AT E Series boards can scan multiple channels at the same
maximum rate as their single-channel rate; however, you should pay
careful attention to the settling times for each of the boards. The
settling time for most of the AT E Series boards is independent of the
selected gain, even at the maximum sampling rate. The settling time for
the high channel count and very high-speed boards is gain dependent,
which can affect the useful sampling rate for a given gain. No extra
settling time is necessary between channels as long as the gain is

AT-MIO/AI E Series User Manual 3-12

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National Instruments Corporation

Chapter 3 Hardware Overview

constant and source impedances are low. Refer to Appendix A,
Specifications, for a complete listing of settling times for each of the
AT E Series boards.

When scanning among channels at various gains, the settling times may
increase. When the PGIA switches to a higher gain, the signal on the
previous channel may be well outside the new, smaller range. For
instance, suppose a 4 V signal is connected to channel 0 and a 1 mV
signal is connected to channel 1, and suppose the PGIA is programmed
to apply a gain of one to channel 0 and a gain of 100 to channel 1. When
the multiplexer switches to channel 1 and the PGIA switches to a gain
of 100, the new full-scale range is 100 mV (if the ADC is in unipolar
mode).

The approximately 4 V step from 4 V to 1 mV is 4,000% of the new
full-scale range. For a 12-bit board to settle within 0.012% (120 ppm
or 1/2 LSB) of the 100 mV full-scale range on channel 1, the input
circuitry has to settle to within 0.0003% (3 ppm or 1/80 LSB) of the
4 V step. It may take as long as 100 µs for the circuitry to settle this
much. For a 16-bit board to settle within 0.0015% (15 ppm or 1 LSB)
of the 100 mV full-scale range on channel 1, the input circuitry has to
settle within 0.00004% (0.4 ppm or 1/400 LSB) of the 4 V step. It may
take as long as 200 µs for the circuitry to settle this much. In general,
this extra settling time is not needed when the PGIA is switching to a
lower gain.

Settling times can also increase when scanning high-impedance signals
due to a phenomenon called charge injection, where the analog input
multiplexer injects a small amount of charge into each signal source
when that source is selected. If the impedance of the source is not low
enough, the effect of the charge—a voltage error—will not have
decayed by the time the ADC samples the signal. For this reason, you
should keep source impedances under 1 kΩ to perform high-speed
scanning.

Due to problems with settling times, multiple-channel scanning is not
recommended unless sampling rates are low enough or it is necessary
to sample several signals as nearly simultaneously as possible. The data
is much more accurate and channel-to-channel independent if you
acquire data from each channel independently (for example, 100 points
from channel 0, then 100 points from channel 1, then 100 points from
channel 2, and so on).



National Instruments Corporation 3-13 AT-MIO/AI E Series User Manual

Chapter 3 Hardware Overview

Analog Output

♦ AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-64E-3,

AT-MIO-16E-10, AT-MIO-16DE-10
The AT E Series boards supply two channels of analog output

voltage at the I/O connector. You can select the reference and
range for the analog output circuitry through software. The
reference can be either internal or external, whereas the range can
be either bipolar or unipolar.

♦ AT-MIO-16XE-50

The AT-MIO-16XE-50 supplies two channels of analog output
voltage at the I/O connector. The range is fixed at bipolar ±10 V.

♦ AT-MIO-16XE-10

The AT-MIO-16XE-10 supplies two channels of analog output
voltage at the I/O connector. The range is software selectable
between unipolar (0 to 10 V) and bipolar (+

Analog Output Reference Selection

♦ AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-64E-3,

AT-MIO-16E-10, AT-MIO-16DE-10 only
You can connect each D/A converter (DAC) to the AT E Series

board internal reference of 10 V or to the external reference signal
connected to the external reference (EXTREF) pin on the I/O
connector. This signal applied to EXTREF should be between

-10 and +10 V. You do not need to configure both channels for the
same mode.

10 V).

Analog Output Polarity Selection

♦ AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-64E-3,

AT-MIO-16E-10, AT-MIO-16DE-10 only
You can configure each analog output channel for either unipolar

or bipolar output. A unipolar configuration has a range of 0 to V
at the analog output. A bipolar configuration has a range of -V
to +V
the DACs in the analog output circuitry and can be either the
+10 V onboard reference or an externally supplied reference
between -10 and +10 V. You do not need to configure both
channels for the same range.

AT-MIO/AI E Series User Manual 3-14

at the analog output. V

ref

is the voltage reference used by

ref



National Instruments Corporation

ref
ref

Selecting a bipolar range for a particular DAC means that any data
written to that DAC will be interpreted as two’s complement
format. In two’s complement mode, data values written to the
analog output channel can be either positive or negative. If you
select unipolar range, data is interpreted in straight binary format.
In straight binary mode, data values written to the analog output
channel range must be positive.

♦ AT-MIO-16XE-10

You can configure each analog output channel for either unipolar
or bipolar output. A unipolar configuration has a range of 0 to 10 V
at the analog output. A bipolar configuration has a range of

-10 to +10 V at the analog output. You do not need to configure
both channels for the same range.

Analog Output Reglitch Selection

♦ AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 only

In normal operation, a DAC output will glitch whenever it is
updated with a new value. The glitch energy differs from code to
code and appears as distortion in the frequency spectrum. Each
analog output of the AT-MIO-16E-1, AT-MIO-16E-2, and
AT-MIO-64E-3 contains a reglitch circuit that generates uniform
glitch energy at every code rather than large glitches at the major
code transitions. This uniform glitch energy appears as a multiple
of the update rate in the frequency spectrum. Notice that this
reglitch circuit does not eliminate the glitches; it only makes them
more uniform in size. Reglitching is normally disabled at startup
and can be independently enabled for each channel through
software.

Chapter 3 Hardware Overview

Analog Trigger

♦ AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-64E-3,

AT-MIO-16XE-10, and AT-AI-16XE-10 only
In addition to supporting internal software triggering and external

digital triggering to initiate a data acquisition sequence, the
AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-64E-3,
AT-MIO-16XE-10, and AT-AI-16XE-10 also support analog
triggering. You can configure the analog trigger circuitry to accept
either a direct analog input from the PFI0/TRIG1 pin on the I/O
connector or a postgain signal from the output of the PGIA, as



National Instruments Corporation 3-15 AT-MIO/AI E Series User Manual

Chapter 3 Hardware Overview

Note: The PFI0/TRIG1 pin is a high-impedance input. Therefore, it is

susceptible to cross-talk from adjacent pins, which can result in false
triggering when the pin is left unconnected. To avoid false triggering, make
sure this pin is connected to a low-impedance signal source (less than
10 kΩ source impedance) if you plan to enable this input via software.

shown in Figure 3-8. The trigger-level range for the direct analog
channel is ±10 V in 78 mV steps for the AT-MIO-16E-1,
AT-MIO-16E-2, and AT-MIO-64E-3, and ±10 V in 4.9 mV steps
for the AT-MIO-16XE-10 and AT-AI-16XE-10. The range for the
post-PGIA trigger selection is simply the full-scale range of the
selected channel, and the resolution is that range divided by 256 for
the AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3, and
divided by 4,096 for the AT-MIO-16XE-10 and AT-AI-16XE-10.

Analog
Input
Channels

PFI0/TRIG1

+

PGIA

-

Mux

Figure 3-8. Analog Trigger Block Diagram

ADC

Analog
Trigger
Circuit

DAQ-STC

There are five analog triggering modes available, as shown in
Figures 3-9 through 3-13. You can set lowValue and highValue
independently in software.

In below-low-level analog triggering mode, the trigger is generated
when the signal value is less than lowValue. HighValue is unused.

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National Instruments Corporation

Chapter 3 Hardware Overview

lowValue

Trigger

Figure 3-9. Below-Low-Level Analog Triggering Mode

In above-high-level analog triggering mode, the trigger is
generated when the signal value is greater than highValue.
LowValue is unused.

highValue

Trigger

Figure 3-10. Above-High-Level Analog Triggering Mode

In inside-region analog triggering mode, the trigger is generated
when the signal value is between the lowValue and the highValue.

highValue

lowValue

Trigger

Figure 3-11. Inside-Region Analog Triggering Mode



National Instruments Corporation 3-17 AT-MIO/AI E Series User Manual

Chapter 3 Hardware Overview

In high-hysteresis analog triggering mode, the trigger is generated
when the signal value is greater than highValue, with the
hysteresis specified by lowValue.

highValue

lowValue

Trigger

Figure 3-12. High-Hysteresis Analog Triggering Mode

In low-hysteresis analog triggering mode, the trigger is generated
when the signal value is less than lowValue, with the hysteresis
specified by highValue.

highValue

lowValue

Trigger

Figure 3-13. Low-Hysteresis Analog Triggering Mode

The analog trigger circuit generates an internal digital trigger based
on the analog input signal and the user-defined trigger levels. This
digital trigger can be used by any of the timing sections of the
DAQ-STC, including the analog input, analog output, and
general-purpose counter/timer sections. For example, the analog
input section can be configured to acquire n scans after the analog
input signal crosses a specific threshold. As another example, the
analog output section can be configured to update its outputs
whenever the analog input signal crosses a specific threshold.

AT-MIO/AI E Series User Manual 3-18

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National Instruments Corporation

Digital I/O

The AT E Series boards contain eight lines of digital I/O for
general-purpose use. You can individually configure each line through
software for either input or output. The AT-MIO-16DE-10 has 24

additional DIO lines, configured as three 8-bit ports: PA<0..7>,
PB<0..7>, and PC<0..7>. You can configure each port for both input and
output in various combinations, with some handshaking capabilities. At

system startup and reset, the digital I/O ports are all high impedance.
The hardware up/down control for general-purpose counters 0 and 1 are

connected onboard to DIO6 and DIO7, respectively. Thus, you can use
DIO6 and DIO7 to control the general-purpose counters. The up/down
control signals are input only and do not affect the operation of the DIO
lines.

Timing Signal Routing

The DAQ-STC provides a very flexible interface for connecting timing
signals to other boards or external circuitry. Your AT E Series board
uses the RTSI bus for interconnecting timing signals between boards
and the Programmable Function Input (PFI) pins on the I/O connector
for connecting to external circuitry. These connections are designed to
enable the AT E Series board to both control and be controlled by other
boards and circuits.

Chapter 3 Hardware Overview

There are a total of 13 timing signals internal to the DAQ-STC that can
be controlled by an external source. These timing signals can also be
controlled by signals generated internally to the DAQ-STC, and these
selections are fully software configurable. For example, the signal
routing multiplexer for controlling the CONVERT* signal is shown in
Figure 3-14.



National Instruments Corporation 3-19 AT-MIO/AI E Series User Manual

Chapter 3 Hardware Overview

RTSI Trigger <0..6>

CONVERT*

PFI<0..9>

Sample Interval Counter TC

GPCTR0_OUT

Figure 3-14. CONVERT* Signal Routing

This figure shows that CONVERT* can be generated from a number of
sources, including the external signals RTSI<0..6> and PFI<0..9> and
the internal signals Sample Interval Counter TC and GPCTR0_OUT.

Many of these timing signals are also available as outputs on the RTSI
pins, as indicated in the RTSI Triggers section later in this chapter, and
on the PFI pins, as indicated in Chapter 4, Signal Connections.

Programmable Function Inputs

The 10 PFIs are connected to the signal routing multiplexer for each
timing signal, and software can select one of the PFIs as the external
source for a given timing signal. It is important to note that any of the
PFIs can be used as an input by any of the timing signals and that
multiple timing signals can use the same PFI simultaneously. This
flexible routing scheme reduces the need to change physical
connections to the I/O connector for different applications.

AT-MIO/AI E Series User Manual 3-20

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National Instruments Corporation

You can also individually enable each of the PFI pins to output a
specific internal timing signal. For example, if you need the UPDATE*
signal as an output on the I/O connector, software can turn on the output
driver for the PFI5/UPDATE* pin.

Board and RTSI Clocks

Many functions performed by the AT E Series boards require a
frequency timebase to generate the necessary timing signals for
controlling A/D conversions, DAC updates, or general-purpose signals
at the I/O connector.

An AT E Series board can use either its internal 20 MHz timebase or a
timebase received over the RTSI bus. In addition, if you configure the
board to use the internal timebase, you can also program the board to
drive its internal timebase over the RTSI bus to another board that is
programmed to receive this timebase signal. This clock source, whether
local or from the RTSI bus, is used directly by the board as the primary
frequency source. The default configuration at startup is to use the
internal timebase without driving the RTSI bus timebase signal. You
select this timebase through software.

Chapter 3 Hardware Overview

RTSI Triggers

The seven RTSI trigger lines on the RTSI bus provide a very flexible
interconnection scheme for any AT E Series board sharing the RTSI
bus. These bidirectional lines can drive any of eight timing signals onto
the RTSI bus and can receive any of these timing signals. This signal
connection scheme is shown in Figure 3-15.



National Instruments Corporation 3-21 AT-MIO/AI E Series User Manual

Chapter 3 Hardware Overview

Trigger

7

RTSI Bus Connector

Clock

RTSI Switch

switch

DAQ-STC
TRIG1
TRIG2
CONVERT*
UPDATE*
WFTRIG
GPCTR0_SOURCE
GPCTR0_GATE
GPCTR0_OUT
STARTSCAN
AIGATE
SISOURCE
UISOURCE
GPCTR1_SOURCE
GPCTR1_GATE
RTSI_OSC (20 MHz)

Figure 3-15. RTSI Bus Signal Connection

Refer to the Timing Connections section of Chapter 4 for a description
of the signals shown in Figure 3-15.

AT-MIO/AI E Series User Manual 3-22

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National Instruments Corporation

Chapter

Signal Connections

This chapter describes how to make input and output signal connections
to your AT E Series board via the board I/O connector.

The I/O connector for the AT-MIO-16E-1, AT-MIO-16E-2,
AT-MIO-16E-10, AT-MIO-16XE-10, AT-AI-16XE-10, and
AT-MIO-16XE-50 has 68 pins that you can connect to 68-pin
accessories with the SH6868 shielded cable or the R6868 ribbon cable.
With the SH6850 shielded cable or R6850 ribbon cable, you can
connect your board to 50-pin signal conditioning modules and terminal
blocks.

The I/O connector for the AT-MIO-64E-3 and AT-MIO-16DE-10 has
100 pins that you can connect to 100-pin accessories with the
SH100100 shielded cable. With the SH1006868 shielded cable you can
connect your board to 68-pin accessories, and with the R1005050
ribbon cable you can connect your board to 50-pin accessories.

I/O Connector

4

Figure 4-1 shows the pin assignments for the 68-pin I/O connector on
the AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-16E-10,
AT-MIO-16XE-10, AT-AI-16XE-10, and AT-MIO-16XE-50.
Figure 4-2 shows the pin assignments for the 100-pin I/O connector on
the AT-MIO-64E-3. Figure 4-3 shows the pin assignments for the
100-pin I/O connector on the AT-MIO-16DE-10 . Refer to
Appendix B, Optional Cable Connector Descriptions, for the pin
assignments for the 50-pin connectors. A signal description follows the
connector pinouts.

Warning: Connections that exceed any of the maximum ratings of input or output

signals on the AT E Series boards can damage the AT E Series board and
the PC. Maximum input ratings for each signal are given in Tables 4-1
through 4-4 in the Protection column. National Instruments is
for any damages resulting from such signal connections.



National Instruments Corporation 4-1 AT-MIO/AI E Series User Manual

NOT

liable

Chapter 4 Signal Connections

ACH8
ACH1

AIGND

ACH10

ACH3

AIGND

ACH4

AIGND

ACH13

ACH6

AIGND

ACH15

DAC0OUT

DAC1OUT

EXTREF

DIO4

DGND

DIO1

DIO6

DGND

+5 V
DGND
DGND

PFI0/TRIG1
PFI1/TRIG2

DGND

+5 V
DGND

PFI5/UPDATE*

PFI6/WFTRIG

DGND

PFI9/GPCTR0_GATE

GPCTR0_OUT

FREQ_OUT

1

Not available on AT-AI-16XE-10

2

Not available on AT-MIO-16XE-10,
AT-AI-16XE-10, or AT-MIO-16XE-50

1
1

2

34 68
33 67
32 66
31 65
30 64
29 63
28 62
27 61
26 60
25 59
24 58
23 57
22 56
21 55
20 54
19 53
18 52
17 51
16 50
15 49
14 48
13 47
12 46
11 45
10 44

943
842
741
640
539
438
337
236
135

ACH0
AIGND
ACH9
ACH2
AIGND
ACH11
AISENSE
ACH12
ACH5
AIGND
ACH14
ACH7
AIGND
AOGND
AOGND

2
2

DGND
DIO0

DIO5
DGND

DIO2
DIO7
DIO3
SCANCLK
EXTSTROBE*
DGND
PFI2/CONVERT*
PFI3/GPCTR1_SOURCE
PFI4/GPCTR1_GATE
GPCTR1_OUT
DGND
PFI7/STARTSCAN
PFI8/GPCTR0_SOURCE
DGND
DGND

Figure 4-1. I/O Connector Pin Assignment for the AT-MIO-16E-1, AT-MIO-16E-2,

AT-MIO-16E-10, AT-MIO-16XE-10, AT-AI-16XE-10, and AT-MIO-16XE-50

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National Instruments Corporation

Chapter 4 Signal Connections

AIGND ACH16
AIGND ACH24

ACH0 ACH17
ACH8 ACH25
ACH1 ACH18
ACH9 ACH26
ACH2 ACH19

ACH10 ACH27

ACH3 ACH20

ACH11 ACH28

ACH4 ACH21

ACH12 ACH29

ACH5 ACH22

ACH13 ACH30

ACH6 ACH23

ACH14 ACH31

ACH7 ACH32

ACH15 ACH40

AISENSE ACH33
DAC0OUT ACH41
DAC1OUT ACH34

EXTREF ACH42

AOGND ACH35

DGND ACH43

DGND ACH39

SCANCLK ACH56

EXTSTROBE* ACH49

PFI0/TRIG1 ACH57
PFI1/TRIG2 ACH50

PFI2/CONVERT* ACH58

PFI3/GPCTR1_SOURCE ACH51

PFI4/GPCTR1_GATE ACH59

GPCTR1_OUT ACH52
PFI5/UPDATE* ACH60

PFI6/WFTRIG ACH53

PFI7/STARTSCAN ACH61

PFI8/GPCTR0_SOURCE ACH54

PFI9/GPCTR0_GATE ACH62

GPCTR0_OUT ACH55

FREQ_OUT ACH63

151
252
353
454
555
656
757
858

959
10 60
11 61
12 62
13 63
14 64
15 65
16 66
17 67
18 68
19 69
20 70
21 71
22 72
23 73
24 74
25 75

DIO0 AISENSE2

26 76

DIO4 AIGND

27 77

DIO1 ACH36

28 78

DIO5 ACH44

29 79

DIO2 ACH37

30 80

DIO6 ACH45

31 81

DIO3 ACH38

32 82

DIO7 ACH46

33 83
34 84

+5 V ACH47

35 85

+5 V ACH48

36 86
37 87
38 88
39 89
40 90
41 91
42 92
43 93
44 94
45 95
46 96
47 97
48 98
49 99
50 100

Figure 4-2. I/O Connector Pin Assignment for the AT-MIO-64E-3



National Instruments Corporation 4-3 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

AIGND PC7
AIGND GND

ACH10 GND

ACH11 GND

ACH12 GND

ACH13 GND

ACH14 GND

ACH15 GND

AISENSE PB6
DAC0OUT GND
DAC1OUT PB5

EXTREF GND

AOGND PB4

DGND GND

DGND PA7

SCANCLK GND

EXTSTROBE* PA5

PFI0/TRIG1 GND
PFI1/TRIG2 PA4

PFI2/CONVERT* GND

PFI3/GPCTR1_SOURCE PA3

PFI4/GPCTR1_GATE GND

GPCTR1_OUT PA2
PFI5/UPDATE* GND

PFI6/WFTRIG PA1

PFI7/STARTSCAN GND

PFI8/GPCTR0_SOURCE PA0

PFI9/GPCTR0_GATE GND

GPCTR0_OUT +5 V

FREQ_OUT GND

151
252
353

ACH0 PC6

454

ACH8 GND

555

ACH1 PC5

656

ACH9 GND

757

ACH2 PC4

858
959

ACH3 PC3

10 60

11 61

ACH4 PC2

12 62
13 63

ACH5 PC1

14 64
15 65

ACH6 PC0

16 66
17 67

ACH7 PB7

18 68
19 69
20 70
21 71
22 72
23 73
24 74
25 75

DIO0 PB3

26 76

DIO4 GND

27 77

DIO1 PB2

28 78

DIO5 GND

29 79

DIO2 PB1

30 80

DIO6 GND

31 81

DIO3 PB0

32 82

DIO7 GND

33 83
34 84

+5 V GND

35 85

+5 V PA6

36 86
37 87
38 88
39 89
40 90
41 91
42 92
43 93
44 94
45 95
46 96
47 97
48 98
49 99
50 100

Figure 4-3. I/O Connector Pin Assignment for the AT-MIO-16DE-10

AT-MIO/AI E Series User Manual 4-4



National Instruments Corporation

I/O Connector Signal Descriptions

Chapter 4 Signal Connections

Signal Name

AIGND

ACH<0..15> AIGND Input Analog Input Channels 0 through 15—Each channel pair,

ACH<16..63> AIGND Input Analog Input Channels 16 through 63 (AT-MIO-64E-3

AISENSE AIGND Input Analog Input Sense—This pin serves as the reference node

AISENSE2 AIGND Input Analog Input Sense (AT-MIO-64E-3 only)—This pin

DAC0OUT AOGND Output Analog Channel 0 Output—This pin supplies the voltage

DAC1OUT AOGND Output Analog Channel 1 Output—This pin supplies the voltage

Reference Direction Description

— — Analog Input Ground—These pins are the reference point

for single-ended measurements and the bias current return
point for differential measurements. All three ground
references—AIGND, AOGND, and DGND—are connected
together on your AT E Series board.

ACH<i, i+8> (i = 0..7), can be configured as either one
differential input or two single-ended inputs.

only)—Each channel pair, ACH<i, i+8> (i = 16..23, 32..39,

48..55), can be configured as either one differential input or
two single-ended inputs.

for any of channels ACH <0..15> in NRSE configuration.

serves as the reference node for any of channels ACH
<16..63> in NRSE configuration.

output of analog output channel 0. This pin is not available
on the AT-AI-16XE-10.

output of analog output channel 1. This pin is not available
on the AT-AI-16XE-10.

EXTREF AOGND Input External Reference—This is the external reference input for

the analog output circuitry. This pin is not available on the
AT-MIO-16XE-10, AT-AI-16XE-10, or
AT-MIO-16XE-50.

AOGND — — Analog Output Ground—The analog output voltages are

referenced to this node. All three ground references—
AIGND, AOGND, and DGND—are connected together on
your AT E Series board.

DGND — — Digital Ground—This pin supplies the reference for the

digital signals at the I/O connector as well as the +5 VDC
supply. All three ground references—AIGND, AOGND,
and DGND—are connected together on your AT E Series
board.



National Instruments Corporation 4-5 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

Signal Name

DIO<0..7>

PA<0..7> DGND Input or

PB<0..7> DGND Input or

PC<0..7> DGND Input or

+5 V DGND Output +5 VDC Source—These pins are fused for up to 1 A of

SCANCLK DGND Output Scan Clock—This pin pulses once for each A/D conversion

EXTSTROBE* DGND Output External Strobe—This output can be toggled under software

PFI0/TRIG1 DGND Input

Reference Direction Description

DGND Input or

Output

Output

Output

Output

Output

Digital I/O signals—DIO6 and 7 can control the up/down
signal of general-purpose counters 0 and 1, respectively.

Port A—These pins are port A of the extra digital I/O signals
on the AT-MIO-16DE-10.

Port B—These pins are port B of the extra digital I/O signals
on the AT-MIO-16DE-10.

Port C—These pins are port C of the extra digital I/O signals
on the AT-MIO-16DE-10.

+5 V supply. The fuse is self-resetting.

in the scanning modes when enabled. The low-to-high edge
indicates when the input signal can be removed from the
input or switched to another signal.

control to latch signals or trigger events on external devices.

PFI0/Trigger 1—As an input, this is either one of the
Programmable Function Inputs (PFIs) or the source for the
hardware analog trigger. PFI signals are explained in the
Timing Connections section later in this chapter. The
hardware analog trigger is explained in the Analog Trigger
section in Chapter 2. Analog trigger is available only on the
AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-16XE-10,
AT-AI-16XE-10, and the AT-MIO-64E-3.

As an output, this is the TRIG1 signal. In posttrigger data
acquisition sequences, a low-to-high transition indicates the
initiation of the acquisition sequence. In pretrigger
applications, a low-to-high transition indicates the initiation
of the pretrigger conversions.

(Continued)

PFI1/TRIG2 DGND Input

Output

AT-MIO/AI E Series User Manual 4-6

PFI1/Trigger 2—As an input, this is one of the PFIs.

As an output, this is the TRIG2 signal. In pretrigger
applications, a low-to-high transition indicates the initiation
of the posttrigger conversions. TRIG2 is not used in
posttrigger applications.



National Instruments Corporation

Chapter 4 Signal Connections

Signal Name

PFI2/CONVERT*

PFI3/GPCTR1_SOURCE DGND Input

PFI4/GPCTR1_GATE DGND Input

GPCTR1_OUT DGND Output Counter 1 Output—This output is from the general-purpose

PFI5/UPDATE* DGND Input

Reference Direction Description

DGND Input

Output

Output

Output

Output

PFI2/Convert—As an input, this is one of the PFIs.

As an output, this is the CONVERT* signal. A high-to-low
edge on CONVERT* indicates that an A/D conversion is
occurring.

PFI3/Counter 1 Source—As an input, this is one of the
PFIs.

As an output, this is the GPCTR1_SOURCE signal. This
signal reflects the actual source connected to the
general-purpose counter 1.

PFI4/Counter 1 Gate—As an input, this is one of the PFIs.

As an output, this is the GPCTR1_GATE signal. This signal
reflects the actual gate signal connected to the
general-purpose counter 1.

counter 1 output.

PFI5/Update—As an input, this is one of the PFIs.

As an output, this is the UPDATE* signal. A high-to-low
edge on UPDATE* indicates that the analog output primary
group is being updated.

(Continued)

PFI6/WFTRIG DGND Input

Output

PFI7/STARTSCAN DGND Input

Output

PFI8/GPCTR0_SOURCE DGND Input

Output



National Instruments Corporation 4-7 AT-MIO/AI E Series User Manual

PFI6/Waveform Trigger—As an input, this is one of the
PFIs.

As an output, this is the WFTRIG signal. In timed analog
output sequences, a low-to-high transition indicates the
initiation of the waveform generation.

PFI7/Start of Scan—As an input, this is one of the PFIs.

As an output, this is the STARTSCAN signal. This pin
pulses once at the start of each analog input scan in the
interval scan. A low-to-high transition indicates the start of
the scan.

PFI8/Counter 0 Source—As an input, this is one of the
PFIs.

As an output, this is the GPCTR0_SOURCE signal. This
signal reflects the actual source connected to the
general-purpose counter 0.

Chapter 4 Signal Connections

Signal Name

PFI9/GPCTR0_GATE

GPCTR0_OUT DGND Output Counter 0 Output—This output is from the general-purpose

FREQ_OUT DGND Output Frequency Output—This output is from the frequency

Reference Direction Description

DGND Input

Output

PFI9/Counter 0 Gate—As an input, this is one of the PFIs.

As an output, this is the GPCTR0_GATE signal. This signal
reflects the actual gate signal connected to the
general-purpose counter 0.

counter 0 output.

generator output.

(Continued)

Table 4-1 shows the I/O signal summary for the AT-MIO-16E-1,
AT-MIO-16E-2 and AT-MIO-64E-3.

Table 4-1. I/O Signal Summary, AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3

Signal Name

ACH<0..63>

Drive Impedance

Input/

Output

AI 100 GΩ

in parallel
with
100 pF

Protection

(Volts)
On/Off

25/15 — — —

Source

(mA at V)

Sink

(mA at

V)

Rise

Time

(ns)

Bias

±200 pA

AISENSE, AISENSE2 AI 100 GΩ

in parallel
with
100 pF

AIGND AO — — — — — —

DAC0OUT AO 0.1 Ω

DAC1OUT AO 0.1 Ω

EXTREF AI 10 kΩ

AOGND AO — — — — — —

DGND DO — — — — — —

VCC DO 0.1Ω

AT-MIO/AI E Series User Manual 4-8

25/15 — — —

Short-circuit
to ground

Short-circuit
to ground

25/15

Short-circuit
to ground

5 at 10 5 at -10 20

5 at 10 5 at -10 20

— — — —

1A — — —



National Instruments Corporation

V/µs

V/µs

±200 pA

—

—

Chapter 4 Signal Connections

Table 4-1. I/O Signal Summary, AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 (Continued)

Signal Name

DIO<0..7>

Drive Impedance

Input/

Output

Protection

(Volts)
On/Off

Source

(mA at V)

(mA at

DIO — Vcc +0.5 13 at (Vcc -0.4) 24 at

Sink

V)

Rise

Bias

Time

(ns)

1.1 50 kΩ pu

0.4

SCANCLK

DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

EXTSTROBE* DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI0/TRIG1 ADIO 10 kΩ

PFI1/TRIG2

DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI2/CONVERT* DIO — V

Vcc +0.5/±35

+0.5

cc

3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI3/GPCTR1_SOURCE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI4/GPCTR1_GATE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

GPCTR1_OUT DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI5/UPDATE* DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI6/WFTRIG DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI7/STARTSCAN DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

1

2

PFI8/GPCTR0_SOURCE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI9/GPCTR0_GATE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

GPCTR0_OUT DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

FREQ_OUT DO — — 3.5 at (Vcc-0.4) 5 at 0.4 1.5 50 kΩ pu

1

DIO <6..7> are also pulled down with a 50 kΩ resistor.

AI = Analog Input DIO = Digital Input/Output pu = pullup
AO = Analog Output DO = Digital Output ADIO = Analog/Digital Input/Output

2

Also pulled down with a 10 kΩ resistor.

Note: The tolerance on the 50 kΩ pullup and pulldown resistors is very large. Actual value may range between

17 kΩ and 100 kΩ.



National Instruments Corporation 4-9 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

Table 4-2. I/O Signal Summary, AT-MIO-16E-10 and AT-MIO-16DE-10

Table 4-2 shows the I/O signal summary for the AT-MIO-16E-10 and
AT-MIO-16DE-10.

Signal Name

ACH<0..15>

AISENSE AI 100 GΩ in

AIGND AO — — — — — —

DAC0OUT AO 0.1 Ω

DAC1OUT AO 0.1 Ω

EXTREF AI 10 kΩ

AOGND AO — — — — — —

DGND DO — — — — — —

VCC DO 0.1 Ω

DIO<0..7> DIO — V

Drive Impedance

Input/

Output

AI 100 GΩ in

parallel
with 50 pF

parallel
with 50 pF

Protection

(Volts)

On/Off

35/25 — — —

35/25 — — —

Short-circuit
to ground

Short-circuit
to ground

35/25

Short-circuit
to ground

+0.5 13 at (Vcc -0.4) 24 at 0.4 1.1 50 kΩ pu

cc

Source

(mA at V)

5 at 10 5 at -10 15

5 at 10 5 at -10 15

— — — —

1A — — —

Sink

(mA at V)

Rise

Time

(ns)

V/µs

V/µs

±200 pA

±200 pA

—

—

Bias

1

PA<0..7>

PB<0..7> DIO — V

PC<0..7> DIO — V

SCANCLK DO — — 3.5 at (V

EXTSTROBE* DO — — 3.5 at (V

PFI0/TRIG1 DIO — V

PFI1/TRIG2 DIO — V

PFI2/CONVERT* DIO — V

DIO — V

+0.5 2.5 at 3.9 2.5 at 0.4 5 100 kΩ pu

cc

+0.5 2.5 at 3.9 2.5 at 0.4 5 100 kΩ pu

cc

+0.5 2.5 at 3.9 2.5 at 0.4 5 100 kΩ pu

cc

+0.5 3.5 at (V

cc

+0.5 3.5 at (V

cc

+0.5 3.5 at (V

cc

AT-MIO/AI E Series User Manual 4-10

-0.4) 5 at 0.4 1.5 50 kΩ pu

cc

-0.4) 5 at 0.4 1.5 50 kΩ pu

cc

-0.4) 5 at 0.4 1.5 50 kΩ pu

cc

-0.4) 5 at 0.4 1.5 50 kΩ pu

cc

-0.4) 5 at 0.4 1.5 50 kΩ pu

cc



National Instruments Corporation

Chapter 4 Signal Connections

Table 4-2. I/O Signal Summary, AT-MIO-16E-10 and AT-MIO-16DE-10 (Continued)

Signal Name

PFI3/GPCTR1_SOURCE

PFI4/GPCTR1_GATE DIO — Vcc +0.5 3.5 at (V

GPCTR1_OUT DO — — 3.5 at (V

PFI5/UPDATE* DIO — V

PFI6/WFTRIG DIO — V

PFI7/STARTSCAN DIO — V

PFI8/GPCTR0_SOURCE DIO — V

PFI9/GPCTR0_GATE DIO — V

GPCTR0_OUT DO — — 3.5 at (V

FREQ_OUT DO — — 3.5 at (V

1

DIO <6..7> are also pulled down with a 50 kΩ resistor.

Drive Impedance

Input/

Output

DIO — V

Protection

(Volts)

On/Off

+0.5 3.5 at (V

cc

+0.5 3.5 at (V

cc

+0.5 3.5 at (V

cc

+0.5 3.5 at (V

cc

+0.5 3.5 at (V

cc

+0.5 3.5 at (V

cc

Source

(mA at V)

-0.4) 5 at 0.4 1.5 50 kΩ pu

cc

-0.4) 5 at 0.4 1.5 50 kΩ pu

cc

-0.4) 5 at 0.4 1.5 50 kΩ pu

cc

-0.4) 5 at 0.4 1.5 50 kΩ pu

cc

-0.4) 5 at 0.4 1.5 50 kΩ pu

cc

-0.4) 5 at 0.4 1.5 50 kΩ pu

cc

-0.4) 5 at 0.4 1.5 50 kΩ pu

cc

0.4) 5 at 0.4 1.5 50 kΩ pu

cc-

-0.4) 5 at 0.4 1.5 50 kΩ pu

cc

-0.4) 5 at 0.4 1.5 50 kΩ pu

cc

Sink

(mA at V)

Time

Rise

(ns)

Bias

AI = Analog Input DIO = Digital Input/Output pu = pullup
AO = Analog Output DO = Digital Output

Note: The tolerance on the 50 kΩ pullup and pulldown resistors is very large. Actual value may range between

17 kΩ and 100 kΩ.



National Instruments Corporation 4-11 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

Table 4-3. I/O Signal Summary, AT-MIO-16XE-10 and AT-AI-16XE-10

Table 4-3 shows the I/O signal summary for the AT-MIO-16XE-10 and
AT-AI-16XE-10.

Signal Name

ACH<0..15>

AISENSE AI 100 GΩ in

AIGND AO — — — — — —

DAC0OUT AO 0.1 Ω Short-circuit

DAC1OUT AO 0.1 Ω Short-circuit

AOGND AO — — — — — —

DGND DO — — — — — —

VCC DO 0.1 Ω Short-circuit

Drive Impedance

Input/

Output

AI 100 GΩ in

parallel
with
100 pF

parallel
with
100 pF

Protection

(Volts)
On/Off

25/15 — — — ±1 nA

25/15 — — — ±1 nA

to ground

to ground

to ground

Source

(mA at V)

5 at 10 5 at -10 5

5 at 10 5 at -10 5

1A — — —

Sink

(mA at

V)

Rise

Time

(ns)

V/µs

V/µs

—

—

Bias

DIO<0..7> DIO — Vcc +0.5 13 at (Vcc -0.4) 24 at 0.4 1.1 50 kΩ pu

SCANCLK DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

EXTSTROBE* DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI0/TRIG1 DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 4.75 kΩ pu

PFI1/TRIG2 DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI2/CONVERT* DIO — V

PFI3/GPCTR1_SOURCE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI4/GPCTR1_GATE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

GPCTR1_OUT DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

AT-MIO/AI E Series User Manual 4-12

+0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

cc



National Instruments Corporation

Chapter 4 Signal Connections

Table 4-3. I/O Signal Summary, AT-MIO-16XE-10 and AT-AI-16XE-10 (Continued)

Signal Name Drive Impedance

Input/

Output

PFI5/UPDATE* DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI6/WFTRIG DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI7/STARTSCAN DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI8/GPCTR0_SOURCE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI9/GPCTR0_GATE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

GPCTR0_OUT DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

FREQ_OUT DO — — 3.5 at (Vcc-0.4) 5 at 0.4 1.5 50 kΩ pu

AI = Analog Input DIO = Digital Input/Output pu = pullup
AO = Analog Output DO = Digital Output

Note: The tolerance on the 50 kΩ pullup and pulldown resistors is very large. Actual value may range between

17 kΩ and 100 kΩ.

Protection

(Volts)
On/Off

Source

(mA at V)

Sink

(mA at

V)

Rise

Time

(ns)

Bias



National Instruments Corporation 4-13 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

Table 4-4 shows the I/O signal summary for the AT-MIO-16XE-50.

Table 4-4. I/O Signal Summary, AT-MIO-16XE-50

Signal Name Drive Impedance

Input/

Output

ACH<0..15> AI 20 GΩ in

parallel
with
100 pF

AISENSE AI 20 GΩ in

parallel
with
100 pF

AIGND AO — — — — — —

DAC0OUT AO 0.1 Ω Short-circuit

DAC1OUT AO 0.1 Ω Short-circuit

AOGND AO — — — — — —

DGND DO — — — — — —

VCC DO 0.1 Ω Short-circuit

DIO<0..7> DIO — Vcc +0.5 13 at (Vcc -0.4) 24 at 0.4 1.1 50 kΩ pu

Protection

(Volts)
On/Off

25/15 — — — ±3 nA

25/15 — — — ±3 nA

to ground

to ground

to ground

Source

(mA at V)

5 at 10 5 at -10 2

5 at 10 5 at -10 2

1A — — —

Sink

(mA at

V)

Rise

Time

(ns)

V/µs

V/µs

Bias

—

—

1

SCANCLK DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

EXTSTROBE* DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI0/TRIG1 DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI1/TRIG2 DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI2/CONVERT* DIO — V

PFI3/GPCTR1_SOURCE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI4/GPCTR1_GATE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

GPCTR1_OUT DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

AT-MIO/AI E Series User Manual 4-14

+0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

cc



National Instruments Corporation

Chapter 4 Signal Connections

Table 4-4. I/O Signal Summary, AT-MIO-16XE-50 (Continued)

Signal Name Drive Impedance

Input/

Output

Protection

(Volts)
On/Off

Source

(mA at V)

Sink

(mA at

V)

Rise

Time

(ns)

Bias

PFI5/UPDATE* DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI6/WFTRIG DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI7/STARTSCAN DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI8/GPCTR0_SOURCE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI9/GPCTR0_GATE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

GPCTR0_OUT DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

FREQ_OUT DO — — 3.5 at (Vcc-0.4) 5 at 0.4 1.5 50 kΩ pu

1

DIO <6..7> are also pulled down with a 50 kΩ resistor.

AI = Analog Input DIO = Digital Input/Output pu = pullup
AO = Analog Output DO = Digital Output

Note: The tolerance on the 50 kΩ pullup and pulldown resistors is very large. Actual value may range between

17 kΩ and 100 kΩ.



National Instruments Corporation 4-15 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

Analog Input Signal Connections

♦ AT-MIO-16E-1, ΑΤ-MIO-16E-2, AT-MIO-16E-10,

AT-MIO-16DE-10, AT-MIO-16XE-10, AT-AI-16XE-10,
AT-MIO-16XE-50

The analog input signals are ACH<0..15>, AISENSE, and AIGND.
The ACH<0..15> signals are tied to the 16 analog input channels of
your AT E Series board. In single-ended mode, signals connected
to ACH<0..15> are routed to the positive input of the board PGIA.
In differential mode, signals connected to ACH<0..7> are routed to
the positive input of the PGIA, and signals connected to
ACH<8..15> are routed to the negative input of the PGIA.

♦ΑΤ-MIO-64E-3

The analog input signals are ACH<0..63>, AISENSE, AISENSE2,
and AIGND. The ACH<0..63> signals are tied to the 64 analog
input channels of the AT-MIO-64E-3. In single-ended mode,
signals connected to ACH<0..63> are routed to the positive input
of the AT-MIO-64E-3 PGIA. In differential mode, signals
connected to ACH<0..7, 16..23, 32..39, 48..55> are routed to the
positive input of the PGIA, and signals connected to ACH<8..15,

24..31, 40..47, 56..63> are routed to the negative input of the PGIA.

Warning: Exceeding the differential and common-mode input ranges distorts your

input signals. Exceeding the maximum input voltage rating can damage
the AT E Series board and the PC. National Instruments is
any damages resulting from such signal connections. The maximum input
voltage ratings are listed in Tables 4-1 through 4-4 in the Protection
column.

In NRSE mode, the AISENSE and AISENSE2 signals are connected
internally to the negative input of the AT E Series board PGIA when
their corresponding channels are selected. In DIFF and RSE modes,
these signals are left unconnected.

AIGND is an analog input common signal that is routed directly to the
ground tie point on the AT E Series boards. You can use this signal for
a general analog ground tie point to your AT E Series board if
necessary.

Connection of analog input signals to your AT E Series board depends
on the configuration of the analog input channels you are using and the
type of input signal source. With the different configurations, you can

AT-MIO/AI E Series User Manual 4-16

NOT

liable for



National Instruments Corporation

Chapter 4 Signal Connections

use the PGIA in different ways. Figure 4-4 shows a diagram of your
AT E Series board PGIA.

Instrumentation

Amplifier

V

in+

+

PGIA

V

in-

-

+

V

m

Measured

Voltage

-

Vm = [V

Figure 4-4. AT E Series PGIA

The PGIA applies gain and common-mode voltage rejection and
presents high input impedance to the analog input signals connected to
your AT E Series board. Signals are routed to the positive and negative
inputs of the PGIA through input multiplexers on the board. The PGIA
converts two input signals to a signal that is the difference between the
two input signals multiplied by the gain setting of the amplifier. The
amplifier output voltage is referenced to the ground for the board. Your
AT E Series board A/D converter (ADC) measures this output voltage
when it performs A/D conversions.

in+

- V

]* Gain

in-

You must reference all signals to ground either at the source device or
at the board. If you have a floating source, you should reference the
signal to ground by using the RSE input mode or the DIFF input
configuration with bias resistors (see the Differential Connections for
Nonreferenced or Floating Signal Sources section later in this chapter).
If you have a grounded source, you should not reference the signal to
AIGND. You can avoid this reference by using DIFF or NRSE input
configurations.



National Instruments Corporation 4-17 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

Types of Signal Sources

When configuring the input channels and making signal connections,
you must first determine whether the signal sources are floating or
ground-referenced. The following sections describe these two types of
signals.

Floating Signal Sources

A floating signal source is one that is not connected in any way to the
building ground system but, rather, has an isolated ground-reference
point. Some examples of floating signal sources are outputs of
transformers, thermocouples, battery-powered devices, optical isolator
outputs, and isolation amplifiers. An instrument or device that has an
isolated output is a floating signal source. You must tie the ground
reference of a floating signal to your AT E Series board analog input
ground to establish a local or onboard reference for the signal.
Otherwise, the measured input signal varies as the source floats out of
the common-mode input range.

Ground-Referenced Signal Sources

A ground-referenced signal source is one that is connected in some way
to the building system ground and is, therefore, already connected to a
common ground point with respect to the AT E Series board, assuming
that the PC is plugged into the same power system. Nonisolated outputs
of instruments and devices that plug into the building power system fall
into this category.

The difference in ground potential between two instruments connected
to the same building power system is typically between 1 and 100 mV
but can be much higher if power distribution circuits are not properly
connected. If a grounded signal source is improperly measured, this
difference may appear as an error in the measurement. The connection
instructions for grounded signal sources are designed to eliminate this
ground potential difference from the measured signal.

Input Configurations

You can configure your AT E Series board for one of three input
modes—NRSE, RSE, or DIFF. The following sections discuss the use
of single-ended and differential measurements and considerations for
measuring both floating and ground-referenced signal sources.

AT-MIO/AI E Series User Manual 4-18

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National Instruments Corporation

Chapter 4 Signal Connections

Figure 4-5 summarizes the recommended input configuration for both
types of signal sources.

Signal Source Type

Input

Differential

(DIFF)

Single-Ended —

Ground

Referenced

(RSE)

Floating Signal Source

(Not Connected to Building Ground)

Examples

• Ungrounded Thermocouples

• Signal conditioning with isolated outputs

• Battery devices

+

V

1

-

ACH(+)

ACH (-)

R

+

-

AIGND

See text for information on bias resistors.

ACH

+

V

1

-

AIGND

+

-

Grounded Signal Source

Examples

• Plug-in instruments with
nonisolated outputs

+

V

1

-

NOT RECOMMENDED

+

V

1

-

+ Vg -

ACH(+)

ACH (-)

ACH

+

-

AIGND

+

-

Ground-loop losses, Vg, are added to
measured signal

Single-Ended —

Nonreferenced

(NRSE)

+

V

1

-

ACH

AISENSE

+

-

R

AIGND

+

V

1

-

ACH

AISENSE

+

-

AIGND

See text for information on bias resistors.

Figure 4-5. Summary of Analog Input Connections



National Instruments Corporation 4-19 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

Differential Connection Considerations (DIFF Input Configuration)

A differential connection is one in which the AT E Series board analog
input signal has its own reference signal or signal return path. These
connections are available when the selected channel is configured in
DIFF input mode. The input signal is tied to the positive input of the
PGIA, and its reference signal, or return, is tied to the negative input of
the PGIA.

When you configure a channel for differential input, each signal uses
two multiplexer inputs—one for the signal and one for its reference
signal. Therefore, with a differential configuration for every channel,
up to eight analog input channels are available (up to 32 channels on the
AT-MIO-64E-3).

You should use differential input connections for any channel that
meets any of the following conditions:

• The input signal is low level (less than 1 V).

• The leads connecting the signal to the AT E Series board are
greater than 10 ft (3 m).

• The input signal requires a separate ground-reference point or
return signal.

• The signal leads travel through noisy environments.

Differential signal connections reduce picked-up noise and increase
common-mode noise rejection. Differential signal connections also
allow input signals to float within the common-mode limits of the
PGIA.

AT-MIO/AI E Series User Manual 4-20

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National Instruments Corporation

Ground-

Referenced

Signal

Source

Chapter 4 Signal Connections

Differential Connections for Ground-Referenced Signal Sources

Figure 4-6 shows how to connect a ground-referenced signal source to
an AT E Series board channel configured in DIFF input mode.

ACH<0..7>

+

V

s

-

Instrumentation

Amplifier

+

Common-

Mode

Noise and

Ground

Potential

I/O Connector

PGIA

ACH<8..15>

-

+

V

cm

-

Input Multiplexers

AISENSE

AIGND

Selected Channel in DIFF Configuration

+

m

Measured

Voltage

-

V

Figure 4-6. Differential Input Connections for Ground-Referenced Signals

With this type of connection, the PGIA rejects both the common-mode
noise in the signal and the ground potential difference between the
signal source and the AT E Series board ground, shown as Vcm in
Figure 4-6.



National Instruments Corporation 4-21 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

Bias
resistors
(see text)

Floating

Signal

Source

+

V

S

-

Differential Connections for Nonreferenced or Floating Signal Sources

Figure 4-7 shows how to connect a floating signal source to an
AT E Series board channel configured in DIFF input mode.

ACH<0..7>

Instrumentation

Amplifier

+

Bias

Current

Return

Paths

I/O Connector

PGIA

ACH<8..15>

-

Input Multiplexers

AISENSE

AIGND

Selected Channel in DIFF Configuration

+

m

Measured

Voltage

-

V

Figure 4-7. Differential Input Connections for Nonreferenced Signals

Figure 4-7 shows two bias resistors connected in parallel with the signal
leads of a floating signal source. If you do not use the resistors and the
source is truly floating, the source is not likely to remain within the
common-mode signal range of the PGIA, and the PGIA will saturate,
causing erroneous readings. You must reference the source to AIGND.
The easiest way is simply to connect the positive side of the signal to
the positive input of the PGIA and connect the negative side of the
signal to AIGND as well as to the negative input of the PGIA, without

AT-MIO/AI E Series User Manual 4-22



National Instruments Corporation

Chapter 4 Signal Connections

any resistors at all. This connection works well for DC-coupled sources
with low source impedance (less than 100 Ω).

However, for larger source impedances, this connection leaves the
differential signal path significantly out of balance. Noise that couples
electrostatically onto the positive line does not couple onto the negative
line because it is connected to ground. Hence, this noise appears as a
differential-mode signal instead of a common-mode signal, and so the
PGIA does not reject it. In this case, instead of directly connecting the
negative line to AIGND, connect it to AIGND through a resistor that is
about 100 times the equivalent source impedance. The resistor puts the
signal path nearly in balance, so that about the same amount of noise
couples onto both connections, yielding better rejection of
electrostatically coupled noise. Also, this configuration does not load
down the source (other than the very high input impedance of the
PGIA).

You can fully balance the signal path by connecting another resistor of
the same value between the positive input and AIGND, as shown in
Figure 4-7. This fully balanced configuration offers slightly better
noise rejection but has the disadvantage of loading the source down
with the series combination (sum) of the two resistors. If, for example,
the source impedance is 2 kΩ and each of the two resistors is 100 kΩ,
the resistors load down the source with 200 kΩ and produce a -1% gain
error.

Both inputs of the PGIA require a DC path to ground in order for the
PGIA to work. If the source is AC coupled (capacitively coupled), the
PGIA needs a resistor between the positive input and AIGND. If the
source has low impedance, choose a resistor that is large enough not to
significantly load the source but small enough not to produce
significant input offset voltage as a result of input bias current
(typically 100 kΩ to 1 MΩ). In this case, you can tie the negative input
directly to AIGND. If the source has high output impedance, you
should balance the signal path as previously described using the same
value resistor on both the positive and negative inputs; you should be
aware that there is some gain error from loading down the source.



National Instruments Corporation 4-23 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

Single-Ended Connection Considerations

A single-ended connection is one in which the AT E Series board
analog input signal is referenced to a ground that can be shared with
other input signals. The input signal is tied to the positive input of the
PGIA, and the ground is tied to the negative input of the PGIA.

When every channel is configured for single-ended input, up to 16
analog input channels are available (up to 64 channels on the
AT-MIO-64E-3).

You can use single-ended input connections for any input signal that
meets the following conditions:

• The input signal is high level (greater than 1 V).

• The leads connecting the signal to the AT E Series board are less
than 10 ft (3 m).

• The input signal can share a common reference point with other
signals.

DIFF input connections are recommended for greater signal integrity
for any input signal that does not meet the preceding conditions.

You can software configure the AT E Series board channels for two
different types of single-ended connections—RSE configuration and
NRSE configuration. The RSE configuration is used for floating signal
sources; in this case, the AT E Series board provides the reference
ground point for the external signal. The NRSE input configuration is
used for ground-referenced signal sources; in this case, the external
signal supplies its own reference ground point and the AT E Series
board should not supply one.

In single-ended configurations, more electrostatic and magnetic noise
couples into the signal connections than in differential configurations.
The coupling is the result of differences in the signal path. Magnetic
coupling is proportional to the area between the two signal conductors.
Electrical coupling is a function of how much the electric field differs
between the two conductors.

AT-MIO/AI E Series User Manual 4-24



National Instruments Corporation

Chapter 4 Signal Connections

Single-Ended Connections for Floating Signal Sources (RSE Configuration)

Figure 4-8 shows how to connect a floating signal source to an
AT E Series board channel configured for RSE mode.

ACH<0..15>

Floating

Signal

Source

+

V

s

-

I/O Connector

Figure 4-8. Single-Ended Input Connections for Nonreferenced or Floating Signals

Single-Ended Connections for Grounded Signal Sources (NRSE Configuration)

To measure a grounded signal source with a single-ended configuration,
you must configure your AT E Series board in the NRSE input
configuration. The signal is then connected to the positive input of the
AT E Series PGIA, and the signal local ground reference is connected
to the negative input of the PGIA. The ground point of the signal
should, therefore, be connected to the AISENSE pin. Any potential
difference between the AT E Series ground and the signal ground
appears as a common-mode signal at both the positive and negative
inputs of the PGIA, and this difference is rejected by the amplifier. If
the input circuitry of an AT E Series board were referenced to ground,
in this situation as in the RSE input configuration, this difference in
ground potentials would appear as an error in the measured voltage.

+

Input Multiplexers

AISENSE

AIGND

Selected Channel in RSE Configuration

-

Instrumentation

Amplifier

PGIA

+

m

Measured

Voltage

-

V



National Instruments Corporation 4-25 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

Figure 4-9 shows how to connect a grounded signal source to an
AT E Series board channel configured for NRSE mode.

ACH<0..15>

Ground-

Referenced

Signal

Source

Common-

Mode
Noise

and Ground

Potential

+

V

s

-

+

V

cm

-

I/O Connector

Input Multiplexers

AIGND

Selected Channel in NRSE Configuration

AISENSE

Figure 4-9. Single-Ended Input Connections for Ground-Referenced Signal

Common-Mode Signal Rejection Considerations

Figures 4-6 and 4-9 show connections for signal sources that are
already referenced to some ground point with respect to the
AT E Series board. In these cases, the PGIA can reject any voltage
caused by ground potential differences between the signal source and
the board. In addition, with differential input connections, the PGIA
can reject common-mode noise pickup in the leads connecting the
signal sources to the board. The PGIA can reject common-mode signals
as long as V

+

in

AT-MIO-16XE-50 has the additional restriction that (V
to the gain times (V
of 10 and 100, this is roughly equivalent to restricting the two input
voltages to within ±8 V of AIGND.

and V

+

-

are both within ±11 V of AIGND. The

in

-

- V

in

) must be within ±26 V of AIGND. At gains

in

Instrumentation

+

PGIA

-

Amplifier

V

m

+

+

in

-

+ V

Measured

Voltage

-

) added

in

AT-MIO/AI E Series User Manual 4-26



National Instruments Corporation

Analog Output Signal Connections

The analog output signals are DAC0OUT, DAC1OUT, EXTREF, and
AOGND. DAC0OUT and DAC1OUT are not available on the

AT-AI-16XE-10. EXTREF is not available on the AT-MIO-16XE-10,
AT-AI-16XE-10, or AT-MIO-16XE-50.

DAC0OUT is the voltage output signal for analog output channel 0.
DAC1OUT is the voltage output signal for analog output channel 1.

EXTREF is the external reference input for both analog output
channels. You must configure each analog output channel individually
for external reference selection in order for the signal applied at the
external reference input to be used by that channel. If you do not
specify an external reference, the channel will use the internal
reference. You cannot use an external analog output reference with the
AT-MIO-16XE-10, AT-AI-16XE-10, or AT-MIO-16XE-50. Analog
output configuration options are explained in the Analog Output section
in Chapter 3, Hardware Overview. The following ranges and ratings
apply to the EXTREF input:

• Usable input voltage range: ±11 V peak with respect to AOGND

• Absolute maximum ratings: ±15 V peak with respect to AOGND

Chapter 4 Signal Connections

AOGND is the ground reference signal for both analog output channels
and the external reference signal.



National Instruments Corporation 4-27 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

External
Reference
Signal
(Optional)

+

V

ref

-

Figure 4-10 shows how to make analog output connections and the
external reference input connection to your AT E Series board.

EXTREF

DAC0OUT

Channel 0

Load

VOUT 0

+

-

-

AO GND

VOUT 1

Load

+

Figure 4-10. Analog Output Connections

The external reference signal can be either a DC or an AC signal. The
board multiplies this reference signal by the DAC code (divided by the
full-scale DAC code) to generate the output voltage.

Digital I/O Signal Connections

The digital I/O signals are DIO<0..7> and DGND. DIO<0..7> are the
signals making up the DIO port, and DGND is the ground reference
signal for the DIO port. You can program all lines individually to be
inputs or outputs. The AT-MIO-16DE-10 has 24 additional DIO lines,

configured as three 8-bit ports: PA<0..7>, PB<0..7>, and PC<0..7>.
You can configure each port for both input and output in various
combinations, with some handshaking capabilities.

DAC1OUT

Channel 1

Analog Output Channels

AT E Series Board

AT-MIO/AI E Series User Manual 4-28



National Instruments Corporation

Chapter 4 Signal Connections

Warning: Exceeding the maximum input voltage ratings, which are listed in

Tables 4-1 through 4-4, can damage the AT E Series board and the PC.
National Instruments is

liable for any damages resulting from such

NOT

signal connections.

Figure 4-11 shows signal connections for three typical digital I/O
applications.

+5 V

LED

DIO<4..7>

+5 V

TTL Signal

DIO<0..3>

Switch

DGND

I/O Connector

AT E Series Board

Figure 4-11. Digital I/O Connections

Figure 4-11 shows DIO<0..3> configured for digital input and
DIO<4..7> configured for digital output. Digital input applications
include receiving TTL signals and sensing external device states such
as the state of the switch shown in the figure. Digital output
applications include sending TTL signals and driving external devices
such as the LED shown in the figure.



National Instruments Corporation 4-29 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

Power Connections

Two pins on the I/0 connector supply +5 V from the PC power supply
via a self-resetting fuse. The fuse will reset automatically within a few
seconds after the overcurrent condition is removed. These pins are
referenced to DGND and can be used to power external digital circuitry.

• Power rating +4.65 VDC to +5.25 VDC at 1 A combined total

Warning: Under no circumstances should you connect these +5 V power pins directly

to analog or digital ground or to any other voltage source on the
AT E Series board or any other device. Doing so can damage the
AT E Series board and the PC. National Instruments is
damages resulting from such a connection.

Timing Connections

Warning: Exceeding the maximum input voltage ratings, which are listed in

Tables 4-1 through 4-4, can damage the AT E Series board and the PC.
National Instruments is
signal connections.

for both pins

NOT

liable for

NOT

liable for any damages resulting from such

All external control over the timing of your AT E Series board is routed
through the 10 programmable function inputs labeled PFI0 through
PFI9. These signals are explained in detail in the next section,
Programmable Function Input Connections. These PFIs are
bidirectional; as outputs they are not programmable and reflect the state
of many data acquisition, waveform generation, and general-purpose
timing signals. There are five other dedicated outputs for the remainder
of the timing signals. As inputs, the PFI signals are programmable and
can control any data acquisition, waveform generation, and
general-purpose timing signals.

The data acquisition signals are explained in the Data Acquisition
Timing Connections section later in this chapter. The waveform
generation signals are explained in the Waveform Generation Timing
Connections section later in this chapter. The general-purpose timing
signals are explained in the General-Purpose Timing Signal Connections
section later in this chapter.

All digital timing connections are referenced to DGND. This reference
is demonstrated in Figure 4-12, which shows how to connect an

AT-MIO/AI E Series User Manual 4-30



National Instruments Corporation

Chapter 4 Signal Connections

external TRIG1 source and an external CONVERT* source to two of
the AT E Series board PFI pins.

PFI0/TRIG1

PFI2/CONVERT*

TRIG1

Source

CONVERT*

Source

I/O Connector

Figure 4-12. Timing I/O Connections

Programmable Function Input Connections

There are a total of 13 internal timing signals that you can externally
control from the PFI pins. The source for each of these signals is
software selectable from any of the PFIs when you want external
control. This flexible routing scheme reduces the need to change the
physical wiring to the board I/O connector for different applications
requiring alternative wiring.

You can individually enable each of the PFI pins to output a specific
internal timing signal. For example, if you need the CONVERT* signal
as an output on the I/O connector, software can turn on the output driver
for the PFI2/CONVERT* pin. You must be careful not to drive a PFI
signal externally when it is configured as an output.

DGND

AT E Series Board

As an input, you can individually configure each PFI for edge or level
detection and for polarity selection, as well. You can use the polarity
selection for any of the 13 timing signals, but the edge or level detection
will depend upon the particular timing signal being controlled. The



National Instruments Corporation 4-31 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

detection requirements for each timing signal are listed within the
section that discusses that individual signal.

In edge-detection mode, the minimum pulse width required is 10 ns.
This applies for both rising-edge and falling-edge polarity settings.
There is no maximum pulse-width requirement in edge-detect mode.

In level-detection mode, there are no minimum or maximum
pulse-width requirements imposed by the PFIs themselves, but there
may be limits imposed by the particular timing signal being controlled.
These requirements are listed later in this chapter.

Data Acquisition Timing Connections

The data acquisition timing signals are SCANCLK, EXTSTROBE*,
TRIG1, TRIG2, STARTSCAN, CONVERT*, AIGATE, and
SISOURCE.

Posttriggered data acquisition allows you to view only data that is
acquired after a trigger event is received. A typical posttriggered data
acquisition sequence is shown in Figure 4-13. Pretriggered data
acquisition allows you to view data that is acquired before the trigger of
interest in addition to data acquired after the trigger. Figure 4-14
shows a typical pretriggered data acquisition sequence. The description
for each signal shown in these figures is included later in this chapter.

TRIG1

STARTSCAN

CONVERT*

Scan Counter

Figure 4-13. Typical Posttriggered Acquisition

AT-MIO/AI E Series User Manual 4-32

13042



National Instruments Corporation

TRIG1

Chapter 4 Signal Connections

TRIG2

STARTSCAN

CONVERT*

Scan Counter

Don't Care

01231 0222

Figure 4-14. Typical Pretriggered Acquisition

SCANCLK Signal

SCANCLK is an output-only signal that generates a pulse with the
leading edge occurring approximately 50 to 100 ns after an A/D
conversion begins. The polarity of this output is software selectable but
is typically configured so that a low-to-high leading edge can clock
external analog input multiplexers indicating when the input signal has
been sampled and can be removed. This signal has a 400 to 500 ns pulse
width and is software enabled. Figure 4-15 shows the timing for the
SCANCLK signal.

CONVERT*

t

SCANCLK

d

t

w

t

= 50 to 100 ns

d

t

= 400 to 500 ns

w

Figure 4-15. SCANCLK Signal Timing

EXTSTROBE* Signal

EXTSTROBE* is an output-only signal that generates either a single
pulse or a sequence of eight pulses in the hardware-strobe mode. An
external device can use this signal to latch signals or to trigger events.
In the single-pulse mode, software controls the level of the



National Instruments Corporation 4-33 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

EXTSTROBE* signal. A 10 µs and a 1.2 µs clock are available for
generating a sequence of eight pulses in the hardware-strobe mode.
Figure 4-16 shows the timing for the hardware-strobe mode
EXTSTROBE* signal.

V

OH

V

OL

t

t

w

w

t

= 600 ns or 5 µs

w

Figure 4-16. EXTSTROBE* Signal Timing

TRIG1 Signal

Any PFI pin can externally input the TRIG1 signal, which is available
as an output on the PFI0/TRIG1 pin.

Refer to Figures 4-13 and 4-14 for the relationship of TRIG1 to the data
acquisition sequence.

As an input, the TRIG1 signal is configured in the edge-detection mode.
You can select any PFI pin as the source for TRIG1 and configure the
polarity selection for either rising or falling edge. The selected edge of
the TRIG1 signal starts the data acquisition sequence for both
posttriggered and pretriggered acquisitions. The AT-MIO-16E-1,
AT-MIO-16E-2, AT-MIO-16XE-10, AT-AI-16XE-10, and
AT-MIO-64E-3 support analog triggering on the PFI0/TRIG1 pin. See
Chapter 3 for more information on analog triggering.

As an output, the TRIG1 signal reflects the action that initiates a data
acquisition sequence. This is true even if the acquisition is being
externally triggered by another PFI. The output is an active high pulse
with a pulse width of 50 to 100 ns. This output is set to tri-state at
startup.

Figures 4-17 and 4-18 show the input and output timing requirements
for the TRIG1 signal.

AT-MIO/AI E Series User Manual 4-34

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National Instruments Corporation

Rising-edge
polarity

Falling-edge
polarity

Chapter 4 Signal Connections

t

w

t

= 10 ns minimum

w

Figure 4-17. TRIG1 Input Signal Timing

t

w

t

= 50-100 ns

w

Figure 4-18. TRIG1 Output Signal Timing

The board also uses the TRIG1 signal to initiate pretriggered data
acquisition operations. In most pretriggered applications, the TRIG1
signal is generated by a software trigger. Refer to the TRIG2 signal
description for a complete description of the use of TRIG1 and TRIG2
in a pretriggered data acquisition operation.

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National Instruments Corporation 4-35 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

TRIG2 Signal

Any PFI pin can externally input the TRIG2 signal, which is available
as an output on the PFI1/TRIG2 pin.

Refer to Figure 4-13 for the relationship of TRIG2 to the data
acquisition sequence.

As an input, the TRIG2 signal is configured in the edge-detection mode.
You can select any PFI pin as the source for TRIG2 and configure the
polarity selection for either rising or falling edge. The selected edge of
the TRIG2 signal initiates the posttriggered phase of a pretriggered
acquisition sequence. In pretriggered mode, the TRIG1 signal initiates
the data acquisition. The scan counter indicates the minimum number
of scans before TRIG2 can be recognized. After the scan counter
decrements to zero, it is loaded with the number of posttrigger scans to
acquire while the acquisition continues. The board ignores the TRIG2
signal if it is asserted prior to the scan counter decrementing to zero.
After the selected edge of TRIG2 is received, the board will acquire a
fixed number of scans and the acquisition will stop. This mode acquires
data both before and after receiving TRIG2.

As an output, the TRIG2 signal reflects the posttrigger in a pretriggered
acquisition sequence. This is true even if the acquisition is being
externally triggered by another PFI. The TRIG2 signal is not used in
posttriggered data acquisition. The output is an active high pulse with
a pulse width of 50 to 100 ns. This output is set to tri-state at startup.

Figures 4-19 and 4-20 show the input and output timing requirements
for the TRIG2 signal.

Rising-edge
polarity

Falling-edge
polarity

Figure 4-19. TRIG2 Input Signal Timing

AT-MIO/AI E Series User Manual 4-36

t

w

t

= 10 ns minimum

w

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National Instruments Corporation

Chapter 4 Signal Connections

t

w

t

= 50-100 ns

w

Figure 4-20. TRIG2 Output Signal Timing

STARTSCAN Signal

Any PFI pin can externally input the STARTSCAN signal, which is
available as an output on the PFI7/STARTSCAN pin.

Refer to Figures 4-13 and 4-14 for the relationship of STARTSCAN to
the data acquisition sequence.

As an input, the STARTSCAN signal is configured in the
edge-detection mode. You can select any PFI pin as the source for
STARTSCAN and configure the polarity selection for either rising or
falling edge. The selected edge of the STARTSCAN signal initiates a
scan. The sample interval counter is started if you select internally
triggered CONVERT*.

As an output, the STARTSCAN signal reflects the actual start pulse that
initiates a scan. This is true even if the starts are being externally
triggered by another PFI. You have two output options. The first is an
active high pulse with a pulse width of 50 to 100 ns, which indicates the
start of the scan. The second action is an active high pulse that
terminates at the start of the last conversion in the scan, which indicates
a scan in progress. STARTSCAN will be deasserted t

after the last

off

conversion in the scan is initiated. This output is set to tri-state at
startup.

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National Instruments Corporation 4-37 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

Figures 4-21 and 4-22 show the input and output timing requirements
for the STARTSCAN signal

t

w

Rising-edge
polarity

Falling-edge
polarity

t

= 10 ns minimum

w

Figure 4-21. STARTSCAN Input Signal Timing

t

w

STARTSCAN

Start Pulse

CONVERT*

STARTSCAN

b. Scan in Progress, Two Conversions per Scan

Figure 4-22. STARTSCAN Output Signal Timing

AT-MIO/AI E Series User Manual 4-38

tw = 50-100 ns

a. Start of Scan

= 10 ns minimum

t

off

t

off

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National Instruments Corporation

Chapter 4 Signal Connections

The CONVERT* pulses are masked off until the board generates the
STARTSCAN signal. If you are using internally generated
conversions, the first CONVERT* will appear when the onboard
sample interval counter reaches zero. If you select an external
CONVERT*, the first external pulse after STARTSCAN will generate
a conversion. The STARTSCAN pulses should be separated by at least
one scan period.

A counter on your AT E Series board internally generates the
STARTSCAN signal unless you select some external source. This
counter is started by the TRIG1 signal and is stopped either by software
or by the sample counter.

Scans generated by either an internal or external STARTSCAN signal
are inhibited unless they occur within a data acquisition sequence.
Scans occurring within a data acquisition sequence may be gated by
either the hardware (AIGATE) signal or software command register
gate.

CONVERT* Signal

Any PFI pin can externally input the CONVERT* signal, which is
available as an output on the PFI2/CONVERT* pin.

Refer to Figures 4-13 and 4-14 for the relationship of CONVERT* to
the data acquisition sequence.

As an input, the CONVERT* signal is configured in the edge-detection
mode. You can select any PFI pin as the source for CONVERT* and
configure the polarity selection for either rising or falling edge. The
selected edge of the CONVERT* signal initiates an A/D conversion.

As an output, the CONVERT* signal reflects the actual convert pulse
that is connected to the ADC. This is true even if the conversions are
being externally generated by another PFI. The output is an active low
pulse with a pulse width of 50 to 100 ns. This output is set to tri-state
at startup.

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National Instruments Corporation 4-39 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

Figures 4-23 and 4-24 show the input and output timing requirements
for the CONVERT* signal.

t

w

Rising-edge
polarity

Falling-edge
polarity

t

= 10 ns minimum

w

Figure 4-23. CONVERT* Input Signal Timing

t

w

Figure 4-24. CONVERT* Output Signal Timing

The ADC switches to hold mode within 60 ns of the selected edge. This
hold-mode delay time is a function of temperature and does not vary
from one conversion to the next. Separate the CONVERT* pulses by at
least one conversion period.

The sample interval counter on the AT E Series board normally
generates the CONVERT* signal unless you select some external
source. The counter is started by the STARTSCAN signal and
continues to count down and reload itself until the scan is finished. It
then reloads itself in readiness for the next STARTSCAN pulse.

A/D conversions generated by either an internal or external
CONVERT* signal are inhibited unless they occur within a data
acquisition sequence. Scans occurring within a data acquisition
sequence may be gated by either the hardware (AIGATE) signal or
software command register gate.

AT-MIO/AI E Series User Manual 4-40

t

= 50-100 ns

w

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National Instruments Corporation

Chapter 4 Signal Connections

AIGATE Signal

Any PFI pin can externally input the AIGATE signal, which is not
available as an output on the I/O connector. The AIGATE signal can
mask off scans in a data acquisition sequence. You can configure the
PFI pin you select as the source for the AIGATE signal in either the
level-detection or edge-detection mode. You can configure the polarity
selection for the PFI pin for either active high or active low.

In the level-detection mode if AIGATE is active, the STARTSCAN
signal is masked off and no scans can occur. In the edge-detection
mode, the first active edge disables the STARTSCAN signal, and the
second active edge enables STARTSCAN.

The AIGATE signal can neither stop a scan in progress nor continue a
previously gated-off scan; in other words, once a scan has started,
AIGATE does not gate off conversions until the beginning of the next
scan and, conversely, if conversions are being gated off, AIGATE does
not gate them back on until the beginning of the next scan.

SISOURCE Signal

Any PFI pin can externally input the SISOURCE signal, which is not
available as an output on the I/O connector. The onboard scan interval
counter uses the SISOURCE signal as a clock to time the generation of
the STARTSCAN signal. You must configure the PFI pin you select as
the source for the SISOURCE signal in the level-detection mode. You
can configure the polarity selection for the PFI pin for either active high
or active low.

The maximum allowed frequency is 20 MHz, with a minimum pulse
width of 23 ns high or low. There is no minimum frequency limitation.

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National Instruments Corporation 4-41 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

Either the 20 MHz or 100 kHz internal timebase generates the
SISOURCE signal unless you select some external source. Figure 4-25
shows the timing requirements for the SISOURCE signal.

t

p

t

Figure 4-25. SISOURCE Signal Timing

t

w

w

t

= 50 ns minimum

p

t

= 23 ns minimum

w

Waveform Generation Timing Connections

The analog group defined for your AT E Series board is controlled by
WFTRIG, UPDATE*, and UISOURCE.

WFTRIG Signal

Any PFI pin can externally input the WFTRIG signal, which is
available as an output on the PFI6/WFTRIG pin.

As an input, the WFTRIG signal is configured in the edge-detection
mode. You can select any PFI pin as the source for WFTRIG and
configure the polarity selection for either rising or falling edge. The
selected edge of the WFTRIG signal starts the waveform generation for
the DACs. The update interval (UI) counter is started if you select
internally generated UPDATE*.

As an output, the WFTRIG signal reflects the trigger that initiates
waveform generation. This is true even if the waveform generation is
being externally triggered by another PFI. The output is an active high
pulse with a pulse width of 50 to 100 ns. This output is set to tri-state
at startup.

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National Instruments Corporation

Chapter 4 Signal Connections

Figures 4-26 and 4-27 show the input and output timing requirements
for the WFTRIG signal.

t

w

Rising-edge
polarity

Falling-edge
polarity

t

= 10 ns minimum

w

Figure 4-26. WFTRIG Input Signal Timing

t

w

t

= 50-100 ns

w

Figure 4-27. WFTRIG Output Signal Timing

UPDATE* Signal

Any PFI pin can externally input the UPDATE* signal, which is
available as an output on the PFI5/UPDATE* pin.

As an input, the UPDATE* signal is configured in the edge-detection
mode. You can select any PFI pin as the source for UPDATE* and
configure the polarity selection for either rising or falling edge. The
selected edge of the UPDATE* signal updates the outputs of the DACs.
In order to use UPDATE*, you must set the DACs to posted-update
mode.

As an output, the UPDATE* signal reflects the actual update pulse that
is connected to the DACs. This is true even if the updates are being
externally generated by another PFI. The output is an active low pulse
with a pulse width of 300 to 350 ns. This output is set to tri-state at
startup.

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National Instruments Corporation 4-43 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

Figures 4-28 and 4-29 show the input and output timing requirements
for the UPDATE* signal.

t

w

Rising-edge
polarity

Falling-edge
polarity

t

= 10 ns minimum

w

Figure 4-28. UPDATE* Input Signal Timing

t

w

Figure 4-29. UPDATE* Output Signal Timing

The DACs are updated within 100 ns of the leading edge. Separate the
UPDATE* pulses with enough time that new data can be written to the
DAC latches.

The AT E Series board UI counter normally generates the UPDATE*
signal unless you select some external source. The UI counter is started
by the WFTRIG signal and can be stopped by software or the internal
Buffer Counter.

D/A conversions generated by either an internal or external UPDATE*
signal do not occur when gated by the software command register gate.

AT-MIO/AI E Series User Manual 4-44

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= 300-350 ns

w

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National Instruments Corporation

Chapter 4 Signal Connections

UISOURCE Signal

Any PFI pin can externally input the UISOURCE signal, which is not
available as an output on the I/O connector. The UI counter uses the
UISOURCE signal as a clock to time the generation of the UPDATE*
signal. You must configure the PFI pin you select as the source for the
UISOURCE signal in the level-detection mode. You can configure the
polarity selection for the PFI pin for either active high or active low.
Figure 4-30 shows the timing requirements for the UISOURCE signal.

t

p

t

t

w

w

t

= 50 ns minimum

p

t

= 23 ns minimum

w

Figure 4-30. UISOURCE Signal Timing

The maximum allowed frequency is 20 MHz, with a minimum pulse
width of 23 ns high or low. There is no minimum frequency limitation.

Either the 20 MHz or 100 kHz internal timebase normally generates the
UISOURCE signal unless you select some external source.

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National Instruments Corporation 4-45 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

General-Purpose Timing Signal Connections

The general-purpose timing signals are GPCTR0_SOURCE,
GPCTR0_GATE, GPCTR0_OUT, GPCTR0_UP_DOWN,
GPCTR1_SOURCE, GPCTR1_GATE, GPCTR1_OUT,
GPCTR1_UP_DOWN, and FREQ_OUT.

GPCTR0_SOURCE Signal

Any PFI pin can externally input the GPCTR0_SOURCE signal, which
is available as an output on the PFI8/GPCTR0_SOURCE pin.

As an input, the GPCTR0_SOURCE signal is configured in the
edge-detection mode. You can select any PFI pin as the source for
GPCTR0_SOURCE and configure the polarity selection for either
rising or falling edge.

As an output, the GPCTR0_SOURCE signal reflects the actual clock
connected to general-purpose counter 0. This is true even if another PFI
is externally inputting the source clock. This output is set to tri-state at
startup.

Figure 4-31 shows the timing requirements for the GPCTR0_SOURCE
signal.

t

w

Figure 4-31. GPCTR0_SOURCE Signal Timing

The maximum allowed frequency is 20 MHz, with a minimum pulse
width of 23 ns high or low. There is no minimum frequency limitation.

The 20 MHz or 100 kHz timebase normally generates the
GPCTR0_SOURCE signal unless you select some external source.

AT-MIO/AI E Series User Manual 4-46

t

p

t

w

t

= 50 ns minimum

p

t

= 23 ns minimum

w

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National Instruments Corporation

Chapter 4 Signal Connections

GPCTR0_GATE Signal

Any PFI pin can externally input the GPCTR0_GATE signal, which is
available as an output on the PFI9/GPCTR0_GATE pin.

As an input, the GPCTR0_GATE signal is configured in the
edge-detection mode. You can select any PFI pin as the source for
GPCTR0_GATE and configure the polarity selection for either rising or
falling edge. You can use the gate signal in a variety of different
applications to perform actions such as starting and stopping the
counter, generating interrupts, saving the counter contents, and so on.

As an output, the GPCTR0_GATE signal reflects the actual gate signal
connected to general-purpose counter 0. This is true even if the gate is
being externally generated by another PFI. This output is set to tri-state
at startup.

Figure 4-32 shows the timing requirements for the GPCTR0_GATE
signal.

t

w

Rising-edge
polarity

Falling-edge
polarity

t

= 10 ns minimum

w

Figure 4-32. GPCTR0_GATE Signal Timing in Edge-Detection Mode

GPCTR0_OUT Signal

This signal is available only as an output on the GPCTR0_OUT pin.
The GPCTR0_OUT signal reflects the terminal count (TC) of
general-purpose counter 0. You have two software-selectable output
options— pulse on TC and toggle output polarity on TC. The output
polarity is software selectable for both options. This output is set to
tri-state at startup. Figure 4-33 shows the timing of the GPCTR0_OUT
signal.

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National Instruments Corporation 4-47 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

GPCTR0_SOURCE

GPCTR0_OUT

(Pulse on TC)

GPCTR0_OUT

(Toggle output on TC)

TC

Figure 4-33. GPCTR0_OUT Signal Timing

GPCTR0_UP_DOWN Signal

This signal can be externally input on the DIO6 pin and is not available
as an output on the I/O connector. The general-purpose counter 0 will
count down when this pin is at a logic low and count up when it is at a
logic high. You can disable this input so that software can control the
up-down functionality and leave the DIO6 pin free for general use.

GPCTR1_SOURCE Signal

Any PFI pin can externally input the GPCTR1_SOURCE signal, which
is available as an output on the PFI3/GPCTR1_SOURCE pin.

As an input, the GPCTR1_SOURCE signal is configured in the
edge-detection mode. You can select any PFI pin as the source for
GPCTR1_SOURCE and configure the polarity selection for either
rising or falling edge.

As an output, the GPCTR1_SOURCE monitors the actual clock
connected to general-purpose counter 1. This is true even if the source
clock is being externally generated by another PFI. This output is set
to tri-state at startup.

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National Instruments Corporation

Chapter 4 Signal Connections

Figure 4-34 shows the timing requirements for the GPCTR1_SOURCE
signal.

t

p

t

t

w

w

t

= 50 ns minimum

p

t

= 23 ns minimum

w

Figure 4-34. GPCTR1_SOURCE Signal Timing

The maximum allowed frequency is 20 MHz, with a minimum pulse
width of 23 ns high or low. There is no minimum frequency limitation.

The 20 MHz or 100 kHz timebase normally generates the
GPCTR1_SOURCE unless you select some external source.

GPCTR1_GATE Signal

Any PFI pin can externally input the GPCTR1_GATE signal, which is
available as an output on the PFI4/GPCTR1_GATE pin.

As an input, the GPCTR1_GATE signal is configured in edge-detection
mode. You can select any PFI pin as the source for GPCTR1_GATE
and configure the polarity selection for either rising or falling edge.
You can use the gate signal in a variety of different applications to
perform such actions as starting and stopping the counter, generating
interrupts, saving the counter contents, and so on.

As an output, the GPCTR1_GATE signal monitors the actual gate
signal connected to general-purpose counter 1. This is true even if the
gate is being externally generated by another PFI. This output is set to
tri-state at startup.

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National Instruments Corporation 4-49 AT-MIO/AI E Series User Manual

Chapter 4 Signal Connections

Figure 4-35 shows the timing requirements for the GPCTR1_GATE
signal.

t

w

Rising-edge
polarity

Falling-edge
polarity

t

= 10 ns minimum

w

Figure 4-35. GPCTR1_GATE Signal Timing in Edge-Detection Mode

GPCTR1_OUT Signal

This signal is available only as an output on the GPCTR1_OUT pin.
The GPCTR1_OUT signal monitors the TC board general-purpose
counter 1. You have two software-selectable output options—pulse on
TC and toggle output polarity on TC. The output polarity is software
selectable for both options. This output is set to tri-state at startup.
Figure 4-36 shows the timing requirements for the GPCTR1_OUT
signal.

GPCTR1_SOURCE

GPCTR1_OUT

(Pulse on TC)

GPCTR1_OUT

(Toggle output on TC)

Figure 4-36. GPCTR1_OUT Signal Timing

AT-MIO/AI E Series User Manual 4-50

TC

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National Instruments Corporation

Chapter 4 Signal Connections

GPCTR1_UP_DOWN Signal

This signal can be externally input on the DIO7 pin and is not available
as an output on the I/O connector. General-purpose counter 1 counts
down when this pin is at a logic low and counts up at a logic high. This
input can be disabled so that software can control the up-down
functionality and leave the DIO7 pin free for general use. Figure 4-37
shows the timing requirements for the GATE and SOURCE input
signals and the timing specifications for the OUT output signals of your
AT E Series board.

SOURCE

GATE

OUT

t

sc

V

IH

V

IL

t

gsu

V

IH

V

IL

V

OH

V

OL

Source Clock Period
Source Pulse Width
Gate Setup Time
Gate Hold Time
Gate Pulse Width
Output Delay Time

t

gw

t

out

t 50 ns minimum

sc

t

sp

t

gsu

t

gh

t

gw

t

out

t

sp

t

gh

23 ns minimum

10 ns minimum

0 ns minimum

10 ns minimum

80 ns maximum

t

sp

Figure 4-37. GPCTR Timing Summary

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National Instruments Corporation 4-51 AT-MIO/AI E Series User Manual