National Instruments 320030-01 User Manual

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GPIB-1014

User Manual

March 1997 Edition

Part Number 320030-01

National Instruments Corporate Headquarters

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Limited Warranty

The GPIB-1014 is warranted against defects in materials and workmanship for a period of two years from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.

The media on which you receive National Instruments software are warranted not to fail to execute programming instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period. National Instruments does not warrant that the operation of the software shall be uninterrupted or error free.

A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work. National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty.

National Instruments believes that the information in this manual is accurate. The document has been carefully reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition. The reader should consult National Instruments if errors are suspected. In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it.

EXCEPT AS SPECIFIED HEREIN, NATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR IMPLIED,

AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OF

NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS,

USE OF PRODUCTS, OR INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY THEREOF

whether in contract or tort, including negligence. Any action against National Instruments must be brought within one year after the cause of action accrues. National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control. The warranty provided herein does not cover damages, defects, malfunctions, or service failures caused by owner's failure to follow the National Instruments installation, operation, or maintenance instructions; owner's modification of the product; owner's abuse, misuse, or negligent acts; and power failure or surges, fire, flood, accident, actions of third parties, or other events outside reasonable control.

. CUSTOMER'S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART

NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER.

. This limitation of the liability of National Instruments will apply regardless of the form of action,

Copyright

Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written consent of National Instruments Corporation.

Trademarks

NI-488M™ is a trademark of National Instruments Corporation. Product and company names listed are trademarks or trade names of their respective companies.

Warning Regarding Medical and Clinical Use

of National Instruments Products

National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the part of the user or application designer. Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel, and all traditional medical safeguards, equipment, and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used. National Instruments products are NOT intended to be a substitute for any form of established process, procedure, or equipment used to monitor or safeguard human health and safety in medical or clinical treatment.

FCC/DOC Radio Frequency Interference Compliance

This equipment generates and uses radio frequency energy and, if not installed and used in strict accordance with the instructions in this manual, may cause interference to radio and television reception. This equipment has been tested and found to comply with the following two regulatory agencies:

Federal Communications Commission

This device complies with Part 15 of the Federal Communications Commission (FCC) Rules for a Class A digital device. Operation is subject to the following two conditions:

1. This device may not cause harmful interference in commercial environments.

2. This device must accept any interference received, including interference that may cause undesired operation.

Canadian Department of Communications

This device complies with the limits for radio noise emissions from digital apparatus set out in the Radio Interference Regulations of the Canadian Department of Communications (DOC).

Le présent appareil numérique n’émiet pas de bruits radioélectriques dépassant les limites applicables aux appareils numériques de classe A prescrites dans le réglement sur le brouillage radioélectrique édicté par le ministére des communications du Canada.

Instructions to Users

These regulations are designed to provide reasonable protection against harmful interference from the equipment to radio reception in commercial areas. Operation of this equipment in a residential area is likely to cause harmful interference, in which case the user will be required to correct the interference at his own expense.

There is no guarantee that interference will not occur in a particular installation. However, the chances of interference are much less if the equipment is installed and used according to this instruction manual.

If the equipment does cause interference to radio or television reception, which can be determined by turning the equipment on and off, one or more of the following suggestions may reduce or eliminate the problem.

• Operate the equipment and the receiver on different branches of your AC electrical system.

• Move the equipment away from the receiver with which it is interfering.

• Reorient or relocate the receiver’s antenna.

• Be sure that the equipment is plugged into a grounded outlet and that the grounding has not been defeated with a cheater plug.

Notice to user: Changes or modifications not expressly approved by National Instruments could void the user’s

authority to operate the equipment under the FCC Rules.

If necessary, consult National Instruments or an experienced radio/television technician for additional suggestions. The following booklet prepared by the FCC may also be helpful: How to Identify and Resolve Radio-TV Interference Problems. This booklet is available from the U.S. Government Printing Office, Washington, DC 20402, Stock Number 004-000-00345-4.

Contents

About This Manual............................................................................................................ xiii

Organization of This Manual ........................................................................................ xiii

Conventions Used in This Manual ................................................................................ xiv

Related Documentation ................................................................................................. xiv

Customer Communication............................................................................................. xv

Chapter 1 Introduction

What Your Kit Should Contain..................................................................................... 1-3

Optional Equipment ...................................................................................................... 1-3

Unpacking ..................................................................................................................... 1-4

Chapter 2 General Description

Electrical Characteristics............................................................................................... 2-1

VMEbus Characteristics................................................................................................ 2-2

Data Transfer Features .................................................................................................. 2-7

GPIB-1014 Functional Description............................................................................... 2-8

.......................................................................................................................... 1-1

........................................................................................................... 2-1

VMEbus Slave-Addressing ............................................................................... 2-2

VMEbus Slave-Data.......................................................................................... 2-3

VMEbus Master-Direct Memory Access.......................................................... 2-5

Interrupter.......................................................................................................... 2-6

Data Transfer Bus (DTB) Requester................................................................. 2-7

VMEbus Modules Not Provided ........................................................... 2-7

Diagnostic Aids ................................................................................................. 2-7

Programmed I/O Transfers................................................................................ 2-8

Chapter 3 Configuration and Installation

Configuration................................................................................................................. 3-1

Access Mode ..................................................................................................... 3-3

Base Address ..................................................................................................... 3-3

Set Base Address Using Jumper Block W1 .......................................... 3-4

Set Base Address Using Compare Address Lines................................. 3-4

DMA Address Modifier Code Output............................................................... 3-5

Other Configuration Parameters........................................................................ 3-7

Installation..................................................................................................................... 3-7

Verification of System Compatibility ............................................................... 3-7

Cabling .............................................................................................................. 3-10

Verification Testing........................................................................................... 3-10

...................................................................................... 3-1

Chapter 4 Register Bit Descriptions

Register Map ................................................................................................................. 4-1

................................................................................................. 4-1

Contents

Interface Registers......................................................................................................... 4-3

Data In Register (DIR) ...................................................................................... 4-6

Command/Data Out Register (CDOR).............................................................. 4-7

Interrupt Status Register 1 (ISR1)..................................................................... 4-8

Interrupt Mask Register 1 (IMR1)..................................................................... 4-8

Interrupt Status Register 2 (ISR2)..................................................................... 4-14

Interrupt Mask Register 2 (IMR2)..................................................................... 4-14

Serial Poll Status Register (SPSR) .................................................................... 4-19

Serial Poll Mode Register (SPMR) ................................................................... 4-19

Address Status Register (ADSR) ...................................................................... 4-20

Address Mode Register (ADMR)...................................................................... 4-22

Command Pass Through Register (CPTR) ....................................................... 4-25

Auxiliary Mode Register (AUXMR) ................................................................ 4-27

Hidden Registers ............................................................................................... 4-33

Internal Counter Register (ICR)............................................................ 4-34

Parallel Poll Register (PPR) .................................................................. 4-35

Auxiliary Register A (AUXRA)............................................................ 4-37

Auxiliary Register B (AUXRB)............................................................ 4-39

Auxiliary Register E (AUXRE) ............................................................ 4-41

Address Register 0 (ADR0) .............................................................................. 4-42

Address Register (ADR) ................................................................................... 4-43

Address Register 1 (ADR1) .............................................................................. 4-44

End of String Register (EOSR) ......................................................................... 4-45

DMA Registers.............................................................................................................. 4-46

Address Registers.............................................................................................. 4-48

Transfer Count Registers................................................................................... 4-48

Function Code Registers ................................................................................... 4-50

Device Control Register .................................................................................... 4-51

Operation Control Register ............................................................................... 4-53

Sequence Control Register ................................................................................ 4-55

Channel Control Register .................................................................................. 4-56

Channel Status Register..................................................................................... 4-58

Channel Error Register...................................................................................... 4-60

Channel Priority Register .................................................................................. 4-61

Interrupt Vector Registers ................................................................................. 4-62

General Control Register................................................................................... 4-63

Configuration Registers..................................................................................... 4-64

Configuration Register 1 (CFG1).......................................................... 4-64

Configuration Register 2 (CFG2).......................................................... 4-66

Chapter 5 Programming Considerations

Initialization................................................................................................................... 5-1

The GPIB-1014 as GPIB Controller ............................................................................. 5-3

Becoming Controller-In-Charge (CIC) and Active Controller ......................... 5-3

Sending Remote Multiline Messages (Commands) .......................................... 5-4

Going from Active to Standby Controller......................................................... 5-4

GPIB-1014 User Manual viii © National Instruments Corporation

........................................................................................ 5-1

Contents

Going from Standby to Active Controller......................................................... 5-4

Going from Active to Idle Controller................................................................ 5-5

The GPIB-1014 as GPIB Talker and Listener............................................................... 5-6

Programmed Implementation of Talker and Listener ....................................... 5-6

Addressed Implementation of the Talker and Listener ..................................... 5-6

Address Mode 1..................................................................................... 5-6

Address Mode 2..................................................................................... 5-6

Address Mode 3..................................................................................... 5-7

Sending/Receiving Messages........................................................................................ 5-8

Using Direct Memory Access ........................................................................... 5-8

DMA Transfers without the Carry Cycle.............................................. 5-10

DMA Transfers with the Carry Cycle ................................................... 5-13

Polling During DMAs ........................................................................... 5-17

Sending END or EOS............................................................................ 5-17

Terminating the Transfer and Checking the Result............................... 5-17

Terminating on END or EOS ................................................................ 5-19

Using Programmed I/O ..................................................................................... 5-19

Sending and Receiving Data ................................................................. 5-19

Sending END or EOS............................................................................ 5-20

Terminating on END or EOS ................................................................ 5-20

Interrupts ....................................................................................................................... 5-20

Serial Polls..................................................................................................................... 5-22

Conducting a Serial Poll.................................................................................... 5-22

Responding to a Serial Poll ............................................................................... 5-22

Parallel Polls.................................................................................................................. 5-22

Conducting a Parallel Poll................................................................................. 5-23

Responding to a Parallel Poll ............................................................................ 5-24

Chapter 6 Theory of Operation

VMEbus Interface ......................................................................................................... 6-1

Data Lines.......................................................................................................... 6-1

Slave Read and Write Transfers............................................................ 6-1

DMA Transfers...................................................................................... 6-1

Control Signals.................................................................................................. 6-2

Address.............................................................................................................. 6-2

Control Equations of Transceivers.................................................................... 6-3

Address Decoding ......................................................................................................... 6-3

Clock and Reset Circuitry ............................................................................................. 6-4

Configuration Registers................................................................................................. 6-5

Configuration Register 1 ................................................................................... 6-5

Configuration Register 2 ................................................................................... 6-6

Timing State Machine ................................................................................................... 6-6

Slave Cycles ...................................................................................................... 6-6

DMA Cycles...................................................................................................... 6-7

DMA Gating and Control.............................................................................................. 6-7

Interrupter...................................................................................................................... 6-9

DTB Requester and Controller...................................................................................... 6-9

GPIB Synchronization and Interrupt Control................................................................ 6-12

.......................................................................................................... 6-1

Contents

68450 DMAC................................................................................................................ 6-14

DMAC Channel Operation................................................................................ 6-15

Initialization and Transfer Phases ......................................................... 6-15

Device (TLC)/DMAC Communication..................................... 6-15

DMA Requests ........................................................................ 6-16

Data Transfers ........................................................................... 6-16

Operands and Addressing.......................................................... 6-17

Address Register Operation....................................................... 6-17

Transfer Count Register Operation ........................................... 6-17

Initiation and Control of Channel Operation......................................... 6-18

Initiating the Operation ............................................................. 6-18

The Continue Mode of Operation ............................................. 6-18

Halt ............................................................................................ 6-18

Software Abort .......................................................................... 6-18

Interrupt Enable......................................................................... 6-19

Block Termination................................................................................. 6-19

Multiple Block Operations ........................................................ 6-19

Continued Operations................................................................ 6-19

Array Chaining Operations ....................................................... 6-19

Linked Chaining Operations ..................................................... 6-20

Error Conditions........................................................................ 6-21

GPIB Interface............................................................................................................... 6-23

Test and Troubleshooting.............................................................................................. 6-24

DMA Stand-Alone Testing ............................................................................... 6-24

GPIB Interface Testing...................................................................................... 6-24

Chapter 7 Diagnostic and Troubleshooting Test Procedures

Interpreting Test Procedures ......................................................................................... 7-1

GPIB-1014 Hardware Installation Tests ....................................................................... 7-2

Appendix A Hardware Specifications

.................................................................................................. A-1

Appendix B Parts List and Schematic Diagrams

............................................................................. B-1

Appendix C Sample Programs

............................................................................................................... C-1

Appendix D Multiline Interface Messages

......................................................................................... D-1

Appendix E Operation of the GPIB

Types of Messages ........................................................................................................ E-1

Talkers, Listeners, and Controllers................................................................................ E-1

The Controller-In-Charge and System Controller......................................................... E-2

GPIB Signals and Lines ................................................................................................ E-2

...................................................................................................... E-1

.................................................. 7-1

GPIB-1014 User Manual x © National Instruments Corporation

Data Lines.......................................................................................................... E-2

Handshake Lines ............................................................................................... E-2

NRFD (not ready for data) .................................................................... E-2

NDAC (not data accepted) .................................................................... E-3

DAV (data valid)................................................................................... E-3

Interface Management Lines............................................................................. E-3

ATN (attention) ..................................................................................... E-3

IFC (interface clear) .............................................................................. E-3

REN (remote enable)............................................................................. E-3

SRQ (service request)............................................................................ E-3

EOI (end or identify) ............................................................................. E-3

Physical and Electrical Characteristics.......................................................................... E-4

Configuration Requirements ......................................................................................... E-6

Related Documents........................................................................................................ E-7

Appendix F Mnemonics Key

................................................................................................................... F-1

Appendix G Customer Communication

Contents

.............................................................................................. G-1

Glossary ..................................................................................................................... Glossary-1

Index.................................................................................................................................. Index-1

Figures

Figure 1-1. GPIB-1014 Interface Board ............................................................................. 1-2

Figure 2-1. GPIB-1014 with a VMEbus Computer............................................................ 2-9

Figure 2-2. GPIB-1014 in a Multiprocessor Application ................................................... 2-10

Figure 2-3. GPIB-1014 Block Diagram.............................................................................. 2-11

Figure 3-1. Parts Locator Diagram ..................................................................................... 3-2

Figure 3-2. Access Mode After RESET ............................................................................. 3-3

Figure 3-3. Configuration for GPIB-1014 Base Address 2000 (hex)................................. 3-4

Figure 3-4. Default Settings of AM Code Jumpers W3, W4, and W5 ............................... 3-5

Figure 4-1. Interface Registers............................................................................................ 4-4

Figure 4-2. Writing to the Hidden Registers....................................................................... 4-5

Figure 4-3. DMA Register Memory Map........................................................................... 4-47

Figure 5-1. DMA Transfer without Carry Cycle ................................................................ 5-10

Figure 5-2. DMA Transfer with Carry Cycle ..................................................................... 5-13

Figure 6-1. DTB Requester and Controller Flip-Flop Operations...................................... 6-10

Figure 6-2. Array Format for Array Chaining Modes ........................................................ 6-20

Contents

Figure 6-3. Array Format for Linked Chaining Modes ...................................................... 6-21

Figure E-1. The GPIB Connector and Signal Assignments................................................ E-4

Figure E-2. Linear Configuration........................................................................................ E-5

Figure E-3. Star Configuration............................................................................................ E-6

Tables

Table 2-1. GPIB-1014 Signals............................................................................................ 2-1

Table 2-2. µPD7210 Internal GPIB Interface Registers..................................................... 2-3

Table 2-3. 68450 Internal DMA Registers ......................................................................... 2-4

Table 2-4. GPIB-1014 Configuration Registers ................................................................. 2-5

Table 2-5. GPIB-1014 IEEE 488 Interface Capabilities..................................................... 2-13

Table 2-6. GPIB-1014 IEEE 1014 Interrupter Compliance Levels.................................... 2-15

Table 3-1. Programming Values for Default Settings of W3, W4, and W5....................... 3-6

Table 3-2. Setting the Address Modifier Code Bits (AM5-AM0)...................................... 3-6

Table 3-3. GPIB-1014 Pin Assignment on VMEbus Connector P1................................... 3-8

Table 3-4. GPIB-1014 Pin Assignment on VMEbus Connector P2................................... 3-9

Table 4-1. GPIB-1014 Register Map.................................................................................. 4-1

Table 4-2. Clues to Understanding Mnemonics ................................................................. 4-3

Table 4-3. Multiline GPIB Commands Recognized by the µPD7210................................ 4-25

Table 4-4. Auxiliary Command Summary ......................................................................... 4-28

Table 4-5. Auxiliary Commands: Detail Description......................................................... 4-29

Table 4-6. Examples for Configuring the PPR................................................................... 4-36

Table 4-7. DMAC DMA Channel Register Set.................................................................. 4-46

Table 6-1. Control Equations of Transceivers.................................................................... 6-3

Table A-1. Electrical Characteristics................................................................................... A-1

Table A-2. Environmental Characteristics .......................................................................... A-1

Table A-3. Physical Characteristics..................................................................................... A-2

GPIB-1014 User Manual xii © National Instruments Corporation

About This Manual

The GPIB-1014 User Manual describes the mechanical and electrical aspects of the GPIB-1014, the data transfer features, and contains information concerning its operation and programming.

Organization of This Manual

The GPIB-1014 User Manual is organized as follows:

• Chapter 1, Introduction, describes the GPIB-1014, lists the contents and optional equipment for your GPIB-1014 kit, and explains how to unpack the GPIB-1014 kit.

• Chapter 2, General Description, contains the electrical specifications for the GPIB-1014, the data transfer features, and describes the characteristics of key interface board components.

• Chapter 3, Configuration and Installation, describes the steps needed to configure and install the GPIB-1014 hardware.

• Chapter 4, Register Bit Descriptions, contains a description of the register map, a list of interface registers, and a description of the DMA registers.

• Chapter 5, Programming Considerations, explains the initialization process, sending/receiving messages, and the serial/parallel poll process.

• Chapter 6, Theory of Operation, contains a functional overview of the GPIB-1014 board and explains the operation of each functional block making up the GPIB-1014.

• Chapter 7, Diagnostic and Troubleshooting Test Procedures, contains test procedures for determining if the GPIB-1014 is installed and operating correctly.

• Appendix A, Hardware Specifications, specifies the electrical, environmental, and physical characteristics of the GPIB-1014 board and the condition under which it should be operated.

• Appendix B, Parts List and Schematic Diagrams, contains the parts list and schematic diagrams for the GPIB-1014.

• Appendix C, Sample Programs, contains listings of routines in 68000 assembly language code that implement the essential elements of the major utility functions.

• Appendix D, Multiline Interface Messages, lists the multiline interface messages and describes the mnemonics and messages that correspond to the interface functions. These functions include initializing the bus, addressing and unaddressing devices, and setting device modes for local or remote programming. The multiline interface messages are IEEE 488-defined commands that are sent and received with ATN TRUE.

• Appendix E, Operation of the GPIB, describes the operation of the GPIB.

About This Manual

• Appendix F, Mnemonics Key, contains a mnemonics key that defines the mnemonics (abbreviations) used throughout this manual for functions, remote messages, local messages, states, bits, registers, integrated circuits, system functions, and VMEbus operations and signals.

• Appendix G, Customer Communication, contains forms for you to complete to facilitate communication with National Instruments concerning our products.

• The Glossary contains an alphabetical list and description of terms used in this manual, including abbreviations, acronyms, metric prefixes, and symbols.

• The Index contains an alphabetical list of key terms and topics used in this manual, including the pages where each one can be found.

Conventions Used in This Manual

The following conventions are used to distinguish elements of text throughout this manual: italic Italic text denotes emphasis, a cross reference, or an introduction to a key

concept.

IEEE 488 IEEE 488 is used throughout this manual to refer to the ANSI/IEEE

Standard 488.1-1987, which defines the GPIB.

IEEE 1014 IEEE 1014 is used throughout this manual to refer to the ANSI/IEEE

Standard 1014-1987, which defines the GPIB.

Customer Communication

National Instruments wants to receive your comments on our products and manuals. We are interested in the applications you develop with our products, and we want to help if you have problems with them. To make it easy for you to contact us, this manual contains comment and configuration forms for you to complete. These forms are in Appendix G, Customer

Communication, at the end of this manual.

Chapter 1 Introduction

This chapter describes the GPIB-1014, lists the contents and oiptional equipment for your GPIB-1014 kit, and explains how to unpack the GPIB-1014 kit.

The GPIB-1014 is a high-performance IEEE 488 interface for the VMEbus. This interface permits IEEE 488 compatible engineering, scientific, or medical instruments to be controlled from a VMEbus-based computer. The GPIB-1014 has the following features:

• Complete IEEE 488 Talker/Listener/Controller (TLC) capability using the NEC µPD7210

GPIB TLC chip

• DMA transfers

- Data rates up to 500 kbytes/sec

- Unlimited data block lengths

- Full 24-bit addressing

- GPIB synchronization detection

- General purpose DMA capability

• Complete software control through programmable configuration parameters

- One out of four Bus Request/Grant lines

- One out of seven Interrupt Request lines

- Supervisor or User access

- Red/Green SYSFAIL LED indicator

- Local Master Reset

• VME laboratories certified

• IEEE 1014 (VMEbus) standard compliance

• Comprehensive software support

Introduction Chapter 1

Art not available in PDF version of document.

Figure 1-1 shows the GPIB-1014 interface board.

Figure 1-1. GPIB-1014 Interface Board

GPIB-1014 User Manual 1-2 © National Instruments Corporation

Chapter 1 Introduction

The GPIB-1014 interface kit includes hardware and programming examples to implement the GPIB functions. Optional cables are supplied for interconnection with other devices on the GPIB.

What Your Kit Should Contain

Your GPIB-1014 kit should contain the following components:

Kit Component Part Number

One of these GPIB-1014 boards:

• GPIB-1014-1 776059-01

• GPIB-1014-2 776060-01

• GPIB-1014-EH (EH=Ejector Handles) 776059-51

• GPIB-1014-1S (no P2 signals) 776059-21

• GPIB-1014-1S-EH (no P2 signals; EH=Ejector Handles) 776059-61 One GPIB-1014 User Manual 320030-01

Optional Equipment

Equipment Part Number

Single-Connector Scrambler Interface Card 180170-01 Dual-Connector Scrambler Interface Card 180170-02

Scrambler Card to P2 Cable Assembly 180173-01 Single-Shielded Cables:

GPIB Type X1 Cable - 1 m 763001-01 GPIB Type X1 Cable - 2 m 763001-02 GPIB Type X1 Cable - 4 m 763001-03

GPIB Monitor/Analyzer:

GPIB-400 776074-01 GPIB-410 776104-01

Introduction Chapter 1

Unpacking

Follow these steps when unpacking your GPIB-1014.

1. Verify that the pieces contained in the package you received match the kit parts list given earlier in this chapter. Do not remove the board from its plastic bag at this point.

2. Your GPIB-1014 board is shipped packaged in an antistatic plastic bag to prevent electrostatic damage to the board. Several components on the board can be damaged by electrostatic discharge. To avoid such damage in handling the board, touch the plastic bag to a metal part of your VMEbus computer chassis before removing the board from the bag.

3. Remove the board from the bag and inspect the board for loose components or any other sign of damage. Notify National Instruments if the board appears damaged in any way. Do not install a damaged board into your computer.

GPIB-1014 User Manual 1-4 © National Instruments Corporation

Chapter 2 General Description

This chapter contains the electrical specifications for the GPIB-1014, the data transfer features, and describes the characteristics of key interface board components.

Electrical Characteristics

All integrated circuit drivers and receivers used on the GPIB-1014 meet the requirements of the VMEbus specification and the IEEE 1014 standard. Table 2-1 contains a list of the VMEbus signals used by the GPIB-1014 and the electrical loading presented by the circuitry on the interface board (in terms of device types and their part numbers).

Note: The asterisk (*) after the bus signal indicates that the signal is active low.

Table 2-1. GPIB-1014 Signals

Driver Device Receiver Device

Bus Signals Part Number Part Number

D00-D15 F245 F245 A23-A16 AS573 – A15-A09 AS573 LS2521 A8 AS573 F1241 A07-A01 F245 F245 AM5-AM3, AM0 F241 LS2521 AM2 F241 LS240 DS0*, DS1*, AS*, WRITE* F241 F1241 LWORD* F241 LS2521 IACK* F241 F1241 SYSCLK – LS240 BG0IN*-BG3IN* – LS241 BG0OUT*-BG3OUT* F241 – DTACK* AS756 LS240

(continues)

General Description Chapter 2

Table 2-1. GPIB-1014 Signals (continued)

Driver Device Receiver Device

Bus Signals Part Number Part Number

BR0*-BR3* AS756 LS241 BBSY* AS756 LS240 IACKIN* – LS240 IACKOUT* F1241 – IRQ1*-IRQ7* 74145 – BERR* – F1241 SYSFAIL* AS756 – SYSRESET* – LS240

All GPIB transceivers meet the requirements of the IEEE 488 standard. The components used are as follows:

Transceivers Component Designation

Data Transceivers DS75160AN Control Transceivers DS75162AN

Note: The GPIB-1014 requires regulated +5 VDC power from the VMEbus. Current load is

typically 1.6 A (2.0 A maximum).

VMEbus Characteristics

The following paragraphs describe each of the VMEbus modules on the GPIB-1014: slave, master, interrupter, and requester. Table 2-5 at the end of this chapter summarizes the capabilities of these modules.

VMEbus Slave-Addressing

The GPIB-1014 occupies 512 bytes (256 words) in the A16 (short) I/O space. As a VMEbus slave, it only responds when the address modifier (AM) lines specify a short supervisory access (AM code = 2D) or a short nonprivileged access (AM code = 29). The board responds to short 16-bit addresses. The GPIB-1014 compares address lines A15 through A9 with its base address

GPIB-1014 User Manual 2-2 © National Instruments Corporation

Chapter 2 General Description

to generate its board select signal. It then decodes the lowest eight lines, A8 through A1, to address the following items:

• The 68450 DMA Controller (DMAC)

• The µPD7210 GPIB Talker/Listener/Controller (TLC)

• Two 8-bit, write-only Configuration Registers

You can configure the base address of the board through the hardware jumper set W1 located on the interface board. Except for the models GPIB-1014-1S and GPIB-1014-1S-EH, the base address can also be set using strapped address lines located on the VMEbus P2 connector. See Chapter 3, Configuration and Installation, on how to set the base address of the board.

VMEbus Slave-Data

The GPIB-1014 can function as a VMEbus slave, decoding short I/O addresses and commands from a VMEbus master. The µPD7210 and the two Configuration Registers function as 8-bit slaves, allowing data to be transferred to and from the VMEbus Master on data lines D07 through D00. The 68450 can function as an 8- or 16-bit slave, allowing transfers on data lines D15 through D00. The board is designed to accommodate Address Only (ADO) cycles. In VMEbus terminology, the slave module of the board is designated as D16 & D08(EO).

The GPIB Interface Registers associated with the µPD7210 are addressed relative to the base address of the board, as shown in Table 2-2. The DMA registers internal to the 68450 are shown in Table 2-3. The two Configuration Registers of the GPIB-1014 are shown in Table 2-4.

Table 2-2. µPD7210 Internal GPIB Interface Registers

Address

(Base + Hex Offset) Mode Register Size

111 R Data In (DIR) 8 bits 111 W Command/Data Out (CDOR) 8 bits 113 R Interrupt Status 1 (ISR1) 8 bits 113 W Interrupt Mask 1 (IMR1) 8 bits 115 R Interrupt Status 2 (ISR2) 8 bits 115 W Interrupt Mask 2 (IMR2) 8 bits 117 R Serial Poll Status (SPSR) 8 bits 117 W Serial Poll Mode (SPMR) 8 bits 119 R Address Status (ADSR) 8 bits

119 W Address Mode (ADMR) 8 bits 11B R Command Pass Through (CPTR) 8 bits 11B W Auxiliary Mode (AUXMR) 8 bits

11D R Address 0 (ADR0) 8 bits 11D W Address (ADR) 8 bits

11F R Address 1 (ADR1) 8 bits 11F W End of String (EOSR) 8 bits

General Description Chapter 2

Table 2-3. 68450 Internal DMA Registers

Address (Base

+ Hex Offset) Mode Register Channel Size

0A R/W Memory Transfer Counter (MTCR0) 0 16 bits 0C R/W Memory Address Register (MAR0) 0 32 bits 29 R/W Memory Function Code (MFCR0) 0 8 bits 14 R/W Device Address Register (DAR0) 0 32 bits 31 R/W Device Function Code (DFCR0) 0 8 bits 1A R/W Base Transfer Counter (BTCR0) 0 16 bits 1C R/W Base Address Register (BAR0) 0 32 bits 39 R/W Base Function Code (BFCR0) 0 8 bits 00 R/W Channel Status (CSR0) 0 8 bits 01 R Channel Error (CER0) 0 8 bits 04 R/W Device Control (DCR0) 0 8 bits 05 R/W Operation Control (OCR0) 0 8 bits 06 R/W Sequence Control (SCR0) 0 8 bits 07 R/W Channel Control (CCR0) 0 8 bits 2D R/W Channel Priority (CPR0) 0 8 bits 25 R/W Normal Interrupt Vector (NIVR0) 0 8 bits 27 R/W Error Interrupt Vector (EIVR0) 0 8 bits

4A R/W Memory Transfer Counter (MTCR1) 1 16 bits 4C R/W Memory Address Register (MAR1) 1 32 bits 69 R/W Memory Function Code (MFCR1) 1 8 bits 54 R/W Device Address Register (DAR1) 1 32 bits 71 R/W Device Function Code (DFCR1) 1 8 bits 5A R/W Base Transfer Counter (BTCR1) 1 16 bit 5C R/W Base Address Register (BAR1) 1 32 bits 79 R/W Base Function Code (BFCR1) 1 8 bits 40 R/W Channel Status (CSR1) 1 8 bits 41 R Channel Error (CER1) 1 8 bits 44 R/W Device Control (DCR1) 1 8 bits 45 R/W Operation Control (OCR1) 1 8 bits 46 R/W Sequence Control (SCR1) 1 8 bits 47 R/W Channel Control (CCR1) 1 8 bits 6D R/W Channel Priority (CPR1) 1 8 bits 65 R/W Normal Interrupt Vector (NIVR1) 1 8 bits 67 R/W Error Interrupt Vector (EIVR1) 1 8 bits

8A R/W Memory Transfer Counter (MTCR2) 2 16 bits 8C R/W Memory Address Register (MAR2) 2 32 bits A9 R/W Memory Function Code (MFCR2) 2 8 bits 94 R/W Device Address Register (DAR2) 2 32 bits B1 R/W Device Function Code (DFCR2) 2 8 bits 9A R/W Base Transfer Counter (BTCR2) 2 16 bits 9C R/W Base Address Register (BAR2) 2 32 bits B9 R/W Base Function Code (BFCR2) 2 8 bits 80 R/W Channel Status (CSR2) 2 8 bits 81 R Channel Error (CER2) 2 8 bits 84 R/W Device Control (DCR2) 2 8 bits

(continues)

GPIB-1014 User Manual 2-4 © National Instruments Corporation

Chapter 2 General Description

Table 2-3. 68450 Internal DMA Registers (continued)

Address (Base + Hex Offset) Mode Register Channel Size

85 R/W Operation Control (OCR2) 2 8 bits 86 R/W Sequence Control (SCR2) 2 8 bits 87 R/W Channel Control (CCR2) 2 8 bits AD R/W Channel Priority (CPR2) 2 8 bits A5 R/W Normal Interrupt Vector (NIVR2) 2 8 bits A7 R/W Error Interrupt Vector (EIVR2) 2 8 bits

CA R/W Memory Transfer Counter (MTCR3) 3 16 bits CC R/W Memory Address Register (MAR3) 3 32 bits E9 R/W Memory Function Code (MFCR3) 3 8 bits D4 R/W Device Address Register (DAR3) 3 32 bits F1 R/W Device Function Code (DFCR3) 3 8 bits DA R/W Base Transfer Counter (BTCR3) 3 16 bits DC R/W Base Address Register (BAR3) 3 32 bits F9 R/W Base Function Code (BFCR3) 3 8 bits C0 R/W Channel Status (CSR3) 3 8 bits C1 R Channel Error (CER3) 3 8 bits C4 R/W Device Control (DCR3) 3 8 bits C5 R/W Operation Control (OCR3) 3 8 bits C6 R/W Sequence Control (SCR3) 3 8 bits C7 R/W Channel Control (CCR3) 3 8 bits ED R/W Channel Priority (CPR3) 3 8 bits E5 R/W Normal Interrupt Vector (NIVR3) 3 8 bits E7 R/W Error Interrupt Vector (EIVR3) 3 8 bits

FF R/W General Control Register (GCR) all 8 bits

Table 2-4. GPIB-1014 Configuration Registers

Address

(Base + Hex Offset) Mode Register Size

101 W Configuration Register 1 8 bits

105 W Configuration Register 2 8 bits

VMEbus Master-Direct Memory Access

The GPIB-1014 can function as a VMEbus master, performing data transfers to and from VMEbus memory. In most applications, the 68450 controls the data transfer to and from the GPIB during DMA, and can transfer the 8-bit data on data lines D07 through D00 or D15 through D08, allowing the packing of data in VMEbus memory. In addition to GPIB-to-VMEbus memory DMA transfers, the board can also perform 8- or 16-bit memory-to-memory DMA transfers.

General Description Chapter 2

Memory addresses generated by the GPIB-1014 are 24 bits wide and the VMEbus Address Modifier Lines (AM5 through AM0) are fully programmable using function code registers located in the 68450 and three hardware jumpers (W3, W4, and W5). (See Chapter 3 for instructions on setting the hardware jumpers. See Chapter 4 for a description of the DMAC Function Code Registers.) The 24-bit addresses, along with selectable Address Modifier codes, eliminate artificial memory boundaries and allow data transfers between the GPIB and data area, program area, or even devices located in the short I/O area. In VMEbus terminology, the GPIB-1014 has A24 / D08(EO) & D16 master capability. The board does not use Unaligned Transfer (UAT), Block Transfer (BLT), or Read Modify Write (RMW) cycles. The chaining feature of the 68450 allows data blocks of unlimited size to be transferred.

Interrupter

Interrupt events that can drive a hardware-programmed VMEbus interrupt request line are as follows:

• GPIB Data In (DI) • Address Status Change (ADSC)

• GPIB Data Out (DO) • Secondary Address Pass Through (APT)

• END Message Received (END RX) • Service Request Input (SRQI)

• GPIB Command Out (CO) • Device Execute Trigger (DET)

• Remote Mode Change (REMC) • Device Clear received (DEC RX)

• GPIB Handshake Error (ERR) • Command Pass Through (CPT)

• Lockout Change (LOKC) • Bus Error (BERR)

• GPIB DMA Transfer Finished and GPIB Synchronized (FIN)

You can select one of seven VMEbus interrupt request lines (IRQ1* through IRQ7*) through software using three bits located in Configuration Register 1.

The onboard hardware implements the VMEbus interrupt acknowledge protocol. Interrupt Vector Registers located in the 68450 let you select, through software, the 8-bit Interrupt Status/ID byte supplied by the GPIB-1014 during an interrupt acknowledge cycle of the correct priority. The GPIB-1014 is a D08(O) interrupter, because it responds to an interrupt acknowledge cycle by providing an 8-bit status/ID byte on data lines D00 through D07. In addition, the board is a Release On Register Access (RORA) interrupter, because it releases its interrupt line when the Channel Status Register is written with the proper value. In VMEbus terminology, the GPIB-1014 has D08(O) / RORA Interrupter capability.

GPIB-1014 User Manual 2-6 © National Instruments Corporation

Chapter 2 General Description

Data Transfer Bus (DTB) Requester

The GPIB-1014 arbitrates for the DTB before each DMA transfer. The board is designed for you to select, through software, one of four VMEbus request lines (BR0* through BR3*) using two bits in Configuration Register 1. To maximize the capabilities of the DTB, the board can be programmed to become a Release On Request (ROR) DTB master. Unless programmed, the GPIB-1014 is a Release When Done (RWD) master.

VMEbus Modules Not Provided

Because the GPIB-1014 is not designed to be VMEbus System Controller, it does not have the following modules:

• Bus Timer

• Arbiter

• Interrupt Handler

• IACK Daisy-Chain Driver

• System Clock Driver

• Serial Clock Driver

• Power Monitor

Diagnostic Aids

The GPIB-1014 is designed to allow stand-alone verification of I/O and DMA functions. See Chapter 7, Diagnostic and Troubleshooting Test Procedures, for details.

Data Transfer Features

The GPIB-1014 can be used to transfer data to and from the GPIB using Direct Memory Access (DMA) and programmed I/O. The overall throughput is dependent upon the following parameters:

• The number of GPIB commands sent

• The amount of time spent setting up the GPIB-1014 DMA transfers

• The size of the DMA data buffers (number of bytes transferred in one DMA operation)

• Operating system overhead

• Interrupt service time

• VMEbus memory response time (DS* low to DTACK* low)

General Description Chapter 2

• GPIB Listener response time (DAV* low to NDAC* high)

• GPIB Talker response time (NRFD* high to DAV* low)

• GPIB-1014 transfer mode: Cycle Steal with hold, programmable timeout

• T1 timing: high-speed

Transfer rates of 250 to 350 kbytes/sec can be expected in typical systems, and rates up to 500 kbytes/sec can be achieved under optimum conditions.

Programmed I/O Transfers

The GPIB-1014 is able to transfer data to and from the GPIB using programmed I/O. Transfer rates using programmed I/O depend on many factors including how fast the program code executes, how fast the microprocessor services interrupts, and the operating system overhead. Typically, the GPIB-1014 transfers data at rates ranging from 10 to 80 kbytes/sec using programmed I/O.

GPIB-1014 Functional Description

In the simplest terms, the GPIB-1014 can be thought of as a bus translator, converting messages and signals present on the VMEbus into appropriate GPIB messages and signals. Expressed in GPIB terminology, the GPIB-1014 implements GPIB interface functions for communicating with other GPIB devices and device functions for communicating with the central processor and memory. Expressed in VMEbus terminology, the GPIB-1014 is an interface to the outside world.

Figures 2-1 and 2-2 show typical applications for the GPIB-1014. In Figure 2-1, the GPIB-1014 is used to interface an assortment of test instruments to a VMEbus computer system, which then functions as an intelligent System Controller. This is the traditional role of the GPIB.

In Figure 2-2, the GPIB-1014 is used along with other National Instruments interface boards to connect a VMEbus computer to other processors to transfer files electrically rather than manually (via a removable storage medium) or to perform other interprocessor communication functions.

GPIB-1014 User Manual 2-8 © National Instruments Corporation

Chapter 2 General Description

Device A

VMEbus Computer with GPIB-1014

Able to Talk, Listen, and Control

Device C

Digital

Voltmeter

Able to Talk

and Listen

8 Lines

3 Lines

Frequency

Counter

Able to Talk

Device B

Printer

Able to Listen

Data Lines DIO1-DIO8

Handshake Lines DAV (Data Valid)

NRFD (Not Ready for Data) NDAC (Not Data Accepted)

Management Lines

5 Lines

IFC (Interface Clear) ATN (Attention) SRQ (Service Request)

REN (Remote Enable) EOI (End or Identify)

Figure 2-1. GPIB-1014 with a VMEbus Computer

General Description Chapter 2

R&D Lab

Microprocessor Work Station

VMEbus Computer with GPIB-1014 IEEE 488 Interface

Computer Center

IBM PC with GPIB-PC IEEE 488 Interface

GPIB-100 Bus Extender

Up to 300 Meters (RS-422)

GPIB-100 Bus Extender

Production & Testing

PDP 11/44 with GPIB11-2 IEEE 488 Interface

S-100 Computer GPIB-696P IEEE 488 Interface

Figure 2-2. GPIB-1014 in a Multiprocessor Application

GPIB-1014 User Manual 2-10 © National Instruments Corporation

Chapter 2 General Description

Figure 2-3 is a block diagram of the GPIB-1014.

GPIB

Configuration

Data

T ransceivers

Control

T ransceivers

Registers

µPD7210

Address

Decoding

Address

Transceivers

TLC

Address

State

Timing

Data

Transceivers

DTB Control

Machine

Data

Transceivers

68450 DMAC

Interrupter

and Control

DMA Gating

GPIB

Synchronization

DTB

Requester

and Interrupt Control

Clock and

Reset Circuitry

Data T ransfer Bus

Priority Interrupt

VMEbus

DTB Arbitration

Utility

Figure 2-3. GPIB-1014 Block Diagram

General Description Chapter 2

The interface consists of these major components, which are discussed in greater detail in Chapter 6.

• VMEbus Interface Consists of the buffers, drivers, and transceivers for the

address, data, status, and control lines used on the VMEbus, plus other logic circuitry that converts internal signals to bus-compatible signals.

• Address Decoder Recognizes when the VMEbus master addresses one of the

GPIB-1014 registers and generates the appropriate strobe to begin the data transfer.

• Clock and Reset Circuitry Monitors the VMEbus utility signals to generate the 8-MHz

clock used by the TLC and DMAC and to detect System Reset, Power Failure, and Bus Error conditions.

• Configuration Registers Programmably configures some of the operating parameters

of the GPIB-1014.

• Timing State Machine Controls the timing of DMA transfers and accesses to the

GPIB-1014 from the VMEbus.

• DMA Gating and Control Controls the DMA request/acknowledge interface between

the DMAC and the TLC.

• Interrupter Implements the VMEbus priority interrupt protocol,

allowing the GPIB-1014 to request and respond to an interrupt acknowledge cycle. All interrupt conditions are also detectable by polling.

• DTB Control Transceivers Performs the necessary VMEbus protocol to request,

obtain, and release control of the VME system bus. Once configured for a DMA transfer, the GPIB-1014 automatically performs data transfers between the GPIB and VMEbus memory.

• GPIB Synchronization and Detects the synchronization of the GPIB after the last byte Interrupt Control in a DMA transfer (all devices on the GPIB have accepted

the last byte) and detects interrupting conditions from the TLC. TLC interrupt requests are routed through the DMAC, which notifies the Interrupter when either a TLC interrupt or one of its own internal interrupt conditions is detected.

• DMAC (68450) Controls DMA transfers between the GPIB and the

VMEbus. The DMA Gating and Control circuitry controls the DMA request/acknowledge interface between the TLC and the DMAC.

• GPIB TLC (NEC µPD7210) Implements many of the GPIB interface functions, either

independently or with assistance of or interpretation by the controlling program. Together with special transceivers, the TLC forms the GPIB interface side of the GPIB-1014.

GPIB-1014 User Manual 2-12 © National Instruments Corporation

Chapter 2 General Description

Table 2-5 lists the capabilities of the GPIB-1014 in terms of the IEEE 488 standard codes.

Table 2-5. GPIB-1014 IEEE 488 Interface Capabilities

Capability Code Description

SH1 Complete Source Handshake capability AH1 Complete Acceptor Handshake capability DAC and RFD

Holdoff on certain events

T5 Complete Talker capability

Basic Talker Serial Poll Talk Only mode Unaddressed on MLA Send END or EOS Dual primary addressing

TE5 Complete Extended Talker capability

Basic Extended Talker Serial Poll

TE5 Complete Extended Talker capability (continued)

Talk Only mode Unaddressed on MSA*LPAS Send END or EOS Dual primary addressing

L3 Complete Listener capability

Basic Listener Listen Only mode Unaddressed on MTA Detect END or EOS Dual extended addressing with software assist

LE3 Complete Extended Listener capability

Basic Listener Listen Only mode Unaddressed on MSA*TPAS Detect END or EOS Dual extended addressing with software assist

SR1 Complete Service Request capability RL1 Complete Remote/Local capability with software

interpretation PP1 Remote Parallel Poll configuration PP2 Local Parallel Poll configuration with software assist

(continues)

General Description Chapter 2

Table 2-5. GPIB-1014 IEEE 488 Interface Capabilities (continued)

Capability Code Description

DC1 Complete Device Clear capability with software

interpretation DT1 Complete Device Trigger capability with software

interpretation

C1, C2, C3, C4, C5 Complete Controller capability

System Controller Send IFC and take charge Send REN Respond to SRQ Send interface messages Receive control Pass control Parallel Poll Take control synchronously or asynchronously

E1, E2 Tri-state bus drivers with automatic switch to open

Collector drivers during Parallel Poll

The GPIB-1014 has complete Source and Acceptor Handshake capability.

• The GPIB-1014 can operate as a basic Talker or Extended Talker and can respond to a Serial Poll. It can be placed in a Talk Only mode and is unaddressed to talk when it receives its listen address.

• The interface can operate as a basic Listener or Extended Listener. It can be placed in a Listen Only mode and is unaddressed to listen when it receives its talk address.

The GPIB-1014 has full capabilities for requesting service from another Controller. The ability to place the GPIB-1014 in local mode is included, but the interpretation of remote versus local mode is software-dependent. Full Parallel Poll capability is included in the interface, although local configuration requires software assistance. Device Clear and Trigger capability is included in the interface, but the interpretation is software-dependent. All Controller functions, as indicated by the IEEE 488 standard, are included in the GPIB-1014. These include the capability to do the following functions:

• Be System Controller

• Initialize the interface

• Send Remote Enable

• Respond to Service Request

• Send multiline command messages

GPIB-1014 User Manual 2-14 © National Instruments Corporation

Chapter 2 General Description

• Receive control

• Pass control

• Conduct a Parallel Poll

• Take control synchronously or asynchronously

Table 2-6 contains the GPIB-1014 IEEE 1014 compliance levels.

Table 2-6. GPIB-1014 IEEE 1014 Interrupter Compliance Levels

Compliance Notation Description

Bus Slave Compliance Levels

D8(O) 8-bit data path to TLC and two Configuration Registers D16 & D8(EO) 8- or 16-bit data path to DMAC registers A16 Responds to 16-bit short I/O addresses when specified

on the address modifier lines.

ADO Accommodate Address Only cycles

Interrupter Compliance Levels

D8(O) Provides an 8-bit status/ID byte on D00-D07 RORA Releases its interrupt request line when an onboard

Bus Master Compliance Levels

D8(EO) 8-bit data path for GPIB DMA transfers D16 & D8(EO) 8- or 16-bit memory-to-memory DMA transfers A24 24-bit memory address path

DTB Requester Compliance Level

ROR Programmable Release on Request Feature

Chapter 3 Configuration and Installation

This chapter describes the steps needed to configure and install the GPIB-1014 hardware.

Configuration

Before installing the GPIB-1014 in the VMEbus backplane, the following options must be configured with hardware jumpers that are located on the GPIB-1014 interface board:

• Access Mode (jumper W2)

• Base Address (jumper block W1)

• DMA Address Modifier (AM) Code Output (jumpers W3, W4, and W5)

Configuration and Installation Chapter 3

Art not available in PDF version of document.

Figure 3-1 shows the locations of the GPIB-1014 configuration jumpers and switches.

Figure 3-1. Parts Locator Diagram

GPIB-1014 User Manual 3-2 © National Instruments Corporation

Chapter 3 Configuration and Installation

Access Mode

The GPIB-1014 can be configured to respond to Supervisor (privileged) or User (non-privileged) access. Hardware jumper W2 is used to select the access mode that is automatically in effect upon a power-up or a system reset. The access mode then can be changed by software via a bit in Configuration Register 2. Figure 3-2 shows the placement of the jumper for the desired mode after a power-up or a system reset. Move the jumper to the side labeled S for Supervisor mode, or to the side labeled U for User mode. Supervisor mode is the default setting configured at the factory. If the board is configured for Supervisor mode, it will initially respond to a 16-bit address and an AM code of 2D. If the board is configured for User mode, the board will initially respond to a 16-bit address and AM codes of 29 and 2D. (Refer to the ANSI/IEEE Std. 1014-1987, IEEE Standard for a Versatile Backplane Bus: VMEbus for more information on Supervisor and User modes.)

a. Supervisor b. User

Figure 3-2. Access Mode After RESET

Base Address

The GPIB-1014 occupies a total of 512 bytes of 16-bit I/O space. The base address is selected with either hardware jumper block W1 on the interface board or compare address lines located on the P2 connector. The 1S and 1S-EH versions of the GPIB-1014 do not have compare address lines located on the P2 connector.

Note: If the base address is configured using the onboard jumpers, the lines must not

be strapped on the P2 connector. Likewise, if the base address is configured on the P2 connector, the jumpers provided on the interface board must be removed.

Configuration and Installation Chapter 3

Set Base Address Using Jumper Block W1

Move the jumper to the side labeled 1 to select a logical one for the corresponding address bit, or to the side labeled 0 to select a logical zero. Figure 3-3 shows the configuration for a base address 2000 (hex), which is the default address configured at the factory.

1 W1

15 9BASE ADD

Figure 3-3. Configuration for GPIB-1014 Base Address 2000 (hex)

(Default Setting)

Set Base Address Using Compare Address Lines

Another method of setting the base address is to use the compare address lines located on the P2 connector. The jumpers on jumper block W1 must be removed and TTL-compatible voltages must be applied to pins CA9 through CA15 on the P2 connector when using this method. Refer to Table 3-4 for the pin assignment numbers of the P2 connector. A scrambler card and interface cable assembly (described under Cabling later in this chapter), available from National Instruments, are necessary when setting the base address of the board using this method.

GPIB-1014 User Manual 3-4 © National Instruments Corporation

Chapter 3 Configuration and Installation

DMA Address Modifier Code Output

During a DMA cycle, the GPIB-1014 sends out a 6-bit Address Modifier (AM) code to the VMEbus lines AM5 through AM0. The correct code is obtained by both programming the DMAC and setting jumpers W3, W4, and W5. Figure 3-4 shows the default settings of W3, W4, and W5.

Note: Because jumper W5 is not located near jumpers W3 and W4, Figure 3-4 outlines and

labels the components on the GPIB-1014 interface board that are found between jumper W5 and the other jumpers.

AM1' AM1

F245 F322

U32 C33 U33

0110US

68450

Figure 3-4. Default Settings of AM Code Jumpers W3, W4, and W5

Rev. D and earlier versions of the GPIB-1014 do not have jumpers W3, W4, and W5. If all of the jumpers on later versions of the board remain in their factory default settings, the address modifier codes generated are equivalent to those generated by the earlier versions.

The GPIB-1014 can produce eight AM codes from the default settings of W3, W4, and W5. These eight codes are the most commonly used. Table 3-1 lists these AM codes next to the corresponding DMAC Function Code Register (FCR) values needed to produce the codes. (See Chapter 4 for a description of the DMAC FCR.)

Configuration and Installation Chapter 3

Table 3-1. Programming Values for Default Settings of W3, W4, and W5

FCR Bits

AM Codes M2 through M0

29 000 2A 001 2D 100 2E 101 39 010 3A 011 3D 110 3E 111

If it is necessary to produce a code other than those listed in Table 3-1, you can produce any arbitrary AM code by changing jumpers W3, W4, and W5 along with programming the DMAC.

Table 3-2 shows how each of the six AM code bits is affected by the jumpers and the values of the DMAC's FCR bits.

Table 3-2. Setting the Address Modifier Code Bits (AM5-AM0)

AM Bits Controlled By Value Default

AM(5) Jumper W3 0 or 1 1 AM(4) Bit M1 in FCR 0 or 1 None AM(3) Jumper W4 0 or 1 1

AM(2) Bit M2 in FCR 0 or 1 None AM(1) Bit M0 in FCR 0 or 1 None AM(0) Jumper W5 AM(1) or AM(1)' AM(1)'

GPIB-1014 User Manual 3-6 © National Instruments Corporation

Chapter 3 Configuration and Installation

For example, to produce an AM code of 17 hex (a binary value of 010111), complete the following steps:

1. Set jumper W3 to 0.

2. Set jumper W4 to 0.

3. Set jumper W5 to AM(1).

4. Write the pattern 00000111 to the FCR of the DMAC.

Other Configuration Parameters

All other configuration parameters for the GPIB-1014 are software-selectable, including the following:

• Selecting one of seven interrupt request lines (IRQ1* through IRQ7*)

• Selecting one of four Bus Request lines (BR0* through BR3*)

• Enabling the Release On Request (ROR) feature

• Selecting the automatic carry cycle feature

• Enabling the GPIB-1014 to be the GPIB System Controller

• Selecting the color of front panel SYSFAIL LED indicator (Red/Green)

• Selecting the DMA transfer mode Software control of these parameters gives you the flexibility to tailor operation and performance

to meet the specific requirements of separate tasks within your system.

Installation

The GPIB-1014 is a dual-height board that interfaces to the VMEbus P1 and P2 connectors. There are two options for the GPIB I/O from the GPIB-1014 interface board. The following paragraphs describe the GPIB-1014 interface to the VMEbus backplane and to the IEEE 488 bus.

Verification of System Compatibility

The GPIB-1014 does not use all of the signals included in the VMEbus specification. Compare signals listed in Tables 3-3 and 3-4 to those signals used by the VMEbus system in which the GPIB-1014 will be installed. This is to ensure that the two are compatible (that is, the GPIB-1014 has all the necessary signals needed by the system and vice versa).

Note: For models GPIB-1014-1S and GPIB-1014-1S-EH, there are no signals connected to the

P2 connector except for power (+5 V) and ground signals.

Configuration and Installation Chapter 3

Table 3-3. GPIB-1014 Pin Assignment on VMEbus Connector P1

Pin No. Signal Used Signal Not Used Pin No. Signal Used Signal Not Used

A1 D00 A17 GND A2 D01 A18 AS* A3 D02 A19 GND A4 D03 A20 IACK* A5 D04 A21 IACKIN* A6 D05 A22 IACKOUT* A7 D06 A23 AM4 A8 D07 A24 A07 A9 GND A25 A06 A10 SYSCLK A26 A05 A11 GND A27 A04 A12 DS1* A28 A03 A13 DS0* A29 A02 A14 WRITE* A30 A01 A15 GND A31 -12V A16 DTACK* A32 +5V

B1 BBSY* B17 AM1 B2 BCLR* B18 AM2 B3 ACFAIL* B19 AM3 B4 BG0IN* B20 GND B5 BG0OUT* B21 SERCLK B6 BG1IN* B22 SERDAT B7 BG1OUT* B23 GND B8 BG2IN* B24 IRQ7* B9 BG2OUT* B25 IRQ6* B10 BG3IN* B26 IRQ5* B11 BG3OUT* B27 IRQ4* B12 BR0* B28 IRQ3* B13 BR1* B29 IRQ2* B14 BR2* B30 IRQ1* B15 BR3* B31 +5V STDBY B16 AM0 B32 +5V

C1 D08 C17 A21 C2 D09 C18 A20 C3 D10 C19 A19 C4 D11 C20 A18 C5 D12 C21 A17 C6 D13 C22 A16 C7 D14 C23 A15 C8 D15 C24 A14 C9 GND C25 A13 C10 SYSFAIL* C26 A12 C11 BERR* C27 A11 C12 SYSRESET* C28 A10 C13 LWORD* C29 A09 C14 AM5 C30 A08 C15 A23 C31 +12V C16 A22 C32 +5V

GPIB-1014 User Manual 3-8 © National Instruments Corporation

Chapter 3 Configuration and Installation

Table 3-4. GPIB-1014 Pin Assignment on VMEbus Connector P2

Signal Signal Signal Signal

Pin No. Used Not Used Notes Pin No. Used Not Used Notes

A1 CA15 1,4 A17 User I/O A2 CA13 1,4 A18 User I/O A3 CA11 1,4 A19 User I/O A4 CA9 1,4 A20 User I/O A5 User I/O A21 DIO5* 2,4 A6 User I/O A22 DIO6* 2,4 A7 User I/O A23 DIO7* 2,4 A8 User I/O A24 DIO8* 2,4 A9 User I/O A25 REN* 2,4 A10 User I/O A26 GND 2,4 A11 User I/O A27 GND 2,4 A12 User I/O A28 GND 2,4 A13 User I/O A29 GND 2,4 A14 User I/O A30 GND 2,4 A15 User I/O A31 GND 2,4 A16 User I/O A32 GND 2,4

B1 +5V B17 D19 B2 GND B18 D20 B3 3 B19 D21 B4 A24 B20 D22 B5 A25 B21 D23 B6 A26 B22 GND B7 A27 B23 D24 B8 A28 B24 D25 B9 A29 B25 D26 B10 A30 B26 D27 B11 A31 B27 D28 B12 GND B28 D29 B13 +5V B29 D30 B14 D16 B30 D31 B15 D17 B31 GND B16 D18 B32 +5V

C1 CA14 1,4 C17 User I/O C2 CA12 1,4 C18 User I/O C3 CA10 1,4 C19 User I/O C4 User I/O C20 User I/O C5 User I/O C21 DIO1* 2,4 C6 User I/O C22 DIO2* 2,4 C7 User I/O C23 DIO3* 2,4 C8 User I/O C24 DIO4* 2,4 C9 User I/O C25 EOI* 2,4 C10 User I/O C26 DAV* 2,4 C11 User I/O C27 NRFD* 2,4 C12 User I/O C28 NDAC* 2,4 C13 User I/O C29 IFC* 2,4 C14 User I/O C30 SRQ* 2,4 C15 User I/O C31 ATN* 2,4 C16 User I/O C32 User I/O

Notes

1. Compare Address lines. Can be used to set base address of GPIB-1014.

2. GPIB signals used for GPIB I/O via P2.

3. Reserved pin. Defined by the VMEbus specification.

4. For models GPIB-1014-1S and GPIB-1014-1S-EH. These signals are not connected to the P2 connector.

Configuration and Installation Chapter 3

Cabling

Two options are available for GPIB I/O from the GPIB-1014:

• A Front Panel Plug-In Connector

• A VMEbus P2 Connector The Model GPIB-1014-1 interface board has a standard 24-pin IEEE 488 connector on the front

panel of the board. A standard GPIB cable can plug in directly to this connector. Two GPIB cables cannot be connected side by side in this configuration; that is, if more than one Model GPIB-1014-1 is installed in the system, they cannot be placed side by side due to the width of the GPIB cable connector housing (another board must be placed between any two GPIB-1014-1 interface boards).

The Model GPIB-1014-2 interface board has no connector on the front panel; therefore, GPIB I/O is performed through the VMEbus P2 connector. A scrambler card and interface cable assembly are available from National Instruments for this configuration. The interface cable assembly is a 96-wire flat ribbon cable used to connect the GPIB I/O signals from the backplane P2 connector to the scrambler card, where they are routed to the IEEE 488 connector. A standard GPIB cable enters the chassis through the rear to plug into the IEEE 488 connector on the scrambler card. The scrambler card is equipped with a 96-pin DIN connector and a 24-pin IEEE 488 connector. A dual connector version of the scrambler card is also available for use with two GPIB-1014-2 Interface Cards.

The Models GPIB-1014-EH, GPIB-1014-1S, and GPIB-1014-1S-EH interface boards use the same cable as the Model GPIB-1014-1.

Verification Testing

A performance verification test can be run to ensure the board has not been damaged during shipment and also to ensure that the board has been configured correctly. To do this, you need an interactive control program or an equivalent mechanism, such as front-panel control jumper or a front-panel emulator, that can load and read memory and I/O addresses.

The tests presented in Chapter 7 of this manual consist of a series of steps written in a pseudo (processor-independent) language with instructions. The steps generally involve writing data to specific GPIB-1014 device registers followed by reading other GPIB-1014 registers to verify that the programming is correct. These tests exercise virtually all of the major functions of the GPIB-1014, including I/O communications, DMA operation, and GPIB communications. All functions except GPIB communications can be performed as stand-alone operations (that is, without another GPIB device). To completely check the GPIB functions, you must use a bus tester or analyzer (such as a National Instruments GPIB-400 or GPIB-410) that can monitor and control GPIB signal lines; emulate GPIB Talker, Listener, and Controller devices; and single-step through the Source and Acceptor Handshakes.

GPIB-1014 User Manual 3-10 © National Instruments Corporation

Chapter 4 Register Bit Descriptions

This chapter contains a description of the register map, a list of interface registers, and a description of the DMA registers.

Register Map

The register map for the GPIB-1014 is shown in Table 4-1. This table gives the register name, the register address, the register size in bits, and the register type (read only, write only, or read and write).

Note: For the sake of brevity, only Channel 0 addresses for the DMA Register Group are listed

in Table 4-1. See Table 2-3 for a complete listing of the addresses for all four channels of the DMA Register Group.

Table 4-1. GPIB-1014 Register Map

GPIB Interface Register Group:

Data In Register Base address + 111 Read only 8-bit Command/Data Out Register Base address + 111 Write only 8-bit Interrupt Status Register 1 Base address + 113 Read only 8-bit Interrupt Mask Register 1 Base address + 113 Write only 8-bit Interrupt Status Register 2 Base address + 115 Read only 8-bit Interrupt Mask Register 2 Base address + 115 Write only 8-bit Serial Poll Status Register Base address + 117 Read only 8-bit Serial Poll Mode Register Base address + 117 Write only 8-bit Address Status Register Base address + 119 Read only 8-bit Address Mode Register Base address + 119 Write only 8-bit Command Pass Through Register Base address + 11B Read only 8-bit Auxiliary Mode Register Base address + 11B Write only 8-bit Hidden Registers

Internal Counter Register Base address + 11B Write only 8-bit Parallel Poll Register Base address + 11B Write only 8-bit Auxiliary Register A Base address + 11B Write only 8-bit Auxiliary Register B Base address + 11B Write only 8-bit

Auxiliary Register E Base address + 11B Write only 8-bit Address Register 0 Base address + 11D Read only 8-bit Address Register Base address + 11D Write only 8-bit Address Register 1 Base address + 11F Read only 8-bit End Of String Register Base address + 11F Write only 8-bit

(continues)

Table 4-1. GPIB-1014 Register Map (continued)

DMA Register Group:

Address Registers

Memory Address Register Base address + 0C Read/Write 32-bit

Base Address Register Base address + 1C Read/Write 32-bit

Device Address Register Base address + 14 Read/Write 32-bit Transfer Count Registers

Memory Transfer Counter Base address + 0A Read/Write 16-bit

Base Transfer Counter Base address + 1A Read/Write 16-bit Function Code Registers

Memory Function Code Base address + 29 Read/Write 8-bit

Base Function Code Base address + 39 Read/Write 8-bit

Device Function Code Base address + 31 Read/Write 8-bit Device Control Register Base address + 04 Read/Write 8-bit Operation Control Register Base address + 05 Read/Write 8-bit Sequence Control Register Base address + 06 Read/Write 8-bit Channel Control Register Base address + 07 Read/Write 8-bit Channel Status Register Base address + 00 Read/Write 8-bit Channel Error Register Base address + 01 Read Only 8-bit Channel Priority Register Base address + 2D Read/Write 8-bit General Control Register Base address + FF Read/Write 8-bit Interrupt Vector Registers

Normal Interrupt Vector Base address + 25 Read/Write 8-bit

Error Interrupt Vector Base address + 27 Read/Write 8-bit

Configuration Register Group:

Configuration Register 1 Base address + 101 Write Only 8-bit Configuration Register 2 Base address + 105 Write Only 8-bit

Register Sizes

VMEbus computers support three transfer sizes for read and write operations: 8-, 16-, or 32-bit. Table 4-1 shows the size of each GPIB-1014 register. For example, reading the Memory Transfer Counter Register requires a 16-bit read operation at the indicated address, whereas writing to the End Of String Register requires an 8-bit write operation at the indicated address.

Register Description

Table 4-1 divides the GPIB-1014 registers into three different register groups. A detailed bit description of each of the registers making up these groups is included later in this chapter.

The GPIB Interface Register Group consists of 21 registers located in the NEC µPD7210 TLC chip. The DMA Register Group consists of 18 registers located in the 68450 DMAC chip. The Configuration Register Group contains two registers used to configure some of the board operating parameters.

GPIB-1014 User Manual 4-2 © National Instruments Corporation

Chapter 4 Register Bit Descriptions

Register Description Format

The remainder of this chapter discusses each of the GPIB-1014 registers in the order shown in Table 4-1. Each register group is introduced, followed by a detailed bit description of each register.

The register bit map shows a diagram of the register with the most significant bit (bit 15 for a 16-bit register, bit 7 for an 8-bit register) shown on the left, and the least significant bit (bit 0) shown on the right. A square is used to represent each bit. Each bit is labeled with a name inside its square. An asterisk (*) after the bit name indicates that the signal is active low. An asterisk is equivalent to an overbar.

In many of the registers, several bits are labeled with an X, indicating don't care bits. When a register is read, these bits may appear set or cleared, and should be ignored. If the register is written to, these bit locations should be cleared.

Mnemonics are assigned to messages, states, registers and bits. Most mnemonics contain a clue to their meaning. Table 4-2 contains a list of clues to look for.

Table 4-2. Clues to Understanding Mnemonics

Clue Mnemonic Probably Stands For:

Ends in IE Interrupt Enable bit Ends in EN Enable bit 4 letters, Interface function as defined in the

ends in S IEEE 488 standard Ends in R,

R0, R1, R2 GPIB Program Register 3 letters,

uppercase Remote GPIB message 3 letters,

lowercase Local GPIB message

Appendix F contains an alphabetical list of mnemonics.

Interface Registers

Twenty-one GPIB Interface registers, eight of which are readable and 13 of which are writable, are located within the NEC µPD7210 Talker/Listener/Controller (TLC) integrated circuit. Each of the 21 interface registers is addressed relative to the GPIB-1014 VMEbus base address.

Figures 4-1 and 4-2 show the register and bit mnemonics of each TLC internal register, its read/write accessibility, and its relative address. Figure 4-1 shows the regular GPIB-1014 GPIB Interface registers. Figure 4-2 shows the hidden GPIB interface registers and illustrates the method of writing to those registers via the Auxiliary Mode Register. Following Figures 4-1 and 4-2 are detailed function descriptions of all 21 interface registers.

GPIB-1014 User Manual 4-4 © National Instruments Corporation

Chapter 4 Register Bit Descriptions

Legend

(Contents of Read Register)

Bit

(Contents of Write Register)

Bit

DIR CDOR

ISR1 IMR1

ISR2 IMR2

SPSR

SPMR

ADSR

ADMR

Address

Offset

(hex)

+111

+113

+115

+117

+119

DI7

CDO7 CDO6

CPT APT DET END RX DEC ERR DO DI

CPT IE APT IE DET IE END IE DEC IE ERR IE DO IE DI IE

INT SRQI LOK

0 SRQI IE DMAO DMAI CO IE LOKC IE REMC IEADSC IE

S8 PEND S8 rsv S6

CIC

ton lon TRM1 TRM0

DI6

ATN*

DI5 DI4 DI3

CDO5

SPMS

CDO4 CDO3 CDO2 CDO1 CDO0

REM

CO LOKC REMC ADSC

S5 S5

LPAS TPAS LA TA MJMN

S4 S4 S3

0 0 ADM1

DI2

S3 S2 S1

DI1

DI0

ADM0

Read/

Write

R W

CPTR AUXMR

ADR0 ADR

ADR1

EOSR

+11B

+11D

+11F

CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0

CNT2 CNT1 CNT0 COM4 COM3 COM2 COM1 COM0

X DT0 DL0 AD5-0 AD4-0

ARS DT DL

EOI DT1 DL1 AD5-1 AD4-1 AD3-1 AD2-1 AD1-1

EOS7 EOS6 EOS0EOS5 EOS4 EOS3 EOS2 EOS1

Note: X indicates bit is not used.

AD5 AD4

AD3-0

AD3

AD2-0 AD1-0

AD2 AD1

R W

Figure 4-1. Interface Registers

Control Code Command Code

+11B

AUXMR

CNT2 CNT1 CNT0 COM4 COM3 COM2

When CNT2-CNT0 is: ICR is loaded with:

COM1 COM0

0 0 1

0 1 1

1 0 0

1 0 1

1 1 0

0 CLK3 CLK2 CLK1 CLK0

PPR is loaded with:

U S P3 P2 P1

AUXRA is loaded with:

BIN XEOS REOS HLDE HLDA

AUXRB is loaded with:

ISS INV TRI SPEOI

AUXRE is loaded with:

0 DHDC DHDT

Figure 4-2. Writing to the Hidden Registers

CPT

ENABLE

GPIB-1014 User Manual 4-6 © National Instruments Corporation

Chapter 4 Register Bit Descriptions

Data In Register (DIR)

VMEbus Address: Base Address + 111 (hex) Attributes: Read Only, Internal to TLC

7 654 3210

DI7

DI6 DI5 DI4 DI3 DI2 DI1 DI0

The Data In Register (DIR) is used to move data from the GPIB to the computer when the interface is a Listener. The GPIB Ready For Data (RFD) message is held false until the byte is removed from the DIR, either by a DMA transfer to the VMEbus memory or by an I/O read from a VMEbus master.

DI0 is the least significant bit of the data byte and corresponds to GPIB DI01. DI7 is the most significant bit of the data byte and corresponds to GPIB DI08.

Bit Mnemonic Description

7-0r DI[7-0] Data In Bits 7 through 0

Command/Data Out Register (CDOR)

VMEbus Address: Base Address + 111 (hex) Attributes: Write Only, Internal to TLC

7 654 3210

CDO7 CDO6 CDO5 CDO4 CDO3 CDO2 CDO1 CDO0

The Command/Data Out Register (CDOR) is used to move data from the VMEbus to the GPIB when the interface (TLC) is the GPIB Talker or the Active Controller. Outgoing data is separately latched by this register and is not destroyed by a read from the DIR. When a byte is written to the CDOR, the TLC GPIB Source Handshake (SH) function is initiated and the byte is transferred to the GPIB.

Bit Mnemonic Description

7-0w CDO[7-0] Command/Data Out Bits 7 through 0

GPIB-1014 User Manual 4-8 © National Instruments Corporation

Chapter 4 Register Bit Descriptions

Interrupt Status Register 1 (ISR1)

VMEbus Address: Base Address + 113 (hex) Attributes: Read Only, Internal to TLC

Bits are cleared when read

Interrupt Mask Register 1 (IMR1)

VMEbus Address: Base Address + 113 (hex) Attributes: Write Only, Internal to TLC

7 654 3210

CPT

CPT IE

APT

APT IE

DET

DET IE

END RX

END IE

DEC

DEC IE

ERR

ERR IE

DO IE

DI IE

The Interrupt Status Register 1 (ISR1) is composed of eight Interrupt Status bits. The Interrupt Mask Register 1 (IMR1) is composed of eight Interrupt Enable bits that directly correspond to the Interrupt Status bits in ISR1. As a result, ISR1 and IMR1 service eight possible interrupt conditions, where each condition has an Interrupt Status bit and an Interrupt Enable bit associated with it. If the Interrupt Enable bit is true when the corresponding status condition or event occurs, a hardware interrupt request is generated. Bits in ISR1 are set and cleared by the TLC regardless of the status of the Interrupt bits in IMR1. If an interrupt condition occurs at the same time ISR1 is being read, the TLC holds off setting the corresponding Status bit until the read has finished.

Bit Mnemonic Description

7r CPT Command Pass Through Bit 7w CPT IE Command Pass Through Interrupt Enable Bit

CPT is set on:

[UCG + ACG & (TADS + LADS)] & undefined & ACDS & (CPT ENABLE) + UDPCF & SCG & ACDS & CPT ENABLE

CPT is cleared by:

pon + (read ISR1)

Notes

UCG: GPIB Universal Command Group message ACG: GPIB Addressed Command Group message TADS: GPIB Talker Addressed State LADS: GPIB Listener Addressed State defined: GPIB command automatically recognized and

executed by TLC

Bit Mnemonic Description

undefined: GPIB command not automatically recognized and

executed by TLC ACDS: GPIB Accept Data State CPT ENABLE: AUXRB[0]w UDPCF: Undefined Primary Command Function SCG: GPIB Secondary Command Group message pon: Power On Reset TAG: GPIB Talk Address Group message LAG: GPIB Listen Address Group message read ISR1: Bit is cleared immediately after it is read

UDPCF is set on:

[UCG + ACG & (TADS + LADS)] & undefined & ACDS & CPT ENABLE

UDPCF is cleared on:

[(UCG + ACG) & defined + TAG + LAG] & ACDS + CPT ENABLE* + pon

The CPT bit flags the occurrence of a GPIB command not recognized by the TLC, and all following GPIB secondary commands when the Command Pass Through feature is enabled by the CPT ENABLE bit, AUXRB[0]w. Any GPIB command message not decoded by the TLC is treated as an undefined command; however, any addressed command is automatically ignored when the TLC is not addressed.

Undefined commands are read using the Command Pass Through Register (CPTR). The TLC holds off the GPIB Acceptor Handshake in the Accept Data State (ACDS) until the Valid auxiliary command function code, 0F hex, is written to the AUXMR. If the CPT feature is not enabled, undefined commands are simply ignored.

6r APT Address Pass Through 6w APT IE Address Pass Through Interrupt Enable

APT is set by:

ADM1 & ADM0 & (TPAS + LPAS) & SCG & ACDS

APT is cleared by:

pon + (read ISR1)

Notes

ADM1: Address Mode Register Bit 1, ADMR[1]w ADM0: Address Mode Register Bit 0, ADMR[0]w TPAS: GPIB Talker Primary Addressed State LPAS: GPIB Listener Primary Addressed State

GPIB-1014 User Manual 4-10 © National Instruments Corporation

Chapter 4 Register Bit Descriptions

Bit Mnemonic Description

SCG: GPIB Secondary Command Group ACDS: GPIB Accept Data State pon: Power On Reset Read ISR1: Bit is cleared immediately after it is read

The APT bit indicates that a secondary GPIB address has been received and is available in the CPTR for inspection

Note: The application program must check this bit when using TLC

address mode 3.

When APT is set, the Data Accepted (DAC) message is held and the GPIB Handshake stops until either the Valid or Non-Valid auxiliary command is issued. The secondary address can be read from the CPTR.

5r DET Device Execute Trigger Bit 5w DET IE Device Execute Trigger Interrupt Enable Bit

DET is set by:

DTAS

DET is cleared by:

pon + (read ISR1)

Notes

DTAS: GPIB Device Trigger Active State pon: Power On Reset read ISR1: Bit is cleared immediately after it is read

The DET bit indicates that the GPIB Device Execute Trigger (DET) command has been received while the TLC was a GPIB Listener (the TLC has been in DTAS).

4r END RX End Received Bit 4w END IE End Received Interrupt Enable Bit

END RX is set by:

LACS & (EOI + EOS & REOS) & ACDS

END RX is cleared by:

pon + (read ISR1)

Notes

LACS: GPIB Listener Active State EOI: GPIB End Of Identify Signal

Bit Mnemonic Description

EOS: GPIB END Of String message REOS: Reception of GPIB EOS allowed, AUXRA[2]w ACDS: GPIB Accept Data State pon: Power On Reset read ISR1: Bit is cleared immediately after it is read

The END RX bit is set when the TLC is a Listener and the GPIB uniline message, END, is received with a data byte from the GPIB Talker, or the data byte in the DIR matches the contents of the End Of String Register (EOSR).

3r DEC Device Clear Bit 3w DEC IE Device Clear Interrupt Enable Bit

DEC is set by:

DCAS

DEC is cleared by:

pon + (read ISR1)

Notes

DCAS: GPIB Device Clear Active State pon: Power On Reset read ISR1: Bit is cleared immediately after it is read

The DEC bit indicates that the GPIB Device Clear (DCL) command has been received or that the GPIB Selected Device Clear (SDC) command has been received while the TLC was a GPIB Listener (the TLC is in DCAS).

2r ERR Error Bit 2w ERR IE Error Interrupt Enable Bit

ERR is set by:

TACS & SDYS & DAC & RFD + SIDS & (write CDOR) + (SDYS to SIDS)

ERR is cleared by:

pon + (read ISR1)

Notes

TACS: GPIB Talker Active State SDYS: GPIB Source Delay State DAC: GPIB Data Accepted message RFD: GPIB Ready For Data message SIDS: GPIB Source Idle State

GPIB-1014 User Manual 4-12 © National Instruments Corporation

Chapter 4 Register Bit Descriptions

Bit Mnemonic Description

write CDOR: Bit is set immediately after writing to the

Command/Data Out Register SDYS to SIDS: Transition from GPIB Source Delay State to Source

Idle State pon: Power On Reset read ISR1; Bit is cleared immediately after it is read

The ERR bit indicates that the contents of the CDOR have been lost. ERR is set when data is sent to the GPIB without a specified Listener or when a byte is written to the CDOR during SIDS or during the SDYS to SIDS transition.

1r DO Data Out Bit 1w DO IE Data Out Interrupt Enable Bit

DO is set as:

(TACS & SGNS) becomes true

DO is cleared by:

(read ISR1) + TACS* + SGNS*

Notes

TACS: GPIB Talker Active State SGNS: GPIB Source Generate State read ISR1: Bit is cleared immediately after it is read

The DO bit indicates that the TLC is ready to accept another data byte from the VMEbus for transmission on to the GPIB when the TLC is the GPIB Talker. The DO bit is cleared when a byte is written to the CDOR and also when the TLC ceases to be the Active Talker. When performing a DMA operation, DO IE must be clear so that an interrupt request does not occur. Instead, the DMA0 bit in the Interrupt Mask Register 2 (IMR2[5]w) must be set to enable a DMA cycle request when DO is asserted.

0r DI Data In Bit 0w DI IE Data In Interrupt Enable Bit Bit

DI is set by:

LACS & ACDS & continuous mode

DI is cleared by:

pon + (read ISR1) + (Finish Handshake) & (Holdoff mode) + (read DIR)

Bit Mnemonic Description

Notes

LACS: GPIB Listener Active State ACDS: GPIB Accept Data State continuous mode: Listen in continuous mode auxiliary command in

effect pon: Power On Reset read ISR1: Bit is cleared immediately after it is read finish Handshake: Finish Handshake auxiliary command issued Holdoff mode: RFD Holdoff state read DIR: Read Data In Register

The DI bit indicates that the TLC, as a GPIB Listener, has accepted a data byte from the GPIB Talker. When performing a DMA operation, DI IE must be clear so that an interrupt request does not occur. Instead, the DMAI bit in the Interrupt Mask Register 2 (IMR1[4]]w) must be set to enable a DMA cycle request when DI is asserted.

GPIB-1014 User Manual 4-14 © National Instruments Corporation

Interrupt Status Register 2 (ISR2)

VMEbus Address: Base Address + 115 (hex) Attributes: Read Only, Internal to TLC

Bits are cleared when read

Interrupt Mask Register 2 (IMR2)

VMEbus Address: Base Address + 115 (hex) Attributes: Write Only, Internal to TLC

7 654 3210

INT

SRQI

SRQI IE

LOK

DMAO

REM

DMAI

CO IE

LOKC

LOKC IE

REMC

REMC IE

ADSC IE

ADSC

The Interrupt Status Register 2 (ISR2) consists of six Interrupt Status bits and two TLC Internal Status bits. The Interrupt Mask Register 2 (IMR2) consists of five Interrupt Enable bits and two TLC Internal Control bits. If the Interrupt Enable bit is true when the corresponding status condition or event occurs, an interrupt request is generated. Bits in ISR2 are set and cleared regardless of the status of the bits in IMR2. If a condition occurs that requires the TLC to set or clear a bit or bits in ISR2 at the same time ISR2 is being read, the TLC holds off setting or clearing the bit or bits until the read is finished.

Bit Mnemonic Description

7r INT Interrupt Bit

This bit is the logical OR of all the Enabled Interrupt Status bits in both ISR1 and ISR2, each one ANDed with its Interrupt Enable bit. There is no corresponding Mask bit for INT.

INT is set by:

(CPT & CPT IE) + (APT & APT IE) + (DET & DET IE) + ERR & ERR IE) + (END RX & END IE) + (DEC & DEC IE) + (DO & DO IE) + (DI & DI IE) + (SRQI & SRQI IE) + (REMC & REMC IE) + (CO & CO IE) + (LOKC & LOKC IE) + (ADSC & ADSC IE)

Notes

CPT: Command Pass Through Bit CPT IE: Enable Interrupt on Command Pass Through Bit APT: Address Pass Through Bit APT IE: Enable Interrupt on Address Pass Through Bit DET: Device Execute Trigger Bit DET IE: Enable Interrupt on Device Execute Trigger Bit ERR: Error Bit

GPIB-1014 User Manual 4-14 © National Instruments Corporation

Bit Mnemonic Description

ERR IE: Enable Interrupt on Error Bit END RX: End Received Bit END IE: Enable Interrupt on End Received Bit DEC: Device Clear Bit DEC IE: Enable Interrupt on Device Clear Bit DO: Data Out Bit DO IE: Enable Interrupt on Data Out Bit DI: Data In Bit DI IE: Enable Interrupt on Data In Bit SRQI: Service Request Input Bit SRQI IE: Enable Interrupt on Service Request Input Bit REMC: Remote Change Bit REMC IE: Enable Interrupt on Remote Change Bit CO: Command Output Bit CO IE: Enable Interrupt on Command Output Bit LOKC: Lockout Change Bit LOKC IE: Enable Interrupt on Lockout Change Bit ADSC: Address Status Change Bit ADSC IE: Enable Interrupt on Address Status Change Bit

7w 0 Reserved Bit

Write zero to this bit.

6r SRQI Service Request Input Bit 6w SRQI IE Service Request Input Interrupt Enable Bit

SRQI is set when:

(CIC & SRQ & -(RQS & DAV)) becomes true or (CIC & SRQ & RQS & DAV) becomes true.

SRQI is cleared by:

pon + (read ISR2)

Notes

CIC: GPIB Controller-In-Charge SRQ: GPIB Service Request message RQS: GPIB Request Service message DAV: GPIB Data Valid message pon: Power On Reset read ISR2: Bit is cleared immediately after it is read

The SRQI bit indicates that a GPIB Service Request (SRQ) message has been received while the TLC function is active (CIC=1).

Note: The set SRQI equation only applies to situations in which two

or more devices are issuing the SRQ message.

Bit Mnemonic Description

5r LOK Lockout Bit

LOK is used, along with the REM bit, to indicate the status of the TLC GPIB Remote/Local (RL) function. If set, the LOK bit indicates that the TLC is in Local With Lockout State (LWLS) or Remote With Lockout State (RWLS). LOK is a Non-Interrupt bit.

5w DMAO DMA Out Enable Bit

The DMAO bit must be set to allow data transfers from VMEbus memory to the CDOR. DO IE must be clear, DMAO must be set, and the TLC must be the active GPIB Talker when a DMAO bit is set, the DO condition causes a data transfer request rather than an interrupt request.

4r REM Remote Bit

This bit is true when the TLC GPIB RL function is in one of two states: Remote State (REMS) or Remote With Lockout State (RWLS). The TLC RL function transfers to one of these states when the System Controller has asserted the Remote Enable line (REN), and the CIC addresses the TLC as a Listener.

4w DMAI DMA Input Enable Bit

The DMAO bit must be set to allow data transfers from the DIR to VMEbus memory. DI IE must be clear, DMAI must be set, and the TLC must be an active GPIB Listener when a DMA in operation is initiated. If DMAI is set, the DI condition causes a data transfer request rather than an interrupt request.

3r CO Command Out Bit 3w CO IE Command Out Interrupt Enable Bit

CO is set when:

(CACS & SGNS) becomes true

CO is cleared by:

(read ISR2) + CACS* + SGNS*

Notes

CACS: GPIB Controller Active State SGNS: GPIB Source Generate State read ISR2: Bit is cleared immediately after it is read CO = 1 indicates that the CDOR is empty and that another command can be written to it for transmission over the GPIB without overwriting a previous command.

GPIB-1014 User Manual 4-16 © National Instruments Corporation

Bit Mnemonic Description

2r LOKC Lockout Change Bit 2w LOKC IE Lockout Change Interrupt Enable Bit

LOKC is set by:

any change in LOK

LOKC is cleared by:

pon + (read ISR2)

Notes

LOK: ISR2[5]r pon: Power On Reset read ISR2: Bit is cleared immediately after it is read

LOKC is set when there is a change in the LOK bit, ISR2[5]r, (REMS +RELS).

1r REMC Remote Change Bit 1w REMC IE Remote Change Interrupt Enable Bit

REMC is set by:

any change in REM

REMC is cleared by:

pon + (read ISR2)

Notes

REM: ISR2[4]r pon: Power On Reset read ISR2: Bit is cleared immediately after it is read

REMC is set when there is a change in the REM bit, ISR2[4]r, (REMS + RELS).

0r ADSC Addressed Status Change Bit 0w ADSC IE Addressed Status Change Interrupt Enable Bit

ADSC is set by:

[(any change in TA) + (any change in LA) + (any change in CIC) + (any change in MJMN)] & -(lon + ton)

ADSC is cleared by:

pon + (read ISR2)

Bit Mnemonic Description

Notes

TA: Talker Active bit, ADSR[1]r LA: Listener Active bit, ADSR[2]r CIC: Controller-In-Charge bit, ADSR[7]r MJMN: Major/Minor bit, ADSR[0]r lon: Listen Only bit, ADMR[6]w ton: Talk Only bit, ADMR[7]w pon: Power On Reset read ISR2: Bit is cleared immediately after it is read ADSR: Address Status Register ADMR: Address Mode Register

ADSC is set when there is a change in one of the four bits–TA, LA, CIC, or MJMN–of the Address Status Register (ADSR).

GPIB-1014 User Manual 4-18 © National Instruments Corporation

Serial Poll Status Register (SPSR)

VMEbus Address: Base Address + 117 (hex) Attributes: Read Only, Internal to TLC

Serial Poll Mode Register (SPMR)

VMEbus Address: Base Address + 117 (hex) Attributes: Write Only, Internal to TLC

7 654 3210

S8 S8

PEND

rsv

S6 S6

S5 S5

S4 S4

S3 S3

S2 S2

Bit Mnemonic Description

7r S8 Serial Poll Status Bit 8 7w, 5-0r, S[6-1] Serial Poll Status Bits 6 through 1 5-0w

Cleared by Power On Reset (pon), and by issuing the Chip Reset auxiliary command. These bits are used for sending device- or system-dependent status information to the GPIB when the TLC is serial polled. When the TLC is addressed as the GPIB Talker and receives the GPIB multiline Serial Poll Enable (SPE) command message, the TLC transmits a byte of status information, SPMR[7- 0], to the Controller-In-Charge after the Controller goes to standby and becomes an Active Listener.

6r PEND Pending Bit

S1 S1

PEND is set when rsv=1 and cleared when the Negative Poll Response State (NPRS) & Request Service (rsv) = 1. Reading the PEND status bit can confirm that a request was accepted and that the Status Byte (STB) was transmitted (PEND=0).

6w rsv Request Service Bit

The rsv bit is used for generating the GPIB local rsv message. When rsv is set and the GPIB Active Controller is not serial polling the TLC, the TLC enters the Service Request State (SRQS) and asserts the GPIB SRQ signal. When the Active Controller reads the STB during the poll, the TLC clears rsv at the Affirmative Poll Response State (APRS). The rsv bit is also cleared by pon, and by issuing the Chip Reset auxiliary command.

Address Status Register (ADSR)

VMEbus Address: Base Address + 119 (hex) Attributes: Read Only, Internal to TLC

756 43210

CIC ATN* SPMS

LPAS TPAS

MJMN

The Address Status Register (ADSR) contains information that can be used to monitor the TLC GPIB address status.

Bit Mnemonic Description

7r CIC Controller-In-Charge Bit

CIC = -(CIDS + CADS) CIC indicates that the TLC GPIB Controller function is in an active or

standby state, with ATN* on or off, respectively. If CIC=0, the Controller function is in an idle state, with ATN* off.

6r ATN* Attention* Bit

ATN* is a Status bit that indicates the current level of the GPIB ATN* signal. If ATN* = 0, the GPIB ATN* signal is asserted.

5r SPMS Serial Poll Mode State Bit

If SPMS=1, the TLC GPIB Talker (T) or Talker Extended (TE) function is able to participate in a Serial Poll. SPMS is set when the TLC has been addressed as a GPIB Talker and the GPIB Active Controller has issued the GPIB Serial Poll Enable (SPE) command message. SPMS is cleared when the GPIB Serial Poll Disable (SPD) command is received by pon, by LMR (CR0[2]w), or by issuing the Chip Reset auxiliary command.

4r LPAS Listener Primary Addressed State Bit

The LPAS bit is used when the TLC is configured for extended GPIB addressing and, when set, indicates that the TLC has received its primary listen address. In mode 3 addressing (see Address Mode Register in this chapter), LPAS=1 indicates that the secondary address being received on the next GPIB command represents the TLC extended (secondary) GPIB listen address. LPAS is cleared by pon, by LMR (CR0[2]w), or by issuing the Chip Reset auxiliary command.

GPIB-1014 User Manual 4-20 © National Instruments Corporation

Bit Mnemonic Description

3r TPAS Talker Primary Addressed State Bit

TPAS is used when the TLC is configured for extended GPIB addressing, and, when set, indicates that the TLC has received its primary GPIB talk address. In extended mode addressing (mode 3 addressing), TPAS=1 indicates that the secondary address being received as the next GPIB command message can represent the TLC extended (secondary) GPIB talk address.

2r LA Listener Active Bit

LA is set when the TLC has been addressed or programmed as a GPIB Listener; that is, the TLC is in the Listener Active State, LACS, or the Listener Addressed State (LADS). The TLC can be addressed to listen either by sending its own listen or extended listen address while it is Controller-In-Charge or by receiving its listen address from another Controller-In-Charge. It can also be programmed to listen using the Listen Only (lon) bit in the Address Mode Register (ADMR).

If the TLC is addressed to listen, it is automatically unaddressed to talk. LA is cleared by pon, or by issuing the Chip Reset auxiliary command.

1r TA Talker Active Bit

TA is set when the TLC has been addressed or programmed as the GPIB Talker; that is, the TLC is in the Talker Active State (TACS), the Talker Addressed State (TADS), or the Serial Poll Active State (SPAS). The TLC can be addressed to talk either by sending its own talk or extended talk address while it is CIC or by receiving its talk address from another CIC. It can also be programmed to talk using the Talk Only (ton) bit in the ADMR.

If the TLC is addressed to talk, it is automatically unaddressed to listen. TA is cleared by pon, or by issuing the Chip Reset auxiliary command.

0r MJMN Major-Minor Bit

The MJMN bit is used to determine whether the information in the other ADSR bits applies to the TLC major or minor Talker and Listener functions. MJMN is set to one when the TLC GPIB minor talk address or minor listen address is received. MJMN is cleared on receipt of the TLC major talk or major listen address.

Note: Only one Talker and Listener can be active at any one time;

thus, the MJMN bit indicates which, if either, of the TLC Talker and Listener functions is addressed or active. MJMN is always zero unless a dual primary addressing mode (mode 1 or mode 3) is enabled (see Address Mode Register later in this chapter).

Address Mode Register (ADMR)

VMEbus Address: Base Address + 119 (hex) Attributes: Write Only, Internal to TLC

7 654 321

ton 1on TRM1 TRM0 0 0 ADM1 ADM0

Bit Mnemonic Description

7w ton Talk Only Bit

By setting ton programs, the TLC becomes a GPIB Talker. If ton is set, the lon, ADM1, and ADM0 bits must be cleared. This method must be used in place of the addressing method when the TLC will be only a Talker.

Note: Clearing ton does not by itself take the TLC out of GPIB

Talker Active State (TACS). It is also necessary to execute the Chip Reset or Immediate Execute pon auxiliary command.

6w lon Listen Only Bit

By setting lon programs, the TLC becomes a GPIB Listener. If lon is set, ton, ADM1, and ADM0 must be cleared.

Note: Clearing lon does not, by itself, take the TLC out of GPIB

Listener Active State (LACS). It is also necessary to execute the Chip Reset or Immediate Execute pon auxiliary command.

5-4w TRM[1-0] Transmit/Receive Mode Bits 1 through 0

TRM1 and TRM0 control the function of the TLC T/R2 and T/R3 output pins.

For proper operation, set both TRM1 and TRM0 to 1. These are set to configure the µPD7210 to match the transceivers chosen for hardware implementation of the GPIB interface.

3-2w 0 Reserved Bits

Write zeros to these bits.

Bit Mnemonic Description

1-0w ADM[1-0] Address Mode Bits 1 through 0

These bits state the addressing mode currently in effect–that is, the manner in which the information in ADR0 and ADR1 is interpreted (see Address Register 0 and Address Register 1 later in this chapter). If both bits are zero, then the TLC does not respond to GPIB address commands. Instead, the ton and lon bits are used to program the Talker and Listener functions, respectively. The ton and lon bits must be cleared if mode 1, 2, or 3 addressing is selected, and the ADM1 through 0 bits must be cleared if either of the bits ton or lon are set.

Mode ADM1 ADM0 Title

0 0 0 ton/lon 1 0 1 Normal dual addressing 2 1 0 Extended single addressing 3 1 1 Extended dual addressing

In mode 1, ADR0 and ADR1 contain the major and minor addresses, respectively, for dual primary GPIB address applications; that is, the TLC responds to two GPIB addresses: a major address and a minor address. The MJMN bit in the ADSR indicates which address was received. In applications where the TLC needs to respond to only one address, the major Talker and Listener function is used and the minor Talker and Listener function should be disabled. The minor Talker and Listener function can be disabled by setting the Disable Talker (DT) and Disable Listener (DL) bits in ADR1 (set ADR and ADR1). In mode 2 (ADM1=1, ADM0=0), the TLC recognizes two sequential GPIB address bytes, a primary followed by a secondary. Both GPIB address bytes must be received in order to enable the TLC to talk or listen. In this manner, mode 2 addressing uses the Extended Talker and Extended Listener functions as defined in IEEE 488, without requiring computer program intervention. In mode 2, ADR0 and ADR1 contain the TLC primary and secondary GPIB addresses, respectively. In mode 3 (ADM1=1, ADM0=1), the TLC handles addressing just as it does in mode 1, except that each major or minor GPIB primary address must be followed by a secondary address. All secondary GPIB addresses must be verified by computer program when mode 3 is used. When the TLC is in Talker Primary Addressed State (TPAS) or Listener Primary Addressed State (LPAS) and a secondary address byte is on the GPIB DIO lines, the APT bit of ISR2 is set and the secondary GPIB address may be inspected in the CPTR. The TLC Acceptor Handshake is held up in the Accept Data State (ACDS) until the Valid or Non-Valid auxiliary command is written to the AUXMR, signaling a valid or invalid secondary address, respectively, to the TLC.

Bit Mnemonic Description

ADM0 and ADM1 must be cleared when either of the two programmable bits ton or lon is set. For more information on the different addressing modes supported by the GPIB-1014, refer to the

Addressed Implementation of Talker and Listener section in Chapter 5.

Command Pass Through Register (CPTR)

VMEbus Address: Base Address + 11B (hex) Attributes: Read Only, Internal to TLC

7 654 3210

CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0

Bit Mnemonic Description

7-0r CPT[7-0] Command Pass Through Bits 7 through 0

These bits are used to transfer undefined multiline GPIB command messages from the GPIB DIO lines to the computer. When the CPT feature is enabled (CPT ENABLE=1, AUXRB[0]w), any GPIB Primary Command Group (PCG) message not decoded by the TLC is treated as an undefined command. The multiline GPIB commands recognized by the µPD7210 are listed in Table 4-3. All GPIB Secondary Command Group (SCG) messages following an undefined GPIB PCG message are also treated as undefined. When an undefined GPIB message is encountered, it is held in the CPTR and the TLC Acceptor Handshake function is held off (in ACDS) until the Valid auxiliary command is written to the AUXMR. The CPTR is also used to inspect secondary addresses when mode 3 addressing is used. The TLC Acceptor Handshake function is held off (in ACDS) until the Valid or Non-Valid auxiliary command is written to the AUXMR.

Table 4-3. Multiline GPIB Commands Recognized by the µPD7210

Hex Number Message Description

01 GTL Go To Local 04 SDC Selected Device Clear 05 PPC Parallel Poll Configure 08 GET Group Execute Trigger 09 TCT Take Control 11 LLO Local Lockout 14 DCL Device Clear

(continues)

Table 4-3. Multiline GPIB Commands Recognized by the µPD7210

(continued)

Hex Number Message Description

15 PPU Parallel Poll Unconfigure 18 SPE Serial Poll Enable 19 SPD Serial Poll Disable

20-3E MLA My Listen Address

3F UNL Unlisten

40-5E MTA My Talk Address

5F UNT Untalk

60-6F MSA, PPE My Secondary Address or Parallel

Poll Enable

70-7E MSA, PPD My Secondary Address or Parallel

Poll Disable

The CPTR is read during a TLC-initiated Parallel Poll operation to retrieve the Parallel Poll response. The PPR message is latched into the CPTR when CPPS is set, until CIDS is set, or until a command byte is sent over the GPIB.

Auxiliary Mode Register (AUXMR)

VMEbus Address: Base Address + 11B (hex) Attributes: Write Only, Internal to TLC

Permits Access to Hidden Registers

7 654 321

CNT1 CNT0CNT2 COM4 COM3 COM2 COM1 COM0

The Auxiliary Mode Register (AUXMR) is used to issue auxiliary commands. It is also used to program the five hidden registers:

• Auxiliary Register A (AUXRA)

• Auxiliary Register B (AUXRB)

• Parallel Poll Register (PPR)

• Auxiliary Register E (AUXRE)

• Internal Counter Register (ICR) Table 4-4 shows the control and command codes used.

Bit Mnemonic Description

7-5w CNT[2-0] Control Code Bits 2 through 0

These bits indicate the control code (that is, the manner in which the information in bits COM[4-0] is to be used). If CNT[2-0] are all zero, the special command selected by COM[4-0] is executed. Otherwise, the hidden register selected by CNT[2-0] is loaded with the data from COM[4-0].

4-0w COM[4-0] Command Code Bits 4 through 0

These bits indicate the command code of the special function if the control code is 000. Table 4-4 is a summary of the implemented special functions. Table 4-5 explains the details of each special function. If the control code is not 000, these bits are written to one of the hidden registers (indicated by the control code in CNT[2-0]).

Table 4-4. Auxiliary Command Summary

Function Code* (COM4-COM0)

Hex

4 3 2 1 0 Code** Auxiliary Command

0 0 0 0 0 00 Immediate Execute pon 0 0 0 1 0 02 Chip Reset 0 0 0 1 1 03 Finish Handshake 0 0 1 0 0 04 Trigger 0 0 1 0 1 05 Return to Local 0 0 1 1 0 06 Send EOI 0 0 1 1 1 07 Non-Valid Secondary Command or Address 0 1 1 1 1 0F Valid Secondary Command or Address 0 0 0 0 1 01 Clear Parallel Poll Flag

0 1 0 0 1 09 Set Parallel Poll Flag 1 0 0 0 1 11 Take Control Asynchronously (Pulsed)

1 0 0 1 0 12 Take Control Synchronously 1 1 0 1 0 1A Take Control Synchronously on End

1 0 0 0 0 10 Go To Standby 1 0 0 1 1 13 Listen

1 1 0 1 1 1B Listen in Continuous Mode 1 1 1 0 0 1C Local Unlisten

1 1 1 0 1 1D Execute Parallel Poll 1 1 1 1 0 1E Set IFC

1 0 1 1 0 16 Clear IFC 1 1 1 1 1 1F Set REN

1 0 1 1 1 17 Clear REN 1 0 1 0 0 14 Disable System Control * CNT[2-0] set to 000 binary

** Represents all eight bits of the Auxiliary Mode Register

Table 4-5 shows the functions that are executed when the AUXMR Control Code (CNT2 through CNT0) is loaded with 000 (binary) and the Command Code (COM4 through COM0) is loaded.

Table 4-5. Auxiliary Commands: Detail Description

Command Code (COM4-COM0) 4 3 2 1 0 Description

0 0 0 0 0 Immediate Execute Pon

This command generates a local pon message that places the following GPIB interface functions into these idle states:

AIDS Acceptor Idle State CIDS Controller Idle State LIDS Listener Idle State LOCS Local State LPIS Listener Primary Idle State NPRS Negative Poll Response State PPIS Parallel Poll Idle State PUCS Parallel Poll to Unaddressed to Configure State SIDS Source Idle State SIIS System Control Interface Clear Idle State SPIS Serial Poll Idle State SRIS System Control Remote Enable Idle State TIDS Talker Idle State TPIS Talker Primary Idle State

If the command is sent while a pon message is already active (by either an external reset pulse or the Chip Reset auxiliary command) the local pon message becomes false.

0 0 0 1 0 Chip Reset

The Chip Reset command resets the TLC in the same way as an external reset pulse. The System Controller bit is also cleared. The TLC is reset to the following conditions:

• The local pon message is set and the interface functions are placed in their idle states.

• All bits of the SPMR are cleared.

• The EOI bit is cleared.

• All bits of the AUXRA, AUXRB, and AUXRE are cleared.

• The Parallel Poll Flag and RSC local message are cleared.

• The contents of the ICR is set to eight (F3 set to 1; F2, F1, and F0 set to 0).

• The TRM0 bit and the TRM1 bit are cleared.

The interface functions are held in their idle states until released by an Immediate Execute pon command. Between these commands, the TLC unitable bits may be programmed to their desired states.

(continues)

Table 4-5. Auxiliary Commands: Detail Description (continued)

Command Code (COM4-COM0) 4 3 2 1 0 Description

0 0 0 1 1 Finish Handshake (FH)

The Finish Handshake command finishes a GPIB Handshake that was stopped because of a Holdoff on RFD or DAC.

0 0 1 0 0 Trigger

Note: Trigger cannot be used with the GPIB-1014. The Trigger command generates a high pulse on the TRIG pin

(T/R3 pin when TRM1=0) of the TLC. The Trigger command performs the same function as if the DET (Device Trigger) bit (ISR1[5]r) were set. (The DET bit is not set by issuing the Trigger command.)

0 0 1 0 1 Return to Local (rtl) 0 1 1 0 1 Return to Local (rtl)

The two Return to Local commands implement the rtl message as defined by IEEE 488. When COM3 is zero, the message is generated in the form of a pulse. When COM3 is one, the rtl command is set in the standard manner.

0 0 1 1 0 Send EOI (SEOI)

The Send EOI command causes the GPIB End Or Identify (EOI) line to go true with the next byte transmitted. The EOI line is then cleared upon completion of the Handshake for that byte. The TLC recognizes the Send EOI command only if TA=1 (that is, the TLC is addressed as the GPIB Talker).

0 0 1 1 1 Non-Valid Secondary Command or Address

The Non-Valid command releases the GPIB DAC message held

off

by the Address Pass Through (APT). The TLC is permitted to operate as if an Other Secondary Address (OSA) message has been received.

0 1 1 1 1 Valid Secondary Command or Address

The Valid command releases the GPIB DAC message held off by APT and allows the TLC to function as if a My Secondary Address (MSA) message had been received. The DAC message is released at the time of Command Pass Through (CPT). DAC is also released if DCAS or DTAS is in Holdoff state.

(continues)

Table 4-5. Auxiliary Commands: Detail Description (continued)

Command Code (COM4-COM0) 4 3 2 1 0 Description

0 0 0 0 1 Clear Parallel Poll Flag 0 1 0 0 1 Set Parallel Poll Flag

These commands set the Parallel Poll Flag to the value of COM3. The value of the Parallel Poll Flag is used as the local message ist when bit four of Auxiliary Register B is zero. The value of SRQS is used as the ist when ISS=1.

1 0 0 0 0 Go To Standby

The Go To Standby command sets the local message gts if the TLC is in Controller Active State (CACS) or when it enters CACS. When the TLC leaves CACS, gts is cleared.

1 0 0 0 1 Take Control Asynchronously

The Take Control Asynchronously command pulses the local message tca.

1 0 0 1 0 Take Control Synchronously

The Take Control Synchronously command sets the local message tcs. The local message tcs is effective only when the TLC is in Controller Standby State (CSBS) or Controller Synchronous Wait State (CSWS). The local message tcs is cleared when the TLC enters Controller Active State (CACS).

1 1 0 1 0 Take Control Synchronously on END

The Take Control Synchronously on END command sets the local message tcs when the data block transfer End message (END bit equal to one) is generated at CSBS. The tcs message is cleared when the TLC enters CACS.

1 0 0 1 1 Listen

The listen command generates the local message ltn in the form of a pulse.

1 1 0 1 1 Listen in Continuous Mode

The Listen in Continuous Mode command generates the local message ltn in the form of a pulse and places the TLC in continuous mode.

(continues)

Table 4-5. Auxiliary Commands: Detail Description (continued)

Command Code (COM4-COM0) 4 3 2 1 0 Description

1 1 0 1 1 In continuous mode, the local message rdy is issued when the (continued) Acceptor Not Ready State (ANRS) is initiated unless data block

transfer end is detected (END RX bit equals one). When END is detected, the TLC is placed in the RFD Holdoff state, preventing generation of the rdy message. In continuous mode, the DI bit is not set when a data byte is received. The continuous mode caused by the Listen in Continuous Mode command is released when the Listen auxiliary command is issued or the TLC enters the Listener Idle State (LIDS).

1 1 1 0 0 Local Unlisten

The Local Unlisten command generates the local message lun in the form of a pulse.

1 1 1 0 1 Execute Parallel Poll

The Execute Parallel Poll command sets the local message Request Parallel Poll (rpp). The rpp message is cleared when the TLC enters either Controller Parallel Poll State (CPPS) or Controller Idle State (CIDS). The transition of the TLC interface function is not guaranteed if the local messages rpp and Go To Standby (gts) are issued simultaneously when the TLC is in Controller Active State (CACS) and Source Transfer State (STRS) or Source Delay State (SDYS).

1 1 1 1 0 Set IFC 1 0 1 1 0 Clear IFC

These commands generate the local message request system control (rsc) and set Interface Clear (IFC) to the value of COM3. These commands should only be issued if the System Controller (SC) bit in CFG2 is set; that is, the GPIB-1014 is SC. In order to meet the IEEE 488 requirements, you must not issue the Clear IFC command until IFC has been held true for at least 100 µsec.

1 1 1 1 1 Set REN 1 0 1 1 1 Clear REN

These commands generate the local message rsc and set REN to the value in COM3. These commands should only be issued if the SC bit in CFG2 is set; that is, the GPIB-1014 is SC. In order to meet IEEE 488 requirements, you must not issue the Set REN command until REN has been held false for at least 100 µsec.

1 0 1 0 0 Disable System Control

The Disable System Control command clears the local message rsc and clears the SC bit.

Chapter 4 Register Descriptions

Hidden Registers

The hidden registers are loaded through the Auxiliary Mode Register (AUXMR). AUXMR[7-5] is loaded with the hidden register number, and AUXMR[4-0] is loaded with the data to be transferred to the hidden register. The hidden registers cannot be read, and in some cases the contents are setable only; that is, they can be cleared or reset to initialized conditions only by issuing the Chip Reset auxiliary command, by a Power On Reset, or by LMR (CR0[2]w). Figure 4-2 earlier in this chapter shows the five hidden registers and illustrates how they are loaded with data from the AUXMR.

Internal Counter Register (ICR)

VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 001 (Binary, Bits 7 - 5) Attributes: Write Only, Internal to TLC

Accessed through AUXMR

43210

0 CLK3 CLK2 CLK1 CLK0

Bit Mnemonic Description

4w 0 Reserved Bit

Write zero to this bit.

3-0w CLK[3-0] Clock Bits 3 through 0

The contents of the ICR are used to divide internal counters that generate TLC state change delay times used by the IEEE 488 specification. The most familiar of these delay times, T1, is the minimum delay between placing the data or command bytes on the GPIB DIO lines and asserting DAV. These delay times vary depending on the type of transfer in progress and the value of the AUXRB bit TRI.

For proper operation, ICR should be set to eight because the TLC is clocked at 8 MHz.

Chapter 4 Register Descriptions

Parallel Poll Register (PPR)

VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 011 (Binary, Bits 7 - 5) Attributes: Write Only, Internal to TLC

Accessed through AUXMR

43210

U S P3 P2 P1

This 5-bit command code determines the manner in which the TLC responds to a Parallel Poll. When using the remote Parallel Poll Configure (IEEE 488 capability code PP1), do not write to

the PPR. The TLC implements remote configuration fully and automatically without software assistance. The hardware recognizes, interprets, and responds to Parallel Poll Configure (PPC), Parallel Poll Enable (PPE), Parallel Poll Disable (PPD), and Identify (IDY) messages. It is only necessary to set or clear the individual status (ist) message (using Set/Clear Parallel Poll Flag auxiliary commands) according to pre-established system protocol convention. Writing to the PPR after it is remotely configured will corrupt the configuration.

When using the local PPC (capability code PP2), a valid PPE or PPD message must be written to the PPR prior to the poll.

Bit Mnemonic Description

4w U Unconfigure Bit

The U bit determines whether or not the TLC participates in a Parallel Poll. If U=0, the TLC participates in Parallel Polls and responds in the manner defined by PPR[3] through PPR[0] and by ist. If U=1, the TLC does not participate in a Parallel Poll.

The U bit is equivalent to the Local Poll Enable, active low (lpe*) message. When U=0, S and P[3-1] mean the same as the bit of the same name in the PPE message, and the I/O write operation (to the PPR) is the same as the receipt of the PPE message from the GPIB Controller. When U=1, S and P[3-1] do not carry any meaning, but they must be cleared.

Bit Mnemonic Description

3w S Status Bit Polarity (Sense) Bit

The S bit is used to indicate the polarity (or sense) of the TLC local ist message. If S=1, the status is in phase, meaning that if, during a Parallel Poll response, S=ist=1, and U=0, the TLC responds to the Parallel Poll by driving one of the eight GPIB DIO lines low, thus asserting it to a logic one. If S=1 and ist=0, the TLC does not drive the DIO line.

If S=0, the status is in reverse phase, meaning that if, during a Parallel Poll, ist=0, and U=0, the TLC responds to the Parallel Poll by driving one of the eight GPIB DIO lines low. If S=0 and ist=1, the TLC does not drive the DIO line.

For more information, refer to Auxiliary Register B and the Clear Parallel Poll Flags/Set Parallel Poll Flags later in this section.

2-0w P[3-1] Parallel Poll Response Bits 3 through 1

PPR bits 3 through 1, designated P[3-1], contain an encoded version of the Parallel Poll response. P[3-1] indicate which of the eight DIO lines is asserted during a Parallel Poll (equal to N-1). The GPIB-1014 normally drives the GPIB DIO lines using three-state drivers. During Parallel Poll responses, however, the drivers automatically convert to Open Collector mode, as required by IEEE 488. For example, if P[3-1]=010 (binary), GPIB DIO line DIO3* is driven low (asserted) if the GPIB-1014 is parallel polled (and S=ist).

Table 4-6 contains some examples of configuring the Parallel Poll Register.

Table 4-6. Examples for Configuring the PPR

Written to the AUXMR 76543210 Result

01110000 Unconfigures PPR 01100000 0 0 0 0 0 is written to the PPR. The GPIB-1014D participates

in a Parallel Poll, asserting the DIO1 line if ist=0. Otherwise, the GPIB-1014D does not participate.

01101001 0 1 0 0 1 is written to the PPR. The GPIB-1014D participates

in a Parallel Poll, asserting the DIO2 line if ist=1. Otherwise, the GPIB-1014D does not participate.

Chapter 4 Register Descriptions

Auxiliary Register A (AUXRA)

VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 100 (Binary, Bits 7 - 5) Attributes: Write Only, Internal to TLC

Accessed through AUXMR

43210

BIN

XEOS

REOS HLDE HLDA

Writing to Auxiliary Register A (AUXRA) is done via the AUXMR. Writing the binary value 100 into the Control Code (CNT[2-0]) and a bit pattern into the Command Code (COM[4-0]) portion of the AUXMR causes the Command Code to be written to AUXRA. When the data is written to AUXRA, the bits are denoted by the mnemonics shown in the register bit map above. This 5-bit code controls the data transfer messages Holdoff and EOS/END.

Bit Mnemonic Description

4w BIN Binary Bit

The BIN bit selects the length of the EOS message. Setting BIN causes the End Of String Register (EOSR) to be treated as a full 8-bit byte. When BIN=0, the EOSR is treated as a 7-bit register (for ASCII characters) and only a 7-bit comparison is done with the data on the GPIB.

3w XEOS Transmit END with EOS Bit

The XEOS bit permits or prohibits automatic transmission of the GPIB END message at the same time as the EOS message when the TLC is in Talker Active State (TACS). If XEOS is set and the byte in the CDOR matches the contents of the EOSR, the EOI line is sent true along with the data.

2w REOS END on EOS Received Bit

The REOS bit permits or prohibits setting the END bit (ISR1[4]r) at reception of the EOS message when the TLC is in Listener Active State (LACS). If REOS is set and the byte in the DIR matches the byte in the EOSR, the END bit (ISR1[4]r) is set.

Bit Mnemonic Description

1-0w HLDE Holdoff on End Bit

HLDA Holdoff on All Bit

HLDE and HLDA together determine the GPIB data receiving mode. The four possible modes are as follows:

HLDE HLDA Data Receiving Mode

0 0 Normal Handshake 0 1 RFD Holdoff on All Data 1 0 RFD Holdoff on END 1 1 Continuous

In Normal Handshake mode, the local message rdy is generated when data is received from the GPIB. When the received data is read from the DIR, rdy is generated in Acceptor Not Ready State (ANRS), the RFD message is transmitted, and the GPIB Handshake continues.

In RFD Holdoff on All Data (HLDA) mode, RFD is not sent true after data is received until the Finish Handshake (FH) auxiliary command is issued. Unlike Normal Handshake mode, the RFD HLDA mode does not generate the rdy message even if the received data is read through the DIR; that is, the GPIB RFD message is not generated.

In RFD Holdoff on End mode, operation is the same as the RFD HLDA mode, but only when the end of the data block (EOS or END message) is detected; that is, the END message is received or, if REOS is set, the EOS character is received. Handshake Holdoff is released by the FH auxiliary command.

In continuous mode, the rdy message is generated when in ANRS until the end of the data block is detected. A Holdoff is generated at the end of a data block. The FH auxiliary command must be issued to release the Holdoff. The continuous mode is useful for monitoring the data block transfer without actually participating in the transfer (no data reception). In continuous mode, the DI bit (ISR1[0]r) is not set by the reception of a data byte.

Chapter 4 Register Descriptions

Auxiliary Register B (AUXRB)

VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 101 (Binary, Bits 7 - 5) Attributes: Write Only, Internal to TLC

Accessed through AUXMR

43210

ISS

INV

TRI SPEOI

CPT

ENABLE

Writing to Auxiliary Register B (AUXRB) is done via the AUXMR. Writing the value 101 into the Control Code (CNT[2-0]) and a bit pattern into the Command Code portion (COM[4-0]) of the AUXMR causes the Command Code to be written to AUXRB. When the data is written to AUXRB, the bits are denoted as shown in the figure above. This 5-bit code affects several interface functions, as described in the following paragraphs.

Bit Mnemonic Description

4w ISS Individual Status Select Bit

The ISS bit determines the value of the TLC ist message. When ISS=1, ist becomes the same value as the TLC Service Request State (SRQS). (The TLC is asserting the GPIB SRQ message when it is in SRQS.) When ISS=0, ist takes on the value of the TLC Parallel Poll Flag. The Parallel Poll Flag is set and cleared using the Set Parallel Poll Flag and Clear Parallel Poll Flag auxiliary commands.

3w INV Invert Bit

The INV bit affects the polarity of the TLC INT pin. Setting INV causes the polarity of the Interrupt (INT) pin on the TLC to be active low. As implemented on the GPIB-1014, configuring the INT pin to active low results in interrupt request errors. Consequently, INV must always be cleared and must never be set except for diagnostic purposes.

INV = 0 : INT pin is active high INV = 1 : INT pin is active low

Bit Mnemonic Description

2w TRI Three-State Timing Bit

The TRI bit determines the TLC GPIB Source Handshake Timing, T1. TRI can be set to enable high-speed data transfers (T1 ≥ 500 nsec) when tri-state GPIB drivers are used. (The GPIB-1014D uses tri-state GPIB drivers except during Parallel Poll responses, in which case the GPIB drivers automatically switch to Open Collector.) Setting TRI enables high-speed timing as T1 of the GPIB Source Handshake after transmission of the first byte. Clearing TRI sets the low-speed timing (T1 ≥ 2 µsec).

1w SPEOI Send Serial Poll EOI Bit

The SPEOI bit permits or prohibits the transmission of the END message in Serial Poll Active State (SPAS). If SPEOI is set, EOI is sent true when the TLC is in SPAS; otherwise, EOI is sent false in SPAS.

0w CPT ENABLE Command Pass Through Enable Bit

The CPT ENABLE bit permits or prohibits the detection of undefined GPIB commands and permits or prohibits the setting of the CPT bit (ISR1[7]r) on receipt of an undefined command. When CPT ENABLE is set and an undefined command has been received, the DAC message is held and the Handshake stops until the Valid auxiliary command is issued. The undefined command can be read from the CPTR and processed by the software.

Chapter 4 Register Descriptions

Auxiliary Register E (AUXRE)

VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 110 (Binary, Bits 7 - 5) Attributes: Write Only, Internal to TLC

Accessed through AUXMR

43210

0 DHDC DHDT

Writing to Auxiliary Register E (AUXRE) is done via the AUXMR. Writing the binary value 110 into the Control Code (CNT[2-0]) and a bit pattern into the the lower five bits of the AUXMR (COM[4-0]) causes the two lowest order bits to be written to AUXRE. The 2-bit code, DHDC and DHDT, determines how the TLC may be placed into DAC Holdoff.

Bit Mnemonic Description

4-2w 0 Reserved Bits

Write zeros to these bits.

1w DHDC DAC Holdoff on DCAS Bit

Setting DHDC enables DAC Holdoff when the TLC enters Device Clear Active State (DCAS). Clearing DHDC disables DAC Holdoff on DCAS. Issuing the Finish Handshake auxiliary command releases the Holdoff.

0w DHDT DAC Holdoff on DTAS Bit

Setting DHDT enables DAC Holdoff when the TLC enters Device Trigger Active State (DTAS). Clearing DHDT disables DAC Holdoff on DTAS. Issuing the Finish Handshake auxiliary command releases the Holdoff.

Address Register 0 (ADR0)

VMEbus Address: Base Address + 11D (hex) Attributes: Read Only, Internal to TLC

76543210

X DT0 DL0 AD5-0 AD4-0 AD3-0 AD2-0 AD1-0

Address Register 0 (ADR0) reflects the internal GPIB address status of the TLC as configured using the ADMR. In addressing mode 2, ADR0 indicates the address and enable bits for the primary GPIB address of the TLC. In dual primary addressing (modes 1 and 3) ADR0 indicates the TLC major primary GPIB address. Refer to the description of the Address Mode Register in this section for information on addressing modes.

Bit Mnemonic Description

7r X Don't Care Bit

Reads as a zero or one.

6r DT0 Disable Talker 0 Bit

If DT0 is set, it indicates that the mode 2 primary (or mode 1 and 3 major) Talker is not enabled; that is, the TLC does not respond to a GPIB talk address matching AD[5-0 – 1-0]. If DT0=0, the TLC responds to a GPIB talk address matching bits AD[5-0 – 1-0].

5r DL0 Disable Listener 0 Bit

If DL0 is set, it indicates that the mode 2 primary (or mode 1 and 3 major) Listener is not enabled; that is, the TLC does not respond to a GPIB listen address matching bits AD[5-0 – 1-0]. If DL0=0, the TLC responds to a GPIB listen address matching bits AD[5-0 – 1-0].

4-0r AD[5-0 – 1-0] Mode 2 Primary TLC GPIB Address Bits 5-0 through 1-0

These are the lower five bits of the TLC GPIB primary (or major) address. The primary talk address is formed by adding hex 40 to AD[5-0 – 1-0], while the listen address is formed by adding hex 20.

Chapter 4 Register Descriptions

Address Register (ADR)

VMEbus Address: Base Address + 11D (hex) Attributes: Write Only, Internal to TLC

76543210

ARS DT DL AD5 AD4 AD3

AD2 AD1

The Address Register (ADR) is used to load the internal registers ADR0 and ADR1. Both ADR0 and ADR1 must be loaded for all addressing modes.

Bit Mnemonic Description

7w ARS Address Register Select Bit

ARS is zero or one to select whether the seven low-order bits of ADR must be loaded into internal registers ADR0 or ADR1, respectively.

6w DT Disable Talker Bit

DT must be set if recognition of the GPIB talk address formed from AD5 through AD1 (ADR[4-0]w) is not to enable.

5w DL Disable Listener Bit

DL must be set if recognition of the GPIB listen address formed from AD5 through AD1 (ADR[4-0]w) is not to enable.

4-0w AD[5-1] TLC GPIB Address Bits 5 through 1

These bits indicate the five low-order bits of the GPIB address that is to be recognized by the TLC. The corresponding GPIB talk address is formed by adding hex 40 to AD[5-1], while the corresponding GPIB listen address is formed by adding hex 20. The value written to AD[5-1] must not be all ones; otherwise, the corresponding talk and listen addresses would conflict with the GPIB Untalk (UNT) and GPIB Unlisten (UNL) commands.

Address Register 1 (ADR1)

VMEbus Address: Base Address + 11F (hex) Attributes: Read Only, Internal to TLC

76543210

EOI

DT1 DL1 AD5-1 AD4-1 AD3-1 AD2-1

AD1-1

Address Register 1 (ADR1) indicates the status of the GPIB address and enable bits for the secondary address of the TLC if mode 2 addressing is used, or the minor primary address of the TLC if dual-primary addressing is used (modes 1 and 3). If mode 1 addressing is used and only a single-primary address is needed, both the talk and listen addresses disable in this register. If mode 2 addressing is used, the talk and listen disable bits in this register must match those in ADR0.

Bit Mnemonic Description

7r EOI End Or Identify Bit

EOI indicates the value of the GPIB EOI line latched when a data byte is received by the TLC GPIB Acceptor Handshake (AH) function. If EOI=1, the EOI line was asserted with the received byte. EOI is cleared by pon or by using the Chip Reset auxiliary command. EOI is updated after each byte is received.

6r DT1 Disable Talker 1 Bit

If DT1 is set, the mode 2 secondary (or mode 1 and 3 minor) Talker function is not enabled; that is, the TLC does not respond to a secondary address (or minor primary talk address) formed from bits AD[5-1 – 1-1]. If DT1 is cleared, the secondary address is checked only if the TLC received its primary talk address (that is, is in TPAS).

5r DL1 Disable Listener 1 Bit

If DL1=1, the mode 2 secondary (or mode 1 and 3 minor) listen function is not enabled; that is, the TLC does not respond to a secondary address (or minor primary listen address formed from bits AD5-1 through AD1-1). If DL1 is cleared and the TLC received its primary listen address (that is, is in LPAS), the secondary address is checked.

4-0r AD[5-1 – 1-1] Mode 2 Secondary TLC GPIB Address Bits 5-1 through 1-1

These are the lower five bits of the TLC secondary or minor address. The secondary address is formed by adding hex A0 to bits AD[5-1 – 1-1]. The minor talk address is formed by adding hex 40 to AD[5-1 – 1-1], while the listen address is formed by adding a hex 20.

Chapter 4 Register Descriptions

End of String Register (EOSR)

VMEbus Address: Base Address + 11F hex Attributes: Write Only, Internal to TLC

7 654 3210

EOS7

EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOS0

The End Of String Register (EOSR) holds the byte used by the TLC to detect the end of a GPIB data block transfer. A 7- or 8-bit byte (ASCII or binary) can be placed in the EOSR to be used in detecting the end of a block of data. The length of the EOS byte to be used in the comparison is selected by the BIN bit in AUXRA (AUXRA[4w]).

If the TLC is a Listener, and bit REOS of AUXRA is set, the END bit is set in ISR1 whenever the byte in the DIR matches the EOSR. If the TLC is a Talker and the data is being transmitted, and bit XEOS of AUXRA is set, the END message (GPIB EOI* line asserted low) is sent along with the data byte whenever the contents of the CDOR match the EOSR.

Bit Mnemonic Description

7-0w EOS[7-0] End of String Bits 7 through 0

DMA Registers

The onboard DMA Controller is a 68450 DMAC. This chip is extremely flexible and uses four independent DMA channels. The DMAC can support single address (flyby) transfers or dual address (flowthrough) transfers. The GPIB-1014 uses two channels (Channel 0 and 1) for 8-bit flyby DMA transfers between VMEbus memory and the GPIB. All four channels are available for 8- or 16-bit flowthrough memory-to-memory DMA transfers. The DMAC supports unchained, continue, array chained, or link chained operations between memory and memory or between memory and device (GPIB). The TLC-to-DMAC interface includes lines for requesting, acknowledging, and providing incidental control of the TLC.

The DMAC contains a large number of internal configuration and status registers. These registers define and control the activity of the DMAC in processing a channel operation. The registers are addressed relative to the base address of the board. Locations not used in the board address space are reserved. The registers set associated with each DMA channel is shown in Table 4-7.

Table 4-7. DMAC DMA Channel Register Set

Memory Address Register MAR 32 bits Memory Transfer Counter Register MTCR 16 bits Memory Function Code Register MFCR 8 bits

Device Address Register DAR 32 bits Device Function Code Register DFCR 8 bits

Base Address Register BAR 32 bits Base Transfer Counter Register BTCR 16 bits Base Function Code Register BFCR 8 bits

Channel Status Register CSR 8 bits Channel Error Register CER 8 bits Device Control Register DCR 8 bits Operation Control Register OCR 8 bits Sequence Control Register SCR 8 bits Channel Control Register CCR 8 bits Channel Priority Register CPR 8 bits

Normal Interrupt Vector Register NIVR 8 bits Error Interrupt Vector Register EIVR 8 bits

The register set for each channel is addressed relative to the base address of the GPIB-1014 as outlined in Table 2-2. Figure 4-3 shows the DMA registers in order of their register offset.

Figure 4-3 is reprinted with permission of the copyright owner from the Motorola MC68440 Dual-Channel Direct Memory Access Controller, Advance Information, February 1984 Edition, p. 3-20. © Copyright 1984 Motorola, Inc.

Chapter 4 Register Descriptions

Key

Null Bit Position.

* The GCR is located at FF only.

Channel

Base

CH0 - 00 CH1 - 40 CH2 - 80

CH3 - C0

Offset

00 02

04 06 08 0A 0C 0E 10 12 14

16 18 1A 1C 1E 20 22 24 26 28 2A

2C 2E 30 32 34 36 38 3A 3C 3E

15 0

CSR CER

DCR

SCR

MSB

MTCR

MAR

DAR

BTCR

BAR

OCR CCR

LSB

NIVR

EIVR

MFCR

CPR

DFCR

BFCR

GCR*

Offset

01 03

05 07 09 0B 0D 0F 11 13 15

17 19 1B 1D 1F 21 23 25 27 29 2B

2D 2F 31 33 35 37 39 3B 3D 3F

Note: The Register Address equals the Channel Base plus the Register Offset.

Reprinted from the Motorola MC68440 Advance Information manual.

Figure 4-3. DMA Register Memory Map

The following paragraphs describe the channel configuration and status registers. More information on the 68450 can be found in the Motorola Semiconductor Technical Data

MC68450 Advance Information Direct Memory Access Controller (DMAC) or the Hitachi Microcomputer System HD68450 DMAC (Direct Memory Access Controller). Each channel

contains the same status and configuration registers.

Address Registers

The Memory Address Register (MAR), Base Address Register (BAR), and Device Address Register (DAR) are 32-bit registers. Due to packaging limitations, only the least significant 24 bits are connected to the address output pins.

The Memory Address Register (MAR) is used to hold the address of the VMEbus memory location, which is where the data is transferred. This register is used in all DMA operations (memory-to-memory or memory-to-device).

The Base Address Register (BAR) is used in continue, array chained, and link chained operations. In continue mode of operation, the BAR holds the address of the next block of data to be transferred. At the end of the last block transfer, the content of the BAR is automatically transferred to the MAR and a next block transfer is started. In array chained and link chained modes of operation, the BAR is used as a pointer to a table in memory which holds the address(es) of the data block(s) to be transferred. Using the BAR in the chained modes of operation, the DMAC first reads (using DMA) the address of the next block to be transferred into the MAR, then starts the actual data transfer. In most GPIB-to-memory transfers, the array chained mode of operation is used. For more information on this mode, see Sending/Receiving Messages in Chapter 5 and Block Termination in Chapter 6.

The Device Address Register (DAR) is used to hold the device address when the DMA transfer is in dual address (flowthrough) mode. This mode is used for devices that cannot be implicitly addressed with an acknowledge (ACK) signal, but must be addressed via the address bus. Flowthrough transfers address both the memory and the device by executing two bus cycles and storing the data temporarily in an internal register. In single-address (flyby) transfers, the device is implicitly addressed with an acknowledge signal, so that the data transfer takes one cycle and the data is transferred directly between the device and memory. DMA transfers between the GPIB and VMEbus memory use only flyby mode, so the device address register is not used. General purpose memory-to-memory (flowthrough) transfers use both the MAR and DAR to hold the source and destination VMEbus memory addresses.

While data transfers between the GPIB and VMEbus memory must use flyby mode, memory-to-memory DMA transfers can be accomplished using any of the four available fullfunction DMA channels (channels 0 to 3). This not only makes the GPIB-1014 available as a general purpose VMEbus DMA Controller, but also enables comprehensive stand-alone diagnostics to be performed on the DMA circuitry without using the GPIB.

Chapter 4 Register Descriptions

Transfer Count Registers

The Memory Transfer Counter Register (MTCR) and the Base Transfer Counter Register (BTCR) are 16-bit registers. The MTCR is used to specify how many operands will be transferred. (An operand can be either a byte (8 bits) or a word (16 bits)). This register is loaded prior to starting the channel and will be decremented with each operand transfer. When the contents of this register are zero and the operation is unchained (or the chain is exhausted), the channel has reached terminal count and the COC bit of the CSR is set. In continue mode of operation, the BTCR holds the size of the next block to be transferred which is then transferred into the MTCR when the last block is finished. In array chaining mode of operation, the BTCR holds the number of memory blocks to be transferred. Linked chaining mode of operation does not use the BTCR.

Function Code Registers

VMEbus Address: Base Address + 29 (hex) for Memory Function Code

Base Address + 31 (hex) for Device Function Code Base Address + 39 (hex) for Base Function Code

Attributes: Read/Write, Internal to DMAC

7 654 321 0

X XXXXM2M1M0

R/W

On each of the four DMAC channels, there are three Function Code Registers (FCRs) associated with the three address registers (MAR, DAR, and BAR). The three FCRs are MFCR, DFCR, and BFCR. During a DMA cycle, when the DMAC outputs the contents of one of the three address registers, the DMAC also outputs the associated FCR. The 3-bit value of an FCR along with jumpers W3, W4, and W5 determine the 6-bit Address Modifier (AM) code on the VMEbus. The AM codes are used to identify the type of cycle specified by the DMAC when the GPIB-1014 is the bus master.

Table 3-1 shows how to program bits M2 through M0 to produce AM codes supported by the default settings of W3, W4, and W5. Tables 3-2 shows how to program bits M2 through M0 to produce any arbitrary AM code.

Bit Mnemonic Description

7-3r/w X Don't Care Bits

Read as zeros or ones.

2r/w M2 Supervisor/User Access Bit

If this bit is a one, the GPIB-1014 will specify Supervisor access. If it is a zero, the GPIB-1014 will specify User access.

1r/w M1 Standard/Short Addressing Bit

If this bit is a one, the GPIB-1014 will specify a standard 24-bit cycle. If it is a zero, the GPIB-1014 will specify a 16-bit short I/O cycle.

0r/w M0 Program/Data Access Bit

If this bit is a one, the GPIB-1014 will access program area. If it is a zero, the GPIB-1014 will access data area.

Chapter 4 Register Descriptions

Device Control Register

VMEbus Address: Base Address + 04 (hex) Attributes: Read/Write, Internal to DMAC

7 654 3210

XRM DTYP DPS 0 PCL R/W

The Device Control Register (DCR) is a device-soriented control register.

Bit Mnemonic Description

7-6r/w XRM External Request Mode Bits 7 through 6

The External Request Mode bits indicate whether the channel is in cycle steal or cycle steal with hold transfer mode. These two modes are used in all GPIB applications. Burst mode is not used in GPIB-1014 GPIB data transfers, but may be used in memory-to-memory transfers.

00 = Burst Transfer Mode 10 = Cycle Steal Mode 01 = Undefined, Reserved 11 = Cycle Steal with Hold Mode

5-4r/w DTYP Device Type Bits 5 through 4

The Device Type bits indicate what type of device is on the channel. For the GPIB-1014 GPIB application, set the device type to 10 (device with ACK). For memory-to-memory transfers, set the device type to 00 (68000-compatible).

00 = 68000-compatible, explicitly addressed 01 = 6800-compatible, explicitly addressed 10 = Device with ACK, implicitly addressed 11 = Device with ACK and READY

3r/w DPS Device Port Size Bit

The Device Port Size bit indicates the size of the device port. For GPIB-1014 GPIB transfers, the device port size is 8 bits. For memory-to-memory transfers, the device port size can be 8 or 16 bits.

0 = 8-bit port 1 = 16-bit port

Bit Mnemonic Description

2r/w 0 Reserved Bit

Write a zero to this bit.

1-0r/w PCL Peripheral Control Line Bits 1 through 0

Each of the four DMAC channels has a Peripheral Control Line (called PCL0* through PCL3*). The two PCL bits define the function of each line. The GPIB-1014 uses the four lines as status inputs. On PCL0*, GPIB signal SRQ* is connected. On PCL2*, signal REN* is connected. If programmed as status inputs, you can determine the state (high or low) of these two GPIB signals by reading the PCS bit in the appropriate CSR. PCL1* is designed to detect an interrupt from the TLC, synchronization of the GPIB handshake, or a bus error during a DMA transfer. PCL1* must be set to 01 (status input with interrupt) if interrupts are used, or 00 (status input) if polling is used. This is described in more detail in the Interrupts section of Chapter 5. PCL3* is left unconnected.

00 = Status Input (can be read by reading CSR) 01 = Status Input with Interrupt 10 = Start Output Pulse, Negative 1/8 CLK 11 = Abort Input

Chapter 4 Register Descriptions

Operation Control Register

VMEbus Address: Base Address + 05 (hex) Attributes: Read/Write, Internal to DMAC

7 654 3210

DIR

0 SIZE CHN REQG R/W

The Operation Control Register (OCR) is an operation-oriented register.

Bit Mnemonic Description

7r/w DIR Direction Bit

The Direction bit specifies the direction of the transfer, to or from VMEbus memory :

0 = Transfer from memory to device 1 = Transfer from device to memory

In GPIB applications, 0 indicates transfers from memory to GPIB and 1 indicates transfers from GPIB to memory.

6r/w 0 Reserved Bit

Write zero to this bit.

5-4r/w SIZE Size Bits 5 through 4

The Size bits indicate the size of the data transfer. For the GPIB-1014 GPIB transfers, the size is always byte 00. For memory-to-memory transfers, the size can be byte, word, or long-word.

00 = Byte (8 bits) 01 = Word (16 bits) 10 = Long-word (32 bits) 11 = (undefined, reserved)

3-2r/w CHN Chain Bits 3 through 2

The Chain bits are used to indicate what type of chaining, if any, is used:

00 = Chain operation is disabled 01 = (undefined, reserved)

10 = Array Chaining 11 = Linked Chaining

Bit Mnemonic Description

In most GPIB applications, either no chaining or array chaining is used. See Chapter 5 for details.

1-0r/w REQG DMA Request Generation Bits 1 through 0

The DMA Request Generation method bits define how requests for transfers are generated. For the GPIB-to-memory DMA transfers, the request mode is always 10 (the REQ line initiates an operand transfer). For memory-to-memory transfers, automatic request mode must be used.

00 = Automatic request at a rate limited by the General Control

01 = Automatic request at maximum rate. 10 = REQ line initiates an operand transfer. 11 = Automatic request the first operand, external request the

remaining operands.

Chapter 4 Register Descriptions

Sequence Control Register

VMEbus Address: Base Address + 06 (hex) Attributes: Read/Write, Internal to DMAC

7 654 3210 0 0 0 0 MAC DAC R/W

The Sequence Control Register (SCR) is used to define the sequencing of memory and device addresses.

Bit Mnemonic Description

7-4r/w 0 Reserved Bits

Write zeros to these bits.

3-2r/w MAC Memory Address Count Bits 3 through 2

The Memory Address Count bits indicate the count sequence of the Memory Address Register:

00 = Memory address does not count 01 = Memory address register counts up 10 = Memory address register counts down 11 = (undefined, reserved)

1-0r/w DAC Device Address Count Bits 1 through 0

The Device Address Count bits indicate the address sequence of the Device Address Register. This is only used in flowthrough memory-to-memory DMA transfers.

00 = Device address does not count 01 = Device address register counts up 10 = Device address register counts down 11 = (undefined, reserved)

Channel Control Register

VMEbus Address: Base Address + 07 (hex) Attributes: Read/Write, Internal to DMAC

7 654 321 0

STR CNT HLT SAB EINT 0 0 0 R/W

This register is used to control the operation of the channel. By writing to this register, a channel operation can be started and set to be continued, halted, and aborted. Also, the channel can be enabled to issue interrupts when an operation is terminated (normal or error termination). Setting the STR bit causes immediate activation of the channel; the channel will be ready to accept requests immediately. The STR and CNT bits of the register cannot be reset by a write to the register. The software abort bit (SAB) can be used to terminate the operation. Setting the SAB resets the STR and CNT. Setting the HLT bit halts the channel and resetting the HLT bit resumes the operation.

Bit Mnemonic Description

7r/w STR Start Bit

The Start bit is used to start the operation of the channel. 0 = No operation is pending

1 = Start operation

6r/w CNT Continue Bit

The Continue bit is used to select the continue option. This bit must be set when the channel is active or at the same time you set the STR bit. Generally, this is not used for GPIB-1014 GPIB transfers.

0 = No continuation is pending 1 = Continue operation

5r/w HLT Halt Bit

The Halt bit is used to temporarily halt channel operation. 0 = Operation not halted

1 = Operation halted

4r/w SAB Software Abort Bit

The Software Abort bit is used to abort channel operation.

National Instruments 320030-01 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Limited Warranty

Copyright

Trademarks

FCC/DOC Radio Frequency Interference Compliance

Figures

Tables

About This Manual

Organization of This Manual

Conventions Used in This Manual

Related Documentation

Customer Communication

Chapter 1 Introduction

Figure 1-1. GPIB-1014 Interface Board

What Your Kit Should Contain

Optional Equipment

Unpacking

Chapter 2 General Description

Electrical Characteristics

Table 2-1. GPIB-1014 Signals

VMEbus Characteristics

VMEbus Slave-Addressing

VMEbus Slave-Data

Table 2-3. 68450 Internal DMA Registers

Table 2-4. GPIB-1014 Configuration Registers

VMEbus Master-Direct Memory Access

Interrupter

Data Transfer Bus (DTB) Requester

VMEbus Modules Not Provided

Diagnostic Aids

Data Transfer Features

Programmed I/O Transfers

GPIB-1014 Functional Description

Figure 2-1. GPIB-1014 with a VMEbus Computer

Figure 2-2. GPIB-1014 in a Multiprocessor Application

Figure 2-3. GPIB-1014 Block Diagram

Table 2-5. GPIB-1014 IEEE 488 Interface Capabilities

Table 2-6. GPIB-1014 IEEE 1014 Interrupter Compliance Levels

Chapter 3 Configuration and Installation

Configuration

Figure 3-1. Parts Locator Diagram

Access Mode

Figure 3-2. Access Mode After RESET

Base Address

Set Base Address Using Jumper Block W1

Figure 3-3. Configuration for GPIB-1014 Base Address 2000 (hex)

Set Base Address Using Compare Address Lines

DMA Address Modifier Code Output

Figure 3-4. Default Settings of AM Code Jumpers W3, W4, and W5

Table 3-1. Programming Values for Default Settings of W3, W4, and W5

Table 3-2. Setting the Address Modifier Code Bits (AM5-AM0)

Other Configuration Parameters

Installation

Verification of System Compatibility

Table 3-3. GPIB-1014 Pin Assignment on VMEbus Connector P1

Table 3-4. GPIB-1014 Pin Assignment on VMEbus Connector P2

Cabling

Verification Testing

Chapter 4 Register Bit Descriptions

Register Map

Table 4-1. GPIB-1014 Register Map

Register Sizes

Register Description

Register Description Format

Table 4-2. Clues to Understanding Mnemonics

Interface Registers

Figure 4-1. Interface Registers

Figure 4-2. Writing to the Hidden Registers

Data In Register (DIR)

Command/Data Out Register (CDOR)

Interrupt Status Register 1 (ISR1)

Interrupt Mask Register 1 (IMR1)

Interrupt Status Register 2 (ISR2)

Interrupt Mask Register 2 (IMR2)

Serial Poll Status Register (SPSR)

Serial Poll Mode Register (SPMR)

Address Status Register (ADSR)