National CP3BT26 User Manual
PRELIMINARY
MAY 2004
CP3BT26 Reprogrammable Connectivity Processor with
Bluetooth®, USB, and CAN Interfaces
1.0 General Description
The CP3BT26 connectivity processor combines high performance with the massive integration needed for embedded
Bluetooth applications. A powerful RISC core with on-chip
SRAM and Flash memory provides high computing bandwidth, hardware communications peripherals provide highI/O bandwidth, and an external bus provides system expandability.
On-chip communications peripherals include: Bluetooth
Lower Link Controller, Universal Serial Bus (USB) 1.1 node,
CAN, Microwire/Plus, SPI, ACCESS.bus, quad UART, 12-bit
A/D converter, and Advanced Audio Interface (AAI). Additional on-chip peripherals include Random Number Generator (RNG), DMA controller, CVSD/PCM conversion
module, Timing and Watchdog Unit, Versatile Timer Unit,
Multi-Function Timer, and Multi-Input Wake-Up (MIWU)
unit.
Bluetooth hand-held devices can be both smaller and lower
in cost for maximum consumer appeal. The low voltage and
advanced power-saving modes achieve new design points
in the trade-off between battery size and operating time for
handheld and portable applications.
In addition to providing the features needed for the next generation of embedded Bluetooth products, the CP3BT26 is
backed up by the software resources designers need for
rapid time-to-market, including an operating system, Bluetooth protocol stack implementation, peripheral drivers, reference designs, and an integrated development
environment. Combined with a Bluetooth radio transceiver
such as National’s LMX5252, the CP3BT26 provides a complete Bluetooth system solution.
National Semiconductor offers a complete and industryproven application development environment for CP3BT26
applications, including the IAR Embedded Workbench,
iSYSTEM winIDEA and iC3000 Active Emulator, Bluetooth
Development Board, Bluetooth Protocol Stack, and Application Software.
CP3BT26 Connectivity Processor with Bluetooth and Dual CAN Interfaces
Block Diagram
Clock Generator
12 MHz and 32 kHz
Oscillator
CR16C
CPU Core
Bus
Interface
Unit
GPIO
PLL and Clock
256K Bytes
Flash
Program
Memory
DMA
Controller
Audio
Interface
Generator
8K Bytes
Flash
Data
Peripheral
Bus
Controller
Microwiire/
SPI
Power-on-Reset
32K Bytes
Static
RAM
Interrupt
Control
Unit
Quad UART
CAN 2.0B
Controller
CPU Core Bus
CVSD/PCM
Peripheral Bus
ACCESS
.bus
Converter
Timer Unit
Versatile
RF Interface
Protocol
Core
Powe r
Manage-
ment
Muti-Func-
tion Timer
Bluetooth Lower
Link Controller
1K Byte
Sequencer RAM
4.5K Bytes
Data RAM
Timing and
Watchdog
Unit
Multi-Input
Wake-Up
Serial
Debug
Interface
Random
Number
Generator
8-Channel
12-bit ADC
USB
DS202
Bluetooth is a registered trademark of Bluetooth SIG, Inc. and is used under license by National Semiconductor.
TRI-STATE is a registered trademark of National Semiconductor Corporation.
©2004 National Semiconductor Corporation www.national.com
1.0 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.0 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
CP3BT26
3.1 CR16C CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.3 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.4 Bus Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.5 Interrupt Control Unit (ICU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.6 Multi-Input Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.7 Bluetooth LLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.8 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.9 CAN Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.10 Quad UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.11 Advanced Audio interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.12 CVSD/PCM Conversion Module. . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.13 12-bit Analog to Digital Converter. . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.14 Random Number Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.15 Microwire/SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.16 ACCESS.bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.17 Multi-Function Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.18 Timing and Watchdog Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.19 Versatile Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.20 Triple Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.21 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.22 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.23 Serial Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.24 Development Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.0 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.0 CPU Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 Dedicated Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Processor Status Register (PSR). . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 Configuration Register (CFG). . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6 Stacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.7 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.0 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1 Operating Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2 Bus Interface Unit (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3 Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4 BIU Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.5 Wait and Hold States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.0 System Configuration Registers . . . . . . . . . . . . . . . 29
7.1 Module Configuration Register (MCFG) . . . . . . . . . . . . . . . . . . . . 29
7.2 Module Status Register (MSTAT). . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3 Software Reset Register (SWRESET) . . . . . . . . . . . . . . . . . . . . . 30
8.0 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.1 Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.2 Flash Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.3 Flash Memory Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.4 Information Block Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.5 Flash Memory Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . 35
9.0 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1 Channel Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.2 Transfer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.3 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.4 Software DMA Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.5 Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.6 DMA Controller Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.0 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1 Non-Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.2 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.3 Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.4 Maskable Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.5 Nested Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.0 Triple Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . 51
11.1 External Crystal Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.2 Main Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.3 Slow Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.4 PLL Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.5 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.6 Auxiliary Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.7 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.8 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.9 Clock and Reset Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
12.0 Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.1 Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.2 Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.3 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.4 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.5 Hardware Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.6 Power Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.7 Switching Between Power Modes . . . . . . . . . . . . . . . . . . . . . . . . 59
13.0 Multi-Input Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . 61
13.1 Multi-Input Wake-Up Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 62
13.2 Programming Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
14.0 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
14.1 Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
14.2 Open-Drain Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
15.0 Bluetooth Controller . . . . . . . . . . . . . . . . . . . . . . . . . 72
15.1 RF Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
15.2 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
15.3 LMX5251 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 76
15.4 LMX5252 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 76
15.5 Bluetooth Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
15.6 Bluetooth Global Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
15.7 Bluetooth Sequencer RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
15.8 Bluetooth Shared Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
16.0 12-Bit Analog to Digital Converter . . . . . . . . . . . . . . 79
16.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
16.2 Touchscreen Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table of Contents
16.3 ADC Operation in Power-Saving Modes . . . . . . . . . . . . . . . . . . . 83
16.4 Freeze. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
16.5 ADC Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
17.0 Random Number Generator (RNG). . . . . . . . . . . . . . 88
17.1 Freeze. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
17.2 Random Number Generator Register Set . . . . . . . . . . . . . . . . . . 89
18.0 USB Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
18.1 Functional States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
18.2 Endpoint Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
18.3 USB Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
18.4 Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
19.0 CAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
19.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
19.2 Basic CAN Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
19.3 Message Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
19.4 Acceptance Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
19.5 Receive Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
19.6 Transmit Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
19.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
19.8 Time Stamp Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
19.9 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
19.10 CAN Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
19.11 System Start-Up and Multi-Input Wake-Up. . . . . . . . . . . . . . . . . 140
19.12 Usage Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
20.0 Advanced Audio Interface . . . . . . . . . . . . . . . . . . . . 143
20.1 Audio Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
20.2 Audio Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
20.3 Bit Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
20.4 Frame Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
20.5 Audio Interface Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
20.6 Communication Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
20.7 Audio Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
21.0 CVSD/PCM Conversion Module . . . . . . . . . . . . . . . 158
21.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
21.2 PCM Conversions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
21.3 CVSD Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
21.4 PCM to CVSD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
21.5 CVSD to PCM Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
21.6 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
21.7 DMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
21.8 Freeze. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
21.9 CVSD/PCM Converter Registers . . . . . . . . . . . . . . . . . . . . . . . . 160
22.0 UART Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
22.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
22.2 UART Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
22.3 UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
22.4 Baud Rate Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
23.0 Microwire/SPI Interface . . . . . . . . . . . . . . . . . . . . . . 175
23.1 Microwire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
23.2 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
23.3 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
23.4 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
23.5 Microwire Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
24.0 ACCESS.bus Interface . . . . . . . . . . . . . . . . . . . . . . . 181
24.1 ACB Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
24.2 ACB Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
24.3 ACCESS.bus Interface Registers. . . . . . . . . . . . . . . . . . . . . . . . 185
24.4 Usage Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
25.0 Timing and Watchdog Module . . . . . . . . . . . . . . . . 192
25.1 TWM Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
25.2 Timer T0 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
25.3 Watchdog Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
25.4 TWM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
25.5 Watchdog Programming Procedure . . . . . . . . . . . . . . . . . . . . . . 195
26.0 Multi-Function Timer . . . . . . . . . . . . . . . . . . . . . . . . 196
26.1 Timer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
26.2 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
26.3 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
26.4 Timer I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
26.5 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
27.0 Versatile Timer Unit (VTU) . . . . . . . . . . . . . . . . . . . . 206
27.1 VTU Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
27.2 VTU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
28.0 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
29.0 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . 230
30.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 243
30.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
30.2 DC Electrical Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
30.3 USB Transceiver Electrical Characteristics . . . . . . . . . . . . . . . . 245
30.4 ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 245
30.5 Flash Memory On-Chip Programming . . . . . . . . . . . . . . . . . . . . 246
30.6 Output Signal Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
30.7 Clock and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
30.8 UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
30.9 I/O Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
30.10 Advanced Audio Interface (AAI) Timing . . . . . . . . . . . . . . . . . . . 251
30.11 Microwire/SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
30.12 ACCESS.bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
30.13 USB Port AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
30.14 Multi-Function Timer (MFT) Timing . . . . . . . . . . . . . . . . . . . . . . 261
30.15 Versatile Timing Unit (VTU) Timing . . . . . . . . . . . . . . . . . . . . . . 262
30.16 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
31.0 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
31.1 LQFP-128 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
31.2 LQFP-144 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
32.0 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
33.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 277
www.national.com 2
2.0 Features
CPU Features
Fully static RISC processor core, capable of operating
from 0 to 24 MHz with zero wait/hold states
Minimum 41.7 ns instruction cycle time with a 24-MHz in-
ternal clock frequency, based on a 12-MHz external input
47 independently vectored peripheral interrupts
On-Chip Memory
256K bytes reprogrammable Flash program memory
8K bytes Flash data memory
32K bytes of static RAM data memory
Addresses up to 12M bytes of external memory
Broad Range of Hardware Communications Peripherals
Bluetooth Lower Link Controller (LLC) including a shared
4.5K byte Bluetooth RAM and 1K byte Bluetooth Sequencer RAM
Universal Serial Bus (USB) 1.1 full-speed node
ACCESS.bus serial bus (compatible with Philips I
CAN interface with 15 message buffers conforming to
CAN specification 2.0B active
8/16-bit SPI, Microwire/Plus serial interface
Four-channel Universal Asynchronous Receiver/Trans-
mitter (UART), one channel has USART capability
Advanced Audio Interface (AAI) to connect to external 8/
13-bit PCM Codecs as well as to ISDN-Controllers
through the IOM-2 interface (slave only)
CVSD/PCM converter supporting one bidirectional audio
connection
General-Purpose Hardware Peripherals
12-bit A/D Converter (ADC)
Dual 16-bit Multi-Function Timer (MFT)
Versatile Timer Unit with four subsystems (VTU)
Four-channel DMA controller
Timing and Watchdog Unit
Random Number Generator peripheral
Extensive Power and Clock Management Support
On-chip Phase Locked Loop
Support for multiple clock options
Dual clock and reset
2
C bus)
CP3BT26
Power-down modes
Flexible I/O
Up to 54 general-purpose I/O pins (shared with on-chip
peripheral I/O)
Programmable I/O pin characteristics: TRI-STATE out-
put, push-pull output, weak pull-up input, high-impedance input
Schmitt triggers on general-purpose inputs
Multi-Input Wake-Up (MIWU) capability
Power Supply
I/O port operation at 2.5V to 3.3V
Core logic operation at 2.5V
On-chip power-on reset
Temperature Range
-40°C to +85°C (Industrial)
Packages
LQFP-128, LQFP-144
Complete Development Environment
Pre-integrated hardware and software support for rapid
prototyping and production
Integrated environment
Project manager
Multi-file C source editor
High-level C source debugger
Comprehensive, integrated, one-stop technical support
Bluetooth Protocol Stack
Applications can interface to the high-level protocols or
directly to the low-level Host Controller Interface (HCI)
Transport layer support allows HCI command-based in-
terface over UART port
Baseband (Link Controller) hardware minimizes the
bandwidth demand on the CPU
Link Manager (LM)
Logical Link Control and Adaptation Protocol (L2CAP)
Service Discovery Protocol (SDP)
RFCOMM Serial Port Emulation Protocol
All packet types, piconet, and scatternet functionality
supported
CP3BT26 Connectivity Processor Selection Guide
NSID
CP3BT26G18NEP 24 -40° to +85°C 256 8 32 0 54 LQFP-128
CP3BT26G18NEPNOPB 24 -40° to +85°C 256 8 32 0 54 LQFP-128
CP3BT26G18NEPX 24 -40° to +85°C 256 8 32 0 54 LQFP-128
CP3BT26G18NEPXNOPB 24 -40° to +85°C 256 8 32 0 54 LQFP-128
CP3BT26Y98NEP 24 -40° to +85°C 256 8 32 23 48 LQFP-144
CP3BT26Y98NEPNOPB 24 -40° to +85°C 256 8 32 23 48 LQFP-144
CP3BT26Y98NEPX 24 -40° to +85°C 256 8 32 23 48 LQFP-144
CP3BT26Y98NEPXNOPB 24 -40° to +85°C 256 8 32 23 48 LQFP-144
NEP - Erased part (Bluetooth device address in Information Block 1); X - Tape and reel; NOPB - No lead solder
Speed
(MHz)
Temp. Range
Program
Flash
(Kbytes)
Data
Flash
(Kbytes)
SRAM
(Kbytes)
External
Address
Lines
I/Os
Package
Type
3 www.national.com
3.0 Device Overview
The CP3BT26 connectivity processor is a complete microcomputer with all system timing, interrupt logic, program
CP3BT26
memory, data memory, and I/O ports included on-chip, making it well-suited to a wide range of embedded applications.
The block diagram on page 1 shows the major on-chip components of the CP3BT26 devices.
3.1 CR16C CPU CORE
The CP3BT26 device implements the CR16C CPU core
module. The high performance of the CPU core results from
the implementation of a pipelined architecture with a twobytes-per-cycle pipelined system bus. As a result, the CPU
can support a peak execution rate of one instruction per
clock cycle.
For more information, please refer to the CR16C Programmer’s Reference Manual (document number 424521772101, which may be downloaded from National’s web site at
http://www.national.com).
3.2 MEMORY
The CP3BT26 devices support a uniform linear address
space of up to 16 megabytes. Three types of on-chip memory occupy specific regions within this address space, along
with any external memory:
256K bytes of Flash program memory
8K bytes of Flash data memory
32K bytes of static RAM
Up to 12M bytes of external memory (144-pin devices)
The 256K bytes of Flash program memory are used to store
the application program, Bluetooth protocol stack, and realtime operating system. The Flash memory has security features to prevent unintentional programming and to prevent
unauthorized access to the program code. This memory
can be programmed with an external programming unit or
with the device installed in the application system (in-system programming).
The 8K bytes of Flash data memory are used for non-volatile storage of data entered by the end-user, such as configuration settings.
The 32K bytes of static RAM are used for temporary storage
of data and for the program stack and interrupt stack. Read
and write operations can be byte-wide or word-wide, depending on the instruction executed by the CPU.
Up to 12M bytes of external memory can be added on an
external bus. The external bus is only available on devices
in 144-pin packages.
For Flash program and data memory, the device internally
generates the necessary voltages for programming. No additional power supply is required.
3.3 INPUT/OUTPUT PORTS
The device has up to 54 software-configurable I/O pins, organized into seven ports called Port B, Port C, Port E, Port
G, Port H, Port I, and Port J. Each pin can be configured to
operate as a general-purpose input or general-purpose output. In addition, many I/O pins can be configured to operate
as inputs or outputs for on-chip peripheral modules such as
the UART, timers, or Microwire/SPI interface.
The I/O pin characteristics are fully programmable. Each pin
can be configured to operate as a TRI-STATE output, pushpull output, weak pull-up input, or high-impedance input.
3.4 BUS INTERFACE UNIT
The Bus Interface Unit (BIU) controls access to internal/external memory and I/O. It determines the configured parameters for bus access (such as the number of wait states for
memory access) and issues the appropriate bus signals for
each requested access.
The BIU uses a set of control registers to determine how
many wait states and hold states are used when accessing
Flash program memory and the I/O area. At start-up, the
configuration registers are set for slowest possible memory
access. To achieve fastest possible program execution, appropriate values must be programmed. These settings vary
with the clock frequency and the type of off-chip device being accessed.
3.5 INTERRUPT CONTROL UNIT (ICU)
The ICU receives interrupt requests from internal and external sources and generates interrupts to the CPU. An interrupt is an event that temporarily stops the normal flow of
program execution and causes a separate interrupt handler
to be executed. After the interrupt is serviced, CPU execution continues with the next instruction in the program following the point of interruption.
Interrupts from the timers, UARTs, Microwire/SPI interface,
and Multi-Input Wake-Up, are all maskable interrupts; they
can be enabled or disabled by software. There are 47
maskable interrupts, assigned to 47 linear priority levels.
The highest-priority interrupt is the Non-Maskable Interrupt
), which is generated by a signal received on the NMI
(NMI
input pin.
3.6 MULTI-INPUT WAKE-UP
The two Multi-Input Wake-Up (MIWU) modules can be used
for two purposes: to provide inputs for waking up (exiting)
from the Halt, Idle, or Power Save mode, and to provide general-purpose edge-triggered maskable interrupts to the level-sensitive interrupt control unit (ICU) inputs. Each 16channel module generates four programmable interrupts to
the ICU, for a total of 8 ICU inputs generated from 32 MIWU
inputs. Channels can be individually enabled or disabled,
and programmed to respond to positive or negative edges.
www.national.com 4
3.7 BLUETOOTH LLC
The integrated hardware Bluetooth Lower Link Controller
(LLC) complies to the Bluetooth Specification Version 1.1
and integrates the following functions:
4.5K-byte dedicated Bluetooth Data RAM
1K-byte dedicated Bluetooth Sequencer RAM
Support of all Bluetooth 1.1 packet types
Support for fast frequency hopping of 1600 hops/s
Access code correlation and slot timing recovery circuit
Power Management Control Logic
BlueRF-compatible interface (mode 2/3) to connect with
National’s LMX5252 and other RF transceiver chips
3.8 USB
The CR16 USB node is a Universal Serial Bus (USB) Node
controller compatible with USB Specification 1.1. It integrates the required USB transceiver, the Serial Interface Engine (SIE), and USB endpoint FIFOs. A total of seven
endpoint pipes are supported: one bidirectional pipe for the
mandatory control EP0 and an additional six pipes for unidirectional endpoints to support USB interrupt, bulk, and isochronous data transfers.
3.9 CAN INTERFACE
The CAN module contains a Full CAN 2.0B class, CAN serial bus interface for applications that require a high-speed
(up to 1 Mbits per second) or a low-speed interface with
CAN bus master capability. The data transfer between CAN
and the CPU is established by 15 memory-mapped message buffers, which can be individually configured as receive or transmit buffers. An incoming message is filtered by
two masks, one for the first 14 message buffers and another
one for the 15th message buffer to provide a basic CAN
path. A priority decoder allows any buffer to have the highest or lowest transmit priority. Remote transmission requests can be processed automatically by automatic
reconfiguration to a receiver after transmission or by automated transmit scheduling upon reception. In addition, a
time stamp counter (16-bits wide) is provided to support
real-time applications.
The CAN module is a fast core bus peripheral, which allows
single-cycle byte or word read/write access. A set of diagnostic features (such as loopback, listen only, and error
identification) support the development with the CAN module and provide a sophisticated error management tool.
The CAN receiver can trigger a wake-up condition out of the
low-power modes through the Multi-Input Wake-Up module.
3.10 QUAD UART
Four UART modules support a wide range of programmable
baud rates and data formats, parity generation, and several
error detection schemes. The baud rate is generated onchip, under software control. One UART channel supports
hardware flow control, DMA, and USART capability (synchronous mode).
The UARTs offer a wake-up condition from the low-power
modes using the Multi-Input Wake-Up module.
CP3BT26
3.11 ADVANCED AUDIO INTERFACE
The audio interface provides a serial synchronous, full-duplex interface to CODECs and similar serial devices. Transmit and receive paths operate asynchronously with respect
to each other. Each path uses three signals for communication: shift clock, frame synchronization, and data.
When the receiver and transmitter use separate shift clocks
and frame sync signals, the interface operates in its asynchronous mode. Alternatively, the transmit and receive path
can share the same shift clock and frame sync signals for
synchronous mode operation.
3.12 CVSD/PCM CONVERSION MODULE
The CVSD/PCM module performs conversion between
CVSD data and PCM data, in which the CVSD encoding is
as defined in the Bluetooth specification and the PCM data
can be 8-bit µ-Law, 8-bit A-Law, or 13-bit to 16-bit Linear.
3.13 12-BIT ANALOG TO DIGITAL CONVERTER
This device contains an 8-channel, multiplexed input, successive approximation, 12-bit Analog-to-Digital Converter. It
supports both Single Ended and Differential modes of operation.
The integrated 12-bit ADC provides the following features:
8-channel, multiplexed input
4 differential channels
Single-ended and differential external filtering capability
12-bit resolution; 11-bit accuracy
15-microsecond conversion time
Support for 4-wire touchscreen applications
External start trigger
Programmable start delay after start trigger
Poll or interrupt on done
The ADC is compatible with 4-wire resistive touchscreen
applications and is intended to provide the resolution necessary to support handwriting recognition. Low-ohmic touchscreen drivers are provided internally on the ADC[3:0] pins.
Pendown detection is also provided.
The ADC provides several options for the voltage reference
source. The positive reference can be ADVCC (internal),
VREFP, ADC0, or ADC3. The negative reference can be
ADVCC (internal), ADC1, or ADC2.
Two specific analog channel selection modes are supported. These are as follows:
Allow any specific channel to be selected at one time.
The A/D Converter performs the specific conversion requested and stops.
Allow any differential channel pair to be selected at one
time. The A/D Converter performs the specific differential
conversion requested and stops.
In both Single-Ended and Differential modes, there is the
capability to connect the analog multiplexer output and A/D
converter input to external pins. This provides the ability to
externally connect a common filter/signal conditioning circuit for the A/D Converter.
5 www.national.com
3.14 RANDOM NUMBER GENERATOR
RNG peripheral for use in Trusted Computer Peripheral Applications (TCPA) to improve the authenticity, integrity, and
privacy of Internet-based communication and commerce.
CP3BT26
3.15 MICROWIRE/SPI
The Microwire/SPI (MWSPI) interface module supports synchronous serial communications with other devices that
conform to Microwire or Serial Peripheral Interface (SPI)
specifications. It supports 8-bit and 16-bit data transfers.
The Microwire interface allows several devices to communicate over a single system consisting of four wires: serial in,
serial out, shift clock, and slave enable. At any given time,
the Microwire interface operates as the master or a slave.
The Microwire interface supports the full set of slave select
for multi-slave implementation.
In master mode, the shift clock is generated on-chip under
software control. In slave mode, a wake-up out of a lowpower mode may be triggered using the Multi-Input WakeUp module.
3.16 ACCESS.BUS INTERFACE
The ACCESS.bus interface module (ACB) is a two-wire serial interface compatible with the ACCESS.bus physical layer. It is also compatible with Intel’s System Management
Bus (SMBus) and Philips’ I
configured as a bus master or slave, and it can maintain bidirectional communications with both multiple master and
slave devices.
The ACCESS.bus receiver can trigger a wake-up condition
out of the low-power modes through the Multi-Input WakeUp module.
2
C bus. The ACB module can be
3.17 MULTI-FUNCTION TIMER
The Multi-Function Timer (MFT) module contains a pair of
16-bit timer/counter registers. Each timer/counter unit can
be configured to operate in any of the following modes:
— Processor-Independent Pulse Width Modulation
(PWM) mode: Generates pulses of a specified width
and duty cycle and provides a general-purpose timer/
counter.
— Dual Input Capture mode: Measures the elapsed time
between occurrences of external event and provides
a general-purpose timer/counter.
— Dual Independent Timer mode: Generates system
timing signals or counts occurrences of external
events.
— Single Input Capture and Single Timer mode: Pro-
vides one external event counter and one system timer.
3.18 TIMING AND WATCHDOG MODULE
The Timing and Watchdog Module (TWM) contains a RealTime timer and a Watchdog unit. The Real-Time Clock Timing function can be used to generate periodic real-time
based system interrupts. The timer output is one of 16 inputs to the Multi-Input Wake-Up module which can be used
to exit from a power-saving mode. The Watchdog unit is designed to detect the application program getting stuck in an
infinite loop resulting in loss of program control or “runaway”
programs. When the watchdog triggers, it resets the device.
The TWM is clocked by the low-speed System Clock.
3.19 VERSATILE TIMER UNIT
The Versatile Timer Unit (VTU) module contains four independent timer subsystems, each operating in either dual 8bit PWM configuration, as a single 16-bit PWM timer, or a
16-bit counter with two input capture channels. Each of the
four timer subsystems offer an 8-bit clock prescaler to accommodate a wide range of frequencies.
3.20 TRIPLE CLOCK AND RESET
The Triple Clock and Reset module generates a high-speed
main System Clock from an external crystal network. It also
provides the main system reset signal and a power-on reset
function.
This module generates a slow System Clock (32.768 kHz)
from an optional external crystal network. The Slow Clock is
used for operating the device in a low-power mode. The
32.768 kHz external crystal network is optional, because
the low speed System Clock can be derived from the highspeed clock by a prescaler. Also, two independent clocks divided down from the high speed clock are available on output pins.
The Triple Clock and Reset module provides the clock signals required for the operation of the various CP3BT26 onchip modules. From external crystal networks, it generates
the Main Clock, which can be scaled up to 24 MHz from an
external 12 MHz input clock, and a 32.768 kHz secondary
System Clock. The 12 MHz external clock is primarily used
as the reference frequency for the on-chip PLL. The clock
for modules which require a fixed clock rate (e.g. the Bluetooth LLC and the CVSD/PCM transcoder) is also generated through prescalers from the 12 MHz clock. The PLL may
be used to drive the high-speed System Clock through a
prescaler. Alternatively, the high speed System Clock can
be derived directly from the 12 MHz Main Clock.
In addition, this module generates the device reset by using
reset input signals coming from an external reset and various on-chip modules.
www.national.com 6
3.21 POWER MANAGEMENT
The Power Management Module (PMM) improves the efficiency of the device by changing the operating mode and
power consumption to match the required level of activity.
The device can operate in any of four power modes:
— Active: The device operates at full speed using the
high-frequency clock. All device functions are fully operational.
— Power Save: The device operates at reduced speed
using the Slow Clock. The CPU and some modules
can continue to operate at this low speed.
— Idle: The device is inactive except for the Power Man-
agement Module and Timing and Watchdog Module,
which continue to operate using the Slow Clock.
— Halt: The device is inactive but still retains its internal
state (RAM and register contents).
3.22 DMA CONTROLLER
The Direct Memory Access Controller (DMAC) can speed
up data transfer between memory and I/O devices or between two memories, relative to data transfers performed directly by the CPU. A method called cycle-stealing allows the
CPU and the DMAC to share the CPU bus efficiently. The
DMAC implements four independent DMA channels. DMA
requests from a primary and a secondary source are recognized for each DMA channel, as well as a software DMA request issued directly by the CPU. Table 1 shows the DMA
channel assignment on the CP3BT26 architecture. The following on-chip modules can assert a DMA request to the
DMAC:
• CR16C (Software DMA request)
•USB
• USART
• Advanced Audio Interface
• CVSD/PCM Converter
Table 1 shows how the four DMA channels are assigned
to the modules listed above.
CP3BT26
In the normal mode of operation, the interface only transfers
one word at a periodic rate. In the network mode, the interface transfers multiple words at a periodic rate. The periodic
rate is also called a data frame and each word within one
frame is called a slot. The beginning of each new data frame
is marked by the frame sync signal.
3.23 SERIAL DEBUG INTERFACE
The Serial Debug Interface module (SDI module) provides
a JTAG-based serial link to an external debugger, for example running on a PC. In addition, the SDI module integrates
an on-chip debug module, which allows the user to set up to
eight hardware breakpoints on instruction execution and
data transfer. The SDI module can act as a CPU bus master
to access all memory mapped resources, such as RAM and
peripherals. Therefore it also allows for fast program code
download into the on-chip Flash program memory using the
JTAG interface.
3.24 DEVELOPMENT SUPPORT
In addition to providing the features needed for the next generation of embedded Bluetooth products, the CP3BT26 devices are backed up by the software resources designers
need for rapid product development, including an operating
system, Bluetooth protocol stack implementation, peripheral drivers, reference designs, and an integrated development environment. Combined with National’s LMX5251
Bluetooth radio transceiver, the CP3BT26 devices provide a
total Bluetooth system solution.
National Semiconductor offers a complete and industryproven application development environment for CP3BT26
applications, including the IAR Embedded Workbench,
iSYSTEM winIDEA and iC3000 Active Emulator, Bluetooth
Development Board, Bluetooth Protocol Stack, and Application Software. See your National Semiconductor sales representative for current information on availability and
features of emulation equipment and evaluation boards.
Table 1 DMA Channel Assignment
Channel
0
1
2
3
The interface can handle data words of either 8- or 16-bit
length and data frames can consist of up to four slots.
Primary/
Secondary
Primary USB Read/Write
Secondary UART0 Read
Primary UART0 Write
Secondary Unused N/A
Primary AAI Read
Secondary CVSD/PCM Read
Primary AAI Write
Secondary CVSD/PCM Write
Peripheral Transaction
7 www.national.com
4.0 Signal Descriptions
U
U
U
C
12 MHz Crystal
or Ext. Clock
CP3BT26
32.768 kHz
Crystal
Supply
Chip Reset
JTAG I/F to
Debugger/
Programmer
Selection
RF/MFT
Touchscreen
ACCESS.bus
AN Bus/MIWU
CAN Bus
Powe r
Mode
ADC/
USB
X1CKI/BBCLK
X1CKO
X2CKI
X2CKO
AVC C
1
AGND
1
ADVCC
1
ADGND
1
VCC
6
GND
6
IOVCC
15
IOGND
14
RESET
TMS
TDI
TDO
TCK
RDY
ENV0
ENV1
ENV2
PG7/BTSEQ3/TA
ADC0/TSX+
ADC1/TSY+
ADC2/TSXADC3/TSYADC4/MUXOUT0
ADC5/MUXOUT1
ADC6
ADC7/ADCIN
PJ7/ASYNC/
WUI9
VREFP
SDA
SCL
PH6/CANRX/
WUI17
PH7/CANTX
D+
DUVCC
UGND
CP3BT26
(LQFP-128)
PGO/RFSYNC
PE4/CKX/TB
PH0/RXD1/WUI11
PH1/TXD1/WUI12
PH2/RXD1/WUI13
PH3/TXD1/WUI14
PH4/RXD1/WUI15
PH5/TXD1/WUI16
PF0/MSK/TIO1
PF1/MDIDO/TIO2
PF2/MDODO/TIO3
PF3/MWCS/TIO4
PF4/SCK/TIO5
PF5/SFS/TIO6
PF6/STD/TIO7
PF7/SRD/TIO8
PE5/SRFS/NMI
PG2/BTSEQ1/SRCLK
PG6/BTSEQ2/WUI10
PB[7:0]
PC[7:0]
RFDATA
PG1/RFCE
PG3/SCLK
PG4/SDAT
PG5/SLE
PE0/RXD0
PE1/TXD0
PE2/RTS
PE3/CTS
PJ0/WUI18
PJ1/WUI19
PJ2/WUI20
PJ3/WUI21
PJ4/WUI22
PJ5/WUI23
PJ6/WUI24
8
8
12 MHz Crystal
GPIO
or Ext. Clock
32.768 kHz
RF Interface
Chip Reset
JTAG I/F to
Debugger/
Programmer
UART0
UART0/MFT
Selection
UART1/MIWU
UART2/MIWU
UART3/MIWU
Touchscreen
Microwire/
SPI/
VTU
AAI/
VTU
ACCESS.bus
AAI/NMI
CAN Bus/MIWU
RF/AAI
MIWU
RF/MIWU
Crystal
Powe r
Supply
Mode
RF/MFT
ADC/
CAN Bus
USB
1
1
1
1
6
6
10
11
X1CKI/BBCLK
X1CKO
X2CKI
X2CKO
AVCC
AGND
ADVCC
ADGND
CP3BT26
VCC
(LQFP-144)
GND
IOVCC
IOGND
RESET
TMS
TDI
TDO
TCK
RDY
ENV0
ENV1
ENV2
PG7/BTSEQ3/TA
ADC0/TSX+
ADC1/TSY+
ADC2/TSXADC3/TSYADC4/MUXOUT0
ADC5/MUXOUT1
ADC6
ADC7/ADCIN
PJ7/ASYNC/
WUI9
VREFP
SDA
SCL
PH6/CANRX/
WUI17
PH7/CANTX
D+
DUVCC
UGND
PG2/BTSEQ1/SRCLK
PB[7:0]
PC[7:0]
A[22:0]
SEL0
SEL1
SEL2
SELIO
WR0
WR1
RD
RFDATA
PGO/RFSYNC
PG1/RFCE
PG3/SCLK
PG4/SDAT
PG5/SLE
PE0/RXD0
PE1/TXD0
PE2/RTS
PE3/CTS
PE4/CKX/TB
PH0/RXD1/WUI11
PH1/TXD1/WUI12
PH2/RXD1/WUI13
PH3/TXD1/WUI14
PH4/RXD1/WUI15
PH5/TXD1/WUI16
PF0/MSK/TIO1
PF1/MDIDO/TIO2
PF2/MDODO/TIO3
PF3/MWCS/TIO4
PF4/SCK/TIO5
PF5/SFS/TIO6
PF6/STD/TIO7
PF7/SRD/TIO8
PE5/SRFS/NMI
PJ0/WUI18
PG6/BTSEQ2/WUI10
8
8
23
External
Bus
Interface
RF Interface
UART0
UART0/MFT
UART1/MIW
UART2/MIW
UART3/MIW
Microwire/
SPI/
VTU
AAI/
VTU
AAI/NMI
RF/AAI
MIWU
RF/MIWU
DS208
Figure 1. CP3BT26 Device SIgnals
Some pins may be enabled as general-purpose I/O-port
pins or as alternate functions associated with specific peripherals or interfaces. These pins may be individually configured as port pins, even when the associated peripheral or
interface is enabled. Table 2 describes the device signals for
the LQFP-128 package. Table 3 describes the device signals for the LQFP-144 package.
www.national.com 8
Table 2 CP3BT26 LQFP-128 Signal Descriptions
CP3BT26
Name Pins I/O Primary Function
X1CKI 1
X1CKO 1
X2CKI 1
X2CKO 1
RESET 1
ENV0 1
ENV1 1
ENV2 1
TMS 1
TCK 1
TDI 1
TDO 1
Input 12 MHz Oscillator Input BBCLK BB reference clock for the RF Interface
Output 12 MHz Oscillator Output None None
Input 32 kHz Oscillator Input None None
Output 32 kHz Oscillator Output None None
Input Chip general reset None None
I/O
I/O
I/O
Input
Input
Input
Output JTAG Test Data Output None None
Special mode select input with
internal pull-up during reset
Special mode select input with
internal pull-up during reset
Special mode select input with
internal pull-up during reset
JTAG Test Mode Select
(with internal weak pull-up)
JTAG Test Clock Input
(with internal weak pull-up)
JTAG Test Data Input
(with internal weak pull-up)
Alternate
Name
PLLCLK PLL Clock Output
CPUCLK CPU Clock Output
SLOWCLK Slow Clock Output
None None
None None
None None
Alternate Function
RDY
VCC 6
GND 6
IOVCC 15
IOGND 14
AVC C 1
AGND
ADVCC 1
ADGND
RFDATA
SCL
SDA
D- 1
D+ 1
UVCC 1
UGND
Output NEXUS Ready Output None None
1
Input
Input Core Ground None None
Input 2.5
Input I/O Ground None None
Input PLL Analog Power Supply None None
1 Input PLL Analog Ground None None
Input ADC Analog Power Supply None None
1 Input ADC Analog Ground None None
1 I/O Bluetooth RX/TX Data Pin None None
1 I/O ACCESS.bus Clock None None
1 I/O ACCESS.bus Serial Data None None
I/O USB D- Upstream Port None None
I/O USB D+ Upstream Port None None
Input 3.3V USB Transceiver Supply None None
1 Input USB Transceiver Ground None None
2.5V Core Logic
Power Supply
None None
–3.3V I/O Power Supply None None
ADC0
ADC1
ADC2
1 I/O ADC Input Channel 0 TSX+ Touchscreen X+ contact
1 I/O ADC Input Channel 1 TSY+ Touchscreen Y+ contact
1 I/O ADC Input Channel 2 TSX- Touchscreen X- contact
9 www.national.com
Name Pins I/O Primary Function
Alternate
Name
Alternate Function
CP3BT26
ADC3
ADC4
ADC5
ADC6
ADC7
VREFP
PB[7:0]
PC[7:0]
PE0
PE1
PE2
PE3
PE4
PE5
PF0
PF1
PF2
1 I/O ADC Input Channel 3 TSY- Touchscreen Y- contact
1 I/O ADC Input Channel 4 MUXOUT0 Analog Multiplexer Output 0
1 I/O ADC Input Channel 5 MUXOUT1 Analog Multiplexer Output 1
1 Input ADC Input Channel 6 None None
1 Input ADC Input Channel 7 ADCIN ADC Input (in MUX mode)
1 Input ADC Positive Voltage Reference None None
8 I/O Generic I/O None None
8 I/O Generic I/O None None
1 I/O Generic I/O RXD0 UART Channel 0 Receive Data Input
1 I/O Generic I/O TXD0 UART Channel 0 Transmit Data Output
1 I/O Generic I/O RTS
1 I/O Generic I/O CTS UART Channel 0 Clear-To-Send Input
CKX UART Channel 0 Clock Input
1 I/O Generic I/O
TB Multi Function Timer Port B
SRFS AAI Receive Frame Sync
1 I/O Generic I/O
NMI
MSK SPI Shift Clock
1 I/O Generic I/O
TIO1 Versatile Timer Channel 1
MDIDO SPI Master In Slave Out
1 I/O Generic I/O
TIO2 Versatile Timer Channel 2
MDODI SPI Master Out Slave In
1 I/O Generic I/O
TIO3 Versatile Timer Channel 3
UART Channel 0 Ready-To-Send Output
Non-Maskable Interrupt Input
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
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1 I/O Generic I/O
1 I/O Generic I/O
1 I/O Generic I/O
1 I/O Generic I/O
1 I/O Generic I/O
1 I/O Generic I/O RFSYNC BT AC Correlation/TX Enable Output
1 I/O Generic I/O RFCE BT RF Chip Enable Output
1 I/O Generic I/O
1 I/O Generic I/O SCLK BT Serial I/F Shift Clock Output
MWCS
TIO4 Versatile Timer Channel 4
SCK AAI Clock
TIO5 Versatile Timer Channel 5
SFS AAI Frame Synchronization
TIO6 Versatile Timer Channel 6
STD AAI Transmit Data Output
TIO7 Versatile Timer Channel 7
SRD AAI Receive Data Input
TIO8 Versatile Timer Channel 8
BTSEQ1 Bluetooth Sequencer Status
SRCLK AAI Receive Clock
SPI Slave Select Input
CP3BT26
Name Pins I/O Primary Function
PG4
PG5
PG6
PG7
PH0
PH1
PH2
PH3
PH4
PH5
1 I/O Generic I/O SDAT BT Serial I/F Data
1 I/O Generic I/O SLE BT Serial I/F Load Enable Output
1 I/O Generic I/O
1 I/O Generic I/O
1 I/O Generic I/O
1 I/O Generic I/O
1 I/O Generic I/O
1 I/O Generic I/O
1 I/O Generic I/O
1 I/O Generic I/O
Alternate
Name
WUI10 Multi-Input Wake-Up Channel 10
BTSEQ2 Bluetooth Sequencer Status
TA Multi Function Timer Port A
BTSEQ3 Bluetooth Sequencer Status
RXD1 UART Channel 1 Receive Data Input
WUI11 Multi-Input Wake-Up Channel 11
TXD1 UART Channel 1 Transmit Data Output
WUI12 Multi-Input Wake-Up Channel 12
RXD2 UART Channel 2 Receive Data Input
WUI13 Multi-Input Wake-Up Channel 13
TXD2 UART Channel 2 Transmit Data Output
WUI14 Multi-Input Wake-Up Channel 14
RXD3 UART Channel 3 Receive Data Input
WUI15 Multi-Input Wake-Up Channel 15
TXD3 UART Channel 3 Transmit Data Output
WUI16 Multi-Input Wake-Up Channel 16
Alternate Function
PH6
PH7
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
1 I/O Generic I/O
CANRX CAN Receive Input
WUI17 Multi-Input Wake-Up Channel 17
1 I/O Generic I/O CANTX CAN Transmit Output
1 I/O Generic I/O WUI18 Multi-Input Wake-Up Channel 18
1 I/O Generic I/O WUI19 Multi-Input Wake-Up Channel 19
1 I/O Generic I/O WUI20 Multi-Input Wake-Up Channel 20
1 I/O Generic I/O WUI21 Multi-Input Wake-Up Channel 21
1 I/O Generic I/O WUI22 Multi-Input Wake-Up Channel 22
1 I/O Generic I/O WUI23 Multi-Input Wake-Up Channel 23
1 I/O Generic I/O WUI24 Multi-Input Wake-Up Channel 24
ASYNC Start convert signal to ADC
1 I/O Generic I/O
WUI9 Multi-Input Wake-Up Channel 9
11 www.national.com
Table 3 CP3BT26 LQFP-144 Signal Descriptions
Name Pins I/O Primary Function
CP3BT26
X1CKI 1
X1CKO 1
X2CKI 1
X2CKO 1
RESET 1
ENV0 1
ENV1 1
ENV2 1
TMS 1
TCK 1
TDI 1
TDO 1
Alternate
Name
Input 12 MHz Oscillator Input BBCLK BB reference clock for the RF Interface
Output 12 MHz Oscillator Output None None
Input 32 kHz Oscillator Input None None
Output 32 kHz Oscillator Output None None
Input Chip general reset None None
I/O
I/O
I/O
Input
Input
Input
Output JTAG Test Data Output None None
Special mode select input with
internal pull-up during reset
Special mode select input with
internal pull-up during reset
Special mode select input with
internal pull-up during reset
JTAG Test Mode Select
(with internal weak pull-up)
JTAG Test Clock Input
(with internal weak pull-up)
JTAG Test Data Input
(with internal weak pull-up)
PLLCLK PLL Clock Output
CPUCLK CPU Clock Output
SLOWCLK Slow Clock Output
None None
None None
None None
Alternate Function
RDY
VCC 6
GND 6
IOVCC 10
IOGND 11
AVC C 1
AGND
ADVCC 1
ADGND
RFDATA
SCL
SDA
D- 1
D+ 1
UVCC 1
UGND
Output NEXUS Ready Output None None
1
Input
Input Core Ground None None
Input 2.5
Input I/O Ground None None
Input PLL Analog Power Supply None None
1 Input PLL Analog Ground None None
Input ADC Analog Power Supply None None
1 Input ADC Analog Ground None None
1 I/O Bluetooth RX/TX Data Pin None None
1 I/O ACCESS.bus Clock None None
1 I/O ACCESS.bus Serial Data None None
I/O USB D- Upstream Port None None
I/O USB D+ Upstream Port None None
Input 3.3V USB Transceiver Supply None None
1 Input USB Transceiver Ground None None
2.5V Core Logic
Power Supply
None None
–3.3V I/O Power Supply None None
ADC0
ADC1
ADC2
www.national.com 12
1 I/O ADC Input Channel 0 TSX+ Touchscreen X+ contact
1 I/O ADC Input Channel 1 TSY+ Touchscreen Y+ contact
1 I/O ADC Input Channel 2 TSX- Touchscreen X- contact
CP3BT26
Name Pins I/O Primary Function
ADC3
ADC4
ADC5
ADC6
ADC7
VREFP
PB[7:0]
PC[7:0]
A[22:0]
SEL0
SEL1
SEL2
SELIO
WR0
WR1
1 I/O ADC Input Channel 3 TSY- Touchscreen Y- contact
1 I/O ADC Input Channel 4 MUXOUT0 Analog Multiplexer Output 0
1 I/O ADC Input Channel 5 MUXOUT1 Analog Multiplexer Output 1
1 Input ADC Input Channel 6 None None
1 Input ADC Input Channel 7 ADCIN ADC Input (in MUX mode)
1 Input ADC Positive Voltage Reference None None
8 I/O Generic I/O D[7:0] External Data Bus Bits 0 to 7
8 I/O Generic I/O D[8:15] External Data Bus Bits 8 to 15
23 Output External Address Bus Bits 0 to 22 None None
1 Output Chip Select for Zone 0 None None
1 Output Chip Select for Zone 1 None None
1 Output Chip Select for Zone 2 None None
1 Output Chip Select for I/O Zone None None
1 Output External Memory Write Low Byte None None
1 Output External Memory Write High Byte None None
Alternate
Name
Alternate Function
RD
PE0
PE1
PE2
PE3
PE4
PE5
PF0
PF1
PF2
PF3
1 Output External Memory Read None None
1 I/O Generic I/O RXD0 UART0 Receive Data Input
1 I/O Generic I/O TXD0 UART0 Transmit Data Output
1 I/O Generic I/O RTS UART0 Ready-To-Send Output
1 I/O Generic I/O CTS UART0 Clear-To-Send Input
1 I/O Generic I/O
1 I/O Generic I/O
1 I/O Generic I/O
1 I/O Generic I/O
1 I/O Generic I/O
1 I/O Generic I/O
CKX UART0 Clock Input
TB Multi Function Timer Port B
SRFS AAI Receive Frame Sync
NMI
MSK SPI Shift Clock
TIO1 Versatile Timer Channel 1
MDIDO SPI Master In Slave Out
TIO2 Versatile Timer Channel 2
MDODI SPI Master Out Slave In
TIO3 Versatile Timer Channel 3
MWCS
TIO4 Versatile Timer Channel 4
Non-Maskable Interrupt Input
SPI Slave Select Input
PF4
PF5
1 I/O Generic I/O
SCK AAI Clock
TIO5 Versatile Timer Channel 5
SFS AAI Frame Synchronization
1 I/O Generic I/O
TIO6 Versatile Timer Channel 6
13 www.national.com
Name Pins I/O Primary Function
Alternate
Name
Alternate Function
CP3BT26
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PH0
PH1
PH2
1 I/O Generic I/O
1 I/O Generic I/O
1 I/O Generic I/O RFSYNC BT AC Correlation/TX Enable Output
1 I/O Generic I/O RFCE BT RF Chip Enable Output
1 I/O Generic I/O
1 I/O Generic I/O SCLK BT Serial I/F Shift Clock Output
1 I/O Generic I/O SDAT BT Serial I/F Data
1 I/O Generic I/O SLE
1 I/O Generic I/O
1 I/O Generic I/O
1 I/O Generic I/O
1 I/O Generic I/O
1 I/O Generic I/O
STD AAI Transmit Data Output
TIO7 Versatile Timer Channel 7
SRD AAI Receive Data Input
TIO8 Versatile Timer Channel 8
BTSEQ1 Bluetooth Sequencer Status
SRCLK AAI Receive Clock
BT Serial I/F Load Enable Output
WUI10 Multi-Input Wake-Up Channel 10
BTSEQ2 Bluetooth Sequencer Status
TA Multi Function Timer Port A
BTSEQ3 Bluetooth Sequencer Status
RXD1 UART Channel 1 Receive Data Input
WUI11 Multi-Input Wake-Up Channel 11
TXD1 UART Channel 1 Transmit Data Output
WUI12 Multi-Input Wake-Up Channel 12
RXD2 UART Channel 2 Receive Data Input
WUI13 Multi-Input Wake-Up Channel 13
PH3
PH4
PH5
PH6
PH7
PJ0
PJ7
1 I/O Generic I/O
TXD2 UART Channel 2 Transmit Data Output
WUI14 Multi-Input Wake-Up Channel 14
RXD3 UART Channel 3 Receive Data Input
1 I/O Generic I/O
WUI15 Multi-Input Wake-Up Channel 15
TXD3 UART Channel 3 Transmit Data Output
1 I/O Generic I/O
WUI16 Multi-Input Wake-Up Channel 16
CANRX CAN Receive Input
1 I/O Generic I/O
WUI17 Multi-Input Wake-Up Channel 17
1 I/O Generic I/O CANTX CAN Transmit Output
1 I/O Generic I/O WUI18 Multi-Input Wake-Up Channel 18
ASYNC Start Convert Signal to ADC
1 I/O Generic I/O
WUI9 Multi-Input Wake-Up Channel 9
www.national.com 14
5.0 CPU Architecture
The CP3BT26 uses the CR16C third-generation 16-bit
CompactRISC processor core. The CPU implements a Reduced Instruction Set Computer (RISC) architecture that allows an effective execution rate of up to one instruction per
clock cycle. For a detailed description of the CPU16C architecture, see the CompactRISC CR16C Programmer’s Ref-
erence Manual which is available on the National
Semiconductor web site (http://www.nsc.com).
The CR16C CPU core includes these internal registers:
General-purpose registers (R0-R13, RA, and SP)
Dedicated address registers (PC, ISP, USP, and INT-
BASE)
Processor Status Register (PSR)
Configuration Register (CFG)
The R0-R11, PSR, and CFG registers are 16 bits wide. The
R12, R13, RA, SP, ISP and USP registers are 32 bits wide.
The PC register is 24 bits wide. Figure 2 shows the CPU
registers.
Dedicated Address Registers
31
ISPH
USPH
INTBASEH
15
23
PC
ISPL
USPL
INTBASEL
Processor Status Register
15
PSR
Configuration Register
15
CFG
0
0
0
31
Figure 2. CPU Registers
Some register bits are designated as “reserved.” Software
must write a zero to these bit locations when it writes to the
register. Read operations from reserved bit locations return
undefined values.
5.1 GENERAL-PURPOSE REGISTERS
The CompactRISC CPU features 16 general-purpose registers. These registers are used individually as 16-bit operands or as register pairs for operations on addresses
greater than 16 bits.
General-purpose registers are defined as R0 through
R13, RA, and SP.
Registers are grouped into pairs based on the setting of
the Short Register bit in the Configuration Register
(CFG.SR). When the CFG.SR bit is set, the grouping of
register pairs is upward-compatible with the architecture
of the earlier CR16A/B CPU cores: (R1,R0), (R2,R1) ...
(R11,R10), (R12_L, R11), (R13_L, R12_L), (R14_L,
R13_L) and SP. (R14_L, R13_L) is the same as
(RA,ERA).
General-Purpose Registers
15 0
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
RA
SP
DS004
CP3BT26
When the CFG.SR bit is clear, register pairs are grouped
in the manner used by native CR16C software: (R1,R0),
(R2,R1) ... (R11,R10), (R12_L, R11), R12, R13, RA, SP.
R12, R13, RA, and SP are 32-bit registers for holding addresses greater than 16 bits.
With the recommended calling convention for the architecture, some of these registers are assigned special hardware
and software functions. Registers R0 to R13 are for generalpurpose use, such as holding variables, addresses, or index
values. The SP register holds a pointer to the program runtime stack. The RA register holds a subroutine return address. The R12 and R13 registers are available to hold base
addresses used in the index addressing mode.
If a general-purpose register is specified by an operation
that is 8 bits long, only the lower byte of the register is used;
the upper part is not referenced or modified. Similarly, for
word operations on register pairs, only the lower word is
used. The upper word is not referenced or modified.
5.2 DEDICATED ADDRESS REGISTERS
The CR16C has four dedicated address registers to implement specific functions: the PC, ISP, USP, and INTBASE
registers.
5.2.1 Program Counter (PC) Register
The 24-bit value in the PC register points to the first byte of
the instruction currently being executed. CR16C instructions are aligned to even addresses, therefore the least significant bit of the PC is always 0. At reset, the PC is
initialized to 0 or an optional predetermined value. When a
warm reset occurs, value of the PC prior to reset is saved in
the (R1,R0) general-purpose register pair.
5.2.2 Interrupt Stack Pointer (ISP)
The 32-bit ISP register points to the top of the interrupt
stack. This stack is used by hardware to service exceptions
(interrupts and traps). The stack pointer may be accessed
as the ISP register for initialization. The interrupt stack can
be located anywhere in the CPU address space. The ISP
cannot be used for any purpose other than the interrupt
stack, which is used for automatic storage of the CPU registers when an exception occurs and restoration of these
registers when the exception handler returns. The interrupt
stack grows downward in memory. The least significant bit
and the 8 most significant bits of the ISP register are always
0.
5.2.3 User Stack Pointer (USP)
The USP register points to the top of the user-mode program stack. Separate stacks are available for user and supervisor modes, to support protection mechanisms for
multitasking software. The processor mode is controlled by
the U bit in the PSR register (which is called PSR.U in the
shorthand convention). Stack grow downward in memory. If
the USP register points to an illegal address (any address
greater than 0x00FF_FFFF) and the USP is used for stack
access, an IAD trap is taken.
15 www.national.com
5.2.4 Interrupt Base Register (INTBASE)
The INTBASE register holds the address of the dispatch table for exceptions. The dispatch table can be located anywhere in the CPU address space. When loading the
CP3BT26
INTBASE register, bits 31 to 24 and bit 0 must written with 0.
5.3 PROCESSOR STATUS REGISTER (PSR)
The PSR provides state information and controls operating
modes for the CPU. The format of the PSR is shown below.
15 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved I P E 0 N Z F 0 U L T C
C The Carry bit indicates whether a carry or bor-
row occurred after addition or subtraction.
0 – No carry or borrow occurred.
1 – Carry or borrow occurred.
T The Trace bit enables execution tracing, in
which a Trace trap (TRC) is taken after every
instruction. Tracing is automatically disabled
during the execution of an exception handler.
– Tracing disabled.
0
1 – Tracing enabled.
L The Low bit indicates the result of the last
comparison operation, with the operands interpreted as unsigned integers.
– Second operand greater than or equal to
0
first operand.
1 – Second operand less than first operand.
U The User Mode bit controls whether the CPU
is in user or supervisor mode. In supervisor
mode, the SP register is used for stack operations. In user mode, the USP register is used
instead. User mode is entered by executing
the Jump USR instruction. When an exception
is taken, the exception handler automatically
begins execution in supervisor mode. The
USP register is accessible using the Load
Processor Register (LPR/LPRD) instruction in
supervisor mode. In user mode, an attempt to
access the USP register generates a UND
trap.
– CPU is executing in supervisor mode.
0
– CPU is executing in user mode.
1
F The Flag bit is a general condition flag for sig-
nalling exception conditions or distinguishing
the results of an instruction, among other
thing uses. For example, integer arithmetic instructions use the F bit to indicate an overflow
condition after an addition or subtraction operation.
Z The Zero bit is used by comparison opera-
tions. In a comparison of integers, the Z bit is
set if the two operands are equal. If the operands are unequal, the Z bit is cleared.
– Source and destination operands un-
0
equal.
1 – Source and destination operands equal.
N The Negative bit indicates the result of the last
comparison operation, with the operands interpreted as signed integers.
– Second operand greater than or equal to
0
first operand.
1 – Second operand less than first operand.
E The Local Maskable Interrupt Enable bit en-
ables or disables maskable interrupts. If this
bit and the Global Maskable Interrupt Enable
(I) bit are both set, all interrupts are enabled.
If either of these bits is clear, only the nonmaskable interrupt is enabled. The E bit is set
by the Enable Interrupts (EI) instruction and
cleared by the Disable Interrupts (DI) instruction.
– Maskable interrupts disabled.
0
1 – Maskable interrupts enabled.
P The Trace Trap Pending bit is used together
with the Trace (T) bit to prevent a Trace (TRC)
trap from occurring more than once for one instruction. At the beginning of the execution of
an instruction, the state of the T bit is copied
into the P bit. If the P bit remains set at the end
of the instruction execution, the TRC trap is
taken.
– No trace trap pending.
0
– Trace trap pending.
1
I The Global Maskable Interrupt Enable bit is
used to enable or disable maskable interrupts.
If this bit and the Local Maskable Interrupt Enable (E) bit are both set, all maskable interrupts are taken. If either bit is clear, only the
non-maskable interrupt is taken. Unlike the E
bit, the I bit is automatically cleared when an
interrupt occurs and automatically set upon
completion of an interrupt handler.
– Maskable interrupts disabled.
0
1 – Maskable interrupts enabled.
Bits Z, C, L, N, and F of the PSR are referenced from assembly language by the condition code in conditional
branch instructions. A conditional branch instruction may
cause a branch in program execution, based on the value of
one or more of these PSR bits. For example, one of the
Bcond instructions, BEQ (Branch EQual), causes a branch
if the PSR.Z bit is set.
On reset, bits 0 through 11 of the PSR are cleared, except
for the PSR.E bit, which is set. On warm reset, the values of
each bit before reset are copied into the R2 general-purpose register. Bits 4 and 8 of the PSR have a constant value
of 0. Bits 12 through 15 are reserved. In general, status bits
are modified only by specific instructions. Otherwise, status
bits maintain their values throughout instructions which do
not implicitly affect them.
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5.4 CONFIGURATION REGISTER (CFG)
The CFG register is used to enable or disable various operating modes and to control optional on-chip caches. Because the CP3BT26 does not have cache memory, the
cache control bits in the CFG register are reserved. All CFG
bits are cleared on reset.
15 10 9 8 7 6 5 2 1 0
Reserved SR ED 0 0 Reserved 0 0
ED The Extended Dispatch bit selects whether
the size of an entry in the interrupt dispatch table (IDT) is 16 or 32 bits. Each entry holds the
address of the appropriate exception handler.
When the IDT has 16-bit entries, and all exception handlers must reside in the first 128K
of the address space. The location of the IDT
is held in the INTBASE register, which is not
affected by the state of the ED bit.
– Interrupt dispatch table has 16-bit entries.
0
1 – Interrupt dispatch table has 32-bit entries.
SR The Short Register bit enables a compatibility
mode for the CR16B large model. In the
CR16C core, registers R12, R13, and RA are
extended to 32 bits. In the CR16B large model, only the lower 16 bits of these registers are
used, and these “short registers” are paired
together for 32-bit operations. In this mode,
the (RA, R13) register pair is used as the extended RA register, and address displacements relative to a single register are
supported with offsets of 0 and 14 bits in place
of the index addressing with these displacements.
– 32-bit registers are used.
0
1 – 16-bit registers are used (CR16B mode).
CP3BT26
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5.5 ADDRESSING MODES
The CR16C CPU core implements a load/store architecture, in which arithmetic and logical instructions operate on
register operands. Memory operands are made accessible
CP3BT26
in registers using load and store instructions. For efficient
implementation of I/O-intensive embedded applications, the
architecture also provides a set of bit operations that operate on memory operands.
The load and store instructions support these addressing
modes: register/pair, immediate, relative, absolute, and index addressing. When register pairs are used, the lower bits
are in the lower index register and the upper bits are in the
higher index register. When the CFG.SR bit is clear, the 32bit registers R12, R13, RA, and SP are also treated as register pairs.
References to register pairs in assembly language use parentheses. With a register pair, the lower numbered register
pair must be on the right. For example,
jump (r5, r4)
load $4(r4,r3), (r6,r5)
load $5(r12), (r13)
The instruction set supports the following addressing
modes:
Register/Pair
Mode
Immediate
Mode
Relative Mode In relative mode, the operand is ad-
In register/pair mode, the operand is held
in a general-purpose register, or in a general-purpose register pair. For example,
the following instruction adds the contents of the low byte of register r1 to the
contents of the low byte of r2, and places
the result in the low byte register r2. The
high byte of register r2 is not modified.
ADDB R1, R2
In immediate mode, the operand is a con-
stant value which is encoded in the instruction. For example, the following
instruction multiplies the value of r4 by 4
and places the result in r4.
MULW $4, R4
dressed using a relative value (displacement) encoded in the instruction. This
displacement is relative to the current
Program Counter (PC), a general-purpose register, or a register pair.
In branch instructions, the displacement
is always relative to the current value of
the PC Register. For example, the following instruction causes an unconditional
branch to an address 10 ahead of the
current PC.
BR *+10
In another example, the operand resides
in memory. Its address is obtained by
adding a displacement encoded in the instruction to the contents of register r5.
The address calculation does not modify
the contents of register r5.
LOADW 12(R5), R6
The following example calculates the ad-
dress of a source operand by adding a
displacement of 4 to the contents of a
register pair (r5, r4) and loads this operand into the register pair (r7, r6). r7 receives the high word of the operand, and
r6 receives the low word.
LOADD 4(r5, r4), (r7, r6)
Index Mode In index mode, the operand address is
calculated with a base address held in either R12 or R13. The CFG.SR bit must
be clear to use this mode.
For relative mode operands, the mem-
ory address is calculated by adding
the value of a register pair and a displacement to the base address. The
displacement can be a 14 or 20-bit unsigned value, which is encoded in the
instruction.
For absolute mode operands, the
memory address is calculated by adding a 20-bit absolute address encoded
in the instruction to the base address.
In the following example, the operand address is the sum of the displacement 4,
the contents of the register pair (r5,r4),
and the base address held in register r12.
The word at this address is loaded into
register r6.
LOADW [r12]4(r5, r4), r6
Absolute Mode In absolute mode, the operand is located
in memory, and its address is encoded in
the instruction (normally 20 or 24 bits).
For example, the following instruction
loads the byte at address 4000 into the
lower 8 bits of register r6.
LOADB 4000, r6
For additional information on the addressing modes, see the
CompactRISC CR16C Programmer's Reference Manual.
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5.6 STACKS
A stack is a last-in, first-out data structure for dynamic storage of data and addresses. A stack consists of a block of
memory used to hold the data and a pointer to the top of the
stack. As more data is pushed onto a stack, the stack grows
downward in memory. The CR16C supports two types of
stacks: the interrupt stack and program stacks.
5.6.1 Interrupt Stack
The processor uses the interrupt stack to save and restore
the program state during the exception handling. Hardware
automatically pushes this data onto the interrupt stack before entering an exception handler. When the exception
handler returns, hardware restores the processor state with
data popped from the interrupt stack. The interrupt stack
pointer is held in the ISP register.
5.6.2 Program Stack
The program stack is normally used by software to save and
restore register values on subroutine entry and exit, hold local and temporary variables, and hold parameters passed
between the calling routine and the subroutine. The only
hardware mechanisms which operate on the program stack
are the PUSH, POP, and POPRET instructions.
5.6.3 User and Supervisor Stack Pointers
To support multitasking operating systems, support is provided for two program stack pointers: a user stack pointer
and a supervisor stack pointer. When the PSR.U bit is clear,
the SP register is used for all program stack operations. This
is the default mode when the user/supervisor protection
mechanism is not used, and it is the supervisor mode when
protection is used.
When the PSR.U bit is set, the processor is in user mode,
and the USP register is used as the program stack pointer.
User mode can only be entered using the JUSR instruction,
which performs a jump and sets the PSR.U bit. User mode
is exited when an exception is taken and re-entered when
the exception handler returns. In user mode, the LPRD instruction cannot be used to change the state of processor
registers (such as the PSR).
5.7 INSTRUCTION SET
Table 4 lists the operand specifiers for the instruction set,
and Table 5 is a summary of all instructions. For each instruction, the table shows the mnemonic and a brief description of the operation performed.
In the mnemonic column, the lower-case letter “i” is used to
indicate the type of integer that the instruction operates on,
either “B” for byte or “W” for word. For example, the notation
ADDi for the “add” instruction means that there are two
forms of this instruction, ADDB and ADDW, which operate
on bytes and words, respectively.
Similarly, the lower-case string “cond” is used to indicate the
type of condition tested by the instruction. For example, the
notation Jcond represents a class of conditional jump instructions: JEQ for Jump on Equal, JNE for Jump on Not
Equal, etc. For detailed information on all instructions, see
the CompactRISC CR16C Programmer's Reference Manu-
al.
Table 4 Key to Operand Specifiers
Operand Specifier Description
abs Absolute address
disp
imm
Iposition Bit position in memory
Rbase Base register (relative mode)
Rdest Destination register
Rindex Index register
RPbase, RPbasex Base register pair (relative mode)
RPdest Destination register pair
RPlink Link register pair
Rposition Bit position in register
Displacement (numeric suffix
indicates number of bits)
Immediate operand (numeric suf-
fix indicates number of bits)
CP3BT26
Rproc 16-bit processor register
Rprocd 32-bit processor register
RPsrc Source register pair
RPtarget Target register pair
Rsrc, Rsrc1, Rsrc2 Source register
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Table 5 Instruction Set Summary
CP3BT26
Mnemonic Operands Description
MOVi Rsrc/imm, Rdest Move
MOVXB Rsrc, Rdest Move with sign extension
MOVZB Rsrc, Rdest Move with zero extension
MOVXW Rsrc, RPdest Move with sign extension
MOVZW Rsrc, RPdest Move with zero extension
MOVD imm, RPdest Move immediate to register-pair
RPsrc, RPdest Move between register-pairs
ADD[U]i Rsrc/imm, Rdest Add
ADDCi Rsrc/imm, Rdest Add with carry
ADDD RPsrc/imm, RPdest Add with RP or immediate.
MACQWa Rsrc1, Rsrc2, RPdest Multiply signed Q15:
RPdest := RPdest + (Rsrc1 × Rsrc2)
MACSWa Rsrc1, Rsrc2, RPdest Multiply signed and add result:
RPdest := RPdest + (Rsrc1 × Rsrc2)
MACUWa Rsrc1, Rsrc2, RPdest Multiply unsigned and add result:
RPdest := RPdest + (Rsrc1 × Rsrc2)
MULi Rsrc/imm, Rdest Multiply: Rdest(8) := Rdest(8) × Rsrc(8)/imm
Rdest(16) := Rdest(16) × Rsrc(16)/imm
MULSB Rsrc, Rdest Multiply: Rdest(16) := Rdest(8) × Rsrc(8)
MULSW Rsrc, RPdest Multiply: RPdest := RPdest(16) × Rsrc(16)
MULUW Rsrc, RPdest Multiply: RPdest := RPdest(16) × Rsrc(16);
SUBi Rsrc/imm, Rdest Subtract: (Rdest := Rdest - Rsrc/imm)
SUBD RPsrc/imm, RPdest Subtract: (RPdest := RPdest - RPsrc/imm)
SUBCi Rsrc/imm, Rdest Subtract with carry: (Rdest := Rdest - Rsrc/imm)
CMPi Rsrc/imm, Rdest Compare Rdest - Rsrc/imm
CMPD RPsrc/imm, RPdest Compare RPdest - RPsrc/imm
BEQ0i Rsrc, disp Compare Rsrc to 0 and branch if EQUAL
BNE0i Rsrc, disp Compare Rsrc to 0 and branch if NOT EQUAL
ANDi Rsrc/imm, Rdest Logical AND: Rdest := Rdest & Rsrc/imm
ANDD RPsrc/imm, RPdest Logical AND: RPdest := RPsrc & RPsrc/imm
ORi Rsrc/imm, Rdest Logical OR: Rdest := Rdest | Rsrc/imm
ORD RPsrc/imm, RPdest Logical OR: Rdest := RPdest | RPsrc/imm
Scond Rdest Save condition code as boolean
XORi Rsrc/imm, Rdest Logical exclusive OR: Rdest := Rdest ^ Rsrc/imm
XORD RPsrc/imm, RPdest Logical exclusive OR: Rdest := RPdest ^ RPsrc/imm
ASHUi Rsrc/imm, Rdest Arithmetic left/right shift
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Table 5 Instruction Set Summary
Mnemonic Operands Description
ASHUD Rsrc/imm, RPdest Arithmetic left/right shift
LSHi Rsrc/imm, Rdest Logical left/right shift
LSHD Rsrc/imm, RPdest Logical left/right shift
SBITi Iposition, disp(Rbase) Set a bit in memory
Iposition, disp(RPbase)
Iposition, (Rindex)disp(RPbasex)
Iposition, abs
Iposition, (Rindex)abs
CBITi Iposition, disp(Rbase) Clear a bit in memory
Iposition, disp(RPbase)
Iposition, (Rindex)disp(RPbasex)
Iposition, abs
Iposition, (Rindex)abs
(Because this instruction treats the destination as a readmodify-write operand, it not be used to set bits in writeonly registers.)
CP3BT26
TBIT
TBITi
LPR Rsrc, Rproc Load processor register
LPRD RPsrc, Rprocd Load double processor register
SPR Rproc, Rdest Store processor register
SPRD Rprocd, RPdest Store 32-bit processor register
Bcond disp9 Conditional branch
BAL RPlink, disp24 Branch and link
BR disp9 Branch
Rposition/imm, Rsrc Test a bit in a register
Iposition, disp(Rbase)
Iposition, disp(RPbase)
Iposition, (Rindex)disp(RPbasex)
Iposition, abs
Iposition, (Rindex)abs
disp17
disp24
disp17
disp24
Test a bit in memory
EXCP vector Trap (vector)
Jcond RPtarget Conditional Jump to a large address
JAL RA, RPtarget, Jump and link to a large address
RPlink, RPtarget
JUMP RPtarget Jump
JUSR RPtarget Jump and set PSR.U
21 www.national.com
Table 5 Instruction Set Summary
Mnemonic Operands Description
CP3BT26
RETX Return from exception
PUSH imm, Rsrc, RA Push “imm” number of registers on user stack, starting
with Rsrc and possibly including RA
POP imm, Rdest, RA Restore “imm” number of registers from user stack,
starting with Rdest and possibly including RA
POPRET imm, Rdest, RA Restore registers (similar to POP) and JUMP RA
LOADi disp(Rbase), Rdest Load (register relative)
abs, Rdest Load (absolute)
(Rindex)abs, Rdest Load (absolute index relative)
(Rindex)disp(RPbasex), Rdest Load (register relative index)
disp(RPbase), Rdest Load (register pair relative)
LOADD disp(Rbase), Rdest Load (register relative)
abs, Rdest Load (absolute)
(Rindex)abs, Rdest Load (absolute index relative)
(Rindex)disp(RPbasex), Rdest Load (register pair relative index)
disp(RPbase), Rdest Load (register pair relative)
STORi Rsrc, disp(Rbase) Store (register relative)
Rsrc, disp(RPbase) Store (register pair relative)
Rsrc, abs Store (absolute)
Rsrc, (Rindex)disp(RPbasex) Store (register pair relative index)
Rsrc, (Rindex)abs Store (absolute index)
STORD RPsrc, disp(Rbase) Store (register relative)
RPsrc, disp(RPbase) Store (register pair relative)
RPsrc, abs Store (absolute)
RPsrc, (Rindex)disp(RPbasex) Store (register pair index relative)
RPsrc, (Rindex)abs Store (absolute index relative)
STOR IMM imm4, disp(Rbase) Store unsigned 4-bit immediate value extended to operand
imm4, disp(RPbase)
imm4, (Rindex)disp(RPbasex)
imm4, abs
imm4, (Rindex)abs
LOADM imm3 Load 1 to 8 registers (R2-R5, R8-R11) from memory
length in memory
starting at (R0)
LOADMP imm3 Load 1 to 8 registers (R2-R5, R8-R11) from memory
starting at (R1, R0)
STORM STORM imm3 Store 1 to 8 registers (R2-R5, R8-R11) to memory starting
at (R2)
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Table 5 Instruction Set Summary
Mnemonic Operands Description
STORMP imm3 Store 1 to 8 registers (R2-R5, R8-R11) to memory starting
at (R7,R6)
DI Disable maskable interrupts
EI Enable maskable interrupts
EIWAIT Enable maskable interrupts and wait for interrupt
NOP No operation
WAIT Wait for interrupt
CP3BT26
23 www.national.com
6.0 Memory
The CP3BT26 supports a uniform 16M-byte linear address
space. Table 6 lists the types of memory and peripherals
CP3BT26
that occupy this memory space. Unlisted address ranges
Table 6 CP3BT26 Memory Map
are reserved and must not be read or written. The BIU
zones are regions of the address space that share the same
control bits in the Bus Interface Unit (BIU).
Start
Address
00 0000h 03 FFFFh 256K
04 0000h 0C FFFFh 576K Reserved
0D 0000h 0D 1FFFh 8K On-chip Flash Data Memory
0D 2000h 0D FFFFh 56K Reserved
0E 0000h 0E 7FFFh 32K System RAM N/A
0E 8000h 0E 91FFh 4.5K Bluetooth Data RAM
0E 9200h 0E E7FFh 21.5K Reserved
0E E800h 0E EBFFh 1K Bluetooth Lower Link Controller Sequencer RAM
0E EC00h 0E EFFFh 1K Reserved
0E F000h 0E F13Fh 320 CAN Buffers and Registers
0E F140h 0E F17Fh 64 Reserved
0E F180h 0E F1FFh 128 Bluetooth Lower Link Controller Registers
0E F200h 0F FFFFh 67K Reserved
10 0000h 3F FFFFh 3072K Reserved
End
Address
Size in
Bytes
Description BIU Zone
On-chip Flash Program Memory, including Boot
Memory
Static Zone 0
(mapped internally
in IRE and ERE
mode; mapped to
the external bus in
DEV mode)
40 0000h 7F FFFFh 4096K External Memory Zone 1 Static Zone 1
80 0000h FE FFFFh 8128K External Memory Zone 2 Static Zone 2
FF 0000h FF F1FFh 61952 Reserved
FF F200h FF F5FFh 1K Peripherals and Other I/O Ports N/A
FF F600h FF FAFFh 1280 BIU, DMA, Flash interfaces IN/A
FF FB00h FF FBFFh 256 I/O Expansion I/O Zone
FF FC00h FF FFFFh 1K Peripherals and Other I/O Ports N/A
6.1 OPERATING ENVIRONMENT
The operating environment controls whether external memory is supported and whether the reset vector jumps to a
code space intended to support In-System Programming
(ISP). Up to 12M of external memory space is available.
The operating mode of the device is controlled by the states
on the ENV[2:0] pins at reset and the states of the EMPTY
bits in the Protection Word, as shown in Table 7. Internal
pullups on the ENV[2:0] pins select IRE mode or ISP mode
if these pins are allowed to float.
When ENV[2:0] = 111b, IRE mode is selected unless the
EMPTY bits in the Protection word indicate that the program
flash memory is empty (unprogrammed), in which case ISP
mode is selected. When ENV[2:0] = 011b, ERE mode is selected unless the EMPTY bits indicate that the program
flash memory is empty, in which case ISP mode is selected.
When ENV[2:0] = 110b, ISP mode is selected without regard to the states of the EMPTY bits. See Section 8.4.2 for
more details.
In the DEV environment, the on-chip flash memory is disabled, and the corresponding region of the address space
is mapped to external memory. DEVINT mode is equivalent
to DEV mode but maps static memory zone 0 to the on-chip
memory.
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Table 7 Operating Environment Selection
ENV[2:0] EMPTY Operating Environment
111 No Internal ROM enabled (IRE) mode
011 No External ROM enabled (ERE) mode
000 N/A Development (DEV) mode
001 N/A
110 N/A In-System-Programming (ISP) mode
111 Yes In-System-Programming (ISP) mode
011 Yes In-System-Programming (ISP) mode
Development (DEVINT) mode with
internal memory
6.2 BUS INTERFACE UNIT (BIU)
The BIU controls the interface between the CPU core bus
and those on-chip modules which are mapped into BIU
zones. These on-chip modules are the flash program memory and the I/O zone. The BIU controls the configured parameters for bus access (such as the number of wait states
for memory access) and issues the appropriate bus signals
for the requested access.
6.3 BUS CYCLES
There are four types of data transfer bus cycles:
Normal read
Fast read
Early write
Late write
The type of data cycle used in a particular transaction depends on the type of CPU operation (a write or a read), the
type of memory or I/O being accessed, and the access type
programmed into the BIU control registers (early/late write
or normal/fast read).
For read operations, a basic normal read takes two clock cycles, and a fast-read bus cycle takes one clock cycle. Normal read bus cycles are enabled by default after reset.
For write operations, a basic late-write bus cycle takes two
clock cycles, and a basic early-write bus cycle takes three
clock cycles. Early-write bus cycles are enabled by default
after reset. However, late-write bus cycles are needed for
ordinary write operations, so this configuration must be
changed by software (see Section 6.4.1).
In certain cases, one or more additional clock cycles are
added to a bus access cycle. There are two types of additional clock cycles for ordinary memory accesses, called internal wait cycles (TIW) and hold (T
A wait cycle is inserted in a bus cycle just after the memory
address has been placed on the address bus. This gives the
accessed memory more time to respond to the transaction
request.
A hold cycle is inserted at the end of a bus cycle. This holds
the data on the data bus for an extended number of clock cycles.
hold
) cycles.
6.4 BIU CONTROL REGISTERS
The BIU has a set of control registers that determine how
many wait cycles and hold cycles are to be used for accessing memory. During initialization of the system, these registers should be programmed with appropriate values so that
the minimum allowable number of cycles is used. This number varies with the clock frequency.
There are five BIU control registers, as listed in Table 8.
These registers control the bus cycle configuration used for
accessing the various on-chip memory types.
Table 8 Bus Control Registers
Name Address Description
BCFG FF F900h BIU Configuration Register
IOCFG FF F902h
SZCFG0 FF F904h
SZCFG1 FF F906h
SZCFG2 FF F908h
6.4.1 BIU Configuration Register (BCFG)
The BCFG register is a byte-wide, read/write register that
selects early-write or late-write bus cycles. At reset, the register is initialized to 07h. The register format is shown below.
7 3 2 1 0
Reserved 1 1 EWR
EWR The Early Write bit controls write cycle timing.
– Late-write operation (2 clock cycles to
0
write).
– Early-write operation.
1
At reset, the BCFG register is initialized to 07h, which selects early-write operation. However, late-write operation is
required for normal device operation, so software must
change the register value to 06h. Bits 1 and 2 of this register
must always be set when writing to this register.
I/O Zone Configuration
Register
Static Zone 0
Configuration Register
Static Zone 1
Configuration Register
Static Zone 2
Configuration Register
CP3BT26
25 www.national.com
6.4.2 I/O Zone Configuration Register (IOCFG)
The IOCFG register is a word-wide, read/write register that
controls the timing and bus characteristics of accesses to
the 256-byte I/O Zone memory space (FF FB00h to FF
CP3BT26
FBFFh). The registers associated with Port B and Port C reside in the I/O memory array. At reset, the register is initialized to 069Fh. The register format is shown below.
7 6 5 4 3 2 0
BW Reserved HOLD WAIT
15 10 9 8
Reserved IPST Res.
WAIT The Memory Wait Cycles field specifies the
number of TIW (internal wait state) clock cycles added for each memory access, ranging
from 000 binary for no additional TIW wait cycles to 111 binary for seven additional TIW
wait cycles.
HOLD The Memory Hold Cycles field specifies the
number of T
memory access, ranging from 00b for no
T
cycles to 11b for three T
hold
cles.
BW The Bus Width bit defines the bus width of the
IO Zone.
– 8-bit bus width.
0
1 – 16-bit bus width (default)
IPST The Post Idle bit controls whether an idle cycle
follows the current bus cycle, when the next
bus cycle accesses a different zone. No idle
cycles are required for on-chip accesses.
– No idle cycle (recommended).
0
1 – Idle cycle.
clock cycles used for each
hold
hold
clock cy-
6.4.3 Static Zone 0 Configuration Register (SZCFG0)
The SZCFG0 register is a word-wide, read/write register
that controls the timing and bus characteristics of Zone 0
memory accesses. Zone 0 is used for the on-chip flash
memory (including the boot area, program memory, and
data memory).
At reset, the register is initialized to 069Fh. The register format is shown below.
7 6 5 4 3 2 0
BW WBR RBE HOLD WAIT
15 12 11 10 9 8
Reserved FRE IPRE IPST Res.
WAIT The Memory Wait field specifies the number
of TIW (internal wait state) clock cycles added
for each memory access, ranging from 000b
for no additional TIW wait cycles to 111b for
seven additional TIW wait cycles. These bits
are ignored if the SZCFG0.FRE bit is set.
HOLD The Memory Hold field specifies the number
of T
access, ranging from 00b for no T
to 11b for three T
are ignored if the SZCFG0.FRE bit is set.
RBE The Read Burst Enable enables burst cycles
on 16-bit reads from 8-bit bus width regions of
the address space. Because the flash program memory is required to be 16-bit bus
width, the RBE bit is a don’t care bit. This bit
is ignored when the SZCFG0.FRE bit is set.
0
1 – Burst read enabled.
WBR The Wait on Burst Read bit controls if a wait
state is added on burst read transaction. This
bit is ignored, when SZCFG0.FRE bit is set or
when SZCFG0.RBE is clear.
0
1 – One TBW on burst read cycles.
BW The Bus Width bit controls the bus width of the
zone. The flash program memory must be
configured for 16-bit bus width.
0
1
FRE The Fast Read Enable bit controls whether
fast read bus cycles are used. A fast read operation takes one clock cycle. A normal read
operation takes at least two clock cycles.
0
1
IPST The Post Idle bit controls whether an idle cycle
follows the current bus cycle, when the next
bus cycle accesses a different zone. No idle
cycles are required for on-chip accesses.
0
1
clock cycles used for each memory
hold
clock cycles. These bits
hold
– Burst read disabled.
– No TBW on burst read cycles.
– 8-bit bus width.
– 16-bit bus width (required).
– Normal read cycles.
– Fast read cycles.
– No idle cycle (recommended).
– Idle cycle inserted.
hold
cycles
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IPRE The Preliminary Idle bit controls whether an
idle cycle is inserted prior to the current bus
cycle, when the new bus cycle accesses a different zone. No idle cycles are required for onchip accesses.
– No idle cycle (recommended).
0
– Idle cycle inserted.
1
6.4.4 Static Zone 1 Configuration Register (SZCFG1)
The SZCFG1 register is a word-wide, read/write register
that controls the timing and bus characteristics for off-chip
accesses selected with the SEL1
At reset, the register is initialized to 069Fh. The register format is shown below.
7 6 5 4 3 2 0
BW WBR RBE HOLD WAIT
output signal.
IPST The Post Idle bit controls whether an idle cycle
follows the current bus cycle, when the next
bus cycle accesses a different zone.
– No idle cycle.
0
1 – Idle cycle inserted.
IPRE The Preliminary Idle bit controls whether an
idle cycle is inserted prior to the current bus
cycle, when the new bus cycle accesses a different zone.
– No idle cycle.
0
1
– Idle cycle inserted.
6.4.5 Static Zone 2 Configuration Register (SZCFG2)
The SZCFG2 register is a word-wide, read/write register
that controls the timing and bus characteristics for off-chip
accesses selected with the SEL2 output signal.
At reset, the register is initialized to 069Fh. The register format is shown below.
CP3BT26
15 12 11 10 9 8
Reserved FRE IPRE IPST Res.
WAIT The Memory Wait field specifies the number
of TIW (internal wait state) clock cycles added
for each memory access, ranging from 000b
for no additional TIW wait cycles to 111b for
seven additional TIW wait cycles. These bits
are ignored if the SZCFG1.FRE bit is set.
HOLD The Memory Hold field specifies the number
of T
access, ranging from 00b for no T
to 11b for three T
are ignored if the SZCFG1.FRE bit is set.
RBE The Read Burst Enable enables burst cycles
on 16-bit reads from 8-bit bus width regions of
the address space. This bit is ignored when
the SZCFG1.FRE bit is set or the
SZCFG1.BW is clear.
0
1
WBR The Wait on Burst Read bit controls if a wait
state is added on burst read transaction. This
bit is ignored, when SZCFG1.FRE bit is set or
when SZCFG1.RBE is clear.
0
1
BW The Bus Width bit controls the bus width of the
zone.
0
1
FRE The Fast Read Enable bit controls whether
fast read bus cycles are used. A fast read operation takes one clock cycle. A normal read
operation takes at least two clock cycles.
0
1
clock cycles used for each memory
hold
clock cycles. These bits
hold
– Burst read disabled.
– Burst read enabled.
– No TBW on burst read cycles.
– One TBW on burst read cycles.
– 8-bit bus width.
– 16-bit bus width.
– Normal read cycles.
– Fast read cycles.
hold
cycles
7 6 5 4 3 2 0
BW WBR RBE HOLD WAIT
15 12 11 10 9 8
Reserved FRE IPRE IPST Res.
WAIT The Memory Wait field specifies the number
of TIW (internal wait state) clock cycles added
for each memory access, ranging from 000b
for no additional TIW wait cycles to 111b for
seven additional TIW wait cycles. These bits
are ignored if the SZCFG2.FRE bit is set.
HOLD The Memory Hold field specifies the number
of T
access, ranging from 00b for no T
to 11b for three T
are ignored if the SZCFG2.FRE bit is set.
RBE The Read Burst Enable enables burst cycles
on 16-bit reads from 8-bit bus width regions of
the address space. This bit is ignored when
the SZCFG2.FRE bit is set or the
SZCFG2.BW is clear.
0
1
WBR The Wait on Burst Read bit controls if a wait
state is added on burst read transaction. This
bit is ignored, when SZCFG2.FRE bit is set or
when SZCFG2.RBE is clear.
0
1
BW The Bus Width bit controls the bus width of the
zone.
0
1
clock cycles used for each memory
hold
clock cycles. These bits
hold
– Burst read disabled.
– Burst read enabled.
– No TBW on burst read cycles.
– One TBW on burst read cycles.
– 8-bit bus width.
– 16-bit bus width.
hold
cycles
27 www.national.com
FRE The Fast Read Enable bit controls whether
fast read bus cycles are used. A fast read operation takes one clock cycle. A normal read
CP3BT26
IPST The Post Idle bit controls whether an idle cycle
IPRE The Preliminary Idle bit controls whether an
operation takes at least two clock cycles.
– Normal read cycles.
0
1 – Fast read cycles.
follows the current bus cycle, when the next
bus cycle accesses a different zone.
– No idle cycle.
0
1
– Idle cycle inserted.
idle cycle is inserted prior to the current bus
cycle, when the new bus cycle accesses a different zone.
– No idle cycle.
0
1 – Idle cycle inserted.
6.5 WAIT AND HOLD STATES
The number of wait cycles and hold cycles inserted into a
bus cycle depends on whether it is a read or write operation,
the type of memory or I/O being accessed, and the control
register settings.
6.5.1 Flash Program/Data Memory
When the CPU accesses the Flash program and data memory (address ranges 000000h
0E1FFFh), the number of added wait and hold cycles depends on the type of access and the BIU register settings.
In fast-read mode (SZCFG0.FRE=1), a read operation is a
single cycle access. This limits the maximum CPU operating frequency to 24 MHz.
For a read operation in normal-read mode
(SZCFG0.FRE=0), the number of inserted wait cycles is
specified in the SZCFG0.WAIT field. The total number of
wait cycles is the value in the WAIT field plus 1, so it can
range from 1 to 8. The number of inserted hold cycles is
specified in the SCCFG0.HOLD field, which can range from
0 to 3.
For a write operation in fast read mode (SZCFG0.FRE=1),
the number of inserted wait cycles is 1. No hold cycles are
used.
For a write operation normal read mode (SZCFG0.FRE=0),
the number of wait cycles is equal to the value written to the
SZCFG0.WAIT field plus 1 (in the late write mode) or 2 (in
the early write mode). The number of inserted hold cycles is
equal to the value written to the SCCFG0.HOLD field, which
can range from 0 to 3.
6.5.2 RAM Memory
Read and write accesses to on-chip RAM is performed within a single cycle, without regard to the BIU settings. The
RAM address is in the range of 0E 0000h
8000h–0E 91FFh.
–03FFFFh and 0E0000h–
–0E 7FFFh and 0E
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6.5.3 Access to Peripherals
When the CPU accesses on-chip peripherals in the range of
0E F000h
cycle and one preliminary idle cycle is used. No hold cycles
are used. The IOCFG register determines the access timing
for the address range FF FB00h
–0E F1FFh and FF 0000h–FF FBFFh, one wait
–FF FBFFh.
7.0 System Configuration Registers
The system configuration registers control and provide status for certain aspects of device setup and operation, such
as indicating the states sampled from the ENV[2:0] inputs.
The system configuration registers are listed in Table 9.
Table 9 System Configuration Registers
Name Address Description
MCFG FF F910h
MSTAT FF F914h
7.1 MODULE CONFIGURATION REGISTER (MCFG)
The MCFG register is a byte-wide, read/write register that
selects the clock output features of the device.
At reset, the register bits are cleared except for the
USB_ENABLE bit, which is set. Initialization software must
write a specific value to this register to enable the SCLK,
MCLK, output pin function.
The register must be written in active mode only, not in power save, HALT, or IDLE mode. However, the register contents are preserved during all power modes.
The MCFG register format is shown below.
Module Configuration
Register
Module Status
Register
USB_ENABLE
MISC_IO_SPEED
MEM_IO_SPEED
The USB_ENABLE bit can be used to force
an external USB transceiver into its low-power
mode. The power mode is dependent on the
USB controller status, the USB_ENABLE bit
in the Function Word (see Section 8.4.1), and
the USB_ENABLE bit in the MCFG register.
0
1 – Transceiver power mode dependent on
The MISC_IO_SPEED bit controls the slew
rate of the output drivers for the ENV[2:0],
RDY
noise, the slow slew rate is recommended.
0 – Fast slew rate.
1
The MEM_IO_SPEED bit controls the slew
rate of the output drivers for the A[22:0], RD,
SEL[2:0]
PC[7:0] pins. Memory speeds for the
CP3BT26 are characterized with fast slew
rate. Slow slew rate reduces the available
memory access time by 5 ns.
0
1
CP3BT26
– External USB transceiver forced into low-
power mode.
USB controller status and programming
of the Function Word. (This is the state of
the USB_ENABLE bit after reset.)
, RFDATA, and TDO pins. To minimize
– Slow slew rate.
, SELIO, WR[1:0], PB[7:0], and
– Fast slew rate.
– Slow slew rate.
7 6 5 4 3 2 1 0
MEM_IO
Res.
_SPEED
EXIOE The EXIOE bit controls whether the external
PLLCLKOE
MCLKOE The MCLKOE bit controls whether the Main
SCLKOE The SCLKOE bit controls whether the Slow
MISC_IO
_SPEED
bus is enabled in the IRE environment for implementing the I/O Zone (FF FB00h
FBFFh).
– External bus disabled.
0
1 – External bus enabled.
The PLLCLKOE bit controls whether the PLL
clock is driven on the ENV0/PLLCLK pin.
– ENV0/PLLCLK pin is high impedance.
0
– PLL clock driven on the ENV0/PLLCLK
1
pin.
Clock is driven on the ENV1/CPUCLK pin.
– ENV1/CPUCLK pin is high impedance.
0
– Main Clock is driven on the ENV1/CPU-
1
CLK pin.
Clock is driven on the ENV2/SLOWCLK pin.
– ENV2/SLOWCLK pin is high impedance.
0
– Slow Clock is driven on the ENV2/SLOW-
1
CLK pin.
USB
_ENABLE
SCLKOEMCLKOEPLLCLKOEEXI
OE
–FF
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7.2 MODULE STATUS REGISTER (MSTAT)
The MSTAT register is a byte-wide, read-only register that
indicates the general status of the device. The MCFG register format is shown below.
CP3BT26
7 6 5 4 3 2 0
ISPRST WDRST Res.
OENV2:0 The Operating Environment bits hold the
states sampled from the ENV[2:0] input pins
at reset. These states are controlled by external hardware at reset and are held constant in
the register until the next reset.
PGMBUSY The Flash Programming Busy bit is automati-
cally set when either the program memory or
the data memory is being programmed or
erased. It is clear when neither of the memories is busy. When this bit is set, software must
not attempt to program or erase either of
these two memories. This bit is a copy of the
FMBUSY bit in the FMSTAT register.
– Flash memory is not busy.
0
1 – Flash memory is busy.
DPGMBUSY
WDRST The Watchdog Reset bit indicates that a
ISPRST The Software ISP Reset bit indicates that a
The Data Flash Programming Busy indicates
that the flash data memory is being erased or
a pipelined programming sequence is currently ongoing. Software must not attempt to perform any write access to the flash program
memory at this time, without also polling the
FSMSTAT.FMFULL bit in the flash memory interface. The DPGMBUSY bit is a copy of the
FMBUSY bit in the FSMSTAT register.
– Flash data memory is not busy.
0
– Flash data memory is busy.
1
Watchdog timer reset has occurred. Write a 1
to this bit to clear it. Power-on reset also
clears this bit.
– No Watchdog timer reset has occurred
0
– A Watchdog timer reset has occurred
1
software ISP reset has occurred since the bit
was last cleared. This bit is cleared by a
SWRESET(CLR) sequence or a power-on reset.
– No software ISP reset has occurred since
0
– A software ISP reset has occurred since
1
DPGMBUSY
since this bit was last cleared.
since this bit was last cleared.
this bit was last cleared.
this bit was last cleared.
PGMBUSY
OENV2:0
7.3 SOFTWARE RESET REGISTER (SWRESET)
The SWRESET register is a byte-wide, write-only register
which provides a mechanism for software to initiate a reset
into ISP mode without regard to the status of the EMPTY
bits in the flash protection word. This form of reset is only allowed when all of the following conditions are true:
The device is in IRE or ERE mode
BOOTAREA is defined (has a value other than 1111b) in
the Protection Word (see Section 8.4.2 for more details).
ISPE is set in the flash protection word, indicating that
there is ISP code in the flash
To initiate a reset under these conditions, it is necessary to
write the value E1h to the SWRESET register, followed within 127 clock cycles by the value 3Eh. The reset then follows
immediately. This sequence is called SWRESET(ISP).
Once the device has been reset into ISP mode by SWRESET(ISP), any subsequent reset (other than internal or external power-on reset) will cause the part to reset into ISP
mode because the EMPTY bits in the Protection Word continue to be ignored.
A second set of special values written to the SWRESET register will cause a reset out of ISP mode (whether or not the
device is currently in ISP mode). This can be used as a simple software reset. In this case, no conditions are checked.
To initiate reset out of ISP mode, write the value E1h to the
SWRESET register, followed within 127 clock cycles by the
value 0Eh. The reset then follows immediately. This sequence is called SWRESET(CLR). This reset also cancels
the effect of any previous SWRESET(ISP), so subsequent
resets will check the EMPTY bits to determine whether to
enter ISP mode.
The ISP reset behaves similarly to the Watchdog reset, for
example, if the flash interface is busy when reset is asserted, the reset to the clock module is delayed until the flash
operations are completed.
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