MYSON MTV312MN64 Datasheet

MYSON

P0.0-7

P2.0-3

P0.0-7

P2.0-3

8051

P1.0-7

P3.0-2

P3.4-5

AD0-3

DA0-13

DDC & IIC

INTERFACE

AUXRAM &

DDCRAM

H/VSYNC

CONTROL

P6.0-7

P5.0-6

AUX

P4.0-2

MTV312M64

TECHNOLOGY

(Rev 0.99)

8051 Embedded Monitor Controller

Flash Type with ISP

FEATURES

• 8051 core, 12MHz operating frequency with double CPU clock option

• 0.35uM process; 5V/3.3V power supply and I/O; 3.3V core operating

• 1024-byte RAM; 64K-byte program Flash-ROM support In System Programming (ISP)

• Maximum 14 channels of PWM DAC

• Maximum 31 I/O pins

• SYNC processor for composite separation/insertion, H/V polarity/frequency check and polarity adjustment

• Built-in low power reset circuit

• Built-in self-test pattern generator with four free-running timings

• Compliant with VESA DDC1/2B/2Bi/2B+ standard

• Dual slave IIC addresses; H/W auto transfer DDC1/DDC2x data

• Single master IIC interface for internal device communication

• Maximum 4-channel 6-bit ADC

• Watchdog timer with programmable interval

• Flash-ROM program code protection selection

• 40-pin DIP, 42-pin SDIP or 44-pin PLCC package

GENERAL DESCRIPTIONS

The MTV312M micro-controller is an 8051 CPU core embedded device especially tailored for CRT/LCD
Monitor applications. It includes an 8051 CPU core, 1024-byte SRAM, 14 built-in PWM DACs, VESA DDC
interface, 4-channel A/D converter, and a 64K-byte internal program Flash-ROM.

BL OCK DIAGRAM

RD
WR
ALE
INT1

PWM DAC

XFR

ADC

HSYNC

VSYNC
HBLANK
VBLANK

ISCL

ISDA

HSCL

HSDA

RST
X1
X2

CORE

I/O

RD

WR

ALE

INT1

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.

Revision 0.99 - 1 - 2001/07/26

MYSON

ISDA/P3.4/T0

ISCL/P3.5/T1

P6.2/AD2/HLFHI

P1.624P1.7

P6.1/AD1
P1.5

P6.0/AD0

HSDA/P3.1/Txd
P1.1

P3.2/INT0

P1.2

P1.3

P1.4

23222120282726

25

NC

6543214443424140

NC

VDD3

DA0/P5.0

DA1/P5.1

DA2/P5.2
VSYNC

HSYNC

DA3/P5.3

DA4/P5.4

DA5/P5.5

19

18

VSS

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P6.2/AD2/HLFHI

P6.3/AD3

ISDA/P3.4/T0

ISCL/P3.5/T1

P6.2/AD2/HLFHI

MTV312M64

TECHNOLOGY

PIN CONNECTION

DA2/P5.2 401

VDD3

VDD

VSS

X2
X1

P1.0
P1.1

P1.2
P1.3
P1.4
P1.5
P1.6

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

MTV312M

40 Pin

PDIP

DA1/P5.1
DA0/P5.0

STOUT/P4.2

P3.2/INT0

VSYNC

39

HSYNC

38

DA3/P5.3

37

DA4/P5.4

36

DA5/P5.5

35

DA8/HLFHO

34

DA9/HALFV

33

HBLANK/P4.1

32

VBLANK/P4.0

31

DA7/HCLAMP

30

DA6/P5.6

29

RST

28

P6.6/DA12

27

P6.5/DA11

26

P6.4/DA10

25

HSCL/P3.0/Rxd

24

HSDA/P3.1/Txd

23

P6.0/AD0

22

P6.1/AD1

21

P1.7

DA2/P5.2401
DA1/P5.1
DA0/P5.0

VDD3

NC
NC

RST

VDD

VSS

X2
X1

STOUT/P4.2

P1.0
P1.1

P3.2/INT0

P1.2
P1.3
P1.4

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

MTV312M

42 Pin

SDIP

(Rev 0.99)

VSYNC

42

HSYNC

41

DA3/P5.3

39

DA4/P5.4

38

DA5/P5.5

37

DA8/HLFHO

36

DA9/HALFV

35

HBLANK/P4.1

34

VBLANK/P4.0

33

DA7/HCLAMP

32

DA6/P5.6

31

P6.6/DA12

30

P6.5/DA11

29

P6.4/DA10

28

HSCL/P3.0/Rxd

27

HSDA/P3.1/Txd

26

P6.0/AD0

25

P6.1/AD1

24

P1.7

23

P1.6

2221

P1.5

RST

VDD

X2
X1

P1.0

7
8
9
10
11
12
13
14
15
16
17

MTV312M

44 Pin

PLCC

39

DA8/HLFHO

38

DA9/HALFV

37

HBLANK/P4.1

36

VBLANK/P4.0

35

DA7/HCLAMP

34

DA6/P5.6

33

P6.7/DA13

32

P6.6/DA12

31

P6.5/DA11

30

P6.4/DA10

29

HSCL/P3.0/Rxd

Revision 0.99 - 2 - 2001/07/26

MYSON

3.3V System

MTV312M64

TECHNOLOGY

(Rev 0.99)

PIN CONFIGURATION

A “CMOS output pin” means it can sink and drive at least 4mA current. It is not recommended to use such
pin as input function.
A “open drain pin” means it can sink at least 4mA current but only drive 10~20uA to VDD. It can be used as
input or output function and needs an external pull up resistor.
A “8051 standard pin” is a pseudo open drain pin. It can sink at least 4mA current when output is at low level,
and drives at least 4mA current for 160nS when output transits from low to high, then keeps driving at 100uA
to maintain the pin at high level. It can be used as input or output function. It needs an external pull up
resistor when driving heavy load device.

Output

Data

2 OSC
period

delay

4mA 10uA

4mA

Input
Data

120uA

Pin

8051 Stand ard Pin

Output

Data

CMOS Outp u t Pin

4mA

4mA

Pin

Input
Data

Output

Data

Open Drain Pin

No Current

Pin

4mA

POWER CONFIGURATION

The MTV312M can work on 5V or 3.3V power supply system.
In 5V power system, the VDD pin is connected to 5V power and the VDD3 needs an external capacitor, all
output pins can swing from 0~5V, input pins can accept 0~5V input range. And ADC conversion range is 5V.
However, X1 and X2 pins must be kept below 3.3V.
In 3.3V power system, the VDD and VDD3 are connected to 3.3V power, all output pins swing from 0~3.3V,
HSYNC, VSYNC and open drain pin can accept 0~5V input range, other pins must be kept below 3.3V. And
the ADC conversion range is 3.3V.

5V

VDD
VDD3

10u

MTV312M in

5V System

3.3V

VDD
VDD3

MTV312M in

Revision 0.99 - 3 - 2001/07/26

MYSON

HSDA/P3.1/Txd

P6.2/AD2/HLFHI

MTV312M64

TECHNOLOGY

PIN DESCRIPTION

Name

VDD3
VDD
VSS
X2
X1
RST
DA0/P5.0
DA1/P5.1
DA2/P5.2
DA3/P5.3
DA4/P5.4
DA5/P5.5
DA6/P5.6
DA7/HCLAMP
DA8/HLFHO
DA9/HALFV
HSCL/P3.0/Rxd

P3.2/INT0
ISDA/P3.4/T0
ISCL/P3.5/T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P6.0/AD0
P6.1/AD1

P6.3/AD3
P6.4/DA10
P6.5/DA11
P6.6/DA12
P6.7/DA13
VBL ANK /P4.0
HBLA NK /P4.1
STOUT/P4.2
HSYNC
VSYNC

40 42 44

4 4 4 O 3.3V core power
5 8 8 - 5V or 3.3V Positive Power Supply
6 9 10 - Ground
7 10 11 O Oscillator output
8 11 12 I Oscillator input

29 7 7 I Active high reset

3 3 3 I/O PWM DAC output / General purpose I/O (CMOS)
2 2 2 I/O PWM DAC output / General purpose I/O (CMOS)

1 1 1 I/O PWM DAC output / General purpose I/O (CMOS)
38 40 42 I/O PWM DAC output / General purpose I/O (CMOS)
37 39 41 I/O PWM DAC output / General purpose I/O (CMOS)
36 38 40 I/O PWM DAC output / General purpose I/O (CMOS)
30 32 34 I/O PWM DAC output / General purpose I/O (CMOS)
31 33 35 O PWM DAC output / Hsync clamp pulse output (CMOS)
35 37 39 O PWM DAC output / Hsync half freq. Output (open drain)
34 36 38 O PWM DAC output / Vsync half freq. Output (open drain)
25 28 29 I/O Slave IIC clock / General purpose I/O / Rxd (open drain)
24 27 28 I/O Slave IIC data / General purpose I/O / Txd (open drain)
15 18 19 I/O General purpose I/O / INT0 (8051 standard)

9 12 13 I/O Master IIC data / General purpose I/O / T0 (open drain)
10 13 14 I/O Master IIC clock / General purpose I/O / T1 (open drain)
13 16 17 I/O General purpose I/O (CMOS output or 8051 standard)
14 17 18 I/O General purpose I/O (CMOS output or 8051 standard)
16 19 20 I/O General purpose I/O (CMOS output or 8051 standard)
17 20 21 I/O General purpose I/O (CMOS output or 8051 standard)
18 21 22 I/O General purpose I/O (CMOS output or 8051 standard)
19 22 23 I/O General purpose I/O (CMOS output or 8051 standard)
20 23 24 I/O General purpose I/O (CMOS output or 8051 standard)
21 24 25 I/O General purpose I/O (CMOS output or 8051 standard)
23 26 27 I/O General purpose I/O / ADC Input (CMOS)
22 25 26 I/O General purpose I/O / ADC Input (CMOS)
12 15 16 I/O General purpose I/O / ADC Input / Half Hsync input (CMOS)

- - 9 I/O General purpose I/O / ADC Input (CMOS)
26 29 30 I/O General purpose I/O / PWM DAC output (CMOS)
27 30 31 I/O General purpose I/O / PWM DAC output (CMOS)
28 31 32 I/O General purpose I/O / PWM DAC output (CMOS)

- - 33 I/O General purpose I/O / PWM DAC output (CMOS)
32 34 36 O Vertical blank (CMOS) / General purpose Output (CMOS)
33 35 37 O Horizontal blank (CMOS) / General purpose Output (CMOS)
11 14 15 O Self-test video output (CMOS) / General purpose Output (CMOS)
39 41 43 I Horizontal SYNC or Composite SYNC Input
40 42 44 I Vertical SYNC input

PIN NO.

(Rev 0.99)

Type Description

Revision 0.99 - 4 - 2001/07/26

MYSON

MTV312M64

TECHNOLOGY

(Rev 0.99)

FUNCTIONAL DESCRIPTIONS

1. 8051 CPU Core

The CPU core of MTV312M is compatible with the industry standard 8051, which includes 256 bytes RAM,
Special Function Registers (SFR), two timers, five interrupt sources and a serial interface. The CPU core
fetches its program code from the 64K bytes Flash in MTV312M. It uses Port0 and Port2 to access the
“external special function register” (XFR) and external auxiliary RAM (AUXRAM).
The CPU core can run at double rate when FclkE is set. Once the bit is set, the CPU runs as if a 24MHz
X’tal is applied on MTV312M, but the peripherals (IIC, DDC, H/V processor) still run at the original frequency.

Note: All registers listed in this document reside in 8051’s external RAM area (XFR). For internal RAM
memory map, please refer to 8051 spec.

2. Memory Allo catio n

2.1 Internal Special Function Registers (SFR)
The SFR is a group of registers that are the same as standard 8051.

2.2 Internal RAM
There are total 256 bytes internal RAM in MTV312M, the same as standard 8052.

2.3 External Special Function Registers (XFR)
The XFR is a group of registers allocated in the 8051 external RAM area F00h - FFFh. These registers are
used for special functions. Programs can use "MOVX" instruction to access these registers .

2.4 Auxiliary RAM (AUXRAM)
There are total 512 bytes auxiliary RAM allocated in the 8051 external RAM area 800h - 9FFh. Programs
can use "MOVX" instruction to access the AUXRAM.

2.5 Dual Port RAM (DDCRAM)
There are 256 bytes Dual Port RAM allocated in the 8051 external RAM area E00h - EFFh. Programs can
use "MOVX" instruction to access the RAM. The external DDC1/2 Host can access the R AM as if a 24LC02
EEPROM is connected onto the interface.

FFh

Internal RAM

Accessible by

addressing only

80h
7Fh

Internal RAM

Accessible by

direct and indirect

indirect

(Using

MOV A,@Ri

instruction)

addressing

SFR

Accessible by

direct addressing

FFFh

F00h

XFR

Accessible by

indirect external

RAM addressing

(Using MOVX

instruction)

EFFh

E00h
9FFh

DDCRAM

Accessible by

indirect external

RAM addressing

(Using MOVX

instruction)

AUXRAM

Accessible by

indirect external

RAM addressing

(Using MOVX

instruction

00h

800h

Revision 0.99 - 5 - 2001/07/26

MYSON

PWMF

MTV312M64

TECHNOLOGY

3. Chip Configu ratio n

The Chip Configuration registers define configuration of the chip and function of the pins.

Reg name addr bit7 bit6 bit5 Bit4 bit3 bit2 bit1 bit0

PADMOD
PADMOD
PADMOD
PADMOD
PADMOD
PADMOD

OPTION

PADMOD (w) : Pad mode control registers. (All are "0" in Chip Reset)

DA13E = 1 → Pin “P6.7/DA13” is DA13.
DA12E = 1 → Pin “P6.6/DA12” is DA12.

DA11E = 1 → Pin “P6.5/DA11” is DA11.
DA10E = 1 → Pin “P6.4/DA10” is DA10.
AD3E = 1 → Pin “P6.3/AD3” is AD3.
AD2E = 1 → Pin “P6.2/AD2” is AD2.
AD1E = 1 → Pin “P6.1/AD1” is AD1.
AD0E = 1 → Pin “P6.0/AD0” is AD0.

P56E = 1 → Pin “DA6/P5.6” is P5.6.
P55E = 1 → Pin “DA5/P5.5” is P5.5.
P54E = 1 → Pin “DA4/P5.4” is P5.4.
P53E = 1 → Pin “DA3/P5.3” is P5.3.
P52E = 1 → Pin “DA2/P5.2” is P5.2.
P51E = 1 → Pin “DA1/P5.1” is P5.1.

P50E = 1 → Pin “DA0/P5.0” is P5.0.
HIICE = 1 → Pin “HSCL/P3.0/Rxd” is HSCL; pin “HSDA/P3.1/Txd” is HSDA.
IIICE = 1 → Pin “ISDA/P3.4/T0” is ISDA; pin “ISCL/P3.5/T1” is ISCL.
HLFVE = 1 → Pin “DA9/HALFV” is VSYNC half frequency output.
HLFHE = 1 → Pin “DA8/HALFH” is HSYNC half frequency output.

F50h(w) DA13E DA12E DA11E DA10E AD3E AD2E AD1E AD0E
F51h(w) P56E P55E P54E P53E P52E P51E P50E
F52h(w) HIICE IIICE HLFVE HLFHE HCLPE P42E P41E P40E
F53h(w) P56oe P55oe P54oe P53oe P52oe P51oe P50oe
F54h(w) P67oe P66oe P65oe P64oe P63oe P62oe P61oe P60oe
F55h(w) COP17 COP16 COP15 COP14 COP13 COP12 COP11 COP10
F56h(w)

= 0 → Pin “P6.7/DA13” is P6.7.

= 0 → Pin “P6.6/DA12” is P6.6.
= 0 → Pin “P6.5/DA11” is P6.5.
= 0 → Pin “P6.4/DA10” is P6.4.
= 0 → Pin “P6.3/AD3” is P6.3.
= 0 → Pin “P6.2/AD2” is P6.2.
= 0 → Pin “P6.1/AD1” is P6.1.

= 0 → Pin “P6.0/AD0” is P6.0.
= 0 → Pin “DA6/P5.6” is DA6.
= 0 → Pin “DA5/P5.5” is DA5.
= 0 → Pin “DA4/P5.4” is DA4.
= 0 → Pin “DA3/P5.3” is DA3.
= 0 → Pin “DA2/P5.2” is DA2.

= 0 → Pin “DA1/P5.1” is DA1.
= 0 → Pin “DA0/P5.0” is DA0.
= 0 → Pin “HSCL/P3.0/Rxd” is P3.0/Rxd; pin “HSDA/P3.1/Txd” is P3.1/Txd.
= 0 → Pin “ISDA/P3.4/T0” is P3.4/T0; pin “ISCL/P3.5/T1” is P3.5/T1.
= 0 → Pin “DA9/HALFV” is DA9.
= 0 → Pin “DA8/HALFH” is DA8.

DIV253 FclkE ENSCL Msel MIICF1 MIICF0

(Rev 0.99)

Revision 0.99 - 6 - 2001/07/26

MYSON

MTV312M64

TECHNOLOGY

HCLPE = 1 → Pin “DA7/HCLAMP” is HSYNC clamp pulse output.

= 0 → Pin “DA7/HCLAMP” is DA7.

P42E = 1 → Pin “STOUT/P4.2” is P4.2.

= 0 → Pin “STOUT/P4.2” is STOUT.

P41E = 1 → Pin “HBLANK/P4.1” is P4.1.

= 0 → Pin “HBLANK/P4.1” is HBLANK.

P40E = 1 → Pin “VBLANK/P4.0” is P4.0.

= 0 → Pin “VBLANK/P4.0” is VBLANK.

P56oe = 1 → P5.6 is output pin.

= 0 → P5.6 is input pin.

P55oe = 1 → P5.5 is output pin.

= 0 → P5.5 is input pin.

P54oe = 1 → P5.4 is output pin.

= 0 → P5.4 is input pin.

P53oe = 1 → P5.3 is output pin.

= 0 → P5.3 is input pin.

P52oe = 1 → P5.2 is output pin.

= 0 → P5.2 is input pin.

P51oe = 1 → P5.1 is output pin.

= 0 → P5.1 is input pin.

P50oe = 1 → P5.0 is output pin.

= 0 → P5.0 is input pin.

P67oe = 1 → P6.7 is output pin.

= 0 → P6.7 is input pin.

P66oe = 1 → P6.6 is output pin.

= 0 → P6.6 is input pin.

P65oe = 1 → P6.5 is output pin.

= 0 → P6.5 is input pin.

P64oe = 1 → P6.4 is output pin.

= 0 → P6.4 is input pin.

P63oe = 1 → P6.3 is output pin.

= 0 → P6.3 is input pin.

P62oe = 1 → P6.2 is output pin.

= 0 → P6.2 is input pin.

P61oe = 1 → P6.1 is output pin.

= 0 → P6.1 is input pin.

P60oe = 1 → P6.0 is output pin.

= 0 → P6.0 is input pin.

COP17 = 1 → Pin “P1.7” is CMOS Output.

= 0 → Pin “P1.7” is 8051 standard I/O.

COP16 = 1 → Pin “P1.6” is CMOS Output.

= 0 → Pin “P1.6” is 8051 standard I/O.

COP15 = 1 → Pin “P1.5” is CMOS Output.

= 0 → Pin “P1.5” is 8051 standard I/O.

COP14 = 1 → Pin “P1.4” is CMOS Output.

= 0 → Pin “P1.4” is 8051 standard I/O.

COP13 = 1 → Pin “P1.3” is CMOS Output.

= 0 → Pin “P1.3” is 8051 standard I/O.

COP12 = 1 → Pin “P1.2” is CMOS Output.

= 0 → Pin “P1.2” is 8051 standard I/O.

COP11 = 1 → Pin “P1.1” is CMOS Output.

= 0 → Pin “P1.1” is 8051 standard I/O.

(Rev 0.99)

Revision 0.99 - 7 - 2001/07/26

MYSON

MTV312M64

TECHNOLOGY

COP10 = 1 → Pin “P1.0” is CMOS Output.

= 0 → Pin “P1.0” is 8051 standard I/O.

OPTION (w) : Chip option configuration (All are "0" in Chip Reset).

PWMF = 1 → Selects 94KHz PWM frequency.

= 0 → Selects 47KHz PWM frequency.

DIV253 = 1 → PWM pulse width is 253-step resolution.

= 0 → PWM pulse width is 256-step resolution.

FclkE = 1 → CPU is running at double rate

= 0 → CPU is running at normal rate

ENSCL = 1 → Enable slave IIC block to hold HSCL pin low while MTV312M64 is unable to

catch-up with the external master's speed.

Msel = 1 → Master IIC block connect to HSCL/HSDA pins.

= 0 → Master IIC block connect to ISCL/ISDA pins .

MIICF1,MIICF0 = 1,1 → Selects 400KHz Master IIC frequency.

= 1,0 → Selects 200KHz Master IIC frequency.
= 0,1 → Selects 50KHz Master IIC frequency.
= 0,0 → Selects 100KHz Master IIC frequency.

4. I/O Ports

(Rev 0.99)

4.1 Port1
Port1 is a group of pseudo open drain pins or CMOS output pins. It can be used as general purpose I/O.
Behavior of Port1 is the same as standard 8051.

4.2 P3.0-2, P3.4-5
If these pins are not set as IIC pins, Port3 can be used as general purpose I/O, interrupt, UART and Timer
pins. Behavior of Port3 is the same as standard 8051.

4.3 Port4, Port5 and Port6
Port5 and Port6 are used as general purpose I/O. S/W needs to set the corresponding P5(n)oe and P6(n)oe
to define whether these pins are input or output. Port4 is pure output.

Reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PORT5
PORT5
PORT5
PORT5
PORT5
PORT5
PORT5
PORT6
PORT6
PORT6
PORT6
PORT6
PORT6
PORT6
PORT6
PORT4
PORT4
PORT4

F30h(r/w) P50
F31h(r/w) P51
F32h(r/w) P52
F33h(r/w) P53
F34h(r/w) P54
F35h(r/w) P55
F36h(r/w) P56
F38h(r/w) P60
F39h(r/w) P61
F3Ah(r/w) P62
F3Bh(r/w) P63
F3Ch(r/w) P64
F3Dh(r/w) P65
F3Eh(r/w) P66
F3Fh(r/w) P67

F58h(w) P40
F59h(w) P41
F5Ah(w) P42

Revision 0.99 - 8 - 2001/07/26

MYSON

MTV312M64

TECHNOLOGY

PORT5 (r/w) : Port 4 data input/output value.
PORT6 (r/w) : Port 5 data input/output value.
PORT4 (w) : Port 6 data output value.

5. PWM DAC

Each output pulse width of PWM DAC converter is controlled by an 8-bit register in XFR. The frequency of
PWM clock is 47KHz or 94KHz, selected by PW MF. And the total duty cycle step of these DAC outputs is
253 or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high
output. If DIV253=0, the output pulses low at least once even if the DAC register's content is FFH. Writing
00H to DAC register generates stable low output.

Reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8

DA9
DA10
DA11
DA12
DA13

F20h(r/w) Pulse width of PWM DAC 0
F21h(r/w) Pulse width of PWM DAC 1
F22h(r/w) Pulse width of PWM DAC 2
F23h(r/w) Pulse width of PWM DAC 3
F24h(r/w) Pulse width of PWM DAC 4
F25h(r/w) Pulse width of PWM DAC 5
F26h(r/w) Pulse width of PWM DAC 6
F27h(r/w) Pulse width of PWM DAC 7
F28h(r/w) Pulse width of PWM DAC 8
F29h(r/w) Pulse width of PWM DAC 9
F2Ah(r/w) Pulse width of PWM DAC 10
F2Bh(r/w) Pulse width of PWM DAC 11
F2Ch(r/w) Pulse width of PWM DAC 12
F2Dh(r/w) Pulse width of PWM DAC 13

(Rev 0.99)

DA0-13 (r/w) : The output pulse width control for DA0-13.
* All of PWM DAC converters are centered with value 80h after power on.

6. H/V SYNC Processin g

The H/V SYNC processing block performs the functions of composite signal separation/insertion. SYNC
inputs presence check, frequency counting, polarity detection and control, as well as the protection of
VBLANK output while VSYNC speeds up in high DDC comm unication clock rate.
Based on the digital filter, the present and frequency function block treat any pulse shorter than one OSC
period (83.33ns) as noise, between one and two OSC period (83.33ns to 166.67ns) as unknown region, and
longer than two OSC period (166.67ns) as pulse.

Revision 0.99 - 9 - 2001/07/26