MYSON MTV212MS64i, MTV212MV64i, MTV212MN64i Datasheet

MYSON

8051 core, 12MHz operating frequency.
1024-byte RAM; 64K-byte program Flash-ROM support In System
Maximum 14 channels of 5V open-drain PWM DAC.

Watchdog timer with pr

The MTV212M64i micro-controller is an 8051 CPU core embedded device especially tailored to Monitor
applications. It includes an 8051 CPU core, 1024-byte SRAM, SYNC process or, 14 built-in PWM DACs,
VESA DDC interface, 4-channel A/D converter and a 64K-byte internal program Flash-ROM.

WR

WR

MTV212M64i

TECHNOLOGY

(Rev 0.9)

8051 Embedded Monitor Controller

Flash Type with ISP

FEATURES

•

•

•

• Maximum 32 bi-directional I/O pins.

• SYNC processor for composite separation/insertion, H/V polarity/frequency check, polarity adjustment

and programmable clamp pulse output.

• Built-in self-test pattern generator with four free-running timings.

• Built-in low power reset circuit.

• Compliant with VESA DDC1/2B/2Bi/2B+ standard.

• Dual slave IIC addresses.

• Single master IIC interface for internal device communication.

• 4-channel 6-bit ADC.

•

• 40-pin DIP, 42-pin SDIP or 44-pin PLCC package.

ogrammable intervals.

GENERAL DESCRIPTIONS

Programming(ISP).

BL OCK DIAGRAM

STOUT
HBLANK
VBLANK
HSYNC
VSYNC
HCLAMP
HALFV
HALFH

P1.0-7
P2.0-2,P2.4-7

P3.2-0

P3.4-5
RST
X1
X2

8051

P0.0-

7

RD

ALE

P0.0-

7

RD

ALE

AD0-2

XFR

ADC

H/VSYNC
CONTROL

14 CHANNEL

PWM DAC

ISCL

DDC & IIC

INTERFACE

ISDA
HSCL
HSDA

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.

Revision 0.9 - 1 - 2000/11/16

MYSON

DA2/P5.2

DA1/P5.1

DA0/P5.0

VSS

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P2.2/AD2

P3.2/INT0

DA2/P5.2

DA1/P5.1

DA0/P5.0

VSS

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P2.2/AD2

P3.2/INT0

P1.624P1.7

P2.1/AD1

P1.5

P2.0/AD0

HSDA/P3.1/Txd
P1.1

P3.2/INT0

P1.2

P1.3

P1.4

23222120282726

25

NC

6543214443424140

NC

NC

DA0/P5.0

DA1/P5.1

DA2/P5.2
VSYNC

HSYNC

DA3/P5.3

DA4/P5.4

DA5/P5.5

19

18

VSS

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P2.2/AD2

P2.3/AD3

MTV212M64i

TECHNOLOGY

(Rev 0.9)

PIN CONNECTION

Note: As long as the pin sequence is not changed, the pin-out of 42 pin SDIP is negotiab le according to
customers’ demand.

401

VSYNC

39

HSYNC

38

DA3/P5.3

37

DA4/P5.4

36

DA5/P5.5

35

DA8/HALFH

34

DA9/HALFV

33

HBLANK/P4.1

32

VBLANK/P4.0

31

DA7/HCLAMP

30

DA6/P5.6

29

P2.7/DA13

28

P2.6/DA12

27

P2.5/DA11

26

P2.4/DA10

25

HSCL/P3.0/Rxd

24

HSDA/P3.1/Txd

23

P2.0/AD0

22

P2.1/AD1

21

P1.7

RST

VDD

X2
X1

P1.0
P1.1

P1.2
P1.3
P1.4
P1.5
P1.6

2
3
4
5
6
7
8

MTV212M64i

9

40 Pin

10
11
12
13
14
15
16
17
18
19
20

PDIP

NC
NC
NC

RST

VDD

X2
X1

P1.0
P1.1

P1.2
P1.3
P1.4

1
2
3
4
5
6
7
8

MTV212M64i

9

42 Pin

10
11
12
13
14
15
16
17
18
19
20

SDIP

VSYNC

42

HSYNC

41
40

DA3/P5.3

39

DA4/P5.4

38

DA5/P5.5

37

DA8/HALFH

36

DA9/HALFV

35

HBLANK/P4.1

34

VBLANK/P4.0

33

DA7/HCLAMP

32

DA6/P5.6

31

P2.6/DA12

30

P2.5/DA11

29

P2.4/DA10

28

HSCL/P3.0/Rxd

27

HSDA/P3.1/Txd

26

P2.0/AD0

25

P2.1/AD1

24

P1.7

23

P1.6

2221

P1.5

RST

VDD

X2
X1

P1.0

7
8
9
10
11
12
13
14
15
16
17

MTV212M64i

44 Pin

PLCC

39

DA8/HALFH

38

DA9/HALFV

37

HBLANK/P4.1

36

VBLANK/P4.0

35

DA7/HCLAMP

34

DA6/P5.6

33

P2.7/DA13

32

P2.6/DA12

31

P2.5/DA11

30

P2.4/DA10

29

HSCL/P3.0/Rxd

Revision 0.9 - 2 - 2000/11/17

MYSON

PWM DAC output (5V open drain) / General purpose I/O (5V open drain)
PWM DAC output (5V open drain) / General purpose I/O (5V open drain)
PWM DAC output (5V open drain) / General purpose I/O (5V open drain)

PWM DAC output (CMOS) /

PWM DAC output (5V open drain) /
PWM DAC output (5V open drain) /

MTV212M64i

TECHNOLOGY

PIN DESCRIPTION

Name Type Description
DA2/P5.2
DA1/P5.1
DA0/P5.0
RST
VDD
P2.3/AD3
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P2.2/AD2
P1.0
P1.1
P3.2/INT0
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.1/AD1
P2.0/AD0
HSDA/P3.1/Txd
HSCL/P3.0/Rxd
P2.4/DA10
P2.5/DA11
P2.6/DA12
P2.7/DA13
DA6/P5.6
DA7/HCLAMP
VBL ANK /P4.0
HBLA NK /P4.1
DA9/HALFV
DA8/HALFH
DA5/P5.5
DA4/P5.4
DA3/P5.3
HSYNC
VSYNC

I/O
I/O
I/O

Active high reset

I

Positive Power Supply

-

General purpose I/O (CMOS output or 8051 standard) / ADC Input

I/O

Ground

-

Oscillator output

O

Oscillator input

I

Master IIC data (5V open drain) / General purpose I/O (8051 standard) / T0

I/O

Master IIC clock (5V open drain) / General purpose I/O (8051 standard) / T1

I/O

Self-test video output (CMOS) / General purpose Output (CMOS)

O

General purpose I/O (CMOS output or 8051 standard) / ADC Input

I/O

General purpose I/O (CMOS output or 8051 standard)

I/O

General purpose I/O (CMOS output or 8051 standard)

I/O

General purpose Input / INT0

I

General purpose I/O (CMOS output or 8051 standard)

I/O

General purpose I/O (CMOS output or 8051 standard)

I/O

General purpose I/O (CMOS output or 8051 standard)

I/O

General purpose I/O (CMOS output or 8051 standard)

I/O

General purpose I/O (CMOS output or 8051 standard)

I/O

General purpose I/O (CMOS output or 8051 standard)

I/O

General purpose I/O (CMOS output or 8051 standard) / ADC Input

I/O

General purpose I/O (CMOS output or 8051 standard) / ADC Input

I/O

Slave IIC data (5V open drain) / General purpose I/O (8051 standard) / Txd

I/O

Slave IIC clock (5V open drain) / General purpose I/O (8051 standard) / Rxd

I/O

General purpose I/O (CMOS output or 8051 standard) / PWM DAC output (CMOS)

I/O

General purpose I/O (CMOS output or 8051 standard) / PWM DAC output (CMOS)

I/O

General purpose I/O (CMOS output or 8051 standard) / PWM DAC output (CMOS)

I/O

General purpose I/O (CMOS output or 8051 standard) / PWM DAC output (CMOS)

I/O

PWM DAC output (CMOS) / General purpose I/O (CMOS output or open drain I/O)

I/O

O

Vertical blank (CMOS) / General purpose Output (CMOS)

O

Horizontal blank (CMOS) / General purpose Output (CMOS)

O
O
O

PWM DAC output (CMOS) / General purpose I/O (CMOS output or open drain I/O)

I/O

PWM DAC output (CMOS) / General purpose I/O (CMOS output or open drain I/O)

I/O

PWM DAC output (CMOS) / General purpose I/O (CMOS output or open drain I/O)

I/O

Horizontal SYNC or Composite SYNC Input

I

Vertical SYNC input

I

Hsync clamp pulse output (CMOS)

(Rev 0.9)

vsync half freq. output (5V open drain)
hsync half freq. output (5V open drain)

Revision 0.9 - 3 - 2000/11/17

MYSON

resistor when driving heavy load devices.

MTV212M64i

TECHNOLOGY

(Rev 0.9)

PIN CONFIGURATION

A “CMOS output pin” means it can sink and drive at least 4mA current. It’s not recommended to use such pin
as input function.
A “5V open drain pin” means it can sink at least 4mA current but only drive 10~20uA to VDD. It can be used
as input or output function and needs an external pull up resistor.
A “8051 standard pin” is a pseudo open drain pin. It can sink at least 4mA current when output is at low level,
and drive at least 4mA current for 160nS when output transits from low to high, then keeps driving at 100uA
to maintain the pin at high level. It can be used as input or output function. It needs an external pull u p

Output

Data

2 OSC
period

delay

4mA 10uA

4mA

Input
Data

120uA

8051 Stand ar d Pin

Pin

Input
Data

Output

Data

Output

Data

4mA

CMOS Outp u t Pin

Pin

4mA

No Current

5V Open Drain Pin

Pin

4mA

Revision 0.9 - 4 - 2000/11/17

MYSON

FUNCTIONAL DESCRIPTIONS

Port2 is shared by special fu

2. Memory All oc ation

2.4 Auxiliary RAM (AUXRAM)

MTV212M64i

TECHNOLOGY

1. 8051 CPU Core

(Rev 0.9)

MTV212M64i includes all 8051 functions with the following exceptions:

1.1 The external RAM access is restricted to XFRs/AUXRAM within the MTV212M64i.

1.2 Port0, port3.3, port3.6 and port3.7 are not general-purpose I/O ports. They are dedicated to monitor
special application.

1.3 INT1 input pin is not provided, it is connected to special interrupt sources.

1.4

In addition, there are 2 timers, 5 interrupt sources and a serial interface compatible with the standard 8051.

nction pins.

Note: All registers listed in this document reside in external RAM area (XFR). For internal RAM memory map,
please refer to 8051 spec.

2.1 Internal Special Function Registers (SFR)

The SFR is a group of registers that are the same as standard 8051.

2.2 Internal RAM

There are total 256 bytes internal RAM in MTV212M64i, same as standard 8052.

2.3 External Special Function Registers (XFR)

The XFR is a group of registers allocated in the 8051 external RAM area 00h - 7Fh. Most of the registers are
used for monitor control or PWM DAC. Program can initialize Ri value and use "MOVX" instruction to access
these registers.

There are a total of 768 bytes auxiliary RAM allocated in the 8051 external RAM area 80h - FFh. The
AUXRAM is divided into six banks, selected by XBANK register. Program can initialize Ri value and use
"MOVX" instruction to access the AUXRAM.

FFh

Internal RAM

addressing only

80h
7Fh

Internal RAM

Accessible by

indirect

(Using

MOV A,@Ri

instruction)

SFR

Accessible by

direct addressing

FFh

80h
7Fh

AUXRAM

Accessible by

indirect external

RAM addressing

(XBANK=0)(Using

MOVX A,@Ri

instruction)

XFR

…..
XBANK=

2,3,4,5

AUXRAM

Accessible by

indirect external

RAM addressing

(XBANK=5)(Using

MOVX A,@Ri

instruction)

Accessible by

direct and indirect

addressing

00h

Accessible by

indirect external

RAM addressing

(Using

MOVX A,@Ri

instruction

00h

Revision 0.9 - 5 - 2000/11/17

MYSON

PWMF

MTV212M64i

TECHNOLOGY

3. Chip Configu r ation

The Chip Configuration registers define the chip pins function, as well as the connection, configuration and
frequency of the functional blocks.

Reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PADMOD
PADMOD
PADMOD
PADMOD
PADMOD
PADMOD

OPTION
OPTION

XBANK

PADMOD (w) : Pad mode control registers. (All are "0" in Chip Reset)

DA13E = 1 → Pin “P2.7/DA13” is DA13.
DA12E = 1 → Pin “P2.6/DA12” is DA12.
DA11E = 1 → Pin “P2.5/DA11” is DA11.
DA10E = 1 → Pin “P2.4/DA10” is DA10.

AD3E = 1 → Pin “P2.3/AD3” is AD3.
AD2E = 1 → Pin “P2.2/AD2” is AD2.
AD1E = 1 → Pin “P2.1/AD1” is AD1.
AD0E = 1 → Pin “P2.0/AD0” is AD0.
P56E = 1 → Pin “DA6/P5.6” is P5.6.
P55E = 1 → Pin “DA5/P5.5” is P5.5.

P54E = 1 → Pin “DA4/P5.4” is P5.4.
P53E = 1 → Pin “DA3/P5.3” is P5.3.
P52E = 1 → Pin “DA2/P5.2” is P5.2.
P51E = 1 → Pin “DA1/P5.1” is P5.1.
P50E = 1 → Pin “DA0/P5.0” is P5.0.
HIICE = 1 →Pin “HSCL/P3.0/Rxd” is HSCL; pin “HSDA/P3.1/Txd” is HSDA.

IIICE = 1 → Pin “ISDA/P3.4/T0” is ISDA; pin “ISCL/P3.5/T1” is ISCL.
HLFVE = 1 →Pin “DA9/HALFV” is VSYNC half frequency output.

30h (w) DA13E DA12E DA11E DA10E AD3E AD2E AD1E AD0E
31h (w) P56E P55E P54E P53E P52E P51E P50E
32h (w) HIICE IIICE HLFVE HLFHE HCLPE P42E P41E P40E
3Ah (w) COP17 COP16 COP15 COP14 COP13 COP12 COP11 COP10
3Bh (w) COP27 COP26 COP25 COP24 COP23 COP22 COP21 COP20

3Ch (w) COP56 COP55 COP54 COP53

33h (w)
34h (w) SlvAbs1 SlvAbs0

35h (r/w) Xbnk2 Xbnk1 Xbnk0

= 0 → Pin “P2.7/DA13” is P2.7.
= 0 → Pin “P2.6/DA12” is P2.6.
= 0 → Pin “P2.5/DA11” is P2.5.

= 0 → Pin “P2.4/DA10” is P2.4.
= 0 → Pin “P2.3/AD3” is P2.3.
= 0 → Pin “P2.2/AD2” is P2.2.
= 0 → Pin “P2.1/AD1” is P2.1.
= 0 → Pin “P2.0/AD0” is P2.0.
= 0 → Pin “DA6/P5.6” is DA6.

= 0 → Pin “DA5/P5.5” is DA5.
= 0 → Pin “DA4/P5.4” is DA4.
= 0 → Pin “DA3/P5.3” is DA3.
= 0 → Pin “DA2/P5.2” is DA2.
= 0 → Pin “DA1/P5.1” is DA1.
= 0 → Pin “DA0/P5.0” is DA0.

= 0 → Pin “HSCL/P3.0/Rxd” is P3.0/Rxd; pin “HSDA/P3.1/Txd” is P3.1/Txd.
= 0 → Pin “ISDA/P3.4/T0” is P3.4/T0; pin “ISCL/P3.5/T1” is P3.5/T1.

DIV253 FclkE IICpass ENSCL Msel MIICF1 MIICF0

(Rev 0.9)

Revision 0.9 - 6 - 2000/11/17

MYSON

is HSYNC half frequency output.

MTV212M64i

TECHNOLOGY

= 0 → Pin “DA9/HALFV” is DA9.

HLFHE = 1 → Pin “DA8/HALFH”

= 0 → Pin “DA8/HALFH” is DA8.

HCLPE = 1 → Pin “DA7/HCLAMP” is HSYNC clamp pulse output.

= 0 → Pin “DA7/HCLAMP” is DA7.

P42E = 1 → Pin “STOUT/P4.2” is P4.2.

= 0 → Pin “STOUT/P4.2” is STOUT.

P41E = 1 →Pin “HBLANK/P4.1” is P4.1.

= 0 → Pin “HBLANK/P4.1” is HBLANK.

P40E = 1 → Pin “VBLANK/P4.0” is P4.0.

= 0 → Pin “VBLANK/P4.0” is VBLANK.

COP17 = 1 → Pin “P1.7” is CMOS Output.

= 0 → Pin “P1.7” is 8051 standard I/O.

COP16 = 1 → Pin “P1.6” is CMOS Output.

= 0 → Pin “P1.6” is 8051 standard I/O.

COP15 = 1 → Pin “P1.5” is CMOS Output.

= 0 → Pin “P1.5” is 8051 standard I/O.

COP14 = 1 → Pin “P1.4” is CMOS Output.

= 0 → Pin “P1.4” is 8051 standard I/O.

COP13 = 1 → Pin “P1.3” is CMOS Output.

= 0 → Pin “P1.3” is 8051 standard I/O.

COP12 = 1 → Pin “P1.2” is CMOS Output.

= 0 → Pin “P1.2” is 8051 standard I/O.

COP11 = 1 → Pin “P1.1” is CMOS Output.

= 0 → Pin “P1.1” is 8051 standard I/O.

COP10 = 1 → Pin “P1.0” is CMOS Output.

= 0 → Pin “P1.0” is 8051 standard I/O.

COP27 = 1 → Pin “P2.7/DA13” is CMOS data Output.

= 0 → Pin “P2.7/DA13” is 8051 standard I/O or CMOS PWM DAC Output.

COP26 = 1 → Pin “P2.6/DA12” is CMOS data Output.

= 0 → Pin “P2.6/DA12” is 8051 standard I/O or CMOS PWM DAC Output.

COP25 = 1 → Pin “P2.5/DA11” is CMOS data Output.

= 0 → Pin “P2.5/DA11” is 8051 standard I/O or CMOS PWM DAC Output.

COP24 = 1 → Pin “P2.4/DA10” is CMOS data Output.

= 0 → Pin “P2.4/DA10” is 8051 standard I/O or CMOS PWM DAC Output.

COP23 = 1 → Pin “P2.3/AD3” is CMOS data Output.

= 0 → Pin “P2.3/AD3” is 8051 standard I/O or ADC Input.

COP22 = 1 → Pin “P2.2/AD2” is CMOS data Output.

= 0 → Pin “P2.2/AD2” is 8051 standard I/O or ADC Input.

COP21 = 1 → Pin “P2.1/AD1” is CMOS data Output.

= 0 → Pin “P2.1/AD1” is 8051 standard I/O or ADC Input.

COP20 = 1 → Pin “P2.0/AD0” is CMOS data Output.

= 0 → Pin “P2.0/AD0” is 8051 standard I/O or ADC Input.

COP56 = 1 → Pin “DA6/P5.6” is CMOS data Output.

= 0 → Pin “DA6/P5.6” is open drain I/O or CMOS PWM DAC.

COP55 = 1 → Pin “DA5/P5.5” is CMOS data Output.

= 0 → Pin “DA5/P5.5” is open drain I/O or CMOS PWM DAC.

COP54 = 1 → Pin “DA4/P5.4” is CMOS data Output.

= 0 → Pin “DA4/P5.4” is open drain I/O or CMOS PWM DAC.

COP53 = 1 → Pin “DA3/P5.3” is CMOS data Output.

= 0 → Pin “DA3/P5.3” is open drain I/O or CMOS PWM DAC.

(Rev 0.9)

Revision 0.9 - 7 - 2000/11/17

MYSON

Selects 94KHz PWM frequency.
Selects 47KHz PWM frequency.

Selects 50KHz Master IIC frequency.

Auxiliary RAM bank switch.

Each output pulse width of PWM DAC converter is controlled by an 8-bit register in XFR. The frequency of

MTV212M64i

TECHNOLOGY

OPTION (w) : Chip option configuration (All are "0" in Chip Reset).

PWMF = 1 →

= 0 →

DIV253 = 1 → PWM pulse width is 253-step resolution.
FclkE = 1 → Double CPU clock freq.

IICpass = 1 → HSCL/HSDA pin bypasses to ISCL/ISDA pin in DDC2 mode.
ENSCL = 1 → Enables slave IIC block to hold HSCL pin low while MTV212M64i is unable to
Msel = 1 → Master IIC block connects to HSCL/HSDA pins.
MIICF1,MIICF0 = 1,1 → Selects 400KHz Master IIC frequency.

SlvAbs1,SlvAbs0 : Slave address length of Slave IIC block A.

XBANK (r/w) :

Xbnk[2:0] = 0 → Selects AUXRAM bank 0.

= 0 → PWM pulse width is 256-step resolution.

= 0 → Separates Master and Slave IIC block.

catch up the external master's speed.

= 0 → Master IIC block connects to ISCL/ISDA pins.

= 1,0 → Selects 200KHz Master IIC frequency.
= 0,1 →
= 0,0 → Selects 100KHz Master IIC frequency.

= 1,0 → 5-bits slave address.
= 0,1 → 6-bits slave address.
= 0,0 → 7-bits slave address.

= 1 → Selects AUXRAM bank 1.
= 2 → Selects AUXRAM bank 0.
= 3 → Selects AUXRAM bank 1.
= 4 → Selects AUXRAM bank 0.
= 5 → Selects AUXRAM bank 1.

(Rev 0.9)

4. Extra I/O

The extra I/O is a group of I/O pins located in XFR area. Port4 is output mode onl y. Port5 can be used as
both output and input for that the pin of Port5 is open drain type, users must write corresponding bit of Port5
to "1" in input mode.

Reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PORT4
PORT5

PORT4 (w) : Port 4 data output value.
PORT5 (r/w) : Port 5 data input/output value.

5. PWM DAC

PWM clk is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is 253
or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high
output. If DIV253=0, the output will pulse low at least once even if the content of DAC reg ister is FFH. Writing
00H to DAC register generates stable low output.

38h (w) P42 P41 P40

39h (r/w) P56 P55 P54 P53 P52 P51 P50

Revision 0.9 - 8 - 2000/11/17