MYSON MTV212MV64, MTV212MS64, MTV212MN64 Datasheet

MYSON

8051 core, 12MHz operating frequency.
1024-byte RAM, 64K-byte
Maximum 14 channels of 9V open-drain PWM DAC.

Watchdog timer with prog

FIFOs), the other one is Interrupt endpoint (8-byte IN FIFO).

applications. It includes an 8051 CPU core, 1024-byte SRAM, SYNC process or, 14 built-in PWM DACs,

MTV212M64

TECHNOLOGY

(Rev. 1.2)

8051 Embedded Monitor Controller

MTP Type

FEATURES

•

•

•

• Maximum 32 bi-directional I/O pins.

• SYNC processor for composite separation/insertion, H/V polarity/frequency check, polarity adjustment

and programmable clamp pulse output.

• Built-in self-test pattern generator with three free-running timings.

• Built-in low power reset circuit.

• Compliant with VESA DDC1/2B/2Bi/2B+ standard.

• Dual slave IIC addresses.

• Single master IIC interface for internal device communication.

• 4-channel 6-bit ADC.

•

• Compliant with Low Speed USB Spec.1.1 including 2 Endpoints: one is Control endp oint (8-byte IN & 8-

byte OUT

• Built-in 3.3V regulator for USB Interface.

• 40-pin DIP, 42-pin SDIP or 44-pin PLCC package.

program Flash-ROM.•

rammable interval.

GENERAL DESCRIPTIONS

The MTV212M micro-controller is an 8051 CPU core embedded device specially tailored to Monitor
VESA DDC interface, 4-channel A/D converter, Low Speed USB Interface and a 64K-byte internal program

Flash-ROM.

BL OCK DIAGRAM

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.

Revision 1.2 - 1 - 2000/07/04

MYSON

Auxiliary RAM (AUXRAM)

MTV212M64

TECHNOLOGY

(Rev. 1.2)

DEVICE SUMMARY

The MTV212M is the MTP (Multi-Time Programming) type device for all of MTV212A mask ROM derivatives,
the memory size and package differences please see the table below:

Part Numb er USB ROM RAM Pack ag e

MTV212A16 No 16K 256 PDIP40, SDIP42, PLCC44
MTV212A24 No 24K 512 PDIP40, SDIP42, PLCC44
MTV212A32 No 32K 512 PDIP40, SDIP42, PLCC44
MTV212A32U Yes 32K 768 PDIP40, SDIP42, PLCC44
MTV212A48U Yes 48K 768 PDIP40, SDIP42, PLCC44
MTV212A64U Yes 64K 1024 PDIP40, SDIP42, PLCC44

The use of
selection is defined as the table below:

Part Numb er RAM Xbnk2 Xbnk1 Xbnk 0

MTV212A16 256 - - ­ MTV212A24 512 0 0 0
0 0 1
MTV212A32 512 0 0 0
0 0 1
MTV212A32U 768 0 0 0

MTV212A48U 768 0 0 0

MTV212A64U 1024 0 0 0

is limited for targeted mask ROM, the allowable XBANK (35h) bank

0 0 1
0 1 0
0 1 1

0 0 1
0 1 0
0 1 1

0 0 1
0 1 0
0 1 1
1 0 0
1 0 1

Remark:

The major pin connection differences between USB (MTV212M64U) and non-USB (MTV212M64) types are
pin# 4, #5 and #6 for SDIP42 and PLCC44. The pin name of USB device is V33CAP(#4), VM(#5) and
VP(#6), while NC (No Connection) for non-USB device.

Revision 1.2 - 2 - 2000/07/04

MYSON

DA2/P5.2

DA1/P5.1

DA0/P5.0

VSS

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P2.2/AD2

P3.2/INT0

DA2/P5.2

DA1/P5.1

DA0/P5.0

VSS

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P2.2/AD2

P3.2/INT0

Non-USB

DA2/P5.2

DA1/P5.1

DA0/P5.0

VSS

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P2.2/AD2

P3.2/INT0

V33CAP/NC

P1.624P1.7

P2.1/AD1

P1.5

P2.0/AD0

HSDA/P3.1/Txd
P1.1

P3.2/INT0

P1.2

P1.3

P1.4

23222120282726

25

DP/NC
6543214443424140

DM/NC

V33CAP/NC
DA0/P5.0

DA1/P5.1

DA2/P5.2
VSYNC

HSYNC

DA3/P5.3

DA4/P5.4

DA5/P5.5

19

18

VSS

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P2.2/AD2

P2.3/AD3

MTV212M64

TECHNOLOGY

PIN CONNECTION

2
3
4

RST

5

VDD

6
7

X2

8

X1

P1.0
P1.1

P1.2
P1.3
P1.4
P1.5
P1.6

9
10
11
12
13
14
15
16
17
18
19
20

MTV212M

40 Pin

PDIP #1

Non-USB

401

VSYNC

39

HSYNC

38

DA3/P5.3

37

DA4/P5.4

36

DA5/P5.5

35

DA8/HALFH

34

DA9/HALFV

33

HBLANK/P4.1

32

VBLANK/P4.0

31

DA7/HCLAMP

30

DA6/P5.6

29

P2.7/DA13

28

P2.6/DA12

27

P2.5/DA11

26

P2.4/DA10

25

HSCL/P3.0/Rxd

24

HSDA/P3.1/Txd

23

P2.0/AD0

22

P2.1/AD1

21

P1.7

V33CAP

DM

DP

RST

VDD

X2
X1

P1.0
P1.1

P1.2
P1.3

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

MTV212M

40 Pin

PDIP #2

USB

(Rev. 1.2)

401

VSYNC

39

HSYNC

38

DA3/P5.3

37

DA4/P5.4

36

DA5/P5.5

35

DA8/HALFH

34

DA9/HALFV

33

HBLANK/P4.1

32

VBLANK/P4.0

31

DA7/HCLAMP

30

DA6/P5.6

29

P2.4/DA10

28

HSCL/P3.0/Rxd

27

HSDA/P3.1/Txd

26

P2.0/AD0

25

P2.1/AD1

24

P1.7

23

P1.6

22

P1.5

21

P1.4

DM/NC

DP/NC

RST

VDD

X2
X1

P1.0
P1.1

P1.2
P1.3
P1.4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

MTV212M

42 Pin

SDIP

USB

or

VSYNC

42

HSYNC

41
40

DA3/P5.3

39

DA4/P5.4

38

DA5/P5.5

37

DA8/HALFH

36

DA9/HALFV

35

HBLANK/P4.1

34

VBLANK/P4.0

33

DA7/HCLAMP

32

DA6/P5.6

31

P2.6/DA12

30

P2.5/DA11

29

P2.4/DA10

28

HSCL/P3.0/Rxd

27

HSDA/P3.1/Txd

26

P2.0/AD0

25

P2.1/AD1

24

P1.7

23

P1.6

2221

P1.5

RST

VDD

X2
X1

P1.0

7
8
9
10
11
12
13
14
15
16
17

MTV212M

44 Pin

PLCC

USB

or

Non-USB

39

DA8/HALFH

38

DA9/HALFV

37

HBLANK/P4.1

36

VBLANK/P4.0

35

DA7/HCLAMP

34

DA6/P5.6

33

P2.7/DA13

32

P2.6/DA12

31

P2.5/DA11

30

P2.4/DA10

29

HSCL/P3.0/Rxd

Revision 1.2 - 3 - 2000/07/04

MYSON

PWM DAC output / Hsync clamp pulse output (open drain).

PWM DAC output /
PWM DAC output / Hsync half freq. output (open drain).

MTV212M64

TECHNOLOGY

PIN DESCRIPTION

Name Type

DA2/P5.2
DA1/P5.1
DA0/P5.0
V33CAP/NC
DM/NC
DP/NC
RST
VDD
P2.3/AD3
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P2.2/AD2
P1.0
P1.1
P3.2/INT0
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.1/AD1
P2.0/AD0
HSDA/P3.1/Txd
HSCL/P3.0/Rxd
P2.4/DA10
P2.5/DA11
P2.6/DA12
P2.7/DA13
DA6/P5.6
DA7/HCLAMP
VBL ANK /P4.0
HBLA NK /P4.1
DA9/HALFV
DA8/HALFH
DA5/P5.5
DA4/P5.4
DA3/P5.3
HSYNC
VSYNC

I/O 1 1 1 1 PWM DAC output / General purpose I/O (open drain).
I/O 2 2 2 2 PWM DAC output / General purpose I/O (open drain).
I/O 3 3 3 3 PWM DAC output / General purpose I/O (open drain).
I/O - 4 4 4 3.3V Regulator Capacitor connection or N C.
I/O - 5 5 5 USB DM or NC.
I/O - 6 6 6 USB DP or NC.

I/O - - - 9 General purpose I/O / ADC Input.

I/O 9 12 12 13 Master IIC data / General purpose I/O / T 0.
I/O 10 13 13 14 Master IIC clock / General purpose I/O / T1.

I/O 12 15 15 16 General purpose I/O / ADC Input.
I/O 13 16 16 17 General purpose I/O.
I/O 14 17 17 18 General purpose I/O.

I/O 16 19 19 20 General purpose I/O.
I/O 17 20 20 21 General purpose I/O.
I/O 18 21 21 22 General purpose I/O.
I/O 19 22 22 23 General purpose I/O.
I/O 20 23 23 24 General purpose I/O.
I/O 21 24 24 25 General purpose I/O.
I/O 22 25 25 26 General purpose I/O / ADC Input.
I/O 23 26 26 27 General purpose I/O / ADC Input.
I/O 24 27 27 28 Slave IIC data / General purpose I/O / Txd.
I/O 25 28 28 29 Slave IIC clock / General purpose I/O / Rxd.
I/O 26 29 29 30 General purpose I/O / PWM DAC output (open drain).
I/O 27 - 30 31 General purpose I/O / PWM DAC output (open drain).
I/O 28 - 31 32 General purpose I/O / PWM DAC output (open drain).
I/O 29 - - 33 General purpose I/O / PWM DAC output (open drain).
I/O 30 30 32 34 PWM DAC output / General purpose I/O (open drain).

I/O 36 36 38 40 PWM DAC output / General purpose I/O (open drain).

(Rev. 1.2)

Pin#

40 40 42 44

I 4 7 7 7 Active high reset.

- 5 8 8 8 Positive Power Supply.

- 6 9 9 10 Ground.

O 7 10 10 11 Oscillator output.

I 8 11 11 12 Oscillator input.

O 11 14 14 15 Self-test video output / General purpose Output.

I 15 18 18 19 General purpose Input / INT0.

O 31 31 33 35
O 32 32 34 36 Vertical blank / General purpose Output.
O 33 33 35 37 Horizontal blank / General purpose Output.
O 34 34 36 38
O 35 35 37 39

O 37 37 39 41 PWM DAC output / General purpose I/O (open drain).
O 38 38 40 42 PWM DAC output / General purpose I/O (open drain).

I 39 39 41 43 Horizontal SYNC or Composite SYNC Input.
I 40 40 42 44 Vertical SYNC input.

Description

Vsync half freq. output (open drain).

Revision 1.2 - 4 - 2000/07/04

MYSON

FUNCTIONAL DESCRIPTIONS

2. Memory Allo catio n

used for monitor control or PWM DAC. Program can initialize

2.4 Auxiliary RAM (AUXRAM)
divided into six banks, selected by XBANK register. Program can initialize Ri value and use "MOVX"

MTV212M64

TECHNOLOGY

1. 8051 CPU Core

MTV212M includes all 8051 functions with the following exceptions:

1.1 PSEN, ALE, RD and WR pins are disabled. The external RAM access is restr icted to XFRs within the
MTV212M.

1.2 Port0, port3.3, port3.6 and port3.7 are not general-purpose I/O ports. They are dedicated to monitor
special application.

1.3 INT1 input pin is not provided, it is connected to special interrupt sources.

1.4 Port2 are shared with special function pins.

In addition, there are 2 timers, 5 interrupt sources and serial interface compatible with the standard 8051.

(Rev. 1.2)

Note: All registers listed in this document reside in external RAM area (XFR). For internal RAM memory map
please refer to 8051 spec.

2.1 Internal Special Function Registers (SFR)

The SFR is a group of registers that are the same as standard 8051.

2.2 Internal RAM

There are total 256 bytes internal RAM in MTV212M, same as standard 8052.

2.3 External Special Function Registers (XFR)

The XFR is a group of registers allocated in the 8051 external RAM area 00h - 7Fh. Most of the registers are

Ri value and use "MOVX" instruction to access

these registers.

There are total 768 bytes auxiliary RAM allocated in the 8051 external RAM area 80h - FFh. The AUXRAM is
instruction to access the AUXRAM.

FFh

Internal RAM

Accessible by

addressing only

MOV A,@Ri

instruction)

80h
7Fh

Internal RAM

Accessible by

direct and indirect

addressing

indirect

(Using

SFR

Accessible by

direct addressing

00h

Revision 1.2 - 5 - 2000/07/04

MYSON

PWMF

MTV212M64

(Rev. 1.2)

AUXRAM

Accessible by

indirect external

RAM addressing

(XBANK=5)(Using

MOVX A,@Ri

instruction)

FFh

80h
7Fh

00h

AUXRAM

Accessible by

indirect external

RAM addressing

(XBANK=0)(Using

MOVX A,@Ri

instruction)

Accessible by

indirect external

RAM addressing

MOVX A,@Ri

instruction

XFR

(Using

TECHNOLOGY

AUXRAM

Accessible by

indirect external

RAM addressing

(XBANK=1)(Using

MOVX A,@Ri

instruction)

AUXRAM

Accessible by

indirect external

RAM addressing

(XBANK=2)(Using

MOVX A,@Ri

instruction)

AUXRAM

Accessible by

indirect external

RAM addressing

(XBANK=3)(Using

MOVX A,@Ri

instruction)

AUXRAM

Accessible by

indirect external

RAM addressing

(XBANK=4)(Using

MOVX A,@Ri

instruction)

3. Chip Configu ratio n

The Chip Configuration registers define the chip pins function, as well as the functional blocks' connection,
configuration and frequency.

Reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PADMOD
PADMOD
PADMOD

OPTION
OPTION

XBANK

30h (w) DA13E DA12E DA11E DA10E AD3E AD2E AD1E AD0E
31h (w) P56E P55E P54E P53E P52E P51E P50E
32h (w) HIICE IIICE HLFVE HLFHE HCLPE P42E P41E P40E
33h (w)

DIV253 FclkE IICpass ENSCL Msel MIICF1 MIICF0

34h (w) SlvAbs1 SlvAbs0

35h (r/w) Xbnk2 Xbnk1 Xbnk0

PADMOD (w) : Pad mode control registers. (All are "0" in Chip Reset)

DA13E = 1 → pin “P2.7/DA13” is DA13.

= 0 → pin “P2.7/DA13” is P2.7.

DA12E = 1 → pin “P2.6/DA12” is DA12.

= 0 → pin “P2.6/DA12” is P2.6.

DA11E = 1 → pin “P2.5/DA11” is DA11.

= 0 → pin “P2.5/DA11” is P2.5.

DA10E = 1 → pin “P2.4/DA10” is DA10.

= 0 → pin “P2.4/DA10” is P2.4.

AD3E = 1 → pin “P2.3/AD3” is AD3.

= 0 → pin “P2.3/AD3” is P2.3.

AD2E = 1 → pin “P2.2/AD2” is AD2.

= 0 → pin “P2.2/AD2” is P2.2.

AD1E = 1 → pin “P2.1/AD1” is AD1.

= 0 → pin “P2.1/AD1” is P2.1.

AD0E = 1 → pin “P2.0/AD0” is AD0.

= 0 → pin “P2.0/AD0” is P2.0.

P56E = 1 → pin “DA6/P5.6” is P5.6.

= 0 → pin “DA6/P5.6” is DA6.

P55E = 1 → pin “DA5/P5.5” is P5.5.

= 0 → pin “DA5/P5.5” is DA5.

Revision 1.2 - 6 - 2000/07/04

MYSON

is HSYNC half frequency output.

is HSYNC clamp pulse output.

Auxiliary RAM bank switch.

MTV212M64

TECHNOLOGY

P54E = 1 → pin “DA4/P5.4” is P5.4.

= 0 → pin “DA4/P5.4” is DA4.

P53E = 1 → pin “DA3/P5.3” is P5.3.

= 0 → pin “DA3/P5.3” is DA3.

P52E = 1 → pin “DA2/P5.2” is P5.2.

= 0 → pin “DA2/P5.2” is DA2.

P51E = 1 → pin “DA1/P5.1” is P5.1.

= 0 → pin “DA1/P5.1” is DA1.

P50E = 1 → pin “DA0/P5.0” is P5.0.

= 0 → pin “DA0/P5.0” is DA0.

HIICE = 1 → pin “HSCL/P3.0/Rxd” is HSCL; pin “HSDA/P3.1/Txd” is HSDA.

= 0 → pin “HSCL/P3.0/Rxd” is P3.0/Rxd; pin “HSDA/P3.1/Txd” is P3.1/Txd.

IIICE = 1 → pin “ISDA/P3.4/T0” is ISDA; pin “ISCL/P3.5/T1” is ISCL.

= 0 → pin “ISDA/P3.4/T0” is P3.4/T0; pin “ISCL/P3.5/T1” is P3.5/T1.

HLFVE = 1 → pin “DA9/HALFV” is VSYNC half frequency output.

= 0 → pin “DA9/HALFV” is DA9.

HLFHE = 1 → pin “DA8/HALFH”

= 0 → pin “DA8/HALFH” is DA8.

HCLPE = 1 → pin “DA7/HCLAMP”

= 0 → pin “DA7/HCLAMP” is DA7.

P42E = 1 → pin “STOUT/P4.2” is P4.2.

= 0 → pin “STOUT/P4.2” is STOUT.

P41E = 1 → pin “HBLANK/P4.1” is P4.1.

= 0 → pin “HBLANK/P4.1” is HBLANK.

P40E = 1 → pin “VBLANK/P4.0” is P4.0.

= 0 → pin “VBLANK/P4.0” is VBLANK.

(Rev. 1.2)

OPTION (w) : Chip option configuration (All are "0" in Chip Reset).

PWMF = 1 → select 94KHz PWM frequency.

= 0 → select 47KHz PWM frequency.

DIV253 = 1 → PW M pulse width is 253 step r esolu tio n.

= 0 → PWM pulse width is 256 step resolution.
FclkE = 1 → Double CPU clock freq.
IICpass = 1 → HSCL/HSDA pin bypass to ISCL/ISDA pin in DDC2 mode.

= 0 → Separate Master and Slave IIC block.
ENSCL = 1 → Enable slave IIC block to hold HSCL pin low while MTV212M can't catch-up the

external master's speed.

Msel = 1 → Master IIC block connect to HSCL/HSDA pins.

= 0 → Master IIC block connect to ISCL/ISDA pins.
MIICF1,MIICF0 = 1,1 → select 400KHz Master IIC frequency.

= 1,0 → select 200KHz Master IIC frequency.
= 0,1 → select 50KHz Master IIC frequency.
= 0,0 → select 100KHz Master IIC frequency.

SlvAbs1,SlvAbs0 : Slave IIC block A's slave address length.

= 1,0 → 5-bits slave address.
= 0,1 → 6-bits slave address.
= 0,0 → 7-bits slave address.

XBANK (r/w) :

Xbnk[2:0] = 0 → Select AUXRAM bank 0.

= 1 → Select AUXRAM bank 1.
= 2 → Select AUXRAM bank 2.
= 3 → Select AUXRAM bank 3.

Revision 1.2 - 7 - 2000/07/04

MYSON

Each PWM DAC converter's output pulse width is controlled by an 8-bit register in XFR. The frequency of

Pulse width of PWM DAC 0
Pulse width of PWM DAC 1
Pulse width of PWM DAC 2
Pulse width of PWM DAC 3
Pulse width of PWM DAC 4
Pulse width of PWM DAC 5
Pulse width of PWM DAC 6
Pulse width of PWM DAC 7
Pulse width of PWM DAC 8

Pulse width of PWM DAC 9
Pulse width of PWM DAC 10
Pulse width of PWM DAC 11
Pulse width of PWM DAC 12
Pulse width of PWM DAC 13

* All of PWM DAC converters are centered with value 80h after power on.

inputs presence check, frequency counting, polarity detection and control, as well as the protection of
function block treat any pulse shorter than one OSC period as noise.

MTV212M64

TECHNOLOGY

= 4 → Select AUXRAM bank 4.
= 5 → Select AUXRAM bank 5.

4. Extra I/O

The extra I/O is a group of I/O pins located in XFR area. Port4 is output mode onl y. Port5 can be used as
both output and input, because Port5's pin is open drain type, user must write Port5's corresponding bit to
"1" in input mode.

Reg name addr bit7 bit6 bit5 bit4 bit3 bit 2 bit1 bit0

PORT4
PORT5

PORT4 (w) : Port 4 data output value.
PORT5 (r/w) : Port 5 data input/output value.

5. PWM DAC

38h (w) P42 P41 P40

39h (r/w) P56 P55 P54 P53 P52 P51 P50

(Rev. 1.2)

PWM clk is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is 253
or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high
output. If DIV253=0, the output will pulse low at least once even if the DAC register's content is FFH. Writing
00H to DAC register generates stable low output.

Reg name addr bit7 bit6 bit5 bit4 bit3 bit 2 bit1 bit0

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8

DA9
DA10
DA11
DA12
DA13

DA0-13 (r/w) : The output pulse width control for DA0-13.

20h (r/w)
21h (r/w)
22h (r/w)
23h (r/w)
24h (r/w)
25h (r/w)
26h (r/w)
27h (r/w)
28h (r/w)
29h (r/w)
2Ah (r/w)

2Bh (r/w)
2Ch (r/w)
2Dh (r/w)

6. H/V SYNC Processing

The H/V SYNC processing block performs the functions of composite signal separation /insertion, SYNC
VBLANK output while VSYNC speed up in high DDC communication clock rate. The present and frequency

Revision 1.2 - 8 - 2000/07/04

MYSON

6.2 H/V Frequency Counter

VSYNC/CVSYNC is present or continuously updated when VSYNC/CVS YNC is non-present. The 12 bits

Hself

Hpol

CVpre

Vbpl

VSYNC

Vpre

Vfreq

Vpol

VBLANK

Vself

HSYNC

CVSYNC

Hpre

Hfreq

Hbpl

HBLANK

XOR

MTV212M64

TECHNOLOGY

Digital Filter

Digital Filter

Present

Check

Polarity Check &

Freq. Count

Polarity Check &

Sync Seperator

Present Check &

Freq. Count

(Rev. 1.2)

XOR

XOR

Present

Check

Composite

Pulse Insert

XOR

H/V SYNC Processor Block Diagram

6.1 Composite SYNC separation/insertion
The MTV212M continuously monitors the input HSYNC, if the vertical SYNC pulse can be extracted from the
input, a CVpre flag is set and user can select the extracted "CVSYNC" for the source of polarity check,
frequency count, and VBLANK output. The CVSYNC will have 8us delay compared to the original signal.
The MTV212M can also insert pulse to HBLANK output during com posite VSYNC’s active time. The insert
pulse’s width is 1/8 HSYNC period and the insertion frequency can adapt to original HSYNC.

MTV212M can discriminate HSYNC/VSYNC frequency and saves the information in XFRs. The 14 bits
Hcounter counts the time of 64xHSYNC period, then load the result into the HCNTH/HCNTL latch. The
output value will be [(128000000/H-Freq) - 1], updated once per VSYNC/CVSYNC period when

Vcounter counts the time between two VSYNC pulses, then load the result into the VCNTH/VCNTL latch.
The output value will be (62500/V-Freq), updated every VSYNC/CVSYNC perio d. An extra overflow bit
indicates the condition of H/V counter overflow. The VFchg/HFchg interrupt is set when VCNT/HCNT value
changes or overflow. Table 4.2.1 and table 4.2.2 shows the HCNT/VCNT value under the operations of
12MHz.

Revision 1.2 - 9 - 2000/07/04