MYSON MTV212AN32, MTV212AS32, MTV212AV32 Datasheet

MYSON

8051 core, 12MHz operating frequency.
512-byte RAM, 32K-byte
Maximum 14 channels of 5V open-drain PWM DAC.

MTV212A32 micro-controller is an 8051 CPU core embedded device specially tailored to Monitor

VESA DDC interface, 3-channel A/D converter and a 32K-byte internal program Mask-ROM.

ISCL

MTV212A32

TECHNOLOGY

(Rev. 1.2)

8051 Embedded Monitor Controller

Mask ROM Type

FEATURES

•

•

•

• Maximum 31 bi-directional I/O pins.

• SYNC processor for composite separation/insertion, H/V polarity/frequency check, polarity adjustment

and programmable clamp pulse output.

• Built-in self-test pattern generator with four free-running timings.

• Built-in low power reset circuit.

• Compliant with VESA DDC1/2B/2Bi/2B+ standard.

• Dual slave IIC addresses.

• Single master IIC interface for internal device communication.

• 3-channel 6-bit ADC.

• Watchdog timer with programmable interval.

• 40-pin DIP, 42-pin SDIP or 44-pin PLCC package.

GENERAL DESCRIPTIONS

program Mask-ROM.

The
applications. It includes an 8051 CPU core, 512-byte SRAM, SYNC processor, 14 built-in PWM DACs,

BL OCK DIAGRAM

P1.0-7
P2.0-2,P2.4-7
P3.0-2
P3.4-5
RST
X1
X2

8051

CORE

P0.0-7
RD
WR
ALE
INT1

P0.0-7
RD
WR
ALE
INT1

AD0-2

XFR

ADC

H/VSYNC
CONTROL

STOUT
HBLANK
VBLANK
HSYNC
VSYNC
HCLAMP
HALFV
HALFH

14 CHANNEL

PWM DAC

DDC & IIC

INTERFACE

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.

ISDA
HSCL
HSDA

Revision 1.2 - 1 - 2000/07/04

MYSON

MTV212A32

TECHNOLOGY

(Rev. 1.2)

DEVICE SUMMARY

The MTV212A32 is one of the MTV212 family device. For other family devices information, please see the
table below:

Part Numb er USB ROM RAM Pack ag e

MTV212A16 No 16K 256 PDIP40, SDIP42, PLCC44
MTV212A24 No 24K 512 PDIP40, SDIP42, PLCC44
MTV212A32 No 32K 512 PDIP40, SDIP42, PLCC44
MTV212A32U Yes 32K 768 PDIP40, SDIP42, PLCC44
MTV212A48U Yes 48K 768 PDIP40, SDIP42, PLCC44
MTV212A64U Yes 64K 1024 PDIP40, SDIP42, PLCC44

The usage of Auxiliary RAM (AUXRAM) is limited for targeted mask ROM, the allowable XBANK (35h) bank
selection is defined as the table below:

Part Numb er RAM Xbnk2 Xbnk1 Xbnk 0

MTV212A16 256 - - ­ MTV212A24 512 0 0 0
0 0 1
MTV212A32 512 0 0 0
0 0 1
MTV212A32U 768 0 0 0

0 0 1
0 1 0
0 1 1

MTV212A48U 768 0 0 0

0 0 1
0 1 0
0 1 1

MTV212A64U 1024 0 0 0

0 0 1
0 1 0
0 1 1
1 0 0
1 0 1

Revision 1.2 - 2 - 2000/07/04

MYSON

DA2/P5.2

DA1/P5.1

DA0/P5.0

VSS

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P2.2/AD2

P3.2/INT0

DA2/P5.2

DA1/P5.1

DA0/P5.0

VSS

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P2.2/AD2

P3.2/INT0

P1.624P1.7

P2.1/AD1

P1.5

P2.0/AD0

HSDA/P3.1/Txd
P1.1

P3.2/INT0

P1.2

P1.3

P1.4

23222120282726

25

NC

6543214443424140

NC

NC

DA0/P5.0

DA1/P5.1

DA2/P5.2
VSYNC

HSYNC

DA3/P5.3

DA4/P5.4

DA5/P5.5

19

18

VSS

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P2.2/AD2

MTV212A32

TECHNOLOGY

PIN CONNECTION

2
3
4

RST

5

VDD

6
7

X2

8

X1

P1.0
P1.1

P1.2
P1.3
P1.4
P1.5
P1.6

MTV212A32

9

40 Pin

10
11
12
13
14
15
16
17
18
19
20

PDIP

401

VSYNC

39

HSYNC

38

DA3/P5.3

37

DA4/P5.4

36

DA5/P5.5

35

DA8/HALFH

34

DA9/HALFV

33

HBLANK/P4.1

32

VBLANK/P4.0

31

DA7/HCLAMP

30

DA6/P5.6

29

P2.7/DA13

28

P2.6/DA12

27

P2.5/DA11

26

P2.4/DA10

25

HSCL/P3.0/Rxd

24

HSDA/P3.1/Txd

23

P2.0/AD0

22

P2.1/AD1

21

P1.7

(Rev. 1.2)

NC
NC
NC

RST

VDD

X2
X1

P1.0
P1.1

P1.2
P1.3
P1.4

1
2
3
4
5
6
7
8

MTV212A32

9

42 Pin

10
11
12
13
14
15
16
17
18
19
20

SDIP

VSYNC

42

HSYNC

41
40

DA3/P5.3

39

DA4/P5.4

38

DA5/P5.5

37

DA8/HALFH

36

DA9/HALFV

35

HBLANK/P4.1

34

VBLANK/P4.0

33

DA7/HCLAMP

32

DA6/P5.6

31

P2.6/DA12

30

P2.5/DA11

29

P2.4/DA10

28

HSCL/P3.0/Rxd

27

HSDA/P3.1/Txd

26

P2.0/AD0

25

P2.1/AD1

24

P1.7

23

P1.6

2221

P1.5

RST

VDD

NC

X2
X1

P1.0

7
8
9
10
11
12
13
14
15
16
17

MTV212A32

44 Pin

PLCC

39

DA8/HALFH

38

DA9/HALFV

37

HBLANK/P4.1

36

VBLANK/P4.0

35

DA7/HCLAMP

34

DA6/P5.6

33

P2.7/DA13

32

P2.6/DA12

31

P2.5/DA11

30

P2.4/DA10

29

HSCL/P3.0/Rxd

Revision 1.2 - 3 - 2000/07/04

MYSON

PWM DAC output (5V open drain) / General purpose I/O (5V open drain).
PWM DAC output (5V open drain) / General purpose I/O (5V open drain).
PWM DAC output (5V open drain) / General purpose I/O (5V open drain).

Slave IIC data (5V open drain) / General purpose I/O (8051 standard) / Txd (8051
Slave IIC clock (5V open drain) / General purpose I/O (8051 standard) / Rxd (8051

PWM DAC output (CMOS) /

PWM DAC output (5V open drain) /
PWM DAC output (5V open drain) /

MTV212A32

TECHNOLOGY

PIN DESCRIPTION

Name Type # Description
DA2/P5.2
DA1/P5.1
DA0/P5.0
RST
VDD
VSS
X2
X1
ISDA/P3.4/T0

ISCL/P3.5/T1
STOUT/P4.2

P2.2/AD2
P1.0
P1.1
P3.2/INT0
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.1/AD1
P2.0/AD0
HSDA/P3.1/Txd

HSCL/P3.0/Rxd
P2.4/DA10
P2.5/DA11
P2.6/DA12
P2.7/DA13
DA6/P5.6
DA7/HCLAMP

VBL ANK /P4.0
HBLA NK /P4.1
DA9/HALFV
DA8/HALFH
DA5/P5.5

DA4/P5.4
DA3/P5.3
HSYNC

VSYNC

I/O 1
I/O 2
I/O 3

I 4

- 5

- 6

O 7

I 8

I/O 9
I/O 10

O 11
I/O 12
I/O 13
I/O 14

I 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24

I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30

O 31
O 32
O 33
O 34
O 35

I/O 36
I/O 37
I/O 38

I 39

I 40

Active high reset.
Positive Power Supply.
Ground.
Oscillator output.
Oscillator input.
Master IIC data (5V open drain) / General purpose I/O (8051 standard) / T0 (8051

standard).
Master IIC clock (5V open drain) / General purpose I/O (8051 standard) / T1 (8051
standard).
Self-test video output (CMOS) / General purpose Output (CMOS).

General purpose I/O (Mask option as CMOS output or 8051 standard) / ADC Input.
General purpose I/O (Mask option as CMOS output or 8051 standard).
General purpose I/O (Mask option as CMOS output or 8051 standard).
General purpose Input / INT0.
General purpose I/O (Mask option as CMOS output or 8051 standard).
General purpose I/O (Mask option as CMOS output or 8051 standard).
General purpose I/O (Mask option as CMOS output or 8051 standard).
General purpose I/O (Mask option as CMOS output or 8051 standard).
General purpose I/O (Mask option as CMOS output or 8051 standard).
General purpose I/O (Mask option as CMOS output or 8051 standard).
General purpose I/O (Mask option as CMOS output or 8051 standard) / ADC Input.
General purpose I/O (Mask option as CMOS output or 8051 standard) / ADC Input.

standard).
standard).

General purpose I/O (Mask option as CMOS output or 8051 standard) / PWM DAC
output (CMOS).
General purpose I/O (Mask option as CMOS output or 8051 standard) / PWM DAC
output (CMOS).
General purpose I/O (Mask option as CMOS output or 8051 standard) / PWM DAC
output (CMOS).
General purpose I/O (Mask option as CMOS output or 8051 standard) / PWM DAC
output (CMOS).
PWM DAC output (CMOS) / General purpose I/O (Mask option as CMOS output or
open drain I/O).

Hsync clamp pulse output (CMOS).
Vertical blank (CMOS) / General purpose Output (CMOS).
Horizontal blank (CMOS) / General purpose Output (CMOS).

vsync half freq. output (5V open drain).

PWM DAC output (CMOS) / General purpose I/O (Mask option as CMOS output or
open drain I/O).
PWM DAC output (CMOS) / General purpose I/O (Mask option as CMOS output or
open drain I/O).
PWM DAC output (CMOS) / General purpose I/O (Mask option as CMOS output or
open drain I/O).
Horizontal SYNC or Composite SYNC Input.

Vertical SYNC input.

hsync half freq. output (5V open drain).

(Rev. 1.2)

Revision 1.2 - 4 - 2000/07/04

MYSON

FUNCTIONAL DESCRIPTIONS

2. Memory Allo catio n

2.4 Auxiliary RAM (AUXRAM)
divided into two banks, selected by XBANK register. Program can initialize

MTV212A32

TECHNOLOGY

(Rev. 1.2)

PIN CONFIGURATION

A “CMOS output pin” means it can sink and drive at least 4mA current. It’s not recommended to use such pin
as input fuction.
A “5V open drain pin” means it can sink at least 4mA current but only drive 10~20uA to VDD. It can be used
as input or output function and need an external pull up resistor.
A “8051 standard pin” is a pseudo open drain pin. It can sink at least 4mA current when output low level, and
drive at least 4mA current for 160nS when output transit from low to high, then keep drive 1 00uA to maintain
the pin at high level. It can be used as input or output function. It need an external pull up resistor when drive
heavy load device.

1. 8051 CPU Core

MTV212A32 includes all 8051 functions with the following exceptions:

1.1 PSEN, ALE, RD and WR pins are disabled. The external RAM access is restr icted to XFRs within the
MTV212A32.

1.2 Port0, port3.3, port3.6 and port3.7 are not general-purpose I/O ports. They are dedicated to monitor
special application.

1.3 INT1 input pin is not provided, it is connected to special interrupt sources.

1.4 Port2 are shared with special function pins.

In addition, there are 2 timers, 5 interrupt sources and serial interface compatible with the standard 8051.

Note: All registers listed in this document reside in external RAM area (XFR). For internal RAM memory map
please refer to 8051 spec.

2.1 Internal Special Function Registers (SFR)

The SFR is a group of registers that are the same as standard 8051.

2.2 Internal RAM

There are total 256 bytes internal RAM in MTV212A32, same as standard 8052.

2.3 External Special Function Registers (XFR)

The XFR is a group of registers allocated in the 8051 external RAM area 00h - 7Fh. Most of the registers are
used for monitor control or PWM DAC. Program can initialize Ri value and use "MOVX" instruction to access
these registers.

There are total 256 bytes auxiliary RAM allocated in the 8051 external RAM area 80h - FFh. The AUXRAM is
instruction to access the AUXRAM.

Ri value and use "MOVX"

Revision 1.2 - 5 - 2000/07/04

MYSON

PWMF

MTV212A32

(Rev. 1.2)

AUXRAM

Accessible by

indirect external

RAM addressing

(XBANK=1)(Using

MOVX A,@Ri

instruction)

FFh

Internal RAM

Accessible by

addressing only

MOV A,@Ri

instruction)

80h
7Fh

Internal RAM

Accessible by

direct and indirect

addressing

00h

TECHNOLOGY

SFR

indirect

(Using

Accessible by

direct addressing

FFh

80h
7Fh

00h

AUXRAM

Accessible by

indirect external

RAM addressing

(XBANK=0)(Using

MOVX A,@Ri

instruction)

Accessible by

indirect external

RAM addressing

MOVX A,@Ri

instruction

XFR

(Using

3. Chip Configu ratio n

The Chip Configuration registers define the chip pins function, as well as the functional blocks' connection,
configuration and frequency.

Reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PADMOD
PADMOD
PADMOD

OPTION
OPTION

XBANK

30h (w) DA13E DA12E DA11E DA10E AD3E AD2E AD1E AD0E
31h (w) P56E P55E P54E P53E P52E P51E P50E
32h (w) HIICE IIICE HLFVE HLFHE HCLPE P42E P41E P40E
33h (w)

DIV253 FclkE IICpass ENSCL Msel MIICF1 MIICF0

34h (w) SlvAbs1 SlvAbs0

35h (r/w) Xbnk2 Xbnk1 Xbnk0

PADMOD (w) : Pad mode control registers. (All are "0" in Chip Reset)

DA13E = 1 → pin “P2.7/DA13” is DA13.

= 0 → pin “P2.7/DA13” is P2.7.

DA12E = 1 → pin “P2.6/DA12” is DA12.

= 0 → pin “P2.6/DA12” is P2.6.

DA11E = 1 → pin “P2.5/DA11” is DA11.

= 0 → pin “P2.5/DA11” is P2.5.

DA10E = 1 → pin “P2.4/DA10” is DA10.

= 0 → pin “P2.4/DA10” is P2.4.

AD3E = 1 → no action

= 0 → no action

AD2E = 1 → pin “P2.2/AD2” is AD2.

= 0 → pin “P2.2/AD2” is P2.2.

AD1E = 1 → pin “P2.1/AD1” is AD1.

= 0 → pin “P2.1/AD1” is P2.1.

AD0E = 1 → pin “P2.0/AD0” is AD0.

= 0 → pin “P2.0/AD0” is P2.0.

P56E = 1 → pin “DA6/P5.6” is P5.6.

= 0 → pin “DA6/P5.6” is DA6.

P55E = 1 → pin “DA5/P5.5” is P5.5.

= 0 → pin “DA5/P5.5” is DA5.

Revision 1.2 - 6 - 2000/07/04

MYSON

is HSYNC half frequency output.

is HSYNC clamp pulse output.

Auxiliary RAM bank switch.

MTV212A32

TECHNOLOGY

P54E = 1 → pin “DA4/P5.4” is P5.4.

= 0 → pin “DA4/P5.4” is DA4.

P53E = 1 → pin “DA3/P5.3” is P5.3.

= 0 → pin “DA3/P5.3” is DA3.

P52E = 1 → pin “DA2/P5.2” is P5.2.

= 0 → pin “DA2/P5.2” is DA2.

P51E = 1 → pin “DA1/P5.1” is P5.1.

= 0 → pin “DA1/P5.1” is DA1.

P50E = 1 → pin “DA0/P5.0” is P5.0.

= 0 → pin “DA0/P5.0” is DA0.

HIICE = 1 → pin “HSCL/P3.0/Rxd” is HSCL; pin “HSDA/P3.1/Txd” is HSDA.

= 0 → pin “HSCL/P3.0/Rxd” is P3.0/Rxd; pin “HSDA/P3.1/Txd” is P3.1/Txd.

IIICE = 1 → pin “ISDA/P3.4/T0” is ISDA; pin “ISCL/P3.5/T1” is ISCL.

= 0 → pin “ISDA/P3.4/T0” is P3.4/T0; pin “ISCL/P3.5/T1” is P3.5/T1.

HLFVE = 1 → pin “DA9/HALFV” is VSYNC half frequency output.

= 0 → pin “DA9/HALFV” is DA9.

HLFHE = 1 → pin “DA8/HALFH”

= 0 → pin “DA8/HALFH” is DA8.

HCLPE = 1 → pin “DA7/HCLAMP”

= 0 → pin “DA7/HCLAMP” is DA7.

P42E = 1 → pin “STOUT/P4.2” is P4.2.

= 0 → pin “STOUT/P4.2” is STOUT.

P41E = 1 → pin “HBLANK/P4.1” is P4.1.

= 0 → pin “HBLANK/P4.1” is HBLANK.

P40E = 1 → pin “VBLANK/P4.0” is P4.0.

= 0 → pin “VBLANK/P4.0” is VBLANK.

(Rev. 1.2)

OPTION (w) : Chip option configuration (All are "0" in Chip Reset).

PWMF = 1 → select 94KHz PWM frequency.

= 0 → select 47KHz PWM frequency.

DIV253 = 1 → PWM pulse width is 253 step resolution.

= 0 → PWM pulse width is 256 step resolution.
FclkE = 1 → Double CPU clock Freq.
IICpass = 1 → HSCL/HSDA pin bypass to ISCL/ISDA pin in DDC2 mode.

= 0 → Separate Master and Slave IIC block.
ENSCL = 1 → Enable slave IIC block to hold HSCL pin low while MTV212A32 can't catch-up
the external master's speed.
Msel = 1 → Master IIC block connect to HSCL/HSDA pins.

= 0 → Master IIC block connect to ISCL/ISDA pins.
MIICF1,MIICF0 = 1,1 → select 400KHz Master IIC frequency.

= 1,0 → select 200KHz Master IIC frequency.
= 0,1 → select 50KHz Master IIC frequency.
= 0,0 → select 100KHz Master IIC frequency.

SlvAbs1,SlvAbs0 : Slave IIC block A's slave address length.

= 1,0 → 5-bits slave address.
= 0,1 → 6-bits slave address.
= 0,0 → 7-bits slave address.

XBANK (r/w) :

Xbnk[2:0] = 0 → Select AUXRAM bank 0.

= 1 → Select AUXRAM bank 1.
= 2 → Select AUXRAM bank 0.
= 3 → Select AUXRAM bank 1.

Revision 1.2 - 7 - 2000/07/04