MYSON MTV130P, MTV130P20 Datasheet

ut notice.

No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.

TECHNOLOGY

GENERAL DESCRIPTION

Character bordering, shadowing and blinking effect.

4-channel/8-bit PWM D/A converter output.

ing on window and full-screen self-test pattern generator.

menu is formed by 15 rows x 30 columns, which can be

On-Screen Display for LCD Monitor

FEATURES

• Horizontal SYNC input up to 150 KHz.

• Acceptable wide-range pixel clock up to 150 MHz.

• Full screen self-test pattern generator.

• Full-screen display consists of 15 (rows) by 30 (columns)
characters.

• Two font size 12x16 or 12x18 dot matrix per character.

• True totally 512 mask ROM fonts including 496 standard
fonts and 16 multi-color fonts.

• 8 color selection maximum per display character.

• Double character height and/or width control.

• Programmable positioning for display screen center.

•

• Programmable character height (18 to 71 lines) control.

• Row to row spacing control to avoid expansion distortion.

• 4 programmable windows with multi-level operation.

• Shadowing on windows with programmable shadow
width/height/color.

• Software clears bit for full-screen erasing.

• Intensity and fast blanking output.

• Fade-in/fade-out or blending-in/blending-out effects.

•

• Compatible with SPI bus or I2C interface with slave
address 7AH (slave address is mask option).

• 16-pin or 20-pin PDIP/SOP package.

MTV130MYSON

MTV130 is designed for LCD monitor applications to
display built-in characters or fonts onto an LCD monitor
screens. The display operation occurs by transferring data
and control information from the micro-controller to RAM
through a serial data interface. It can execute full-screen
display automatically, as well as specific functions such as
character background, bordering, shadowing, blinking,
double height and width, font by font color control, frame
positioning, frame size control by character height and row­to-row spacing, horizontal display resolution, full-screen
erasing, fade-in/fade-out effect, windowing effect, shadow-

MTV130 provides true 512 fonts including 496 standard
fonts and 16 multi-color fonts and 2 font sizes, 12x16 or
12x18 for more efficacious applications. So each one of the
512 fonts can be displayed at the same time. The full OSD

positioned anywhere on the monitor screen by changing
vertical or horizontal delay.

BL OCK DIAGRAM

SSB

SCK

SDA

ARWDB
HDREN

VDREN

NROW

VFLB

VSP

VERTD

HFLB

HORD

HSP

NC

XIN

PWM0
PWM1
PWM2
PWM3

SERIAL DATA

ADDRESS BUS

ADMINISTRATOR

7

CH

CHS

8

8

DISPLAY CONTROL

CONVERTER

INTERFACE

VERTICAL

DISPLAY

CONTROL

HORIZONTAL

CLOCK

GENERATOR

PWM D/A

8

DATA

9

ROW, COL
ACK

5

RCADDR

9

DADDR

9

FONTADDR

5

WINADDR

5

PWMADDR

5

LPN
NROW
VDREN

ARWDB
HDREN

VCLKX

8

DATA

8 LUMAR

DATA

DISPLAY & ROW

CWS

DATA

LPN

CWS

VCLKS

8

VERTD

8

HORD

7

LUMAR
LUMAG
LUMAB

BLINK

VCLKX

CHS

DATA

CH

CONTROL

REGISTERS

8

CHARACTER ROM

USER FONT RAM

5

LUMINANCE &

BORDGER

GENERATOR

8

WINDOWS &

FRAME

CONTROL

WRWGWB

FBKGC

COLOR

ENCODER

BLANK

POWER ON

RESET

LUMAG
LUMAB
BLINK

8

CRADDR

LUMA
BORDER

BSEN
SHADOW
OSDENB
HSP
VSP

PRB

VDD

VSS

VDDA

VSSA

ROUT
GOUT
BOUT
FBKG
HTONE

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification witho

Revision 1.0 1/18 28/April/2000

TECHNOLOGY

This ground pin is used to internal circuitry.

This is a clock input pin. MTV130 is driven by an

external pixel clock source for all the logics inside. The frequency of XIN

must be the integral time of pin HFLB.

Positive 5 V DC supply for internal circuitry. And a 0.1uF

This pin is used to input the horizontal synchronizing

signal. It is a leading edge triggered and has an internal pull-up resistor.

Open-Drain PWM D/A conv er t er 0.

The output pulse width is program-

mable by the register of Row 15, Column 23.

Open-Drain PWM D/A conv er t er 1.

The output pulse width is program-

mable by the register of Row 15, Column 24.

Open-Drain PWM D/A conv er t er 2.

The output pulse width is program-

mable by the register of Row 15, Column 25.

Open-Drain PWM D/A conv er t er 3.

The output pulse width is program-

mable by the register of Row 15, Column 26.

1.0 PIN CONNECTION

MTV130MYSON

VSS

XIN

NC

VDD

HFLB

SSB
SDA
SCK

1
2
3
4
5
6
7
8

16

VSS

15

ROUT

14

GOUT

13

BOUT

12

FBKG

MTV130P-xx

11

INT
VFLB

10

VDD

9

2.0 PIN DESCRIPTIONS

Name I/O

VSS - 1 1 Ground .

XIN I 2 2 Pixel clock input .

Pin No.

P16 P20

1

VSS

2

XIN

3

NC

4

VDD

SSB
SDA
SCK

5
6
7
8
9
10

HFLB

PWM0
PWM1

Des cripti ons

20

VSS

19

ROUT

18

GOUT

17

BOUT

16

FBKG

15

INT
VFLB

14

MTV130P20-xx

VDD

13

PWM3

12

PWM2

11

NC I 3 3 No connection .

VDD - 4 4 Pow er supp ly.

decoupling capacitor should be connected across to VDD and VSS.

HFLB I 5 5 Horizont al input.

SSB I 6 6 Serial in t erf ace enable. It is used to enable the serial data and is also

used to select the operation of I2C or SPI bus. If this pin is left floating,
I2C bus is enabled, otherwise the SPI bus is enabled.

SDA I 7 7 Serial data input . The external data transfer through this pin to internal

display registers and control registers. It has an internal pull-up resistor.

SCK I 8 8 Serial clo ck in put . The clock-input pin is used to synchronize the data

transfer. It has an internal pull-up resistor.

PWM0 O - 9

PWM1 O - 10

PWM2 O - 11

PWM3 O - 12

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TECHNOLOGY

3.0 FUNCTIONAL DESCRIPTIONS

3.1 SERIAL DATA INTERFACE

While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission

should be starting from pulling SSB to "low" level, enabling MTV130 to receiving mode, and retain "low" level

until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.

Format (a) R - C - D

Format (b) R - C - D

Format (c) R - C - D

C bus operation is only selected when SSB pin is left floating. And a valid transmission should be starting

Vert i cal inpu t .

It is leading triggered and has an internal pull-up resistor.

16-color selection is achievable by combining

this intensity pin with R/G/B output pins.

This ground pin is used to internal circuitry.

MTV130MYSON

Name I/O

VDD - 9 13 Power supp ly. Positive 5 V DC supply for internal circuitry and a 0.1uF

VFLB I 10 14

INT O 11 15 Intensity color output.

FBKG O 12 16 Fast Blanking outpu t. It is used to cut off external R, G, B signals of

BOUT O 13 17 Blu e color output. It is a blue color video signal output.

GOUT O 14 18 Green c ol o r outp ut . It is a green color video signal output.

ROUT O 15 19 Red color outp ut . It is a red color video signal output.

VSS - 16 20 Groun d.

The serial data interface receives data transmitted from an external controller. And there are 2 types of bus
can be accessed through the serial data interface, one is SPI bus and other is I2C bus.

Pin No.

Des cripti ons

P16 P20

decoupling capacitor should be connected across to VDD and VSS.

This pin is used to input the vertical synchronizing signal.

VGA while this chip is displaying characters or windows.

3.1.1 SPI bus

SSB

SCK

SDA

There are three transmission formats shown as below:

→ R - C - D → R - C - D .....

→ C - D → C - D → C - D .....

→ D → D → D → D → D .....

Where R=Row address, C=Column address, D=Display data

3.1.2 I2C bus

2

I
from writing the slave address 7AH to MTV130. The protocol is shown in Figure 2.

MS
B

first byte last byte

FIGURE 1. Data Tran s m issio n Prot ocol (SPI)

LSB

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TECHNOLOGY

Format (a) S - R - C - D

Format (b) S - R - C - D

Format (c) S - R - C - D

Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and

increase transmission efficiency. The row and column address will be incremented automatically when the for-

mat (c) is applied. Furthermore, the undefined locations in display or fonts RAM should be filled with dummy

There are 2 types of data should be accessed through the serial data interface, one is

ADDRESS

bytes of dis-

play registers, and other is

of row address and the bit5 of column address. The MSB(b7) is used to distinguish row and column

addresses when transferring data from external controller. The bit6 of column address is used to differentiate

the column address for format (a), (b) and format (c) respectively. Bit5 of row address for display register is

addres s byt es, bit 5 of col u m n addr ess is th e MSB (bit8) and data bytes are the 8 LSB (bit7~bi t 0) of dis-

play fonts address

played at the same time. See Table 1. And for format (c), since D8 is filled while program column address of

column address of address bytes again.

(a) and (c), but not from format (c) back to format (a) and (b). The alternation between transmission formats is

configured as the state diagram shown in Figure 3.

The configuration of transmission formats.

Addr ess Bytes

Attr ibut e Bytes

FIGURE 2. Dat a Trans m i ssion Pro t o c ol (I

SCK

MTV130MYSON

SDA

START ACK

B7 B6 B0 B7 B0

First byte

second byte last byte

2

ACK STOP

C)

There are three transmission formats shown as below:

→ R - C - D → R - C - D .....

→ C - D → C - D → C - D .....

→ D → D → D → D → D .....

Where S=Slave address, R=Row address, C=Column address, D=Display data

Display data (D). Format (a) is suitable for updating small amount of data which will be allocated with different
row address and column address. Format (b) is recommended for updating data that has same row address
but different column address. Massive data updating or full screen data change should use format (c) to

data.

TABLE 1.

Address b7 b6 b5 b4 b3 b2 b1 b0 Format

Row 1 0 0 x R3 R2 R1 R0 a,b,c

of Displ ay Reg.

Column

Column

0 0 D8 C4 C3 C2 C1 C0 a,b

ab

0 1 D8 C4 C3 C2 C1 C0 c

c

Data D7 D6 D5 D4 D3 D2 D1 D0 a,b,c
Row 1 0 1 R4 R3 R2 R1 R0 a,b,c

of Displ ay Reg.

Column

Column

0 0 x C4 C3 C2 C1 C0 a,b

ab

0 1 x C4 C3 C2 C1 C0 c

c

Data D7 D6 D5 D4 D3 D2 D1 D0 a,b,c

ATTRIBUTE bytes of display registers, the protocol are same for all except the bit5

used to distinguish ADDRESS byte when it is set to "0" and ATTRIBUTE byte when it is set to "1". And at

to save half MCU memory for true 512 fonts. So each one of the 512 fonts can be dis­address bytes, the continued data will be the same bank of upper 256 fonts or lower 256 fonts until program
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format

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TECHNOLOGY

3.2 Address bus adminis tr ator

The administrator manages bus address arbitration of internal registers or user fonts RAM during external

data write in. The external data write through serial data interface to registers must be synchronized by inter-

nal display timing. In addition, the administrator also provides automatic increment to address bus when exter-

nal write using format (c).

3.3 Verti cal di sp l ay cont r ol

The vertical display control can generates different vertical display sizes for most display standards in current

cal display height control register(CH6-CH0).The algorithm of repeating character line display are shown as

The vertical display center for full screen display could be figured out according to the information of vertical

Repeat Li n e Weigh t

FIGURE 3. Transmi s s i on State Diagram

0, X

MTV130MYSON

X, X

DA

format (c)

COL

X, X

c

1, X

c

0, 1

Initiate

1, X

ROW

0, 1

0, 0

Input = b7, b6

format (a)

format (b)

COL

ab

0, 0

X, X

DA

1, X

ab

monitors. The vertical display size is calculated with the information of double character height bit(CHS), verti­Table 2 and Table 3. The programmable vertical size range is 270 lines to maximum 2130 lines.

starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB,
is calculated with the following equation:

Vertical delay time = ( VERTD * 4 + 1 ) * H Where H = one horizontal line display time

TA B L E 2. Repeat lin e weig h t of ch aract er

CH6 - CH0

CH6,CH5=11 +18*3
CH6,CH5=10 +18*2
CH6,CH5=0x +18

CH4=1 +16
CH3=1 +8
CH2=1 +4
CH1=1 +2
CH0=1 +1

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TECHNOLOGY

character would not be repeated.

3.4 Hori zontal dis pl ay contr o l

The horizontal display control is used to generate control timing for horizontal display based on double char-

3.5 Disp l ay & Row contr ol regist ers

are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure 4 and Figure 5. Each dis-

play register has its corresponding character address on ADDRESS byte, its corresponding background color,

30

of DISPLAY REGISTERS

A TTRIBUTE

CRTL REG

TA B L E 3. Repeat line nu m ber of ch arac ter

MTV130MYSON

Repeat Line

Weight

+1 - - - - - - - - v - - - - - - - - ­+2 - - - - v - - - - - - - v - - - - ­+4 - - v - - - v - - - v - - - v - - -

+8 - v - v - v - v - v - v - v - v - ­+16 - v v v v v v v v v v v v v v v v ­+17 v v v v v v v v v v v v v v v v v ­+18 v v v v v v v v v v v v v v v v v v

Note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the

acter width bit (CWS), horizontal positioning register (HORD) and HFLB input. A horizontal display line
includes 360 dots for 30 display characters and the remaining dots for blank region. The horizontal delay
starting from HFLB leading edge is calculated with the following equation,

Horizontal delay time = ( HORD * 6 + 49) * P
Where P = 1 XIN pixel display time

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Repeat Lin e #

The internal RAM contains display and row control registers. The display registers have 450 locations which

1 blink bit and its corresponding color bits on ATTRIBUTE bytes. The row control register is allocated at col­umn 30 for row 0 to row 14 of attribute bytes, it is used to set character size to each respective row. If double
width character is chosen, only even column characters could be displayed on screen and the odd column
characters will be hidden.

ROW # COLUMN #

0 1 28 29

0
1

ROW

CHARACTER ADDRESS BYTES

13
14

FIGURE 4. Ad d r ess By t es of Disp l ay Regist ers Memory Map

31

R
E
S
E
R
V
E
D

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