MYSON MTV121N20, MTV121N24, MTV121 Datasheet
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product.
1/18 MTV121 Revision 5.0 06/29/1999
MTV121MYSON
TECHNOLOGY
FEATURES GENERAL DESCRIPTION
BLOCK DIAGRAM
• Horizontal sync input may be up to 130 KHz.
• Acceptable wide-range pixel clock up to 96MHz.
• Full screen display consists of 15 (rows) by 30 (columns)
characters.
• 12 x 18 dot matrix per character.
• Total 272 characters and graphic fonts including 256
standard and 16 multi-color mask ROM fonts.
• 8 color selectable maximum per display character.
• 7 color selectable maximum for character background.
• Double character height and/or width control.
• Programmable positioning for display screen center.
• Bordering, shadowing and blinking effect.
• Programmable character height (18 to 71 lines) control.
• Row to row spacing register to manipulate the constant
display height.
• 4 programmable background windows with multi-level
operation and shadowing on window effect.
• Software clears bit for full-screen erasing.
• Half tone and fast blanking output.
• Fade-in/fade-out effect.
• 8 channels 8 bits PWM D/A converters output.
• Compatible to SPI bus or I2C interface with slave
address 7AH (Slave address is mask option).
• 16 / 20 / 24 pins PDIP / SOP package.
Super On-Screen-Display for LCD Monitor
MTV121 is designed for LCD monitor applications
to display the built-in characters or fonts onto an LCD
monitor screen. The display operation is by transferring data and control information from micro controller to RAM through a serial data interface. It can
execute full screen display automatically and specific functions such as character background color,
bordering, shadowing, blinking, double height and
width, font by font color control, frame positioning,
frame size control by character height and row-torow spacing, horizontal display resolution, full-screen
erasing, fade-in/fade-out effect, windowing effect and
shadowing on window.
MTV121 provide 256 standard and 16 multi-color
fonts for more efficacious applications. The full OSD
menu is formed of 15 rows x 30 columns which can
be positioned on anywhere of the monitor screen by
changing vertical delay or horizontal delay.
Moreover, MTV121 also provide 8 PWM DAC
channels with 8 bits resolution and a PWM clock output for external digital to analog control.
SERIAL DATA
INTERFACE
ADDRESS BUS
ADMINISTRATOR
VERTICAL
DISPLAY
CONTROL
DISPLAY & ROW
CONTROL
REGISTERS
COLOR
ENCODER
WINDOWS &
FRAME
CONTROL
WRWGWB
FBKGC
BLANK
LUMAR
LUMAG
LUMAB
BLINK
VCLKX
DATA
VERTD
HORD
CH
8
8
7
BSEN
SHADOW
OSDENB
HSP
VSP
HORIZONTAL
DISPLAY CONTROL
CLOCK
GENERATOR
8
DATA
LPN
CWS
VCLKS
5
DATA
CWS
CHS
8 LUMAR
LUMAG
LUMAB
BLINK
CRADDR
8
LUMA
BORDER
ARWDB
HDREN
VCLKX
HORD
8
CH
CHS
VERTD
7
8
LPN
NROW
VDREN
5
RCADDR
DADDR
FONTADDR
WINADDR
PWMADDR
5
9
9
5
5
ARWDB
HDREN
VDREN
NROW
DATA
ROW, COL
ACK
8
9
CHARACTER ROM
USER FONT RAM
LUMINANCE &
BORDGER
GENERATOR
VDD
VSS
VDDA
VSSA
ROUT
GOUT
BOUT
FBKG
HTONE
HFLB
NC
XIN
VFLB
SSB
SCK
SDA
VSP
HSP
PWM D/A
CONVERTER
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
8
DATA
8
POWER ON
RESET
PRB
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TECHNOLOGY
1.0 PIN CONNECTION
2.0 PIN DESCRIPTIONS
Name I/O
Pin No.
Descriptions
N16 N20 N24
VSS - 1 1 1 Ground. This ground pin is used to internal circuitry.
XIN I 2 2 2 Pixel clock input. This is a clock input pin. MTV121 is driven by an exter-
nal pixel clock source for all the logics inside. The frequency of XIN must
be the integral time of pin HFLB.
NC I 3 3 3 No connection.
VDD - 4 4 4 Power supply. Positive 5 V DC supply for internal circuitry. And a 0.1uF
decoupling capacitor should be connected across to VDD and VSS.
HFLB I 5 5 5 Horizontal input. This pin is used to input the horizontal synchronizing
signal. It is a leading edge triggered and has an internal pull-up resistor.
SSB I 6 6 6 Serial interface enable. It is used to enable the serial data and is also
used to select the operation of I2C or SPI bus. If this pin is left floating, I2C
bus is enabled, otherwise the SPI bus is enabled.
SDA I 7 7 7 Serial data input. The external data transfer through this pin to internal
display registers and control registers. It has an internal pull-up resistor.
SCK I 8 8 8 Serial clock input. The clock-input pin is used to synchronize the data
transfer. It has an internal pull-up resistor.
PWM0 O - 9 9 Open-Drain PWM D/A converter 0. The output pulse width is program-
mable by the register of Row 15, Column 23.
PWM1 O - 10 10 Open-Drain PWM D/A converter 1. The output pulse width is program-
mable by the register of Row 15, Column 24.
PWM2 O - - 11 Open-Drain PWM D/A converter 2. The output pulse width is program-
mable by the register of Row 15, Column 25.
PWM3 O - - 12 Open-Drain PWM D/A converter 3. The output pulse width is program-
mable by the register of Row 15, Column 26.
VSSA
XIN
NC
VDDA
HFLB
SSB
SDA
SCK
VSS
ROUT
GOUT
BOUT
FBKG
HTONE/PWMCK
VFLB
VDD
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
MTV121
VSSA
XIN
NC
VDDA
HFLB
SSB
SDA
SCK
PWM0
PWM1
PWM2
PWM3
VSS
ROUT
GOUT
BOUT
FBKG
HTONE/PWMCK
VFLB
VDD
PWM7
PWM6
PWM5
PWM4
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
MTV121N24
VSSA
XIN
NC
VDDA
HFLB
SSB
SDA
SCK
PWM0
PWM1
VSS
ROUT
GOUT
BOUT
FBKG
HTONE/PWMCK
VFLB
VDD
PWM7
PWM6
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
MTV121N20
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TECHNOLOGY
3.0 FUNCTIONAL DESCRIPTIONS
3.1 SERIAL DATA INTERFACE
The serial data interface receives data transmitted from an external controller. And there are 2 types of bus
can be accessed through the serial data interface, one is SPI bus and other is I2C bus.
3.1.1 SPI bus
While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission
should be starting from pulling SSB to "low" level, enabling mtv121 to receiving mode, and retain "low" level
until the last cycle for a complete data packet transfer. The protocol is shown in Figure1.
PWM4 O - - 13 Open-Drain PWM D/A converter 4. The output pulse width is program-
mable by the register of Row 15, Column 27.
PWM5 O - - 14 Open-Drain PWM D/A converter 5. The output pulse width is program-
mable by the register of Row 15, Column 28.
PWM6 O - 11 15 Open-Drain PWM D/A converter 6. The output pulse width is program-
mable by the register of Row 15, Column 29.
PWM7 O - 12 16 Open-Drain PWM D/A converter 7. The output pulse width is program-
mable by the register of Row 15, Column 30.
VDD - 9 13 17 Power supply. Positive 5 V DC supply for internal circuitry and a 0.1uF
decoupling capacitor should be connected across to VDD and VSS.
VFLB I 10 14 18 Vertical input. This pin is used to input the vertical synchronizing signal.
It is leading triggered and has an internal pull-up resistor.
HTONE /
PWMCK
O 11 15 19 Half tone output / PWM clock output. This is a multiplexed pin selected
by PWMCK bit. This pin can be a PWM clock or used to attenuate R, G, B
gain of VGA for the transparent windowing effect.
FBKG O 12 16 20 Fast Blanking output. It is used to cut off external R, G, B signals of
VGA while this chip is displaying characters or windows.
BOUT O 13 17 21 Blue color output. It is a blue color video signal output.
GOUT O 14 18 22 Green color output. It is a green color video signal output.
ROUT O 15 19 23 Red color output. It is a red color video signal output.
VSS - 16 20 24 Ground. This ground pin is used to internal circuitry.
Name I/O
Pin No.
Descriptions
N16 N20 N24
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TECHNOLOGY
There are three transmission formats shown as below:
Format (a) R - C - D → R - C - D → R - C - D
Format (b) R - C - D → C - D → C - D → C - D
Format (c) R - C - D → D → D → D → D → D
Where R=Row address, C=Column address, D=Display data
3.1.2 I2C bus
I2C bus operation is only selected when SSB pin is left floating. And a valid transmission should be starting
from writing the slave address 7AH, which is mask option, to MTV121. The protocol is shown in Figure2.
There are three transmission formats shown as below:
Format (a) S - R - C - D → R - C - D → R - C - D
Format (b) S - R - C - D → C - D → C - D → C - D
Format (c) S - R - C - D → D → D → D → D → D
Where S=Slave address, R=Row address, C=Column address, D=Display data
Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and
Display data (D). Format (a) is suitable for updating small amount of data which will be allocated with different
row address and column address. Format (b) is recommended for updating data that has same row address
but different column address. Massive data updating or full screen data change should use format (c) to
increase transmission efficiency. The row and column address will be incremented automatically when the
format (c) is applied. Furthermore, the undefined locations in display or fonts RAM should be filled with
dummy data.
There are 2 types of data should be accessed through the serial data interface, one is ADDRESS bytes of display registers, and other is ATTRIBUTE bytes of display registers, the protocol are same for all except bit5 of
row address. The MSB(b7) is used to distinguish row and column addresses when transferring data from
external controller. The bit6 of column address is used to differentiate the column address for format (a), (b)
and format (c) respectively. Bit5 of row address for display register is used to distinguish ADDRESS byte
when it is set to "0" and ATTRIBUTE byte when it is set to "1". See Table 1 on page 4.
MS
B
LSB
SSB
SCK
SDA
first byte last byte
FIGURE 1. Data Transmission Protocol (SPI)
FIGURE 2. Data Transmission Protocol (I2C)
SCK
SDA
first byte
¡@¡@¡@¡@
¡@
START ACK
second byte last byte
ACK STOP
B7 B6 B0 B7 B0
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The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format
(a), but not from format (c) back to format (a) and (b). The alternation between transmission formats is configured as the state diagram shown in Figure3.
3.2 Address bus administrator
The administrator manages bus address arbitration of internal registers or user fonts RAM during external
data write in. The external data write through serial data interface to registers must be synchronized by internal display timing. In addition, the administrator also provides automatic increment to address bus when external write using format (c).
3.3 Vertical display control
The vertical display control can generates different vertical display sizes for most display standards in current
monitors. The vertical display size is calculated with the information of double character height bit(CHS), vertical display height control register(CH6-CH0).The algorithm of repeating character line display are shown as
Table 2 and Table 3. The programmable vertical size range is 270 lines to maximum 2130 lines.
TABLE 1. The configuration of transmission formats.
Address b7 b6 b5 b4 b3 b2 b1 b0 Format
Address Bytes
of Display Reg.
Row 1 0 0 x R3 R2 R1 R0 a,b,c
Column
ab
0 0 x C4 C3 C2 C1 C0 a,b
Column
c
0 1 x C4 C3 C2 C1 C0 c
Attribute Bytes
of Display Reg.
Row 1 0 1 x R3 R2 R1 R0 a,b,c
Column
ab
0 0 x C4 C3 C2 C1 C0 a,b
Column
c
0 1 x C4 C3 C2 C1 C0 c
Initiate
ROW
COL
c
COL
ab
DA
c
DA
ab
1, X
0, 1
0, 0
X, X
X, X
0, 1
1, X
1, X
format (a)
format (b)
format (c)
X, X
0, X
Input = b7, b6
0, 0
FIGURE 3. Transmission State Diagram
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The vertical display center for full screen display could be figured out according to the information of vertical
starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB,
is calculated with the following equation:
Vertical delay time = ( VERTD * 4 + 1 ) * H Where H = one horizontal line display time
Note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the
character would not be repeated.
3.4 Horizontal display control
The horizontal display control is used to generate control timing for horizontal display based on double character width bit (CWS), horizontal positioning register (HORD), horizontal resolution register (HORR), and
HFLB input. A horizontal display line consists of (HORR*12) dots which include 360 dots for 30 display characters and the remaining dots for blank region. The horizontal delay starting from HFLB leading edge is calculated with the following equation,
Horizontal delay time = ( HORD * 6 + 49) * P Where P = 1 XIN pixel display time
3.5 Display & Row control registers
The internal RAM contains display and row control registers. The display registers have 450 locations which
are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure4. Each display register
has its corresponding character address on ADDRESS byte, its corresponding background color, 1 blink bit
and its corresponding color bits on ATTRIBUTE bytes. The row control register is allocated at column 30 for
row 0 to row 14, it is used to set character size to each respective row. If double width character is chosen,
only even column characters could be displayed on screen and the odd column characters will be hidden.
TABLE 2. Repeat line weight of character
CH6 - CH0 Repeat Line Weight
CH6,CH5=11 +18*3
CH6,CH5=10 +18*2
CH6,CH5=0x +18
CH4=1 +16
CH3=1 +8
CH2=1 +4
CH1=1 +2
CH0=1 +1
TABLE 3. Repeat line number of character
Repeat Line
Weight
Repeat Line #
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
+1 - - - - - - - - v - - - - - - - - +2 - - - - v - - - - - - - v - - - - +4 - - v - - - v - - - v - - - v - - -
+8 - v - v - v - v - v - v - v - v - +16 - v v v v v v v v v v v v v v v v +17 v v v v v v v v v v v v v v v v v +18 v v v v v v v v v v v v v v v v v v
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