MYSON MTV118, MTV118N24 Datasheet

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification
without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of
the product.

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TECHNOLOGY

FEATURES GENERAL DESCRIPTION

BLOCK DIAGRAM

• Horizontal sync input may be up to 120 KHz.

• Acceptable wide-range pixel clock up to 96MHz
from XIN pin.

• Full-screen display consists of 15 (rows) by 30 (col­umns) characters.

• 12 x 18 dot matrix per character.

• Total of 256 characters and graphic fonts including
248 mask ROM fonts and 8 programmable RAM
fonts.

• 8 color selection maximum per display character.

• Double character height and/or width control.

• Programmable positioning for display screen cen­ter.

• Bordering, shadowing and blinking effect.

• Programmable vertical character height (18 to 71
lines) control.

• Row to row spacing register to manipulate the con­stant display height.

• 4 programmable background windows with multi­level operation.

• Software clears for display frame.

• Half tone and fast blanking output.

• 8-channel/8-bit PWM D/A converter output.

• Compatible with SPI bus or I2C interface with
address 7AH (slave address is mask option).

• 16 or 24-pin PDIP/SOP package.

On-Screen-Display for LCD Monitor

MTV118 is designed for LCD monitor appli­cations to display the built-in characters or fonts
onto an LCD monitor screen. The display oper­ates by transferring data and control information
from the micro controller to the RAM through a
serial data interface. It can execute full screen
displays automatically and specific functions such
as character bordering, shadowing, blinking, dou­ble height and width, font by font color control,
frame positioning, frame size control by character
height and windowing effect. Moreover, MTV118
also provides 8 PWM DAC channels with 8-bit
resolution and a PWM clock output for external
digital-to-analog control.

SERIAL DATA

INTERFACE

ADDRESS BUS

ADMINISTRATOR

VERTICAL

DISPLAY

CONTROL

DISPLAY & ROW

CONTROL

REGISTERS

COLOR

ENCODER

WINDOWS &

FRAME

CONTROL

WRWGWB

FBKGC

BLANK

LUMAR
LUMAG
LUMAB

BLINK

VCLKX

DATA

VERTD

HORD

CH

8
8
7

BSEN
SHADOW
OSDENB
HSP
VSP

HORIZONTAL

DISPLAY CONTROL

CLOCK

GENERATOR

8

DATA

LPN

CWS

VCLKS

5

DATA

CWS

CHS

8 LUMAR

LUMAG
LUMAB
BLINK
CRADDR

8

LUMA
BORDER

ARWDB
HDREN

VCLKX

HORD

8

CH

CHS

VERTD

7
8

LPN
NROW
VDREN

5

RCADDR
DADDR
FONTADDR
WINADDR
PWMADDR

5
9
9
5
5

ARWDB
HDREN

VDREN

NROW

DATA
ROW, COL
ACK

8
9

CHARACTER ROM

USER FONT RAM

LUMINANCE &

BORDGER

GENERATOR

VDD

VSS

VDDA

VSSA

ROUT
GOUT
BOUT
FBKG
HTONE

HFLB

NC

XIN

VFLB

SSB

SCK

SDA

VSP

HSP

PWM D/A

CONVERTER

PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7

8

DATA

8

POWER ON

RESET

PRB

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1.0 PIN CONNECTION

2.0 PIN DESCRIPTIONS

Name I/O

Pin #

Descriptions

N16 N24

VSS - 1 1 Ground. This ground pin is used for internal circuitry.

XIN I 2 2

Pixel Clock Input. This is a clock input pin. MTV118 is driven by
an external pixel clock source for all the logics inside. The fre­quency of XIN must be the integral time of pin HFLB.

NC I 3 3 No connection.

VDD - 4 4

Power supply. Positive 5 V DC supply for internal circuitry. A

0.1uF decoupling capacitor should be connected across VDD and
VSS.

HFLB I 5 5

Horizontal Input. This pin is used to input the horizontal synchro­nizing signal. It is a leading edge trigger and has an internal pull­up resistor.

SSB I 6 6

Serial Interface Enabler. It is used to enable the serial data and
is also used to select the operation of I2C or SPI bus. If this pin is
left floating, I2C bus is enabled, otherwise the SPI bus is enabled.

SDA I 7 7

Serial Data Input. The external data transfers through this pin to
internal display registers and control registers. It has an internal
pull-up resistor.

SCK I 8 8

Serial Clock Input. The clock-input pin is used to synchronize the
data transfer. It has an internal pull-up resistor.

PWM0 O - 9

Open-Drain PWM D/A Converter 0. The output pulse width is
programmable by the register of row 15, column 19.

PWM1 O - 10

Open-Drain PWM D/A Converter 1. The output pulse width is
programmable by the register of row 15, column 20.

PWM2 O - 11

Open-Drain PWM D/A Converter 2. The output pulse width is
programmable by the register of row 15, column 21.

VSS

XIN

NC

VDD

HFLB

SSB
SDA
SCK

VSS
ROUT
GOUT
BOUT
FBKG
HTONE/PWMCK
VFLB
VDD

16
15
14
13
12
11
10

9

1
2
3
4
5
6
7
8

MTV118

VSS

XIN

NC

VDD

HFLB

SSB
SDA
SCK

PWM0
PWM1
PWM2
PWM3

VSS
ROUT
GOUT
BOUT
FBKG
HTONE/PWMCK
VFLB
VDD
PWM7
PWM6
PWM5
PWM4

24
23
22
21
20
19
18
17
16
15
14
13

1
2
3
4
5
6
7
8
9
10
11
12

MTV118N24

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3.0 FUNCTIONAL DESCRIPTIONS

3.1 Serial Data Interface

The serial data interface receives data transmitted from an external controller. There are 2 types of bus
which can be accessed through the serial data interface: SPI bus and I2C bus.

3.1.1 SPI Bus

When the SSB pin is pulled to a HIGH or LOW level, the SPI bus operation is selected. A valid trans­mission should start from pulling SSB to LOW level, enabling the MTV118 receiving mode and retaining
the LOW level until the last cycle for a complete data packet transfer. The protocol is shown in Figure1
on page4.

There are 3 transmission formats as shown below:
Format (a) R - C - D → R - C - D → R - C - D
Format (b) R - C - D → C - D → C - D → C - D
Format (c) R - C - D → D → D → D → D → D
R=row address, C=column address, D=display data

PWM3 O - 12

Open-Drain PWM D/A Converter 3. The output pulse width is
programmable by the register of row 15, column 22.

PWM4 O - 13

Open-Drain PWM D/A Converter 4. The output pulse width is
programmable by the register of row 15, column 23.

PWM5 O - 14

Open-Drain PWM D/A Converter 5. The output pulse width is
programmable by the register of row 15, column 24.

PWM6 O - 15

Open-Drain PWM D/A Converter 6. The output pulse width is
programmable by the register of row 15, column 25.

PWM7 O - 16

Open-Drain PWM D/A Converter 7. The output pulse width is
programmable by the register of row 15, column 26.

VDD - 9 17

Power Supply. Positive 5 V DC supply for internal circuitry and a

0.1uF decoupling capacitor should be connected across VDD and
VSS.

VFLB I 10 18

Vertical Input. This pin is used to input the vertical synchronizing
signal. It is triggered by lead and has an internal pull-up resistor.

HTONE /

PWMCK

O 11 19

Half Tone Output / PWM Clock Output. This is a multiplexed pin
selected by the PWMCK bit. This pin can be a PWM clock or used
to attenuate R, G, B gain of VGA for the transparent windowing
effect.

FBKG O 12 20

Fast Blanking Output. It is used to cut off external R, G, B sig­nals of VGA while this chip is displaying characters or windows.

BOUT O 13 21 Blue Color Output. This is a blue color video signal output.
GOUT O 14 22 Green Color Output. This is a green color video signal output.
ROUT O 15 23 Red Color Output. This is a red color video signal output.

VSS - 16 24 Ground. This ground pin is used for internal circuitry.

Name I/O

Pin #

Descriptions

N16 N24

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3.1.2 I2C Bus

I2C bus operation is only selected when the SSB pin is left floating. A valid transmission should begin
from writing the slave address 7AH, which is mask option, to MTV118. The protocol is shown in Figure
2 on page 4..

There are 3 transmission formats as shown below:
Format (a) S - R - C - D → R - C - D → R - C - D
Format (b) S - R - C - D → C - D → C - D → C - D
Format (c) S - R - C - D → D → D → D → D → D
S=slave address, R=row address, C=column address, D=display data

Each arbitrary length of data packet consists of 3 portions: row address (R), column address (C) and
display data (D). Format (a) is suitable for updating small amounts of data which will be allocated with
different row and column addresses. Format (b) is recommended for updating data that has the same
row address but a different column address. Massive data updating or full screen data changes should
be done in format (c) to increase transmission efficiency. The row and column addresses will be incre­mented automatically when format (c) is applied. Furthermore, the undefined locations in display or font
RAM should be filled with dummy data.

There are 3 types of data which should be accessed through the serial data interface: address bytes of
display registers, attribute bytes of display registers and user font RAM data. The protocol is the same
for all except bits 5 and 6 of the row addresses. The MSB(b7) is used to distinguish row and column
addresses when transferring data from an external controller. Bit 6 of the row address is used to distin­guish display registers and user font RAM data and bit6 of the column address is used to differentiate
the column address for formats (a), (b) and (c), respectively. Bit 5 of the row address for display regis­ters is used to distinguish the address byte when it is set to "0" and the attribute byte when it is set to
"1". The configuration of transmission formats is shown in Table1 on page5.

MS
B

LSB

SSB

SCK

SDA

first byte last byte

FIGURE 1. Data Transmission Protocol (SPI)

FIGURE 2. Data Transmission Protocol (I2C)

SCK

SDA

first byte

¡@¡@¡@¡@

¡@

START ACK

second byte last byte

ACK STOP

B7 B6 B0 B7 B0

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The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to
format (a), but not from format (c) back to format (a) and (b). The alternation between transmission for­mats is configured as the state diagram shown in Figure3 on page5.

3.2 Address Bus Administrator

The administrator manages bus address arbitration of internal registers or user font RAM during exter­nal data write-in. The external data write through serial data interface to registers must be synchronized
by internal display timing. In addition, the administrator also provides automatic incrementation to the
address bus when external writing occurs using format (c).

3.3 Vertical Display Control

The vertical display control can generate different vertical display sizes for most display standards in
current monitors. The vertical display size is calculated with the information of a double character height
bit(CHS) and a vertical display height control register(CH6-CH0).The algorithms of a repeating charac­ter line display are shown in Tables 2 and 3. The programmable vertical size range is 270 lines to max­imum 2130 lines.

TABLE 1. Configuration of Transmission Formats

Address b7 b6 b5 b4 b3 b2 b1 b0 Format

Address
Bytes of

Display

Reg.

Row 1 0 0 x R3 R2 R1 R0 a,b,c

Column

ab

0 0 x C4 C3 C2 C1 C0 a,b

Column

c

0 1 x C4 C3 C2 C1 C0 c

Attribute
Bytes of

Display

Reg.

Row 1 0 1 x R3 R2 R1 R0 a,b,c

Column

ab

0 0 x C4 C3 C2 C1 C0 a,b

Column

c

0 1 x C4 C3 C2 C1 C0 c

User

Fonts

RAM

Row 1 1 x x x R2 R1 R0 a,b,c

Column

ab

0 0 C5 C4 C3 C2 C1 C0 a,b

Column

c

0 1 C5 C4 C3 C2 C1 C0 c

Initiate

ROW

COL

c

COL

ab

DA

c

DA

ab

1, X

0, 1

0, 0

X, X

X, X

0, 1

1, X

1, X

format (a)

format (b)

format (c)

X, X

0, X

Input = b7, b6

0, 0

FIGURE 3. Transmission State Diagram

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The vertical display center for a full-screen display may be figured out according to the information of
the vertical starting position register (VERTD) and VFLB input. The vertical delay starting from the lead­ing edge of VFLB is calculated using the following equation:

Vertical delay time = ( VERTD * 4 + 1 ) * H
Where H = 1 horizontal line display time

Note: “v” means the nth line in the character would be repeated once, while “-” means the nth line in the

character would not be repeated.

3.4 Horizontal Display Control

The horizontal display control is used to generate control timing for a horizontal display based on dou­ble character width bit (CWS), horizontal positioning register (HORD) and HFLB input. A horizontal dis­play line includes 360 dots for 30 display characters and the remaining dots for a blank region. The
horizontal delay starting from the HFLB leading edge is calculated using the following equation:

Horizontal delay time = ( HORD * 6 + 49) * P
Where P = 1 XIN pixel display time

3.5 Display & Row Control Registers

The internal RAM contains display and row control registers. The display registers have 450 locations
which are allocated between row 0/column 0 and row 14/column 29 as shown in Figure 4. Each display
register has its corresponding character address on the address byte, and 1 blink bit and its corre­sponding color bits on attribute bytes. The row control register is allocated at column 30 for row 0 to row
14; it is used to set character size for each respective row. If the double width character (CWS) is cho-

TABLE 2. Repeat Line Weight of Character

CH6-CH0 Repeat Line Weight

CH6,CH5=11 +18*3
CH6,CH5=10 +18*2
CH6,CH5=0x +18

CH4=1 +16
CH3=1 +8
CH2=1 +4
CH1=1 +2
CH0=1 +1

TABLE 3. Repeat Line Number of Character

Repeater Line

Weight

Repeat Line #

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

+1 - - - - - - - - v - - - - - - - - ­+2 - - - - v - - - - - - - v - - - - ­+4 - - v - - - v - - - v - - - v - - -

+8 - v - v - v - v - v - v - v - v - ­+16 - v v v v v v v v v v v v v v v v ­+17 v v v v v v v v v v v v v v v v v ­+18 v v v v v v v v v v v v v v v v v v

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sen, only even column characters may be displayed on-screen and the odd column characters will be
hidden.

FIGURE 4. Memory map

3.5.1 Register Descriptions

1. (i) Display Register, (Row 0 - 14, Column 0 - 29)

ADDRESS BYTE

CRADDR - Defines ROM character and user-programmable fonts address.

(a) 0 ~ 247 ⇒ 248 built-in characters and graphic symbols
(b) 248 ~ 255 ⇒ 8 user-programmable fonts

ATTRIBUTE BYTE

BLINK - Enables blinking effect when this bit is set to " 1 ". The blinking is alternated per 32 vertical

frames.

R1, G1, B1 - These bits are used to specify its relative address character color 1.

2. Row Control Registers, (Row 0 - 14)

R2, G2, B2 - These bits are used to specify its relative row character color 2. While the corresponding

CCS bit is set to 1, color 2 should be chosen.
CHS - Defines double height character to the respective row.
CWS - Defines double width character to the respective row.

ROW #

COLUMN #

0 1 28 29 30 31

0
1

13
14

DISPLAY REGISTERS

ROW CTRL

REG

RESERVED

ROW 15

COLUMN#

0 23 5 6 8 9 11 12 18 19 26

WINDOW1 WINDOW2 WINDOW3 WINDOW4

FRAME CRTL

REG

PWM D/A

CRTL REG

b7 b6 b5 b4 b3 b2 b1 b0

CRADDR

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

- - - - BLINK R1 G1 B1

COLN 30

b7 b6 b5 b4 b3 b2 b1 b0

- - - R2 G2 B2 CHS CWS

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3.6 User Font RAM

The user font RAM has 288 locations which are allocated between row 0/column 0 and row 7/column
35 to specify 8 user-programmable fonts, as shown in Figure 5. Each programmable font consists of a
12x18 dot matrix. Each row of dot matrix consists of 2 bytes of data which include 4 dummy bits as
shown in figure 6. That is, the dot matrix data of each font is stored in 36-byte registers. For example,
font 0 is stored in row 0 from column 0 to column 35 and font 1 is stored in row 1 from column 0 to col­umn 35, etc.

FIGURE 5. User Font RAM Memory Map

3.7 Character ROM

The character ROM contains 248 built-in characters and symbols from addresses 0 to 247. Each char­acter and symbol consists of a 12x18 dot matrix. The detail pattern structures for each character and
symbol are shown in 10.0“CHARACTER AND SYMBOL PATTERN” on page 15.

3.8 Luminance & Border Generator

There are 2 shift registers included in the design which can shift out of luminance and border dots to the
color encoder. The bordering and shadowing feature is configured in this block. For bordering effect,
the character will be enveloped with blackedge on 4 sides. For shadowing effect, the character is envel­oped with blackedge on right and bottom sides only.

3.9 Window and Frame Control

The display frame position is completely controlled by the contents of VERTD and HORD. The window
size and position control are specified in columns 0 to 11 on row 15 of the memory map, as shown in
Figure 4. Window 1 has the highest priority and window 4 has the least, when 2 windows are overlap­ping. More detailed information is described as follows:

ROW # COLUMN #

0 1 34 35 36 63

0
1

6
7

USER FONT RAM RESERVED

FIGURE 6. Data Format of Font Dot Matrix

Nth byte (N+1)th byte

12 bits for 1-row data of font dot matrix Dummy bits

rightmost dot of font

N=even number

b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

leftmost dot of font

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1. Window control registers:
ROW 15

START(END) ADDR - These addresses are used to specify the window size. It should be noted that

when the start address is greater than the end address, the window will be disa-

bled.
WEN - Enables the window display.
CCS - When a window is overlapping with the character, character color 2 should be chosen while this

bit is set to 1. Color 1 is selected otherwise.

R, G, B - Specifies the color of the relative background window.

2. Frame control registers:
ROW 15

VERTD - Specifies the starting position for vertical display. The total steps are 256, and the increment
of each step is 4 horizontal display lines. The initial value is 4 after power-up.

HORD - Defines the starting position for horizontal display. The total steps are 256 and the increment of

each step is 6 dots. The initial value is 15 after power-up.

CH6-CH0 - Defines the character vertical height, which is programmable from 18 to 71 lines. The char-

acter vertical height is at least 18 lines if the contents of CH6-CH0 are less than 18. For
example, when the content is " 2 ", the character vertical height is regarded as equal to 20
lines. If the contents of CH4-CH0 are greater than or equal to 18, it will be regarded as equal
to 17. See Tables 2 and 3 for a detailed description of this operation.

This byte is reserved for internal testing.

Column
0,3,6,OR 9

b7 b6 b5 b4 b3 b2 b1 b0

ROW START ADDR

MSB LSB

ROW END ADDR

MSB LSB

Column
1,4,7,OR 10

b7 b6 b5 b4 b3 b2 b1 b0

COL START ADDR

MSB LSB

WEN CCS -

Column
2,5,8,OR 11

b7 b6 b5 b4 b3 b2 b1 b0

COL END ADDR

MSB LSB

R G B

Column 12

b7 b6 b5 b4 b3 b2 b1 b0

VERTD

MSB LSB

Column 13

b7 b6 b5 b4 b3 b2 b1 b0

HORD

MSB LSB

Column 14

b7 b6 b5 b4 b3 b2 b1 b0

- CH6 CH5 CH4 CH3 CH2 CH1 CH0

Column 15

b7 b6 b5 b4 b3 b2 b1 b0

Reserved