MYSON MTV112EV-OTP Datasheet

MYSON

-byte internal RAM.

32K-byte program EPROM.

The MTV112E micro-controller is an 8051 CPU core embedded device specially tailored to CRT monitor
24Cxx series EEPROM interface, A/D converter and a 32K-byte internal program EPROM.

MTV112E

TECHNOLOGY

(Rev 1.8)

8051 Embedded CRT Monitor Controller

OTP Version

FEATURES

8051 core.
384

14-channel 10V open-drain PWM DAC, 10 dedicated channels and 4 channels shared with I/O pin.
MAX, 23 I/O pins.

SYNC processor for composite separation, polarity and frequency check, and polarity adjustment.

Built-in monitor self-test pattern generator.
Built-in low power reset circuit.
One slave mode IIC interface and one master mode IIC interface.
IIC interface for DDC1/DDC2B and EEPROM; only one EEPROM needed to store DDC1/DDC2B and
display mode information.
Dual 4-bit ADC.
Watchdog timer with programmable interval.
40-pin PDIP and 44-pin PLCC package.

GENERAL DESCRIPTION

applications. It includes an 8051 CPU core, 384-byte SRAM, 14 built-in PWM DACs, DDC1/DDC2B interface,

STOUT

P1.0-7

X1

X2

P2.0-3

P3.0-P3.2

HSCL
HSDA

P0.0-7

8051

CORE

P2.4-7

P3.4

DDC 1/2 B & FIFO

P0.0-7

RD

WR

INT
1

RST

INTERFACE

WR

XFR

RD

WATCH-DOG

TIMER

RST

H / VSYNC
CONTROL

14 CHANNEL

PWM DAC

IIC INTERFACE

HSYNC

VSYNC
HBLANK
VBLANK

DA0-9

DA10-13

ADC

ISCL

ISDA

AD0
AD1

BL OCK DIAGRAM

This datasheet contains new product information. Myson Technology reserv es the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.

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MTV112E Revision 1.8 05/18/2001

MYSON

PINT1B are only for MICE

HBLANK/P4.1

VBLANK/P4.0

MTV112E

TECHNOLOGY

1.0 PIN CONNECTION

P1.0
P1.1
P1.2
P1.3
P1.4

P1.5
P1.6/AD0
P1.7/AD1

RST

HSCL/P3.0/Rxd
HSDA/P3.1/Txd

ISDA/P3.2/INT0

HSYNC

ISCL/P3.4/T0

VSYNC
HBLANK/P4.1
VBLANK/P4.0

X2
X1

VSS

MTV112E

VDD
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
STOUT/P4.2
DA10/P2.7
DA11/P2.6
DA12/P2.5
DA13/P2.4
P2.3
P2.2
P2.1
P2.0/INT0

NC
P1.5
P1.6
P1.7

RESET

HSCL

HSDA

ISDA

HSYNC

ISCL

VSYNC

P1.4

P1.3

P1.2

P1.1

P1.0

VDD

DAC0

DAC1

6

5

4

3

2

1

4443424140

7
8
9
10
11
12
13
14
15
16
17

1819202122232425262728

PWDTO

MTV112E

X2

X1

VSS

P2.0

P2.1

(Rev 1.8)

DAC2

DAC3

PICEB

39
38
37
36
35
34
33
32
31
30
29

P2.2

P2.3

DAC13

DAC4
CAC5
DAC6
CAC7
DAC8
DAC9
STO
DAC10
DAC11
DAC12
PINT1B

Note: 44-pin PLCC, PICEB, PALE, PWDTO and

P1.0
P1.1/HALFV
P1.2/HALFH

P1.3/HCLAMP

P1.4/AD2
P1.5/AD3
P1.6/AD0
P1.7/AD1

RST

HSCL/P3.0/Rxd
HSDA/P3.1/Txd
ISDA/P3.2/INT0

HSYNC

ISCL/P3.4/T0

VSYNC

NC
HBLANK/P4.1
VBLANK/P4.0

X2
X1

VSS

MTV112E

Mode.

VDD
DA0/P5.0
DA1/P5.1
DA2/P5.2
DA3/P5.3
DA4/P5.4
DA5/P5.5
DA6/P5.6
DA7/P5.7
DA8
DA9
NC
STOUT/P4.2
DA10/P2.7
DA11/P2.6
DA12/P2.5
DA13/P2.4
P2.3
P2.2
P2.1
P2.0/INT0

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MTV112E Revision 1.8 05/18/2001

MYSON

ISDA/P3.2/INT0

PWM DAC output (open-drain)
PWM DAC output (open-drain)
PWM DAC output (open-drain)
PWM DAC output (open-drain)
PWM DAC output (open-drain)
PWM DAC output (open-drain)
PWM DAC output (open-drain)
PWM DAC output (open-drain)
PWM DAC output (open-drain)
PWM DAC output (open-drain)

MTV112E

TECHNOLOGY

2.0 PIN DESCRIPTIONS

Name Type Pin# Description
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6/AD0
P1.7/AD1
RST
HSCL/P3.0/Rxd
HSDA/P3.1/Txd

HSYNC
ISCL/P3.4/T0
VSYNC
HBLA NK /P4.1
VBL ANK /P4.0
X2
X1
VSS
P2.0/INT0
P2.1
P2.2
P2.3
DA13/P2.4
DA12/P2.5
DA11/P2.6
DA10/P2.7
STOUT/P4.2
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
VDD

(Rev 1.8)

I/O 1 General purpose I/O
I/O 2 General purpose I/O
I/O 3 General purpose I/O
I/O 4 General purpose I/O
I/O 5 General purpose I/O
I/O 6 General purpose I/O
I/O 7 General purpose I/O / ADC input
I/O 8 General purpose I/O / ADC input

I 9 Active high reset
I/O 10 IIC clock / General purpose I/O / Rxd
I/O 11 IIC data / General purpose I/O / Txd
I/O 12 IIC data / General purpose I/O / INT0

I 13 Horizontal SYNC or Composite SYNC
I/O 14 IIC clock / General purpose I/O / T0

I 15 Vertical SYNC

O 16 Horizontal blank / General purpose output
O 17 Vertical blank / General purpose output
O 18 Oscillator output

I 19 Oscillator input

- 20 Ground
I/O 21 General purpose I/O / INT0
I/O 22 General purpose I/O
I/O 23 General purpose I/O
I/O 24 General purpose I/O
I/O 25 PWM DAC output / General purpose I/O (open-drain)
I/O 26 PWM DAC output / General purpose I/O (open-drain)
I/O 27 PWM DAC output / General purpose I/O (open-drain)
I/O 28 PWM DAC output / General purpose I/O (open-drain)

O 29 Self-test video output / General purpose output
O 30
O 31
O 32
O 33
O 34
O 35
O 36
O 37
O 38
O 39

- 40 Positive power supply

3.0 FUNCTIONAL DESCRIPTION

1. 8051 CPU Core

MTV112E includes all 8051 functions with the following exceptions:

1.1 PSEN, ALE, RD and WR pins are disabled. The external RAM access is restricted to XFRs within
MTV112E.

MTV112E Revision 1.8 05/18/2001

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MYSON

PADMOD

Memory Alloc ation

256 bytes, accessible by

MTV112E

TECHNOLOGY

1.2 Port 0, port 3.3, and ports 3.5 ~ 3.7 are not general-purpose I/O ports. They are dedicated to monitor
control or DAC pins.

1.3 INT1 and T1 input pins are not provided.

1.4 Ports 2.4 ~ 2.7 are shared with DAC pins; ports 3.0 ~ 3.2, and port3.4 are shared with monitor control
pins.

In addition, there are 2 timers, 5 interrupt sources and a serial interface compatible with the standard 8051.
The Txd/Rxd (P3.0/P3.1) pins are shared with DDC interface. INT0/T0 pins are shared with IIC interface. An
extra option can be used to switch the INT0 source from P3.2 to P2.0. This feature maintains an external
interrupt source when IIC interface is enabled.

Note: All regis t ers li st ed in th i s do c um ent resid e in the external RAM area (XFR). For the int ernal

RAM memory m ap pl ease refer to th e 8051 spec.

reg name

addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

30h (w) SINT0 IICF DDCE IICE DA13E DA12E DA11E DA10E

SINT0 = 1 → INT0 source is pin #21.

= 0 → INT0 source is pin #12.

IICF = 1 → Selects 400kHz master IIC speed.

= 0 → Selects 100kHz master IIC speed.

DDCE = 1 → Pin #10 is HSCL; pin #11 is HSDA.

= 0 → Pin #10 is P3.0/Rxd; pin #11 is P3.1/Txd.

IICE = 1 → Pin #12 is ISDA; pin #14 is ISCL.

= 0 → Pin #12 is P3.2/(INT0*); pin #14 is P3.4/T0.

DA13E = 1 → Pin #25 is DA13.

= 0 → Pin #25 is P2.4.

DA12E = 1 → Pin #26 is DA12.

= 0 → Pin #26 is P2.5.

DA11E = 1 → Pin #27 is DA11.

= 0 → Pin #27 is P2.6.

DA10E = 1 → Pin #28 is DA10.

= 0 → Pin #28 is P2.7.

* SINT0 should be 0 in this case.

(Rev 1.8)

2.

2.1 Internal Special Function Registers (SFR)

SFR is a group of registers that is the same as standard 8051.

2.2 Internal RAM

There is a 384 bytes RAM in MTV112E. The first portion of the RAM area contains
setting PSW.1=0; the second portion of the RAM area contains 128 bytes, accessible by setting PSW.1=1.

2.3 External Special Function Registers (XFR)

XFR is a group of registers allocated in the 8051 external RAM area. Most of the registers are used for
monitor control or PWM DAC. The program can initialize Ri value and use "MOVX" instruction to access
these registers.

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MTV112E Revision 1.8 05/18/2001

MYSON

Each D/A converter's output pulse width is controlled by an 8-bit register in XFR. The frequency of these

Xtal frequency/253 or Xtal frequency/256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH

WCLR

WDT2

WDT1

WDT0

MTV112E

TECHNOLOGY

FFH

80H
7FH

00H

3. PWM DAC

outputs is
to the DAC register generates stable high output. If DIV253=0, the output will pulse low at least once even if
the DAC register's content is FFH. Writing 00H to the DAC register generates stable low output.

Accessible by indirect

addressing only.

The value of PSW.1 =

both 0 and 1.

(Using MOV A, @Ri

instruction)

Accessible by direct

and indirect

addressing.

PSW.1=0

Accessible by direct

Accessible by direct

SFR

addressing.

and indirect
addressing.

PSW.1 =1

FFH

00H

XFR

Accessible by indirect

external RAM

addressing.

(Using MOVX A, @Ri

Instruction.)

(Rev 1.8)

reg name

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8

DA9
DA10
DA11
DA12
DA13

WDT

addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

20h (r/w)
21h (r/w) DA1
22h (r/w) DA2
23h (r/w)
24h (r/w) DA4
25h (r/w) DA5
26h (r/w) DA6
27h (r/w)
28h (r/w) DA8
29h (r/w) DA9

2Ah (r/w)
2Bh (r/w)
2Ch (r/w)
2Dh (r/w)

80h WEN

DA0 (r/w) : The output pulse width control for DA0.
DA1 (r/w) : The output pulse width control for DA1.
DA2 (r/w) : The output pulse width control for DA2.
DA3 (r/w) : The output pulse width control for DA3.
DA4 (r/w) : The output pulse width control for DA4.
DA5 (r/w) : The output pulse width control for DA5.
DA6 (r/w) : The output pulse width control for DA6.
DA7 (r/w) : The output pulse width control for DA7.
DA8 (r/w) : The output pulse width control for DA8.
DA9 (r/w) : The output pulse width control for DA9.
DA10 (r/w) : The output pulse width contro l f or DA10.

DA0

DA3

DA7

DA10b7DA10b6DA10b5DA10b4DA10b3DA10b2DA10b1DA10
DA11b7DA11b6DA11b5DA11b4DA11b3DA11b2DA11b1DA11
DA12b7DA12b6DA12b5DA12b4DA12b3DA12b2DA12b1DA12
DA13b7DA13b6DA13b5DA13b4DA13b3DA13b2DA13b1DA13

b7
b7
b7
b7
b7
b7
b7
b7
b7
b7

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9

b6
b6
b6
b6
b6
b6
b6
b6
b6
b6

DA0

b5

DA1

b5

DA2

b5

DA3

b5

DA4

b5

DA5

b5

DA6

b5

DA7

b5

DA8

b5

DA9

b5

CLRDDC

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9

DIV253 X

b4
b4
b4
b4
b4
b4
b4
b4
b4
b4

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9

b3
b3
b3
b3
b3
b3
b3
b3
b3
b3

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9

DA0

b2

DA1

b2

DA2

b2

DA3

b2

DA4

b2

DA5

b2

DA6

b2

DA7

b2

DA8

b2

DA9

b2

MTV112E Revision 1.8 05/18/2001

b1
b1
b1
b1
b1
b1
b1
b1
b1
b1

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9

b0
b0
b0
b0
b0
b0
b0
b0
b0
b0

b0
b0
b0
b0

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MYSON

The PWM DAC output frequency is
The PWM DAC output frequency is

4.2 H/V Frequency Counter

VSYNC/CVSYNC period when VSYNC/CVSYNC is present or continuously updated when VSYNC/CVSYNC

MTV112E

TECHNOLOGY

DA11 (r/w) : The output pulse width contro l f or DA11.
DA12 (r/w) : The output pulse width contro l f or DA12.
DA13 (r/w) : The output pulse width contro l f or DA13.
WDT (w) : Watchdog timer & special control bit.
DIV253 = 1 →

= 0 →

*1. All D/A converters are centered with value 80h after power-on.

4. H/V SYNC Proces sin g

The H/V SYNC processing block performs the functions of composite signa l separation, SYNC input
presence check, frequency counting, and polarity detection and control, as well as the protection of VBLANK
output while VSYNC speeds up to a high DDC communication clock rate. The present and frequency
function block treat any pulse less than one OSC period as noise.

4.1 Composite SYNC Separation
MTV112E continuously monitors the input HSYNC. If the vertical SYNC pulse can be extracted from the
input, a CVpre flag is set and the user can select the extracted "CVSYNC" for the source of polarity check,
frequency count and VBLANK. The CVSYNC will have a 10-16 us delay compared to the original signal. The
delay depends on the OSC frequency and composite mix method.

Xtal frequency/253.
Xtal frequency/256.

(Rev 1.8)

MTV112E can discriminate HSYNC/VSYNC frequency and saves the information in XFRs. The 15-bit
Hcounter counts the time of the 64xHSYNC period, but only 11 upper bits are loaded into the
HCNTH/HCNTL latch. The 11-bit output value is {2/H-Freq} / {1/OSC-Freq}, updated once per

is not present. The 14-bit Vcounter counts the time between 2 VSYNC pulses, but only 9 upper bits are
loaded into the VCNTH/VCNTL latch. The 9-bit output value is {1/V-Freq} / {512/OSC-Freq}, updated every
VSYNC/CVSYNC period. An extra overflow bit indicates the condition of the H/V counter overflow. The
VFchg/HFchg interrupt is active when VCNT/HCNT value changes or overflows. Tables 4.2.1 and 4.2.2
show the HCNT/VCNT value under the operations of 8MHz and 12MHz.

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MTV112E Revision 1.8 05/18/2001