MYSON MTV048N Datasheet
MYSON
SERIAL DATA
VERTICAL
HORIZONTAL
DISPLAY & ROW
(RAM)
FONTS ROM &
WINDOWS & FRAME
LUMINANCE & BORDER
GENERATOR
HFLB
VFLB
VCORPSSB
SCK
SDA
ROUT
GOUT
BOUT
FBKG
INT
SHADOW
WINDOW
MTV048
TECHNOLOGY
(Rev 0.9)
On-Screen-Display Controller
for CRT/LCD Monitor
FEATURES
• Software control for CRT/LCD applications.
• Full screen self-test pattern generator with programmable pattern color.
• On-chip PLL circuitry (CRT) or external pixel clock input (LCD) up to 150 MHz.
• Horizontal SYNC input up to 150 KHz.
• Programmable horizontal resolutions up to 1524 dots per display line.
• Full screen display consists of 15 (rows) by 30 (columns).
• 12x16 or 12x18 dot matrix selection.
• A total of 384 fonts including 360 standard fonts, 16 multi-color fonts and 8 user fonts.
• 8 color selections for character foreground, background and window color.
• Character button boxes with programmable box length.
• Character bordering, shadowing and blinking effect for display.
• Full-screen character double width control.
• Double character height and/or width control per row.
• Programmable positioning for display screen center.
• Row to row spacing control per row to avoid expansion distortion.
• 4 programmable background windows with multi-level operation and programmable shadow width/height/color.
• Software clear bit for full-screen erasing.
• Programmable adaptive approach to handle H, V sync collision automatically by hardware.
• Fade-in/fade-out or blend-in/blend-out effects.
• Compatible with SPI bus or I
• 5V or 3.3V power supply.
• 16-pin PDIP/SOP package.
2
C interface with address 7AH (slave address is mask option).
GENERAL DESCRIPTION
MTV048 is designed for monitor applications to display built-in fonts onto monitor screens. The display operation
occurs by transferring data and controls information from the micro controller to RAM through a serial data
interface. It can execute a full-screen display automatically, as well as specific functions such as character
background, bordering, shadowing, blinking, double height and width, font-by-font color control, button boxes,
frame positioning, frame size control by character height and row-to-row spacing, horizontal display resolution, fullscreen erasing, fade-in/fade-out effect, windowing effect, shadowing on window and full-screen self-test pattern
generator.
MTV048 provides 384 fonts including 360 standard fonts, 16 multi-color fonts and 8 user fonts and 2 font sizes,
12x16 or 12x18 for more efficacious applications. The full OSD menu is formed by 15 rows x 30 columns, which
can be positioned anywhere on the monitor screen by changing vertical or horizontal delay.
BL OCK DIAGRAM
9 RAMADDR
INTERFACE
DISPLAY CONTROL
DISPLAY CONTROL
R/WEN
8 DATA
ROW
COLUMN
CONTROL
REGISTERS
CONTROL
9 ROMADDR
USER FONTS RAM
LUMA
COLOR ENCODER
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Rev 0.9 - 1 - 2001/03/15
PHASE LOCK LOOP
VCLK
MYSON
This ground pin is used for internal analog circuitry.
inside. The frequency of XIN must be the integral time of pin HFLB.
internal display registers and control registers. It has an internal pull-
Positive 5V / 3.3V DC supply for internal
MTV048N-xx
MTV048
TECHNOLOGY
1.0 PIN CONNECTION
VSSA
VCO/XIN
RP/NC
VDDA
HFLB
SSB
SDA
SCK
1
2
3
4
5
6
7
8
2.0 PIN DESCRIPTIONS
Name I/O Pin NO. Descriptions
VSS - 1
VCO / XIN I/O 2
Analog ground .
Voltage contr ol osc i l lato r (bit LCD = 0). This pin is used to control
the internal oscillator frequency by DC voltage input from external
low pass filter.
Pixel clo c k in p u t (bit LCD = 1). This is a clock input pin. MTV048
can be driven by an external pixel clock source for all the logic
16
15
14
13
12
11
10
9
VSS
ROUT
GOUT
BOUT
FBKG
V33CAP
VFLB
VDD
(Rev 0.9)
RP / NC I/O 3
VDDA - 4
HFLB I 5
SSB I 6
SDA I 7
SCK I 8
VDD - 9
VFLB I 10
Bias Resis t o r (bi t LCD = 0). The bias resistor is used to regulate
the appropriate bias current for internal oscillator to resonate at
specific dot frequency.
No conn ect i o n (bit LCD = 1).
Analog power supply. Positive 5V / 3.3V DC supply for internal
analog circuitry. And a 0.1uF decoupling capacitor should be
connected across to VDDA and VSSA.
Horizontal input . This pin is used to input the horizontal
synchronizing signal. It is a leading edge triggered and has an
internal pull-up resistor.
Serial int erf ace enable. It is used to enable the serial data and is
also used to select the operation of I2C or SPI bus. If this pin is left
floating, I2C bus would be enabled. Otherwise the SPI bus is
enabled.
Serial data inpu t . The external data transfer through this pin to
up resistor.
Serial clock inp ut . The clock-input pin is used to synchronize the
data transfer. It has an internal pull-up resistor.
Digital power supply.
digital circuitry and a 0.1uF decoupling capacitor should be
connected across to VDD and VSS.
Vertic al input . This pin is used to input the vertical synchronizing
signal. It is leading triggered and has an internal pull-up resistor.
Rev 0.9 - 2 - 2001/03/15
MYSON
directly when DC supply = 3.3V.
This ground pin is used for internal digital circuitry.
While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a va lid transmission
C bus operation is only selected when SSB pin is left floating. And a valid transmission should start writing
MTV048
TECHNOLOGY
V33CAP I/O 11
FBKG O 12
BOUT O 13
GOUT O 14
ROUT O 15
VSS - 16
3.3V Regulator Capacitor con n ect io n . Connect a decoupling
capacitor to VSS pin when DC supply = 5V, or connect to 3.3V
Fast Blanking outp ut . It is used to cut off external R, G, B signals
of VGA while this chip is displaying characters or windows.
Blue color output . It is a blue color video signal output. And it is a
DAC output if bit LCD = 0 or CMOS output if bit LCD =1.
Green color outp ut . It is a green color video signal output. And it is
a DAC output if bit LCD = 0 or CMOS output if bit LCD =1.
Red color outp ut . It is a red color video signal output. And it is a
DAC output if bit LCD = 0 or CMOS output if bit LCD =1.
Digital ground .
(Rev 0.9)
3.0 FUNCTIONAL DESCRIPTIONS
3.1 Serial Data Interf ac e
The serial data interface receives data transmitted from an external controller. T here are 2 types of buses,
which can be accessed through the serial data interface. One is SPI bus and the other is I2C bus.
3.1.1 SPI bus
should start pulling SSB to "low" level, enabling MTV048 to receiving mode, and retain at "low" level
till the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.
SSB
SCK
SDA
There are three transmission formats, shown as below:
Format (a) R - C - D → R - C - D → R - C - D …..
Format (b) R - C - D → C - D → C - D → C - D …..
Format (c) R - C - D → D → D → D → D → D …..
Where R=Row address, C=Column address, D=Display data
MSB LSB
First byte Last byte
FIGURE 1. Data Transm i s s i o n Prot o c ol (SPI)
3.1.2 I2C bus
2
I
the slave address 7AH to MTV048. The protocol is shown in Figure 2.
Rev 0.9 - 3 - 2001/03/15
MYSON
Where S=Slave address, R=Row address, C=Column address, D=Display data
ab
c
ab
c
ab
c
There are 3 types of data, which should be accessed through the serial data interface. One is ADDRESS
bytes of display registers,
The bit6 of row address is used to distinguish display registers and user fonts RAM data
respectively. Bit5 of row address for display register is used to distinguish ADDRESS byte when it is set to
MTV048
TECHNOLOGY
(Rev 0.9)
SCK
SDA
START ACK
There are three transmission formats for I2C write mode, shown as below:
Format (a) S - R - C - D → R - C - D → R - C - D …..
Format (b) S - R - C - D → C - D → C - D → C - D …..
Format (c) S - R - C - D → D → D → D → D → D …..
Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and
Display data (D). Format (a) is suitable for updating small amount of data, which will be allocat ed with a
different row address and column address. Format (b) is recommended for updating data that has the same
row address but a different column address. Massive data updating or full screen data chan ge should use
format (c) to increase transmission efficiency. The row and column address will be incremented
automatically when the format (c) is applied. Furthermore, the undefined locations in display or user fonts
RAM should be filled with dummy data.
B7 B6 B0 B7 B0
first byte
second byte last byte
FIGURE 2. Data Transm iss i o n Pro t o c o l (I2C)
ACK STOP
TABL E 1. The Configuration of Transmission Formats
Address b7 b6 b5 b4 b3 b2 b1 b0 Format
Row 1 0 0 R4 R3 R2 R1 R0 a,b,c
Address Bytes
of Disp lay Reg.
Attribu te Bytes
of Disp lay Reg.
User Fonts
bytes of display registers, another is ATTRIBUTE
RAM data. The protocols are all the same except the bit6 and bit5 of row address and the bit5 of column
address. The MSB (b7) is used to distinguish row and column addresses when transferring data from
external controller.
and the bit6 of column address is used to differentiate the column address for format (a), (b) and format (c)
"0" and ATTRIBUTE byte when it is set to "1". And at address bytes, bit5 of colum n address is the MSB
(bit8) and data bytes are the 8 LSB (bit7~bit0) of disp l ay fon t s address to save half MCU memory for
true 392 fonts display. So each one of the 384 fonts can be displayed at the same time. See Table 1. And for
format (c), since D8 is filled while program column address of address bytes, the continued d ata will be the
same bank of upper 128 fonts or lower 256 fonts until program column address is of address bytes again.
Column
Column
Data D7 D6 D5 D4 D3 D2 D1 D0 a,b,c
Row 1 0 1 R4 R3 R2 R1 R0 a,b,c
Column
Column
Data D7 D6 D5 D4 D3 D2 D1 D0 a,b,c
Row 1 1 - - - R2 R1 R0 a,b,c
Column
Column
Data D7 D6 D5 D4 D3 D2 D1 D0 a,b,c
0 0
0 1
0 0 x C4 C3 C2 C1 C0 a,b
0 1 x C4 C3 C2 C1 C0 c
0 0 C5 C4 C3 C2 C1 C0 a,b
0 1 C5 C4 C3 C2 C1 C0 c
D8
D8
C4 C3 C2 C1 C0 a,b
C4 C3 C2 C1 C0 c
and the other is user fonts
Rev 0.9 - 4 - 2001/03/15
MYSON
3.2 Address Bus Admin ist rator
The external data write through serial data interface to registers must be synchronized by inter-
The vertical display control can generate different vertical display sizes for most display standards in current
( VERTD * 4 + 1 ) * H Where H = one horizontal line display time
MTV048
TECHNOLOGY
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to
format (a), but not from format (c) back to format (a) and (b). The alternation between transmission formats is
configured as the state diagram shown in Figure 3 .
FIGURE 3. Transmi s s i o n State Diagram
(Rev 0.9)
The administrator manages bus address arbitration of internal registers or user fonts RA M during external
data write in.
nal display timing. In addition, the administrator also provides automatic increment to address bus when
external write using format (c).
3.3 Vertical Display Cont ro l
monitors. The vertical display size is calculated with the information of double character he ight bit (CHS),
vertical display height control register (CH6-CH0). The algorithms of repeating character line display are
shown as Table 2 and Table 3. The range of programmable vertical size is 270 lines to 2130 lines maximum.
The vertical display center for full screen display could be figured out according to the information of vertical
starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB
is calculated by using the following equation:
Vertical delay time =
TABLE 2. Repeat Line Weight of Character
CH6 – CH0 Repeat Line Weight
CH6, CH5 = 11 +18*3
CH6, CH5 = 10 +18*2
CH6, CH5 = 0x +18
CH4 = 1 +16
CH3 = 1 +8
CH2 = 1 +4
CH1 = 1 +2
CH0 = 1 +1
Rev 0.9 - 5 - 2001/03/15
MYSON
The horizontal display control is used to generate control timing for horizontal display based on double char-
Where P = One XIN pixel dis
input is not present to MTV048, the PLL will generate a specific system clock, approximately 2.5MHz, by a
has its corresponding character address on ADDRESS byte
only even column characters could be displayed on screen and the odd colum n characters will be hidden.
MTV048
TECHNOLOGY
TABLE 3. Repeat Line Number of Character
Repeat Line #Repeat Lin e
Weight
+1 - - - - - - - - v - - - - - - - - +2 - - - - v - - - - - - - v - - - - +4 - - v - - - v - - - v - - - v - - +8 - v - v - v - v - v - v - v - v - -
+16 - v v v v v v v v v v v v v v v v +17 v v v v v v v v v v v v v v v v v +18 v v v v v v v v v v v v v v v v v v
Note: “v” means the nth line in the character would be repeated once, while “-“ means the nth line in the
character would not be repeated.
3.4 Horizont al Display Contro l
acter width bit (CWS), horizontal positioning register (HORD), horizontal resolution register (HORR), and
HFLB input. A horizontal display line consists of (HORR*12) dots which include 360 dots for 30 display characters and the remaining dots for blank region. The horizontal delay starting from HFLB leading edge is
calculated by using the following equation:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
(Rev 0.9)
For CRT: Horizontal delay time = ( HORD * 6 + 49) * P - phase error detection pulse width
Where P = One pixel display time = One horizontal line display time / (HORR*12)
For LCD: Horizontal delay time = ( HORD * 6 + 49) * P
play time
3.5 Phase lock loo p (PLL)
On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB and horizontal resolution register (HORR). The frequency of VCLK is determined by the following equation:
VCLK Freq. = HFLB Freq. * HORR * 12
The VCLK frequency ranges from 6MHz to 150MHz selected by (VCO1, VCO0). In addition, when HFLB
built-in oscillator to ensure data integrity.
3.6 Displ ay & Row Contro l Registers
The internal RAM contains display and row control registers. The display registers ha ve 450 locations, which
are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure 4. Each display register
, its corresponding background color, 1 blink bit
and its corresponding color bits on ATTRIBUTE bytes. The row control register is allocated at column 30 for
row 0 to row 14, it is used to set character size to each respective row. If double width character is chosen,
Rev 0.9 - 6 - 2001/03/15
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