MYSON MTV038N20, MTV038N Datasheet

ut notice.

No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.

MYSON

GENERAL DESCRIPTION

among HFLB, VFLB, RIN, GIN and BIN for auto sizing

Full-screen display consists of 15 (rows) by 30 (columns)

Character bordering, shadowing and blinking effect.

resolution, full-screen erasing, fade-in/fade-out effect, win-

menu is formed by 15 rows x 30 columns, which can be

MTV038

TECHNOLOGY

(Revision 1.1)

On-Screen Display Controller for CRT/LCD Monitor

FEATURES

• Horizontal SYNC input up to 150 KHz.

• On-chip PLL circuitry or external pixel clock input up to
150 MHz.

• Software control for CRT/LCD applications.

• Programmable R,G,B input level for timing measurement

.

• Full screen self-test pattern generator.

• Programmable Hor. resolutions up to 1524 dots per line.

•

• Two font size 12x16 or 12x18 dot matrix per character.

• True totally 544 mask ROM fonts including 512 standard
fonts and 32 multi-color fonts.

• Character button boxes with programmable box length.

• Double character height and/or width control.

• Programmable positioning for display screen center.

•

•

Character (per row) and window intensity control

.

• Row to row spacing control to avoid expansion distortion.

• 4 programmable windows with multi-level operation.

• Shadowing on windows with programmable shadow
width/height/color.

• Programmable adaptive approach to handle H, V sync
collision automatically by hardware.

• Software clears bit for full-screen erasing.

• Fade-in/fade-out or blending-in/blending-out effects.

• Compatible with SPI bus or I2C interface with slave
address 7AH/7BH (slave address is mask option).

• 16-pin or 20-pin PDIP/SOP package.

MTV038 is designed for CRT/LCD monitor applications
to display built-in characters or fonts onto monitor screens.
The display operation occurs by transferring data and con­trol information from the micro-controller to RAM through a
serial data interface. It can execute full-screen display
automatically, as well as specific functions such as charac­ter background, bordering, shadowing, blinking, double
height and width, font by font color control, character but­ton boxes, frame positioning, frame size control by charac­ter height and row-to-row spacing, horizontal display

dowing effect, shadowing on window and full-screen self­test pattern generator.

MTV038 provides 544 fonts including 512 standard
fonts and 32 multi-color fonts and 2 font sizes, 12x16 or
12x18 for more efficacious applications. The full OSD

positioned anywhere on the monitor screen by changing
vertical or horizontal delay.

The auto sizing video measurement module measure
the timing relationship among HFLB, VFLB, and R, G, BIN
with 12-bit resolution at the speed related to the OSD pixel
clock. And the R, G, BIN input level can be programming
by software. MCU can get the measurement data, active

video, front porth and back porth, through I2C bus read/
write operation to keep the appropriate display size and
center.

BL OCK DIAGRAM

SSB

SCK

SDA

VFLB

HFLB

VCO

RIN
GIN
BIN

8

SERIAL DATA

INTERFACE

ARWDB

ADDRESS BUS

HDREN

VDREN

ADMINISTRATOR

NROW

VERTICAL

7

VSP

HSP

RP

CHS

VERTD

HORD

CH

8

8

DISPLAY

CONTROL

HORIZONTAL

DISPLAY CONTROL

PHASE LOCK LOOP

AUTO SIZING

MEASUREMENT

DATA

9

ROW, COL
ACK

5

RCADDR

9

DADDR

9

FONTADDR

5

WINADDR

5

PWMADDR

5

LPN
NROW
VDREN

ARWDB
HDREN

VCLKX

8

DATA

8 LUMAR

DATA

DISPLAY & ROW

REGISTERS

8

CHARACTER ROM

5

LUMINANCE &

GENERATOR

8

WINDOWS &

CH

CONTROL

WRWGWB

COLOUR

ENCODER

POWER ON

CONTROL

BORDGER

FRAME

FBKGC

BLANK

RESET

DATA

LPN

CWS

VCLKS

8

VERTD

8
7

LUMAR
LUMAG
LUMAB

VCLKX

PRB

CWS

CHS

DATA

HORD

BLINK

LUMAG
LUMAB
BLINK

8

CRADDR

LUMA
BORDER

BSEN
SHADOW
OSDENB
HSP
VSP

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification witho

VDD

VSS

VDDA

VSSA

ROUT
GOUT
BOUT
FBKG
HTONE

Revision 1.1 -1- 2001/8/21

MYSON

Analog ground.

This is a clock input pin.

time of pin HFLB.

Analog pow er supply.

Positive 5 V DC supply for internal

This pin is used to input the horizontal syn-

Serial data in put .

internal display registers and control registers. It has an inter-

MTV038

TECHNOLOGY

1.0 PIN CONNECTION

SSB
SDA
SCK

Pin No.

16 20

1
2
3
4
5
6
7
8

VSSA

VCO/XIN

RP/NC

VDDA

HFLB

2.0 PIN DESCRIPTIONS

Name I/O

VSSA - 1 1

VCO/XIN I/O 2 2

(Revision 1.1)

VSS

16

ROUT

15

GOUT

14

BOUT

13

FBKG

12

MTV038N-xx

INT

11

VFLB

10

VDD

9

VSSA

VCO/XIN

RP/NC

VDDA

HFLB

SSB
SDA
SCK

RIN
GIN

1
2
3
4
5
6
7
8
9
10

MTV038N20-xx

Des criptio ns

This ground pin is used to internal analog cir-

cuitry.
Vo l tag e Contro l Osci l l ato r (bit LCD= 0). This pin is used to

control the internal oscillator frequency by DC voltage input
from external low pass filter.

Pixel Cloc k Inp u t (bit LCD= 1).

MTV038 can be driven by an external pixel clock source for all
the logics inside. The frequency of XIN must be the integral

VSS

20

ROUT

19

GOUT

18

BOUT

17

FBKG

16

INT

15

VFLB

14

VDD

13

NC

12

BIN

11

Bias Resis t o r (bit LCD= 0). The bias resistor is used to regu-

RP/NC I/O 3 3

late the appropriate bias current for internal oscillator to reso­nate at specific dot frequency.

No conn ect i o n (bit LCD= 1).

VDDA - 4 4

analog circuitry. And a 0.1uF decoupling capacitor should be
connected across to VDDA and VSSA.

Horizontal input .

HFLB I 5 5

chronizing signal. It is a leading edge triggered and has an
internal pull-up resistor.

Serial interf ace enable. It is used to enable the serial data

SSB I 6 6

and is also used to select the operation of I2C or SPI bus. If
this pin is left floating, I2C bus is enabled, otherwise the SPI
bus is enabled.

The external data transfer through this pin to

SDA I 7 7

nal pull-up resistor.

Revision 1.1 -2- 2001/8/21

MYSON

3.0 FUNCTIONAL DESCRIPTIONS

3.1 SERIAL DATA INTERFACE

While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission

should be starting from pulling SSB to "low" level, enabling MTV038 to receiving mode, and retain "low" level

until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.

The clock-input pin is used to synchronize

It is used for auto sizing measurement and

Green v i deo inp ut .

It is used for auto sizing measurement and

Digital power suppl y.

Positive 5 V DC supply for internal digi-

Vert ic al inpu t .

This pin is used to input the vertical synchroniz-

Intensity color output.

16-color selection is achievable by

It is used to cut off external R, G, B sig-

MTV038

TECHNOLOGY

Name I/O

SCK I 8 8

RIN I - 9

GIN I - 10

BIN I - 11

NC - - 12 No conn ection .

VDD - 9 13

VFLB I 10 14

INT O 1 1 15

FBKG O 12 16

BOUT O 13 17 Bl ue color outpu t. It is a blue color video signal output.
GOUT O 14 18 Green color outpu t. It is a green color video signal output.
ROUT O 15 19 Red color output . It is a red color video signal output.

VSS - 16 20

Pin No.

Des criptio ns

16 20

Serial clock inpu t.

the data transfer. It has an internal pull-up resistor.

Red video inp ut .

this signal is came from video pre-amp red output.

It is used for auto sizing measurement and

this signal is came from video pre-amp green output.

Blue video input.

this signal is came from video pre-amp blue output.

tal circuitry and a 0.1uF decoupling capacitor should be con­nected across to VDD and VSS.

ing signal. It is leading triggered and has an internal pull-up
resistor.

combining this intensity pin with R/G/B output pins.

Fast Blanking outpu t.

nals of VGA while this chip is displaying characters or win­dows.

Digital groun d. This ground pin is used to internal digital cir­cuitry.

(Revision 1.1)

The serial data interface receives data transmitted from an external controller. And there are 2 types of bus
can be accessed through the serial data interface, one is SPI bus and other is I2C bus.

3.1.1 SPI bus

Revision 1.1 -3- 2001/8/21

MYSON

C bus operation is only selected when SSB pin is left floating. And a valid transmission should be starting

Figure 2. And the auto sizing video measurement data (total 12 bytes) are read only registers and the others

are write only registers.

There are three transmission formats for I

C write mode shown as below:

And there is one transmission formats for I

C read mode shown as below:

Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and

address but a different column address. Massive data updating or full screen data change should use format

(c) to increase transmission efficiency. The row and column address will be incremented automatically when

FIGURE 2. Dat a Trans m i ssion Pro t o c ol (I

MTV038

TECHNOLOGY

SSB

SCK

SDA

There are three transmission formats shown as below:

Format (a) R - C - D -> R - C - D -> R - C - D .....

Format (b) R - C - D -> C - D -> C - D -> C - D .....

Format (c) R - C - D -> D -> D -> D -> D -> D .....

Where R=Row address, C=Column address, D=Display data

3.1.2 I2C bus

2

I
from writing the slave address 7AH(write mode), or 7BH(read mode) to MTV038. The protocol is shown in

MSB

First byte Last byte

FIGURE 1. Dat a Trans mis sio n Prot ocol (SPI)

(Revision 1.1)

LSB

SCK

B7

SDA

START STOPACK ACKFirst byte Last byteSecondbyte

Format (a) S - R - C - D -> R - C - D -> R - C - D .....

Format (b) S - R - C - D -> C - D -> C - D -> C - D .....

Format (c) S - R - C - D -> D -> D -> D -> D -> D .....

Where S=Slave address, R=Row address, C=Column address, D=Display data

Format (a) S -> D -> D -> D -> D -> D -> D -> D -> D -> D -> D -> D -> D -> D -> D -> dummy D .....

Where S=Slave address, D=Measurement data

In the I2C read mode, 14 bytes of auto sizing video measurement data will be outputed directly from byte 0 to
byte 9 and continues with dummy data until stop condition occurred when R/W bit is set to 1.

Display data (D). Format (a) is suitable for updating small amount of data which will be allocated with a differ­ent row address and column address. Format (b) is recommended for updating data that has the same row

B6

B0 B7 B0

2

2

2

C)

Revision 1.1 -4- 2001/8/21

MYSON

the format (c) is applied. Furthermore, the undefined locations in display or fonts RAM should be filled with

The Conf ig urati on of Tran sm is si on Formats

There are 2 types of data which should be accessed through the serial data interface, one is

ADDRESS

of display registers, and the other is

column addresses when transferring data from external controller. The bit6 of column address is used to dif-

ferentiate the column address for format (a), (b) and format (c) respectively. Bit5 of row address for display

of display fonts address

can be displayed at the same time (see Table 1). And for format (c), since D8 is filled while program column

address of address bytes, the continued data will be the same bank of upper 256 fonts or lower 256 fonts until

(a) and (c), but not from format (c) back to format (a) and (b). The alternation between transmission formats is

configured as the state diagram shown in Figure 3.

Addr ess Bytes

Attr ibut e Bytes

FIGURE 3. Trans m issio n State Diagram

MTV038

TECHNOLOGY

(Revision 1.1)

dummy data.

TABLE 1.

Address b7 b6 b5 b4 b3 b2 b1 b0 Format

Row 1 0 0 R4 R3 R2 R1 R0 a,b,c

of Displ ay Reg.

Column

Column

0 0 D8 C4 C3 C2 C1 C0 a,b

ab

0 1 D8 C4 C3 C2 C1 C0 c

c

Data D7 D6 D5 D4 D3 D2 D1 D0 a,b,c
Row 1 0 1 R4 R3 R2 R1 R0 a,b,c

of Displ ay Reg.

Column

Column

0 0 x C4 C3 C 2 C1 C0 a,b

ab

0 1 x C4 C3 C 2 C1 C0 c

c

Data D7 D6 D5 D4 D3 D2 D1 D0 a,b,c

bytes

ATTRIBUTE bytes of display registers, the protocols are same for all

except the bit5 of row address and the bit5 of column address. The MSB(b7) is used to distinguish row and

register is used to distinguish ADDRESS byte when it is set to "0" and ATTRIBUTE byte when it is set to "1".
And at address by tes, bit5 of col umn address is the MSB (bit 8) and data bytes are the 8 LSB (bit 7~bi t 0)

to save half MCU memory for true 512 fonts display. So each one of the 512 fonts

program column address of address bytes again.
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format

0, X

Input = b7, b6

format (a)

format (b)

COL

ab

0, 0

X, X

DA

1, X

ab

X, X

DA

format (c)

COL

X, X

c

1, X

c

0, 1

Initiate

1, X

ROW

0, 0

0, 1

Revision 1.1 -5- 2001/8/21

MYSON

3.2 Address bus adminis tr ator

The administrator manages bus address arbitration of internal registers or user fonts RAM during external

data write in. The external data write through serial data interface to registers must be synchronized by inter-

nal display timing. In addition, the administrator also provides automatic increment to address bus when exter-

nal write using format (c).

3.3 Verti cal di sp l ay cont r ol

The vertical display control can generates different vertical display sizes for most display standards in current

cal display height control register(CH6-CH0).The algorithm of repeating character line display are shown as

The vertical display center for full screen display could be figured out according to the information of vertical

character would not be repeated.

3.4 Hori zontal dis pl ay contr o l

The horizontal display control is used to generate control timing for horizontal display based on double char-

HFLB input. A horizontal display line consists of (HORR*12) dots which include 360 dots for 30 display char-

Repeat Li n e Weigh t

MTV038

TECHNOLOGY

monitors. The vertical display size is calculated with the information of double character height bit(CHS), verti­Table 2 and Table 3. The programmable vertical size range is 270 lines to maximum 2130 lines.

starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB,
is calculated with the following equation:

Vertical delay time = ( VERTD * 4 + 1 ) * H Where H = one horizontal line display time

TA B LE 2. Repeat Li n e Weight of Character

CH6 - CH0

CH6,CH5=11 +18*3
CH6,CH5=10 +18*2
CH6,CH5=0x +18

CH4=1 +16
CH3=1 +8
CH2=1 +4
CH1=1 +2
CH0=1 +1

(Revision 1.1)

TA B LE 3. Repeat Line Number of Charact er

Repeat Line

Weight

+1 - - - - - - - - v - - - - - - - - ­+2 - - - - v - - - - - - - v - - - - ­+4 - - v - - - v - - - v - - - v - - -

+8 - v - v - v - v - v - v - v - v - ­+16 - v v v v v v v v v v v v v v v v ­+17 v v v v v v v v v v v v v v v v v ­+18 v v v v v v v v v v v v v v v v v v

Note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the

acter width bit (CWS), horizontal positioning register (HORD), horizontal resolution register (HORR), and

Revision 1.1 -6- 2001/8/21

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Repeat Lin e #

MYSON

acters and the remaining dots for blank region. The horizontal delay starting from HFLB leading edge is calcu-

The VCLK frequency ranges from 6MHz to 150MHz selected by (VCO1, VCO0). In addition, when HFLB input

is not present to MTV038, the PLL will generate a specific system clock, approximately 2.5MHz, by a built-in

3.6 Disp l ay & Row contr ol regist ers

are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure 4 and Figure 5. Each dis-

play register has its corresponding character address on ADDRESS byte, its corresponding background color,

button box format, 1 blink bit and its corresponding color bits on ATTRIBUTE bytes. The row control register is

and set character size to each respective row. If double width character is chosen, only even column charac-

30

of DISPLAY REGISTERS

A TTRIBUTE

CRTL REG

MTV038

TECHNOLOGY

lated with the following equation,
For CRT: Horizontal delay time = ( HORD * 6 + 49) * P - phase error detection pulse width

Where P = One pixel display time = One horizontal line display time / (HORR*12)

For LCD: Horizontal delay time = ( HORD * 6 + 49) * P

Where P = 1 XIN pixel display time

3.5 Phase loc k l o o p (PLL)

On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB and horizontal resolution reg­ister (HORR). The frequency of VCLK is determined by the following equation:

VCLK Freq = HFLB Freq * HORR * 12

oscillator to ensure data integrity.

(Revision 1.1)

The internal RAM contains display and row control registers. The display registers have 450 locations which

allocated at column 30 for row 0 to row 14 of attribute bytes, it is used to select background color or button box
ters could be displayed on screen and the odd column characters will be hidden.

ROW # COLUMN #

0 1 28 29

0
1

CHARACTER ADDRESS BYTES

13
14

FIGURE 4. Ad d r ess By t es of Disp l ay Regist ers Memory Map

ROW

31

R
E
S
E
R
V
E
D

Revision 1.1 -7- 2001/8/21

MYSON

CRADDR - Define ROM character address from address 0 to 511.

Row Control Registers, (Row 0 - 14)

BGINT - The displayed character/symbol background color intensity control to the respective row. Setting this

bit to 0 means low intensity in this row. 16 character background color is achievable by this bit.

FGINT - The displayed character/symbol foreground color intensity control to the respective row. Setting this

bit to 0 means low intensity in this row. 16 character foreground color is achie vable by this bit.

CHARACTER ATTRIBUTE BYTES

of DISPLAY REGISTERS

WINDOW1 ~ WINDOW4

FRAME CRTL REG

WINDOW SHADOW COLOR

MTV038

TECHNOLOGY

ROW # COLUMN #

0 1 28 29 30 31

0
1

13
14

COLUMN#

ROW 15

ROW 16

0 11 12 22 23 31

COLUMN#

0 1 2 4 5 31

FRAME CRTL REG RESERVED

FIGURE 5. Attri b ut e Byt es of Disp l ay Registers Memory Map

(Revision 1.1)

RESERVED

RESERVED

ADDRESS BYTES:
Address registers,

b8 b7 b6 b5 b4 b3 b2 b1 b0

CRADDR

MSB LSB

COLN 30

BOX - Select BGR, BGG, BGB or B2, B1, B0 of attributes bytes to the respective row.

= 0 -> Background color bits BGR, BGG, BGB are selected.
= 1 -> Button box bits B2, B1, B0 are selected.

CHS - Define double height character to the respective row.

b7 b6 b5 b4 b3 b2 b1 b0

- - - BOX BGINT FGINT CHS CWS

CWS - Define double width character to the respective row.

Revision 1.1 -8- 2001/8/21