MYSON MTV030N202, MTV030N24, MTV030N201, MTV030N Datasheet

ut notice.

No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.

TECHNOLOGY

GENERAL DESCRIPTION

Full-screen display consists of 15 (rows) by 30 (columns)

Character bordering, shadowing and blinking effect.

5-channel/8-bit PWM D/A converter output.

and full-screen self-test pattern generator.

menu is formed by 15 rows x 30 columns, which can be

at the speed related to the OSD resolution. MCU can get

appropriate display size and center.

On-Screen Display with Auto-Sizing Controller

FEATURES

• Horizontal SYNC input up to 150 KHz.

• On-chip PLL circuitry up to 150 MHz.

• Minimum timing measurement among HFLB, VFLB, RIN,
GIN and BIN for auto sizing.

• Full screen self-test pattern generator.

• Programmable Hor. resolutions up to 1524 dots per line.

•

• Two font size 12x16 or 12x18 dot matrix per character.

• True totally 512 mask ROM fonts including 496 standard
fonts and 16 multi-color fonts.

• Double character height and/or width control.

• Programmable positioning for display screen center.

•

• Programmable character height (18 to 71 lines) control.

• Row to row spacing control to avoid expansion distortion.

• 4 programmable windows with multi-level operation.

• Shadowing on windows with programmable shadow
width/height/color.

• Programmable adaptive approach to handle H, V sync
collision automatically by hardware.

• Software clears bit for full-screen erasing.

• Fade-in/fade-out or blending-in/blending-out effects.

•

• Compatible with SPI bus or I2C interface with slave
address 7AH/7BH (slave address is mask option).

• 16-pin, 20-pin or 24-pin PDIP package.

MTV030MYSON

MTV030 is designed for monitor applications to display
built-in characters or fonts onto monitor screens. The dis­play operation occurs by transferring data and control infor­mation from the micro-controller to RAM through a serial
data interface. It can execute full-screen display automati­cally , as well as specific functions such as character back­ground, bordering, shadowing, blinking, double height and
width, font by font color control, frame positioning, frame
size control by character height and row-to-row spacing,
horizontal display resolution, full-screen erasing, fade-in/
fade-out effect, windowing effect, shadowing on window

MTV030 provides true 512 fonts including 496 standard
fonts and 16 multi-color fonts and 2 font sizes, 12x16 or
12x18 for more efficacious applications. So each one of the
512 fonts can be displayed at the same time. The full OSD

positioned anywhere on the monitor screen by changing
vertical or horizontal delay.

The auto sizing video measurement module measure
the timing relationship among HFLB, VFLB, and R, G, BIN

the measurement data, active video, front porth and back
porth, through I2C bus read/write operation to keep the

BL OCK DIAGRAM

SSB

SCK

SDA

VFLB

HFLB

VCO

PWM0
PWM1
PWM2
PWM3
PWM4

8

SERIAL DATA

INTERFACE

ARWDB

ADDRESS BUS

HDREN
VDREN

ADMINISTRATOR

NROW

VERTICAL

7

VSP

HSP

RP

CHS

VERTD

HORD

CH

8

8

DISPLAY

CONTROL

HORIZONTAL

DISPLAY CONTROL

PHASE LOCK LOOP

DATA

9

ROW, COL
ACK

5

RCADDR

9

DADDR

9

FONTADDR

5

WINADDR

5

PWMADDR

5

LPN
NROW
VDREN

ARWDB
HDREN

VCLKX

PWM D/A

CONVERTER

POWER ON RESET

PRB

8

DATA

8 LUMAR

DATA

DISPLAY & ROW

REGISTERS

8

CHARACTER ROM

5

LUMINANCE &

GENERATOR

8

WINDOWS &

CH

CONTROL

WRWGWB

ENCODER

8

AUTO SIZING

CONTROL

BORDGER

FRAME

FBKGC

BLANK

COLOUR

DATA

LPN

CWS

VCLKS

8

VERTD
8
7

LUMAR
LUMAG
LUMAB

VCLKX

DATA

CWS

CHS

DATA

HORD

BLINK

MEASUREMENT

LUMAG
LUMAB
BLINK

8

CRADDR

LUMA
BORDER

BSEN
SHADOW
OSDENB
HSP
VSP

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification witho

VDD

VSS

VDDA

VSSA

ROUT
GOUT
BOUT
FBKG
HTONE

RIN
GIN
BIN

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TECHNOLOGY

Analog ground .

Vol t age Control Oscil l ato r.

low pass filter.

Analog pow er supply.

Positive 5 V DC supply for internal

This pin is used to input the horizontal syn-

1.0 PIN CONNECTION

MTV030MYSON

VSSA

VCO

RP

VDDA

HFLB

SSB
SDA
SCK

VSSA

VCO

RP

VDDA

HFLB

SSB
SDA
SCK

RIN
GIN

20

VSS

19

ROUT

18

GOUT

17

BOUT

16

FBKG

15

INT
VFLB

14

MTV030N201-xx

MTV030N24-xx

VDD

13

PWM3

12

PWM2

11

24

VSS

23

ROUT

22

GOUT
BOUT

21

FBKG

20

INT

19

VFLB

18

VDD

17

PWM4

16

PWM3

15

PWM2

14

PWM1

13

VCO

RP

SSB
SDA
SCK

VCO

RP

SSB
SDA
SCK

RIN
GIN

BIN

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8

1
2
3
4
5
6
7
8
9
10

16

VSS

15

ROUT

14

GOUT

13

BOUT

12

FBKG

MTV030N-xx

11

INT
VFLB

10

VDD

9

20

VSS

19

ROUT

18

GOUT

17

BOUT

16

FBKG

15

INT
VFLB

14

MTV030N202-xx

VDD

13

NC

12

BIN

11

VSSA

VDDA

HFLB

PWM0
PWM1

VSSA

VDDA

HFLB

PWM0

2.0 PIN DESCRIPTIONS

Name I/O

N16 N201 N202 N24

VSSA - 1 1 1 1

VCO I/O 2 2 2 2

RP I/O 3 3 3 3 Bias Resistor. The bias resistor is used to regulate the appro-

VDDA - 4 4 4 4

HFLB I 5 5 5 5 Hori zontal inpu t.

Pin No.

Desc ripti ons

This ground pin is used to internal analog cir-

cuitry.

This pin is used to control the

internal oscillator frequency by DC voltage input from external

priate bias current for internal oscillator to resonate at specific
dot frequency.

analog circuitry. And a 0.1uF decoupling capacitor should be
connected across to VDDA and VSSA.

chronizing signal. It is a leading edge triggered and has an
internal pull-up resistor.

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TECHNOLOGY

Serial data in p ut.

internal display registers and control registers. It has an inter-

nal pull-up resistor.

The clock-input pin is used to synchronize

It is used for auto sizing measurement and

this signal is came from video pre-amp red output.

Green video inpu t .

this signal is came from video pre-amp green output.

It is used for auto sizing measurement and

this signal is came from video pre-amp blue output.

Open-Drain PWM D/A con v ert er 0.

Open-Drain PWM D/A con v ert er 1.

Open-Drain PWM D/A con v ert er 2.

Open-Drain PWM D/A con v ert er 3.

Open-Drain PWM D/A con v ert er 4.

Positive 5 V DC supply for internal digi-

Vert ic al inpu t .

This pin is used to input the vertical synchroniz-

16-color selection is achievable by

It is used to cut off external R, G, B sig-

MTV030MYSON

Name I/O

N16 N201 N202 N24

SSB I 6 6 6 6 Serial interf ace enable. It is used to enable the serial data

SDA I 7 7 7 7

SCK I 8 8 8 8 Serial clock inpu t.

RIN I - - 9 9 Red video input .

GIN I - - 10 10

BIN I - - 11 11 Blue video input.

NC - - - 12 - No connection.

PWM0 O - 9 - 12

PWM1 O - 10 - 13

PWM2 O - 11 - 14

PWM3 O - 12 - 15

PWM4 O - - - 16

VDD - 9 13 13 17 Digital power supp ly.

VFLB I 10 14 14 18

INT O 11 15 15 19 Intensity color output .

FBKG O 12 16 16 20 Fast Blanking outpu t.

BOUT O 13 17 17 21 Bl ue color output . It is a blue color video signal output.

GOUT O 14 18 18 22 Green color outp ut. It is a green color video signal output.

ROUT O 15 19 19 23 Red colo r outp ut . It is a red color video signal output.

VSS - 16 20 20 24 Digital ground. This ground pin is used to internal digital cir-

Pin No.

Desc ripti ons

and is also used to select the operation of I2C or SPI bus. If
this pin is left floating, I2C bus is enabled, otherwise the SPI
bus is enabled.

The external data transfer through this pin to

the data transfer. It has an internal pull-up resistor.

It is used for auto sizing measurement and

The output pulse width is

programmable by the register of Row 15, Column 23.

The output pulse width is

programmable by the register of Row 15, Column 24.

The output pulse width is

programmable by the register of Row 15, Column 25.

The output pulse width is

programmable by the register of Row 15, Column 26.

The output pulse width is

programmable by the register of Row 15, Column 27.

tal circuitry and a 0.1uF decoupling capacitor should be con­nected across to VDD and VSS.

ing signal. It is leading triggered and has an internal pull-up
resistor.

combining this intensity pin with R/G/B output pins.

nals of VGA while this chip is displaying characters or win­dows.

cuitry.

3/21 MTV030 Revision 1.0 10/15/1999

MTV030MYSON

3.0 FUNCTIONAL DESCRIPTIONS

3.1 SERIAL DATA INTERFACE

While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission

should be starting from pulling SSB to "low" level, enabling MTV030 to receiving mode, and retain "low" level

until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.

Format (a) R - C - D

Format (b) R - C - D

Format (c) R - C - D

C bus operation is only selected when SSB pin is left floating. And a valid transmission should be starting

Figure 2. And the auto sizing video measurement data (total 10 bytes) are read only registers and the others

are write only registers.

There are three transmission formats for I

C write mode shown as below:

Format (a) S - R - C - D

Format (b) S - R - C - D

Format (c) S - R - C - D

And there is one transmission format for I

FIGURE 2. Dat a Trans m i ssion Pro t o c ol (I

TECHNOLOGY

The serial data interface receives data transmitted from an external controller. And there are 2 types of bus
can be accessed through the serial data interface, one is SPI bus and other is I2C bus.

3.1.1 SPI bus

SSB

SCK

SDA

MSB LSB

first byte last byte

FIGURE 1. Data Tran s m issio n Prot ocol (SPI)

There are three transmission formats shown as below:

→ R - C - D → R - C - D .....

→ C - D → C - D → C - D .....

→ D → D → D → D → D .....

Where R=Row address, C=Column address, D=Display data

3.1.2 I2C bus

2

I
from writing the slave address 7AH(write mode), or 7BH(read mode) to MTV030. The protocol is shown in

SCK

SDA

START ACK

B7 B6 B0 B7 B0

first byte

second byte last byte

2

C)

ACK STOP

2

→ R - C - D → R - C - D .....

→ C - D → C - D → C - D .....

→ D → D → D → D → D .....

Where S=Slave address, R=Row address, C=Column address, D=Display data

2

C read mode shown as below:

Format (a) S → D → D → D → D → D → D → D → D → D → D → dummy D → dummy D .....

Where S=Slave address, D=Measurement data

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TECHNOLOGY

C read mode, 10 bytes of auto sizing video measurement data will be output directly from byte 0 to

C R/W bit is set to “1”.

Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and

increase transmission efficiency. The row and column address will be incremented automatically when the for-

mat (c) is applied. Furthermore, the undefined locations in display or fonts RAM should be filled with dummy

There are 2 types of data should be accessed through the serial data interface, one is

ADDRESS

bytes of dis-

play registers, and other is

of row address and the bit5 of column address. The MSB(b7) is used to distinguish row and column

addresses when transferring data from external controller. The bit6 of column address is used to differentiate

the column address for format (a), (b) and format (c) respectively. Bit5 of row address for display register is

addres s byt es, bit 5 of col u m n addr ess is th e MSB (bit8) and data bytes are the 8 LSB (bit7~bi t 0) of dis-

play fonts address

played at the same time. See Table 1. And for format (c), since D8 is filled while program column address of

column address of address bytes again.

(a) and (c), but not from format (c) back to format (a) and (b). The alternation between transmission formats is

configured as the state diagram shown in Figure 3.

3.2 Address bus adminis tr ator

The administrator manages bus address arbitration of internal registers or user fonts RAM during external

data write in. The external data write through serial data interface to registers must be synchronized by inter-

nal display timing. In addition, the administrator also provides automatic increment to address bus when exter-

nal write using format (c).

3.3 Verti cal di sp l ay cont r ol

The vertical display control can generates different vertical display sizes for most display standards in current

The configuration of transmission formats.

Addr ess Bytes

Attr ibut e Bytes

MTV030MYSON

In the I
byte 9 and continues with dummy data until stop condition occurred when I

Display data (D). Format (a) is suitable for updating small amount of data which will be allocated with different
row address and column address. Format (b) is recommended for updating data that has same row address
but different column address. Massive data updating or full screen data change should use format (c) to

data.

2

TABLE 1.

of Displ ay Reg.

of Displ ay Reg.

2

Address b7 b6 b5 b4 b3 b2 b1 b0 Format

Row 1 0 0 R4 R3 R2 R1 R0 a,b,c

Column

Column

Data D7 D6 D5 D4 D3 D2 D1 D0 a,b,c
Row 1 0 1 R4 R3 R2 R1 R0 a,b,c

Column

Column

Data D7 D6 D5 D4 D3 D2 D1 D0 a,b,c

0 0 D8 C4 C3 C2 C1 C0 a,b

ab

0 1 D8 C4 C3 C2 C1 C0 c

c

0 0 x C4 C3 C 2 C1 C0 a,b

ab

0 1 x C4 C3 C 2 C1 C0 c

c

ATTRIBUTE bytes of display registers, the protocol are same for all except the bit5

used to distinguish ADDRESS byte when it is set to "0" and ATTRIBUTE byte when it is set to "1". And at

to save half MCU memory for true 512 fonts. So each one of the 512 fonts can be dis­address bytes, the continued data will be the same bank of upper 256 fonts or lower 256 fonts until program
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format

monitors. The vertical display size is calculated with the information of double character height bit(CHS), verti-

5/21 MTV030 Revision 1.0 10/15/1999

TECHNOLOGY

cal display height control register(CH6-CH0).The algorithm of repeating character line display are shown as

The vertical display center for full screen display could be figured out according to the information of vertical

character would not be repeated.

Repeat Li n e Weigh t

FIGURE 3. Trans m issio n State Diagram

0, X

Initiate

MTV030MYSON

Input = b7, b6

X, X

DA

format (c)

COL

X, X

c

1, X

1, X

ROW

0, 1

c

0, 1

0, 0

format (b)

COL

format (a)

0, 0

ab

X, X

DA

1, X

ab

Table 2 and Table 3. The programmable vertical size range is 270 lines to maximum 2130 lines.

starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB,
is calculated with the following equation:

Vertical delay time = ( VERTD * 4 + 1 ) * H Where H = one horizontal line display time

TA B L E 2. Repeat lin e weig h t of ch aract er

CH6 - CH0

CH6,CH5=11 +18*3
CH6,CH5=10 +18*2
CH6,CH5=0x +18

CH4=1 +16
CH3=1 +8
CH2=1 +4
CH1=1 +2
CH0=1 +1

TA B L E 3. Repeat line nu m ber of ch arac ter

Repeat Line

Weight

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Repeat Lin e #

+1 - - - - - - - - v - - - - - - - - ­+2 - - - - v - - - - - - - v - - - - ­+4 - - v - - - v - - - v - - - v - - -

+8 - v - v - v - v - v - v - v - v - ­+16 - v v v v v v v v v v v v v v v v ­+17 v v v v v v v v v v v v v v v v v ­+18 v v v v v v v v v v v v v v v v v v

Note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the

6/21 MTV030 Revision 1.0 10/15/1999

MTV030MYSON

3.4 Hori zontal dis pl ay contr o l

The horizontal display control is used to generate control timing for horizontal display based on double char-

HFLB input. A horizontal display line consists of (HORR*12) dots which include 360 dots for 30 display char-

acters and the remaining dots for blank region. The horizontal delay starting from HFLB leading edge is calcu-

Where P = One pixel display time = One horizontal line display time / (HORR*12)

The VCLK frequency ranges from 6MHz to 150MHz selected by (VCO1, VCO0). In addition, when HFLB input

is not present to MTV030, the PLL will generate a specific system clock, approximately 2.5MHz, by a built-in

3.6 Disp l ay & Row contr ol regist ers

are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure 4 and Figure 5. Each dis-

play register has its corresponding character address on ADDRESS byte, its corresponding background color,

30

of DISPLAY REGISTERS

A TTRIBUTE

CRTL REG

TECHNOLOGY

acter width bit (CWS), horizontal positioning register (HORD), horizontal resolution register (HORR), and

lated with the following equation,

Horizontal delay time = ( HORD * 6 + 49) * P - phase error detection pulse width

3.5 Phase loc k l o o p (PLL)

On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB and horizontal resolution reg­ister (HORR). The frequency of VCLK is determined by the following equation:

VCLK Freq = HFLB Freq * HORR * 12

oscillator to ensure data integrity.

The internal RAM contains display and row control registers. The display registers have 450 locations which

1 blink bit and its corresponding color bits on ATTRIBUTE bytes. The row control register is allocated at col­umn 30 for row 0 to row 14 of attribute bytes, it is used to set character size to each respective row. If double
width character is chosen, only even column characters could be displayed on screen and the odd column
characters will be hidden.

ROW # COLUMN #

0 1 28 29

0
1

ROW

CHARACTER ADDRESS BYTES

13
14

31

R
E
S
E
R
V
E
D

FIGURE 4. Ad d r ess By t es of Disp l ay Regist ers Memory Map

7/21 MTV030 Revision 1.0 10/15/1999