MYSON MTV012A Datasheet

MYSON

MTV012A

TECHNOLOGY

8051 Embedded CRT Monitor Controller

Mask Version

FEATURES

8051 core.
256 bytes internal RAM.
8K bytes program Mask ROM.
14 channels 10V open drain PWM DAC, 10 dedicated channels and 4 channels shared with I/O pin.
20 bi-direction I/O pin, 12 dedicated pin, 4 shared with DAC, 4 shared with DDC/IIC interface.
3 output pins shared with H/V sync output and self test output pins.
SYNC processor for composite sync separation, polarity and frequency check, and polarity adjustment.
Built-in monitor self test pattern generator.
Built-in Low Power Reset circuit.
IIC interface for DDC1/DDC2B and EEPROM, only one EEPROM needed to store DDC1/DDC2B and
display mode information.
Watch dog timer with programmable interval.
40 pin PDIP package.

GENERAL DESCRIPTION

The MTV012A micro controller is an 8051 CPU core-embedded device specially tailored to CRT monitor
applications. It includes an 8051 CPU core, 256-byte SRAM, 14 built-in PWM DACs, DDC1/DDC2B
interface, 24Cxx series EEPROM interface and an 8K-byte internal program ROM.

BL OCK DIAGRAM

STOUT

P1.0-7

X1

X2

P2.0-3

P3.0-P3.2

8051

CORE

P3.4

P0.0-7

RD

WR

INT1

RST

P2.4-7

P0.0-7

XFR

RD

WR

WATCH-DOG

TIMER

RST

H/VSYNC
CONTROL

14 CHANNEL

PWM DAC

HSYNC

VSYNC
HBLANK
VBLANK

DA0-9

DA10-13

HSCL
HSDA

This datasheet contains new product information. Myson Technology reserv es the rights to modify the product specification
without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the
product.

DDC 1/2 B & FIFO

INTERFACE

IIC INTERFACE

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ISCL

ISDA

MYSON
TECHNOLOGY

1.0 PIN CONNECTION

MTV012A

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

RST
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
ISDA/P3.2/INT0

HSYNC

ISCL/P3.4/T0

VSYNC
HBLANK/P4.1
VBLANK/P4.0

X2
X1

VSS

MTV012A

VDD
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
STOUT/P4.2
DA10/P2.7
DA11/P2.6
DA12/P2.5
DA13/P2.4
P2.3
P2.2
P2.1
P2.0/INT0

2.0 PIN DESCRIPTION

Name Type Pin# Description

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

RST
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
ISDA/P3.2/INT0

HSYNC

ISCL/P3.4/T0

VSYNC
HBLA NK /P4.1
VBL ANK /P4.0

X2
X1

VSS

P2.0/INT0

I/O 1 General purpose I/O.
I/O 2 General purpose I/O.
I/O 3 General purpose I/O.
I/O 4 General purpose I/O.
I/O 5 General purpose I/O.
I/O 6 General purpose I/O.
I/O 7 General purpose I/O.
I/O 8 General purpose I/O.

I 9 Active high reset.
I/O 10 IIC clock / General purpose I/O / Rxd.
I/O 11 IIC data / General purpose I/O / Txd.
I/O 12 IIC data / General purpose I/O / INT0.

I 13 Horizontal SYNC or composite SYNC.
I/O 14 IIC clock / General purpose I/O / T0.

I 15 Vertical SYNC.

O 16 Horizontal blank / General purpose output.
O 17 Vertical blank / General purpose output.
O 18 Oscillator output.

I 19 Oscillator input.

- 20 Negative power supply.

I/O 21 General purpose I/O / INT0.

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TECHNOLOGY

MTV012A

P2.1
P2.2

P2.3
DA13/P2.4
DA12/P2.5
DA11/P2.6
DA10/P2.7

STOUT/P4.2

DA9

DA8

DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

VDD

I/O 22 General purpose I/O.
I/O 23 General purpose I/O.
I/O 24 General purpose I/O.
I/O 25 PWM DAC output / General purpose I/O (open-drain).
I/O 26 PWM DAC output / General purpose I/O (open-drain).
I/O 27 PWM DAC output / General purpose I/O (open-drain).
I/O 28 PWM DAC output / General purpose I/O (open-drain).

O 29 Self-test video output / General purpose output.
O 30 PWM DAC output (open-drain).
O 31 PWM DAC output (open-drain).
O 32 PWM DAC output (open-drain).
O 33 PWM DAC output (open-drain).
O 34 PWM DAC output (open-drain).
O 35 PWM DAC output (open-drain).
O 36 PWM DAC output (open-drain).
O 37 PWM DAC output (open-drain).
O 38 PWM DAC output (open-drain).
O 39 PWM DAC output (open-drain).

- 40 Positive power supply.

3.0 FUNCTIONAL DESCRIPTION

1. 8051 CPU Core

MTV012A includes all the 8051 functions with the following exceptions:

1.1 PSEN, ALE, RD and WR pins are disabled. The external RAM access is restricted to XFRs within
MTV012A.

1.2 Port0, port3.3 and ports3.5 ~ 3.7 are not general purpose I/O ports. They are dedicated to monitoring
control/DAC pins.

1.3 INT1 and T1 input pins are not provided.

1.4 Ports2.4 ~ 2.7 are shared with DAC pins; ports3.0 ~ 3.2 and port3.4 are shared with monitor control
pins.

In addition, there are 2 timers, 5 interrupt sources and a serial interface compatible with the standard

8051. The Txd/Rxd (P3.0/P3.1) pins are shared with the DDC interface. INT0/T0 pins are shared with

the IIC interface. An extra option can be used to switch the INT0 source from P3.2 to P2.0. This feature
maintains an external interrupt source when the IIC interface is enabled.

Note: All regis t ers lis t ed in thi s doc u m ent resid e in the external RAM area (XFR). For the intern al
RAM memory map , please refer to th e 8051 spec.

reg name addr bi t7 bit6 bit5 bit4 bit3 bit2 bit1 b it0
PADMOD

30h (w) SINT0 X DDCE IICE DA13E DA12E DA11E DA10E

SINT0 = 1 → INT0 source is pin #21.

= 0 → INT0 source is pin #12.

DDCE = 1 → Pin #10 is HSCL; pin #11 is HSDA.

= 0 → Pin #10 is P3.0/Rxd; pin #11 is P3.1/Txd.

IICE = 1 → Pin #12 is ISDA; pin #14 is ISCL.

= 0 → Pin #12 is P3.2/(INT0*); pin #14 is P3.4/T0.

DA13E = 1 → Pin #25 is DA13.

= 0 → Pin #25 is P2.4.

DA12E = 1 → Pin #26 is DA12.

= 0 → Pin #26 is P2.5.

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MTV012A

TECHNOLOGY

DA11E = 1 → Pin #27 is DA11.

= 0 → Pin #27 is P2.6.

DA10E = 1 → Pin #28 is DA10.

= 0 → Pin #28 is P2.7.

* SINT0 should be 0 in this case.

2. External Special Func t i o n Regist ers (XFR)

The XFR is a group of registers allocated in the 8051 external RAM area. Most of the registers are used
for monitor control or PWM DAC. The program can initialize Ri value and use "MOVX" instruction to
access these registers.

3. PWM DAC

Each D/A converter's output pulse width is controlled by an 8-bit register in the XFR. The frequenc y of
these outputs is (Xtal frequency)/253 or (Xtal frequency)/256, selected by DIV253. If DIV253=1, writing
FDH/FEH/FFH to the DAC register generates a stable high output. If DIV253=0, the output will pulse low
at least once even if the DAC register's content is FFH. Writing 00H to the DAC register generates stable
low output.

reg name addr bi t7 bit6 b it5 bit4 bit3 b it2 bit1 bit0

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8

DA9
DA10
DA11
DA12
DA13

WDT

20h (r/w) DA0
21h (r/w) DA1
22h (r/w) DA2
23h (r/w)
24h (r/w) DA4
25h (r/w)
26h (r/w) DA6
27h (r/w) DA7
28h (r/w)
29h (r/w) DA9
2Ah (r/w)

2Bh (r/w) DA11
2Ch (r/w) DA12
2Dh (r/w) DA13

80h WEN WCLR CLRDDC DIV253 X WDT2 WDT1 WDT0

DA3

DA5

DA8

DA10

b7
b7
b7
b7
b7
b7
b7
b7
b7
b7

b7
b7
b7
b7

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8

DA9
DA10
DA11
DA12
DA13

b6
b6
b6
b6
b6
b6
b6
b6
b6
b6

b6
b6
b6
b6

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8

DA9
DA10
DA11
DA12
DA13

b5
b5
b5
b5
b5
b5
b5
b5
b5
b5

b5
b5
b5
b5

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8

DA9
DA10
DA11
DA12
DA13

b4
b4
b4
b4
b4
b4
b4
b4
b4
b4

b4
b4
b4
b4

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8

DA9
DA10
DA11
DA12
DA13

b3
b3
b3
b3
b3
b3
b3
b3
b3
b3

b3
b3
b3
b3

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8

DA9
DA10
DA11
DA12
DA13

b2
b2
b2
b2
b2
b2
b2
b2
b2
b2

b2
b2
b2
b2

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8

DA9
DA10
DA11
DA12
DA13

b1
b1
b1
b1
b1
b1
b1
b1
b1
b1

b1
b1
b1
b1

DA0 (r/w) : The output pulse width control for DA0.
DA1 (r/w) : The output pulse width control for DA1.
DA2 (r/w) : The output pulse width control for DA2.
DA3 (r/w) : The output pulse width control for DA3.
DA4 (r/w) : The output pulse width control for DA4.
DA5 (r/w) : The output pulse width control for DA5.
DA6 (r/w) : The output pulse width control for DA6.
DA7 (r/w) : The output pulse width control for DA7.
DA8 (r/w) : The output pulse width control for DA8.
DA9 (r/w) : The output pulse width control for DA9.
DA10 (r/w) : The output pulse width contro l f or DA10.
DA11 (r/w) : The output pulse width contro l f or DA11.
DA12 (r/w) : The output pulse width control for DA12.
DA13 (r/w) : The output pulse width contro l f or DA13.
WDT (w) : Watchdog timer & special control bit.

DIV253 = 1 → The PWM DAC output frequency is (Xtal frequency)/253.

= 0 → The PWM DAC output frequency is (Xtal frequency)/256.

*1. All D/A converters are centered with value 80h after power-on.

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8

DA9
DA10
DA11
DA12
DA13

b0
b0
b0
b0
b0
b0
b0
b0
b0
b0

b0
b0
b0
b0

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TECHNOLOGY

4. H/V SYNC Proces sing

The H/V SYNC processing block performs the functions of composite signal separation , SYNC input
presence check, frequency counting, and polarity detection and control, as well as protection of
VBLANK output while VSYNC speeds up to a high DDC comm unication clock rate. The present and
frequency function block treat any pulse shorter than 1 OSC period as noise.

4.1 Composite SYNC Separate
MTV012A continuously monitors the input HSYNC. If the vertical SYNC pulse can be extracted from the
input, a CVpre flag is set and the user can select the extracted "CVSYNC" for the source of polari ty
check, frequency count and VBLANK. The CVSYNC will have a 10-16 us delay compared to the original
signal. The delay depends on the OSC frequency and composite m ix method.

4.2 H/V Frequency Counter
MTV012A can discriminate between HSYNC/VSYNC frequency and saves the information in XFRs. The
15-bit H counter counts the time of the 64xHSYNC period, but only 11 upper bits are loade d into the
HCNTH/HCNTL latch.

The 11-bit output value will be (2/Hfreq) / (1/OSCfreq), updated once per VSYNC/CVSYNC period when
VSYNC/CVSYNC is present, or continuously updated when VSYNC/CVSYNC is not present. The 14-bit
V counter counts the time between 2 VSYNC pulses, but only 9 upper bits are loaded i nto the
VCNTH/VCNTL latch. The 9-bit output value will be (1/Vfreq) / (512/OSCfreq), updated every
VSYNC/CVSYNC period. An extra overflow bit indicates the condition of H/V counter overflow. The
VFchg/HFchg interrupt is active when VCNT/HCNT value changes or overflows. Tables 4.2.1 and 4.2.2
show the HCNT/VCNT value under the 8MHz OSC operations.

4.2.1 H-Freq Table

H-Freq(KHZ)

1
2
3
4
5
6
7
8

9
10
11
12
13

*1. The H-Freq output (HF10 - HF0) is valid.
*2. The tolerance deviation is + 1 LSB.

4.2.2 V-Freq Table

V-Freq(Hz)

1

2

3

4

30 215h / 533 320h / 800

31.5 1FBh / 507 2F9h / 761

33.5 1DDh /477 2CCh / 716

35.5 1C2h / 450 2A4h / 676

36.8 1B2h / 434 28Ch / 652
38 1A5h / 421 277h / 631
40 190h / 400 258h / 600
48 14Dh / 333 1F4h / 500
50 140h / 320 1E0h / 480
57 118h / 280 1A5h / 421
60 10Ah / 266 190h / 400
64 0FAh / 250 177h / 375

100 0A0h / 160 0F0h / 240

56.25 115h / 277 1A0h / 416

59.94 104h / 260 187h / 391
60 104h / 260 186h / 390

60.32 103h / 259 184h / 388

8MHz OSC (hex / dec) 12MHz OSC (hex / dec)

8MHz OSC (hex / dec) 12MHz OSC (hex / dec)

Outpu t Value (11 bit s )

Outpu t Value (9 bits)

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