MYSON MTU8B55E, MTU8B55EM, MTU8B54EP, MTU8B54E, MTU8B56EP Datasheet

notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of th

TECHNOLOGY

GENERAL DESCRIPTION

MTU8B57E and 24 to 72 bytes of static RAM.

cycle instructions under 20MHz operating.

24 bytes for MTU8B55E,

PA3:PA0

512 X 14 TO

- XTAL : Standard crystal oscillator

EPROM-Based 8-Bit CMOS Microcontroller

FEATURES

• Total of 33 single word instructions .

• The fast execution time may be 200ns for all single

• Operating voltage range: 2.3V ~ 6.5V

• 8-bit data bus.

• 14-bit instruction word.

• Four-level stacks.

• On chip EPROM size : 512x14 bits for MTU8B54E/55E,
1Kx14 bits for MTU8B56E,
2Kx14 bits for MTU8B57E.

• Internal RAM size : 25 bytes for MTU8B54E/56E,

• 72 bytes for MTU8B57E.

• Direct and indirect addressing modes for data accessing

• 8-bit real time clock/counter with 8-bit programmable
prescaler.

• Internal power-on Reset.

• Device Reset Timer.

• Code protection.

• Sleep mode for power saving.

• On chip Watchdog Timer(WDT) based on internal RC
oscillator.

• Three I/O ports PA, PB nad PC with independent direc-

tion control.

MTU8B54E/55E/56E/57EMYSON

• 4 types of oscillator can be selected by code options:

- RC : Low-cost RC oscillator

- HFXTAL : High frequency crystal oscillator

- LFXTAL : Low frequency crystal oscillator

MTU8B5X series is an EPROM based 8-bit micro­controller which employs a full CMOS technology
enhanced with low-cost, high speed and high noise
immunity. W atchdog Timer, RAM, EPROM, tri-state
I/O port, power down mode, and real time program­mable clock/counter are integrated into this chip.
MTU8B5X contains 33 instructions, all are single
cycle except for program branches which take two
cycles.

On chip memory is available with 512x14 bits of
EPROM for MTU8B54E/55E, 1Kx14 bits of EPROM
for MTU8B56E, 2Kx14 bits of EPROM for

BL OCK DIAGRAM

V

dd

V

ss

OSCI
OSCO
MCLR

T0CKI

Sleep

WDT/Timer0

Accumulator

Configuration

Word

Osc Mode

2

Select

Oscillator

Circuit

Prescaler

6

T0MODE

Register

6

Status

/Disable

Enable

WDT

Time Out

Four-level

Stack

WatchDog

Timer

Timer0

RAM

24, 25 or 27 Bytes

FSR

ALU

11

Data

8

8

Program

Counter

11

EPROM

2048 X 14

14

Instruction

Register

14

Instruction

Decoder

PortA

PortB

PortC

Only in MTU8B55E/57E

4

8

8

PB7:PB0

PC7:PC0

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without

Revision 1.2 - 1 - 24 October 2000

e product.

TECHNOLOGY

RC type: Input pin of RC oscillator

this pin is low, the device is reset.

In programmimg mode, this pin is connected to 12V. In normal operating

mode, this pin must not exceed Vdd to avoid entering unintended program-

PA0~PA3 as bi-directional I/O port

1.0 PIN CONNECTION

MTU8B54E/55E/56E/57EMYSON

PA2

PA3

T0CKI

MCLR/Vpp

Vss
PB0
PB1
PB2
PB3

1
2
3
4

MTU8B54E

5

MTU8B56E

6
7
8
9

2.0 PIN DESCRIPTIONS

Name I/O Descriptions

18
17
16
15
14
13
12
11
10

PA1
PA0
OSCI
OSCO

Vdd

PB7
PB6
PB5
PB4

T0CKI

Vdd

N/C

Vss

N/C

PA0

PA1

PA2
PA3
PB0
PB1
PB2
PB3
PB4

1
2
3
4
5
6
7

MTU8B55E

8

MTU8B57E

9
10
11
12
13
14

28
27
26
25
24

23
22
21
20
19

18

17

16
15

MCLR/Vpp
OSCI

OSCO
PC7
PC6

PC5

PC4
PC3
PC2
PC1
PC0

PB7

PB6

PB5

OSCI I

OSCO O

T0CKI/SCL I Input pin of real time counter/clock. Must be tied to Vss or Vdd if not in use.

MCLR/Vpp I

PA0~PA3 I/O
PB0~PB7 I/O PB0~PB7 as bi-directional I/O port
PC0~PC7 I/O PC0~PC7 as bi-directional I/O port

Vdd - Power supply
Vss - Ground

XTAL type: Input terminal of crystal oscillator
RC type: OSCO outputs with 1/4 frequency of OSCI to denotes the cycle

rate for instruction.
XTAL type: Output terminal of crystal oscillator

Input pin for device reset or high voltage programming input for EPROM. If

ming mode.

Revision 1.2 - 2 - 24 October 2000

TECHNOLOGY

3.0 FUNCTIONAL DESCRIPTIONS

The Regis ter Map of MTU8B54E/56E

The Regist er Map of MTU8B55E

The Regi ster Map of MTU8B57E

Map back to address in Bank 0

3.1 REGISTER MAP

The register map of MTU8B5X is depicted as below:.

MTU8B54E/55E/56E/57EMYSON

Address Description

00h Indirect Addressing Register
01h Timer0
02h PC
03h STA TUS
04h FSR
05h PORTA
06h PORTB

07h-1Fh General Purpose Register

Address Description

FSR<6:5>

00h

Bank 0

00

Indirect Address­ing Register

Bank 1

01

Address Description

00h Indirect Addressing Register
01h Timer0
02h PC
03h STATUS
04h FSR
05h PORTA
06h PORTB
07h PORTC

08h-1Fh General Purpose Register

Bank 2

10

Bank 3

11

01h Timer0
02h PC
03h STATUS
04h FSR
05h PORTA
06h PORTB
07h PORTC

08h~0Fh

Revision 1.2 - 3 - 24 October 2000

General Purpose
Register

10h~1Fh
General Purpose
Register

30h~3Fh
General Purpose
Register

50h~5Fh
General Purpose
Register

70h~7Fh
General Purpose
Register

MTU8B54E/55E/56E/57EMYSON

INA R(Indir ect Ad d res s Regist er) : R0

R0 is not a physically implemented register. It is used a s an indirect addressing pointer. Any instruction

accessing this register can access data pointed by FSR(R4).

This register increases by an external signal edge applied to T0CKI pin, or by internal instruction cycle. It can

be read or written as any other register.

STATUS(Status Regis t er ):

The content of R3 is listed in Table 1.

LCALL, LGOTO : from instruction word

RETIA : from STACK

TABL E 1. STATUS Regis ter

= 1, a carry occurred = 1, a borrow did not occur

Half carry/half

= 0, a carry from the 4th low order bit of the result did not occur

= 1, the result of a logic operation is zero

Power down flag bit:

= 0, by the SLEEP instruction

Time overflow flag bit:

= 0, a WDT time-overflow occurred

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3.1.1

3.1.2 Timer0(8-bit real-time cl o ck /ti m er) : R1

3.1.3 PC(Pro g r am Coun ter) : R2

This register increases itself every instruction cycle, except the following condition shown in Figure 1:

LCALL

A10~A0

RETIA

FIGURE 1. Pr o g ram Counter

Stack1
Stack2
Stack3
Stack4

3.1.4

Bit Symbol Description

Carry/borrow bit

0 C

1 DC

2 Z

3 PD

ADDWF SUBWF

= 0, a carry did not occur = 0, a borrow occurred

borrow bit
ADDWF
= 1, a carry from the 4th low order bit of the result occurred

SUBWF
= 1, a borrow from the 4th low order bit of the result did not occur
= 0, a borrow from the 4th low order bit of the result occurred

Zero bit:

= 0, the result of a logic operation is not zero

= 1, after power-up or by the CLRWDT instruction

4 TO

5, 6, 7 - Unused

Revision 1.2 - 4 - 24 October 2000

= 1, after power-up or by the CLRWDT or SLEEP instruction

TECHNOLOGY

Bit 0~4 are used to select up to 32 registers (address: 00h~1Fh) and Bit 5~6 are Bank Select (Bank0~3) in the

PA3:PA0, bi-directional I/O Register

T0MODE REGISTER:

T0MODE is a write-only register and the content is listed in Table 2.

= 0, I/O pin in output mode;

= 1, I/O pin in input mode.

FIGURE 2. Data Memory Conf i g u raion

Timer0

STA TUS

PORT A

PORT B

8 Bytes

3.1.5 FSR(File select regi st er po i n t er): R4

indirect addressing mode shown in Figure 2.

3.1.6 PORT A: R5

3.1.7 PORT B: R6

PB7:PB0, bi-directional I/O Register

3.1.8 PORT C: R7

PB7:PB0, bi-directional I/O Register, and for MTU8B55E/57E only

3.1.9

3.1.10 IOST (Contr o l Por t I/O Mode Regist er)

The IOST register is “write-only”

MTU8B54E/55E/56E/57EMYSON

Bank Select

B7 B6 B5 B4 B3 B2 B1 B0

Read 1

70h

7Fh

50h

5Fh

Bank 3

30h

3Fh

Bank 2

Bank 1

Bank 0

16 Bytes

SRAM

Indirect Addressing Mode

Location Select

00h INAR

10h

1Fh

01h
02h PC
03h
04h FSR
05h
06h
07h PORT C
08h

0Fh

SRAM

Bank 0

Revision 1.2 - 5 - 24 October 2000

MTU8B54E/55E/56E/57EMYSON

TABLE 2. T0MODE Regi ster

Timer Rate

WDT Rate

Timer0 source signal edge select bit:

= 1, increment when high-to-low transition on T0CKI pin

Timer0 source signal select bit:

= 0, internal instruction clock cycle

TECHNOLOGY

Bit Symbol Description

Bit Value

2-0 PS2:PS0

Prescaler assign bit:

3 PSC

4 TE

5 TS

6, 7 - Unused

= 0, Timer0
= 1, WDT

= 0, increment when low-to-high transition on T0CKI pin

= 1, transition on T0CKI pin

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

1:2
1:4

1:8
1:16
1:32
1:64

1:128
1:256

1:1
1:2
1:4

1:8
1:16
1:32
1:64

1:128

Revision 1.2 - 6 - 24 October 2000

TECHNOLOGY

Affected

Test bit in R and skip if clear

Test bit in R and skip if set

Clear Watchdog Timer

Go into standby mode

Load IOST Register

AND immediate with Acc

Exclusive OR immediate with Acc

Move immediate to Acc

Inclusive OR immediate with Acc

Return, place immediate in A

Complement R

Increment R, Skip if 0

3.2 INSTRUCTION SET

MTU8B54E/55E/56E/57EMYSON

Mnem oni c

Instruction

Status

Descr ipti on Cycl es

Operands

BCR R, bit Clear bit in R 1 11 11bb brrr rrrr None
BSR R, bit Set bit in R 1 11 10bb brrr rrrr None

BTRSC R, bit

BTRSS R, bit

CLRWDT
T0MODE Load T0MODE Register 1 01 0000 0000 0010 None
SLEEP
IOST R
ANDIA I
XORIA I
MOVIA I
IORIA I

1 or

2(skip)

1 or

2(skip)

1 01 0000 0000 0001 TO, PD

1 01 0000 0000 0011 TO, PD
1 01 0000 0000 0rrr None
1 00 1001 iiii iiii Z
1 00 1000 iiii iiii Z
1 00 0001 iiii iiii None
1 00 0011 iiii iiii Z

11 01bb brrr rrrr None

11 00bb brrr rrrr None

Code

RETIA I
LCALL I Call subroutine 2 10 0iii iiii iiii None
LGOTO I Unconditional branch 2 10 1iii iiii iiii None
NOP No operation 1 01 0000 0000 0000 None
MOVAR R Move Acc to R 1 01 0000 1rrr rrrr None
COMR R, d
MOVR R Move R 1 01 0011 drrr rrrr Z
RRR R, d Rotate right R 1 01 1110 drrr rrrr C
RLR R, d Rotate left R 1 01 1100 drrr rrrr C
SWAPR R, d Swap halves R 1 01 1101 drrr rrrr None
CLRA Clear Acc 1 01 0001 0000 0000 Z
CLRR R Clear R 1 01 0001 1rrr rrrr Z
INCR R, d Increment R 1 01 1000 drrr rrrr Z

INCRSZ R, d

2 00 1100 iiii iiii None

1 01 0010 drrr rrrr Z

1 or

2(skip)

01 1001 drrr rrrr None

Revision 1.2 - 7 - 24 October 2000