MYSON MTL004 Datasheet

MYSON

Double scan capability for interlaced input.

MTL004

TECHNOLOGY

(Rev. 0.95)

XGA Flat Panel Controller

FEATURES
General

• Auto configuration of sampling clock frequency, phase, H/V center, as well as white ba lance.

• Auto detection of present or non-present or over range sync signals and their polarities.

• Composite sync separation and odd/even field detection of interlaced video.

• No external memory required.

• On-chip output PLL provide clock frequency fine-tune (inverse, duty cycle and delay).

• Selection of serial 2-wire I

• 3.3V supplier, 5V I/O tolerance in 208-pin PQFP package.

Input Processor

• Single RGB (24-bit) or Dual RGB (48-bit) input rates up to 100MHz.

• Support both non-interlaced and interlaced RGB graphic input signals..

• Compliant with digital LVDS/PanelLink TMDS input interface.

• PC input resolution up to XGA 1024x768 @85Hz.

2

C or 3-wire serial or 8-bit direct host interface to 8-bit MCU.

Video Processor

• Independent programmable Horizontal and Vertical scaling up ratios from 1 to 32

• Built-in programmable gain control for white balance alignments.

• Built-in programmable 8-bit gamma correction table.

• Built-in programmable temporal color dithering.

• Built-in programmable interpolation look-up table.

• Support smooth panning under viewing window change.

Output Processo r

• Single pixel (18/24-bit) or Dual pixel (36/48-bit) per clock digital RGB output.

• Built-in output timing generator with programmable clock and H/V sync.

• Support VGA/SVGA/XGA display resolution.

• Overlay input interface with external OSD controller.

•

GENERAL DESCRIPTION

The MTL004 Flat Panel Display (FPD) Controller is an input format converter for TFT-LCD Monitor or LCD
TV application which accepts 15-pin D-sub RGB graphic signals (through ADC), or di gital RGB graphic
signals from PanelLink TMDS receiver. It includes a RGB input processor, video scaling up processor, OSD
input interface and output display processor in 208-pin PQFP.

Revision 0.95 - 1 - 2000/06/14

MYSON

RGB

8-bit MCU

MTV130

OSD

Generator

MTL004

TECHNOLOGY

BL OCK DIAGRAM

PC

RGB
Input

Auto

Calibration

Mode

Detect

Zoom
Buffer

Host

Interface

To I2C Bus

Scale

Up

Gain

Control

Dithering

Gamma

Correct

(Rev. 0.95)

To external OSD

OSD

&

Output

MUX

Display

Timing

RGB

output

APPLICA TIONS

LVDS/PanelLink

TMDS Receiver

D-sub RGB
graphic signals

ADC1

ADC2

MTL004

FPD Monitor

Controller

MTV212

TFT-LCD

Flat Panel

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.

Revision 0.95 - 2 - 2000/06/14

MYSON

052* PVSS

051* AD6

050* AD7

049* ALE

048* DVDD

047* B1OUT3

NC *105

NC *106

NC *107

TDIE *108

PVSS *109

B1IN1 *110

MTL004

1. PIN CONNECTION

VSYNC2 *150

PVDD *151

AVDD *152

XO *153

XI *154

NC *157
NC *158

NC *193

NC *197

NC *207

AVSS *155

006* G1OUT6

005* PVSS

004* OSDINT

003* NC

002* NC

007* G1OUT7

GPIO1 *159
GPIO0 *160

PVSS *161

OHSYNC *162

OCLK *163

OVSYNC *164

G2IN7 *165
G2IN6 *166
G2IN5 *167
G2IN4 *168
G2IN3 *169
G2IN2 *170
G2IN1 *171

DVDD *172

EXTDCLK2 *173

DVSS *174

EXTDCLK1 *175

PVDD *176

G2IN0 *177

G2OUT0 *178

PVSS *179
G2OUT1 *180
G2OUT2 *181
G2OUT3 *182

DVDD *183
G2OUT4 *184
G2OUT5 *185
G2OUT6 *186
G2OUT7 *187

DVSS *188
R2OUT0 *189
R2OUT1 *190
R2OUT2 *191
R2OUT3 *192

RSTZ *194

PVDD *195
G1OUT0 *196

G1OUT1 *198

PVSS *199
G1OUT2 *200
G1OUT3 *201
G1OUT4 *202
G1OUT5 *203

PVDD *204

BUSSEL0 *205
BUSSEL1 *206

PVSS *208

TECHNOLOGY

NC *130

DVDD *131

R1IN0 *132

G1IN7 *133

G1IN6 *134

G1IN5 *135

G1IN4 *136

G1IN3 *137

G1IN2 *138

G1IN1 *139

G1IN0 *140

VSYNC1 *141

IPCLK1 *142

RAWHS *143

NC *144

HSYNC1 *145

NC *146

NC *147

IPCLK2 *148

HSYNC2 *149

MTL004

(208-pin PQFP)

027* DVDD

026* DHCLK

025* DDEN

024* DDCLK

023* DVSS

022* NC

021* GPIO2

020* GPIO3

019* NC

018* OSDEN

017* OSDBLU

016* DVDD

015* OSDGRN

014* OSDRED

013* DVSS

012* R1OUT3

011* R1OUT2

010* DVDD

009* R1OUT1

008* R1OUT0

CLAMP *125

R1IN2 *126

DVSS *127

R1IN1 *128

TMDSSEL *129

032* DVSS

031* HWRZ

030* DOEZ

029* DHSYNC

028* DVSYNC

R1IN7 *120

R1IN6 *121

R1IN5 *122

R1IN4 *123

R1IN3 *124

037* R1OUT4

036* DVSS

035* DVDD

034* HRDZ

033* NC

R2IN4 *115

R2IN3 *116

R2IN2 *117

R2IN1 *118

R2IN0 *119

042* PVDD

041* R1OUT7

040* R1OUT6

039* PVSS

038* R1OUT5

B1IN0 *111

R2IN7 *112

R2IN6 *113

R2IN5 *114

046* B1OUT2

045* DVSS

044* B1OUT1

043* B1OUT0

(Rev. 0.95)

104* NC
103* NC
102* DVSS
101* NC
100* DVDD
099* B1IN2
098* B1IN3
097* B1IN4
096* B1IN5
095* B1IN6
094* B1IN7
093* B2IN0
092* B2IN1
091* PVDD
090* B2IN2
089* B2IN3
088* B2IN4
087* B2IN5
086* B2IN6
085* B2IN7
084* PVSS
083* B2OUT7
082* B2OUT6
081* B2OUT5
080* B2OUT4
079* DVDD
078* B2OUT3
077* B2OUT2
076* B2OUT1
075* DVSS
074* B2OUT0
073* R2OUT7
072* DVDD
071* R2OUT6
070* R2OUT5
069* R2OUT4
068* DVSS
067* IRQ
066* AD2
065* AD1
064* AD0
063* HCSZ
062* PVDD
061* B1OUT7
060* B1OUT6
059* B1OUT5
058* B1OUT4
057* PVSS
056* AD3
055* AD4

Revision 0.95 - 3 - 2000/06/14

MYSON

Input source HSYNC or Input Sync On Green

tri_state all Display port

MTL004

TECHNOLOGY

(Rev. 0.95)

2. PIN DESCRIPTION
ADC1 Inpu t Inter f ac e (RGB or TMDS Inp u t Data)

Name Type Pin# Description

IPCLK1 I 142 Input pixel clock 1
VSYNC1 I 141 Input Vertical s ync 1
HSYNC1/CS1 I 145 Input Horizontal or Composite sync 1
R1IN[7:0] I 120-124,

126,128,

132
G1IN[7:0] I 133-140 Green channel or TMDS input data (Single/Dual ADC)
B1IN[7:0] I 94-99,

110-111
RAWHS/SOG I 143
TDIE I 108 TMDS digital input enable
NC O 130 No connection
TMDSSEL O 129 TMDS input select, active high
CLAMP O 125 Clamp pulse output for ADC

Red channel or TMDS input data (Single/Dual ADC)

Blue channel or TMDS input data (Single/Dual ADC)

ADC2 Inpu t Inter f ac e (RGB or TMDS Inp u t Data)

Name Type Pin# Description

IPCLK2 I 148 Input pixel clock 2
VSYNC2 I 150 Input Vertical s ync 2
HSYNC2/CS2 I 149 Input Horizontal or Composite sync 2
R2IN[7:0] I 112-119 Red or TMDS input data (Single/Dual ADC)
G2IN[7:0] I 165-171,

177

B2IN[7:0] I 85-90,

92-93
NC I 144 No connection
NC I 147 No connection
NC I 146 No connection

Green channel or TMDS input data (Single/Dual ADC)
Blue or TMDS input data (Single/Dual ADC)

Displ ay Outp ut Interface

Name Type Pin# Description

DDEN O 25 Display data output enable
DVSYNC O 28 Display Vertical sync output
DHSYNC O 29 Display Horizontal sync output
DDCLK O 24 Display output clock
DHCLK O 26 Display half rate output clock
DOE# I 30 Display port output enable, “1” will

output signals

R1OUT[7:0] O 41-40

38-37,

12-11,9-8

G1OUT[7:0] O 7-6,

203-200,

198,196

B1OUT[7:0] O 61-58,47,

46,44,43

R2OUT[7:0] O 73,71-69,

192-189

G2OUT[7:0] O 187-184,

182-180,

178

Revision 0.95 - 4 - 2000/06/14

Red output even data , bit[7:2] for 6-bit panel

Green output even data , bit[7:2] for 6-bit panel

Blue output even data , bit[7:2] for 6-bit panel
Red output odd data , bit[7:2] for 6-bit panel
Green output odd data , bit[7:2] for 6-bit panel

MYSON

Vertical sync for external OSD
Horizontal sync for external OSD

OSD intensity input
OSD overlay enable

Oscillator frequency input
Oscillator frequency output

Bit 0: ADHS, Horizontal sync for A/D converter

MTL004

TECHNOLOGY

B2OUT[7:0] O 83-80,

78-76,74

Blue output odd data , bit[7:2] for 6-bit panel

(Rev. 0.95)

Host Interface

Name Type Pin# Descrip tio n

RST# I 194 System reset input, active low.
AD[7:0] I/O 50-51,

54-56,

66-64

HWR# I 31 Host write strobe, active low
HRD# I 34 Host read strobe, active low
ALE I 49 Host address latch enable for 8-bit direct bus
HCS# I 63 Host chip select
BUSSEL[1:0] I 206,205 Bus mode selection. 0x: 3-wire bus, 10: I2C bus,

IRQ O 67 Interrupt request output

The address and data bus of 8-bit direct interface or
2-wire I2C / 3-wire series bus
Bit 2: SDAO, 3-wire serial bus data out
Bit 1: SDA, serial bus data / 3-wire serial bus data in
Bit 0: SCK, serial bus clock

11: 8-bit direct bus

OSD Interf ac e

Name Type Pin# Description

OCLK O 163 Clock for external OSD
OVSYNC O 164
OHSYNC O 162
OSDRED I 14 OSD red input
OSDGRN I 15 OSD green input
OSDBLU I 17 OSD blue input
OSDINT I 4
OSDEN I 18

Other Interface

Name Type Pin# Description

XI I 154
XO O 153
EXTDCLK1 I 175 External display clock input 1
EXTDCLK2 I 173 External display clock input 2
GPIO[3:0] I/O 20-21,

General purpose I/O or

159-160

Bit 1: ADVS, Vertical sync for A/D converter
Default: Input direction

NC - 1-3, 19,

22, 33,
53, 101,
103-107,
156-158,
193, 197,
207

No connection

3.3V Power and Grou n d

Name Pin# Descrip tio n

DVDD 10, 16, 27, 35, 48, 72, 79, 100, 131, 172, 183 Digital power 3.3V
DVSS 13, 23, 32, 36, 45, 68, 75, 102, 127, 174, 188 Digital ground
PVDD 42, 62, 91, 151, 176, 195, 204 Pad power 3.3V
PVSS 5, 39, 52, 57, 84, 109, 161, 179, 199, 208 Pad ground

Revision 0.95 - 5 - 2000/06/14

MYSON

MTL004

TECHNOLOGY

AVDD 152 Analog power 3.3V
AVSS 155 Analog ground

(Rev. 0.95)

Revision 0.95 - 6 - 2000/06/14

MYSON

The Digital RGB input port works just in the same way as Sec 3.1.1 except that pin
With a flexible single or double pixel input interface, the supported format is up to true color, includi ng 18

In general, the synchronous HSYNC input for HSYNC1 or HSYNC2 generated by an ADC may have a very

In this mode, only one field is displayed at the time. First field and second field are toggling displayed. The

interpolating the neighboring lines. This mode has a generally good quality for still and moving pictures.

inputs presence check, frequency counting, polarity detection and control. It contains

MTL004 can measure VSYNC/HSYNC frequency counted in proper clock and save the information in

MTL004

TECHNOLOGY

(Rev. 0.95)

3. FUNCTIONAL DESCRIPTION

3.1 Input Process or

General Descrip t io n

The function of Input Interface is to provide the interface between MTL004 and external in put devices. It can
process non-interlaced and interlaced RGB graphic input, and digital RGB input compliant with digital
LVDS/PanelLink TMDS interface.

3.1.1 RGB Input Format

The RGB input port works in two modes: Single Pixel mode (24 bits) and Double Pixel mode (48 bits). For
Single Pixel mode, either ports R/G/B1IN[7:0] or R/G/B2IN[7:0] selected by Reg.16h/D0 can be chosen to be
internally sampled. For the Double Pixel mode, besides ports R/G/B1IN[7:0], ports R/G/B2IN[7:0] are also
needed. The R/G/B1IN ports are sampled at the rising edge of the RGB input clock, and the R/G/B2IN ports
are sampled at the falling edge.

3.1.2 TMDS Inpu t Form at

“Digital Input Enable

DIEN “ is needed.
bit/pixel or 24 bit/pixel in 1 or 2 pixels/clock mode.

3.1.4 Inpu t HSYNC Path

In addition to the pins HSYNC1/2, MTL004 provides another pin RAWHS to support the Sync Processor.
narrow pulse width and a different polarity comparing to the original HSYNC provided by the source. The

RAWHS input provides the path of original HSYNC connection to MTL004, thus making Sync Processor in
MTL004 working properly.

3.1.6 De-int erlace mod e

For the interlace input, MTL004 features several de-interlacing algorithms for processing interlaced video
data depending on the type of input images.

¨ Togg le Mode

missing lines are calculated by duplicating the neighboring lines. This m ode gives good quality for moving
pictures.

¨ Spatial Mode

In this mode, two fields are toggling displayed just like the Toggle mode. The m issing lines are calculated by

3.1.7 Sync Processo r

The V/H SYNC processing block performs the functions of Composite signal separation/insertion, SYNC

a de-glitch circuit to

filter out any pulse shorter than one OSC period which is treated as noise am ong V/H SYNC pulses.

¨ V/H SYNC Frequency Cou n ter

register. Users can read the figure and calculate VSYNC/HSYNC frequency as following formulas:

the

f

= f
= f

osc
osc

/ N
/ N

f
f

vsync

f

hsync

,Where f

Revision 0.95 - 7 - 2000/06/14

vsync
hsync
osc

51/256

vsync

58

hsync

: VSYNC frequency
: HSYNC frequency
: oscillator clock with 14.31818 MHz

MYSON

input sample registers to aid in centering the screen automatically.

s phase and frequency. MTL004

This advanced function helps Firmware to analyze ADC performance. Usually Firmware can use the

MTL004

TECHNOLOGY

N
N

¨ V/H SYNC Pres en ce Check

This function checks the input VSYNC, where Vpre flag is set when VSYNC is over 40Hz or cleared when
VSYNC is under 10Hz and the input HSYNC, where Hpre flag is set when HSYNC is over 10Khz or cleared
when HSYNC is under 10Hz.

¨ V/H Polarity Detect

This function detects the input VSYNC/HSYNC high and low pulse duty cycle. If the high pulse duration is
longer than that of low pulse, the negative polarity is asserted; otherwise, positive polarity is asserted.

¨ Compos it e SYNC separatio n/ins erti on

MTL004 continuously monitors the input HSYNC. If the input VSYNC can be extracted from it, a CVpre flag is
set. MTL004 can insert HSYNC pulse during Composite VSYNC’s active time and the insertion frequency
can adapt to the original HSYNC’s.

3.1.8 Auto Tune

Auto Tune function consists of Auto Position which automatically centering the screen an d A uto Calibration
which contains Phase Calibration, Histogram, Min/Max Value, and Pixel Grab that are described in the
following paragraphs. With such auto adjustment support it is possible to measure the correct phase,
frequency, gain, and offset of ADC. The horizontal and vertical back porches of input image and the
horizontal and vertical active regions can also be measured. Firmware can adjust input image registers
automatically by reading Auto Tune’s registers in single or burst mode.

: counted number of VSYNC

vsync

: counted number of HSYNC

hsync

(Rev. 0.95)

¨ Auto Position

MTL004 provides Horizontal/Vertical back porch and active region values. Users can use these values to set

¨ Phase Calibration

MTL004 provides Auto Calibration registers to measure the quality of current ADC’s phase and frequency.
The biggest Auto Calibration registers value means the right value of ADC’
has two kinds of algorithms to calculate Auto Calibration’s value. One is traditional Difference method,
another is MYSON’s proprietary method. The latter one is recommended for a better performance.

¨ Histogram

Histogram is the total number of input pixels below/above one threshold value for individual R, G, B colors.
information to measure ADC’s noise margin, adjust its offset and gain, or even aid in the mode detection.

¨ Min /Max Value

Min/Max value is the minimum or maximum pixel value within the specified input active image region for each
RGB channel. This information is usually used to adjust ADC’s offset and gain.

¨ Pixel Grab

Pixel Grab means user can grab a single input pixel at any one point. The position of the point can be
programmed by the user. This is another traditional method to measure ADC’s phase and frequency.

Revision 0.95 - 8 - 2000/06/14

MYSON

MTL004

TECHNOLOGY

(Rev. 0.95)

3.2 Video Proc ess o r

General Descrip t io n

MTL004 possesses a powerful and programmable video processor b y providing the following functions:
Scaling Up, Gain Control, Brightness Control, Gamma Correction, and Dithering Control.

The block diagram of Video Processor is as follows:

Fig. 3.2.1 Video Processor Block Diagram

SCALING

3.2.1 Scaling

MTL004 provides scaling function ranging from 1 to 32 for up scaling, and for both horizo ntal and vertical

GAIN

BRIGHTNESS

Scaling Factor

Interpolation Table

Gain Factor

Brightness Factor

GAMMA

DITHERING

processing. For scaling up, both horizontal and vertical processing, MTL004 provides four methods:

¨ Pass Mode: Image will be passed through without taking scaling factor into account.
¨ Dupli cate Mode: Image will be scaled up based on the scaling factor. Every point of output image

comes from the input. In this method, the output image will have a good contrast but the picture could be
non-uniformed.

¨ Bilin ear Mode: Image will be scaled up based on the scaling factor. Every point of output image data

will be filtered by bilinear filter. In this method, the output image will have a good scaling quality but the
picture could be blurred.

¨ Interpol atio n Table Mode: Image will be scaled up based on the scaling factor. The user-defined filter

will filter every point of output image data. In this mode, every output point is calculated based on the 3
input points.

Gamma Table

Dithering Table

Input pixels:

I

k-1

Output pixels:

Revision 0.95 - 9 - 2000/06/14

A

Y

I

k

l

l-1

B

l

Y

l

I

k+1

C

l

Y

l+1

MYSON

programming the gain and brightness coefficients. This adjustment is applied to RGB colors individually.

Gamma Correction is used to compensate the non-linearity of LCD display panel. MTL004 contains an 8-bit

true color (8 bits per color) or high color (6 bits per color) display.

Output processor provides the interface for both LCD panel and OSD controller. The output frame rate must
be equal to the input frame rate and output display time must be equal to input display time since there is no

MTL004

TECHNOLOGY

,where Yl=Al*I

3.2.2 Gain/Bright ness Control

MTL004 provides Gain and Brightness control to adjust the contrast and brightness of output color by
Auto-white balance can be achieved by using this function.

3.2.3 Gamma Correction

Gamma table to fix this phenomenon.

3.2.4 Color Dithering

MTL004 supports
In the latter case, users can turn on dithering function to avoid artificial contour due to truncation. The
dithering function works in two modes:

¨ Static dith ering: Dithering coefficient is f ixed.
¨ Temporal dithering: Dithering coefficient is time dependent.

k-1+Bl*Ik+Cl*Ik+1

and A, B, C are the scaling factors from interpolation table

Fig. 3.2.2 Scaling filter

(Rev. 0.95)

3.3 Outpu t Process or

General Descrip t io n

frame buffer present.

Revision 0.95 - 10 - 2000/06/14

MYSON

Because of no frame buffer, output displaying timing is locked by input timing and output frame rate is equal
to input frame rate. Users must program output timing and lock position to make sure that line buffer will not
overflow or underflow. MTL004 can automatically calculate Display Horizontal Total count to make the output
timing calculation easier. MTL004 also provides line buffer overflow/underflow status for calibrating lock

3.2.2 Display Timing modes

with a resolution of 6/8 bits per color. These two ports are PORT1 and PORT 2 respectively.

MTL004

TECHNOLOGY

3.3.1 Display Timing Generation

position.

Input Frame Output Frame

X

X: lock position

(Rev. 0.95)

Fig.

3.3.2 OSD Overl ay

MTL004 allows the integration of overlay data with the scaled output pixel stream. It provides a fully
compatible OSD interface. Individual OSD clock, OSD HSYNC and OSD VSYNC are sent to external OSD
device. MTL004 receives OSD Enable, OSD Red, OSD Green, OSD Blue, and OSD Intensity from external
OSD device.

3.3.3 RGB Out pu t Format

MTL004 output interface consists of two pixel ports, each containing Red, Green, and Blue color information
The control signals for the output port are display horizontal sync signal (DHSYNC), display vertical sync

signal (DVSYNC) and display data enable signal (DDEN).
All the signals mentioned above are synchronous to the output clock. The output timing relative to the active

edge of the output clock is programmable.
There are two RGB output formats:

¨ Singl e Pixel Mode

Is designed to support TFT panels with single pixel input. Only PORT1 is active. The frequency of DCLK is
equal to internal display clock.

¨ Dual Pixel Mode

Is designed to support TFT panels with dual pixel input. PORT1 and PORT2 are used. The first pixel is at
PORT1, with the second at PORT2.

Revision 0.95 - 11 - 2000/06/14

MYSON

R1OUT/G1OUT

R1OUT/G1OUT

R2OUT/G2OUT

SINGLE PO RT

3.2.3 Display Data Timing

MTL004

TECHNOLOGY

DDCLK
DDEN

000 rgb0 rgb1 rgb2 rgb3 rgb4

000 rgb0 rgb2 rgb4 rgb6 rgb8

DUAL PORT

/B1OUT

DDCLK

DHCLK
DDEN

/B1OUT

(Rev. 0.95)

/B2OUT

Fig.

000 rgb1 rgb3 rgb5 rgb7 rgb9

3.5 Host Inter fac e

Revision 0.95 - 12 - 2000/06/14

MYSON

means a LOW to HIGH transition of SDA when SCK is high. And data of SDA only changes when SCK is low.

C interface supports Random Write, Sequential Write, Current Address Read, Random Read and

For Random Write operation, it contains the slave address with R/W bit set to 0 and the word address which
is comprised of eight bits that provides the access to any one of the 256 bytes in the selected memory range.

MTL004

TECHNOLOGY

General Descrip t io n

The main function of Host Interface is to provide the interface between MTL004 and externa l CPU by 2-wire
I2C Bus or 3-wire series Bus or 8-bit Direct Bus selected by the input pins BUSSEL[1:0]. It can generate all
the I/O decoded control timing to control all the registers in MTL004. The other function is Screen Write,
which allows users to clear frame buffer, and display output as well.

3.5.1 I2C Serial Bus

The I2C serial interface use 2 wires, SCK (clock) and SDA(data I/O). The SCK is used as the sampling clock
and SDA is a bi-directional signal for data. The communication must be started with a valid START condition,
concluded with STOP condition and acknowledged with ACK condition by receiver.

The I2C bus device address of MTL004 is 0111010x.

AD[0] SCK, serial bus clock.

AD[1] SDA, bi-directional serial bus data.
The START condition means a HIGH to LOW transition of SDA when SCK is high, the STOP condition
Ref. Fig.3.5.1.

(Rev. 0.95)

SDA

SCK

START

Fig. 3.5.1 START, STOP ,and DATA definition

2

The I
Sequential Read operations.

¨ Random Write

Upon receipt of the word address, MTL004 responds with an Acknowledge and waits for the next eight bits of
data again, responding with an Acknowledge, and then the master generates a stop co ndition. Ref. Fig.3.5.2.

DATA
CHANGE

DATA
CHANGE

STOP

Revision 0.95 - 13 - 2000/06/14

MYSON

3.5.2 Random Write

Current Add ress Read

access address is n, the read data should access from address n+1. Upon receipt of the slave address with

bits data. After receiving data

S

MTL004

TECHNOLOGY

S
T
A
R
T

SDA

¨ Sequential Write

The initial step of Sequential Write is the same as Random Write, after the receipt of each word data,
MTL004 will respond with an Acknowledge and then internal address counter will increment by one for next
data write. If the master stops writing data, it will generate stop condition. Ref. Fig. 3.5.3.

T
A

SLAVE

R

ADDRESS

T

SLAVE

ADDRESS

ADDRESS

A

W

C
K

Fig.

WORD

WORD

ADDRESS

DATA n

DATA

A
C
K

DATA n+1

(Rev. 0.95)

S
T

O

P

A
C
K

S
T
O

DATA n+x

P

SDA

A

W

C
K

Fig. 3.5.3 Sequential Write

¨

MTL004 contains an address counter which maintains the last access address incremented by one. If the last
R/W bit set to 1, MTL004 generates an Acknowledge and transmits the eight

the master will generate a stop condition instead of an Acknowledge. Ref. Fig. 3.5.4.

S
T
A

R

ADDRESS

T

SDA

SLAVE

A
C
K

R

A
C
K

DATA

A
C
K

A
C
K

S
T
O
P

A
C
K

Fig. 3.5.4 Current Address Read

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MYSON

The operation of Random Read allows access to any address. Before the reading data operation, it must

the master issues the start condition, slave address and then the word
address it is to read. After the word address acknowledge, the master generating a start condition again and
slave address with R/W bit is set to 1. MTL004 then transmits the 8 bits of data. Upon the completion of

The Direct Bus use AD[7:0], HWR#, HRD#, ALE, HCS# as the interface with host. ALE is used to latch read

S

MTL004

TECHNOLOGY

¨ Random Read

issue a “dummy write” operation —

receiving data, the master will generate a stop condition instead of an Acknowledge. Ref. Fig 3.5.5.

S

T
A

R

T

A
C
K

SLAVE

ADDRESS

A

R

C

K

SDA

T
A
R
T

SLAVE

ADDRESS

WORD

ADDRESS

A

W

C
K

Fig. 3.5.5 Random Read

(Rev. 0.95)

S
T

DATA

O
P

¨ Sequenti al Read

The initial step can be as either Current Address Read or Random Read. The first read data is transmitted in
the same manner as for other read methods. However, the master generates an Acknowledge indicating it
requires more data to read. MTL004 continues to output data for each Acknowledge received. The output
data is sequential and the internal address counter increments by one for next read data. Ref. Fig. 3.5.6.

S
T
A

SLAVE

R

ADDRESS

T

SDA

A

R

C
K

Fig. 3.5.6 Sequential Read

3.5.2 3-wire Serial Bus

The 3-wire serial interface use 3 wires, SCK (clock) and SDA(data I) and SDAO(data O). The SCK is used as
the sampling clock, SDA is an input signal for data, and SDAO is an output signal for data. T he h andshaking
protocol is the same as for the 2-wire I2C serial bus.

DATA n

A
C
K

DATA n+1

DATA n+x

A
C
K

S
T

O

P

AD[0] SCK, serial bus clock.
AD[1] SDA, serial bus data in.
AD[2] SDAO, serial bus data out.

3.5.3 8-bit Direct Bus

or write address from AD[7:0] and HRD#, HWR# to access data. Ref. Fig. 3.5.7.

AD[7:0] Address and data multiplex bus.

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Writing data to Reg. F4h/D2 when

ADVS/ADHS Output con tr ol pro cess

pin to output ADHS which is HSYNC signal decoded from VGA input Composite signal by the

Writing data to F4h/D0 when

HWR/HRD

MTL004

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HRD# CPU re ad data strobe, Active Low.
HWR# CPU write data strobe, Active Low.
ALE ALE =1 latch read or write address, ALE=0 represents I/O data.
HCS# Enable signal for CPU access, Active Low.

AD[7:0]

ALE

Fig. 3.5.7 Direct Bus Timing

3.5.4 Interrupt

MTL004 supports one interrupt output signal (IRQ) which can be programmed to provide SYNC related or
function status related interrupts to the system. Upon receiving the interrupt request, Firmware needs to
firstly check the interrupt event by reading the Interrupt Flag Control registers (Reg. E8h and E9 h) to decide
what events are happening. After the operation is finished, Firmware needs to clear interrupt status by writing
the same registers Reg. E8h and E9h. Furthermore, by using the Interrupt Flag Enable registers (Reg. EAh
and EBh), each interrupt event can be masked.

DATAADDRESS

(Rev. 0.95)

3.5.5 Bi-dir ecti o n al GPIO

MTL004 supports four General Purpose Input and Output (GPIO) pins GPIO[3:0] on chip. The GPIO[3:0] pins
are bi-directional GPIO pins. There are two functions for GPIO[1:0] pins. One is to set them as bi-directional
GPIO pins, and the other is to set them as Composite decoded VSYNC/HSYNC for A/D converters in VGA
input path. The data and I/O direction of GPIO[3:0] pins are respectively controlled by Reg. F4h and F5h, and
each bit in registers is respectively mapped to GPIO[3:0] one by one. The following descript io n is t he process
to control GPIO[0] and GPIO[2] in detail, and the control processes of GPIO[1] and GPIO[3] are also the
same as follows respectively.

¨ Bi-directi on al GPIO control proc ess

q Setting Reg. F5h /D2 = 0 or 1 to assign GPIO[2] as input or output.
q

Reg. F4h/D2 when GPIO[2] is input.

¨

q Setting Reg. F5h/D0= 1 to assign GPIO[0] as output.
q Setting Reg. F6h/D0 = 0 to select output source from Reg. F4h/D6 or setting it as 1 to make GPIO[0]

MTL004.

q

F5h/D0 = 0. If F6h/D0 is set to 1, the GPIO[0] pin outputs ADHS for AD converters in VGA input path.

3.5.6 Update Register Contents

I/O write operation to some consecutive register set can have the “Double Buffer” effect by setting the
Reg. C1h/D4. Written data is first stored in an intermediate bank of latches and then transf erred to the active
register set by setting Reg. C1h/D1-0.

GPIO[2] is assigned to output status, otherwise reading data from

GPIO[0] is assigned to output only GPIO pin, that is, F6h/D0 = 0 and

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XI and XO by an external quartz crystal at 14.31818 MHz. First one is the same as to the oscillator clock at

: the desired display clock

MTL004

TECHNOLOGY

(Rev. 0.95)

3.6 On-Chip PLL

General Descrip t io n

The MTL004 needs two clock sources to drive synchronous circuits on chip. These clocks are generated
from the internal Phase Lock Loop (PLL) circuits with reference to the oscillator clock which is applied to pin

frequency (14.31818 MHz) to detect and measure graphic vertical and horizontal SYNC Frequency, Polarity
as well as Presence. The second is the display clock for display controller on chip and output signals to LCD
panel.

3.6.1 Reference Clock

It is the counting basis of counter values in SYNC Processor such as VS and HS period count registers; that
is, the read back values from these registers must multiply the period of this clock to estimate VS and HS
frequency. Incorporating with polarity and frequency information of VS and HS, it can show the input graphic
image mode and pixel clock frequency.

3.6.2 Display Clock

This clock is the synchronous clock for LCD panel. According to the LCD panel resolution of applications, the
display clock range is from 50 MHz to 100 MHz by means of choosing a set of appropriate values for M, N as
well as R. The formula used to calculate the desired frequency of display clock is as follows:

f

= f

mclk

5(M+2)/(N+2)51/R

osc

Where f

mclk

f

osc

M : post-divider ratio
N : pre-divider ratio
R : optional divider ratio

: oscillator clock with 14.31818 MHz

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