MXIC MX98715BEC Datasheet
1. INTRODUCTION
PRELIMINARY
MX98715BEC
APPLICATION NOTE
The purpose of this application note is to describe the
implementation of a PCI bus master 100 Base-TX F ast
Ethernet node using MXIC’ highly integrated single chip
Fast Ethernet NIC controller MX98715BEC. In details,
this document presents product overview , programming
guide, hardware design and layout recommendations that
can help you to quickly and smoothly implement a F ast
Ethernet adapter card.
As you can find in the MX98715BEC driver diskette,
MXIC already provideds a complete set of high quality
drivers for easier and more efficient way to interface with
MX98715BEC on the most popular Network Operating
Systems. Nev ertheless, there are still some special applications or environment not covered in the
MX98715BEC driver diskette. Driver developers, however, could still refer to the section of driver programming guide to accomplish the required driver. It is recommended that you should be familiar with the
MX98715BEC data sheet before reading this guide.
2. PRODUCT OVERVIEW
The MX98715BEC implements the 10/100Mbps MAC
layer and Physical layer on a single chip in accordance
with the IEEE 802.3 standard.
The MX98715BEC highly integrates with direct PCI bus
interface, including PCI bus master with DMA channel
capability, direct EEPROM as well as Boot ROM interface, and large on chip transmit/receive FIFOs. Also,
the MX98715BEC is equipped with intelligent
IEEE802.3u-compliant Nway auto-negotiation capability
allowing a single RJ-45 connector to link with the other
IEEE802.3u-compliant device without re-configuration.
T o optimiz e operating bandwidth, network data integrity
and throughput, the proprietary Adaptive Network
Throughput Control (ANTC) function is implemented. For
detailed product specification information, please refer
to the MX98715BEC data sheet.
3. HARDWARE DESIGN CONSIDERATIONS
3.1 SYSTEM APPLICA TION BLOCK DIAGRAM
A system block diagram for the MX98715BEC based
Fast Ethernet adapter card is shown as f ollowing:
P/N:PM0706
PCI Bus
Osc or Crystal
25MHz
EEPROM
MX98715BEC
Fig. 1
Boot ROM
LED
Magnetic
1
RJ45
REV. 0.2, NOV. 30, 2000
3.2 PCI CONNECTION
The MX98715BEC provides direct PCI bus interface to
PCI connector. Board designers should especially take
care of the four pins of TDI,TDO,PRSNT1# & PRSNT2#
that are only related to PCI bus connector . Boards that
do not implement JT A G Boundary Scan should tight TDI
and TDO together to pre vent the scan chain from being
broken.
Both pins PRSNT1# and PRSNT2# should be connected to ground indicating that the board physically
exists in a PCI slot and provids information about the
total power requirements ( less than 7.5W ) of the board.
3.3 OSCILLA TOR OR CR YST AL
The MX98715BEC is designed to operate with a 25MHz
oscillator or crystal module. The clock specification of
this oscillator should meet 25MHz +/- 50PPM.
MX98715BEC
CSR 9 <28> 0 1
LED 0 Activity Link speed
CSR 9<29> 0 1
LED 1 Good Link Link Activity
CSR 9<30> 0 1
LED 2 Link Speed Colision
CSR 9<31> 0 1
LED 3 Receive F/H duplex
CSR 9<24> 0 1
LED 4 Colision PMEB
3.4 BOOT R OM
The MX98715BEC support a direct boot ROM interface
allowing diskless workstations to remotely download operating system from network server. F or proper oper ation, the access time of adapt EPROM should not exceed 240ns.
3.5 SERIAL EEPROM
The MX98715BEC provides pins EECS,BPA0 (EECK),
BPA1 (EEDI) and BPD0 (EEDO) for directly accessing
the serial EEPROM. BPA0-1 and BPD0 ser ve as SK
(EECK), DI (EEDI) and DO (EEDO) respectively. The
contents of the EEPROM includes the ID information of
the MX98715BEC (V endorID , DeviceID , Sub-vendorID ,
Sub-deviceID and MAC ID), and the configuration parameters for software driver. The EEPROM contents
should be programmed according to MXIC's definition
as mentioned in Appendix A. Detailed software programming example is described in section 4.5.
3.6 PROGRAMMABLE LED SUPPORT
The MX98715BEC provides five pins LED[0:4] to control display LEDs. Displayed messages are programmable through setting CSR9 bits[31:28] & bit24. The maximum sinking current of these output pins is 16mA. Current limiting resistor (560 ohm) should be added to ensure proper operation. The following indicates the configuration setting table for LED display programming.
3.7 NETWORK INTERFACE TO MAGNETIC
COMPONENT
For isolating and impedance matching purpose, an isolating transformer with 1:1 transmit and 1:1 receive turns
ratio is required for transmit and receive twisted pair
interface. In Appendix B, several transformers that we
had verified successfully with MX98715BEC are listed
for quick reference purpose.
3.8 OPTIMIZED EQUALIZER COMPONENTS
M XI C ’ Fast Ethernet solution utilizes adaptive equalizer to compensate the attenuation and phase distortion induced by different lengths of cable. To optimize
transmit and receive signal quality, pins RTX should be
connected to external resistors 1K ohm (±1%) and then
to ground respectively.
3.9 Remote-Power -On and ACPI application
MX98715BEC fully supports Remote-Power-ON and
ACPI spec that meet PC99 requirement for powersensitive applications. It accepts the following wake-up
events in the power-down mode.
* Reception of a Magic Pack et.
* Reception of a Network wake-up frame.
* Detection of change in the network link state.
To put MX98715BEC into the sleep mode and enable
the wake-up events detection are done as following:
P/N:PM0706 REV. 0.2, NOV. 30, 2000
2
1. Write 1 to PPMCSR [8] to enable power management
feature.
MX98715BEC
(struct TX_RESOURCE *)((((unsigned int)tx_temp[i])+4)&
0xfffc);
}
2. Write the value to PPMCSR [1:0] to determine which
power state to enter .
If D1, D2 or D3
state is set, the PC is still turned on
hot
and is commonly called entering the Remote W ak e-up
mode. Otherwise if the main power on a PC is totally
shut off, we call that it is in the D3
state or Remote
cold
Po wer-On mode. T o sustain the oper ation of the Lancard,
a 5V standby power is required. Once the PC is turned
on, MX98715BEC loads the magic ID from EEPROM
and sets it up automatically . No register is needed to be
programmed. After then, simply turn off PC to enter D3
cold
state. In either Remote W ake-up mode or Remote P owerOn mode, the transceiver and the RX block are still alive
to monitor the network activity . If one of the three wak eup events occured, the following status is changed:
1. PPMCSR [15] (PME status) is set to 1.
2. CRS5 [28] (WKUPI) is set to 1.
3. PCI interrupt pin INTA# is asserted low .
4. LANWAKE pin is asserted high.
4. DRIVER PROGRAMMING GUIDE
This chapter will provide you the necessary information
for programming driver for the MX98715BEC based node.
Initialization module is introduced first that describes how
MX98715BEC is initialized before any other operations
can commence, then followed by actual implementation
examples for both transmit and receive operations.
4.1 INITIALIZA TION
initializeTheTransmitRing()
{
unsigned int i,j;
unsigned long physicaladdress;
for (i=0; i<NumTXBuffers; i++) {
/* memory allocation for tx descriptor_buffer (align 4) */
tx_resource[i]=
for (i=0; i<NumTXBuffers; i++) {
/* initialize the own bit to host tdes0 */
tx_resource[i]->ownership=0x00;
tx_resource[i]->tstatus=0x0000;
tx_resource[i]->tdes0_unused=0x00;
/* fill buffer_1_address tdes2 */
get_ea((void far *)(tx_resource[i]->tx_buffer_data),
&physicaladdress);
tx_resource[i]->buff_1_addr=physicaladdress;
/* fill buffer_2_address tdes3 */
if (i==NumTXBuffers-1) j=0;
else j=i+1;
get_ea((void far *)(tx_resource[j], &physicaladdress);
tx_resource[i]->buff_2_addr=physicaladdress;
}
}
initializeTheReceiveRing()
{
unsigned int i,j;
unsigned long physicaladdress;
for (i=0; i<NumRXBuffers; i++) {
/* memory allocation for rx descriptor_buffer (allign 4) */
rx_resource[i]=
(struct RX_RESOURCE *)((((unsigned int)rx_temp[i])+4)&
0xfffc);
}
for (i=0; i<NumRXBuffers; i++) {
/* set the own bit to chip rdes0 */
rx_resource[i]->frame_length=RDES0_OWN_BIT;
rx_resource[i]->rstatus=0x0000;
/* fill rdes1 */
rx_resource[i]->command=RDES1_BUFFRX_BUFFER_SIZE+rxpkt_size[i];
/* fill buffer_1_address rdes2 */
get_ea((void far *)(rx_resource[i]->rx_buffer_data),
&physicaladdress);
rx_resource[i]->buff_1_addr=physicaladdress;
/* fill buffer_2_address rdes3 */
if (i==NumRXBuffers-1) j=0;
else j=i+1;
get_ea((void far *)(rx_resource[j], &physicaladdress);
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MX98715BEC
rx_resource[i]->buff_2_addr=physicaladdress;
}
}
initialize()
{
unsigned long physicaladdress;
NIC_read_reg(&csr6);
NIC_write_reg(&csr6,csr6.value&(~(CSR6_SR|CSR6_ST)));
delay(200) : //wait TX&RX to enter stop state, or you can
//check bit17~bit19 (RX state) & bit 20~bit21 (TX state) in
//CSR5 to assure this condition.
InitializeTheTransmitRing (6);
InitializeTheReceiveRing (6);
NIC_write_reg(&csr0,CSR0_L_SWR);
delay(50);
NIC_write_reg(&csr0,csr0shadow);
//CSR0 shadow=0xFE58A000
get_ea((void far *)rx_resource[0],&physicaladdress);
NIC_write_reg(&csr3,physicaladdress);
get_ea((void far *)tx_resource[0],&physicaladdress);
NIC_write_reg(&csr4,physicaladdress);
NIC_write_reg(&csr7,csr7shadow);
//csr7shadow=9xE7FFa06D
NIC_write_reg(&csr16,csr16shadow);
//csr16shadow=0x0B2C000
//Clear status register
NIC_write_reg(&csr5,(unsigned long)0xffffffff);
NIC_write_reg(&csr6,csr6shadow);
//csr6shadow=0x01A8E202
setup_frame(TDES1_SETUP_LAST,perfect);
//Initialize CAM to accept self-address/broadcost address
//fromes
}
NIC_write_reg(&csr0,csr0.value|0x020000); //TAP=01
tx_pointer=tx_resource[0];
j=0;
editmode=1;
while (editmode) {
if ((tx_pointer->ownership & 0x80)==0) {
j++;
j%=tx_pkt_num;
if (tx_pointer->command & TDES1_LS_BIT)
tx_error_detect(tx_pointer->tstatus);
tx_pointer->ownership |= 0x80;
tx_pointer=tx_resource[j];
}
if (kbhit()) {
keycode_get();
if (M_code!=0) {
switch (M_code) {
case 0x1b: // ESC: quit
editmode=0;
break;
case 0x20:
NIC_read_reg(&csr6);
NIC_write_reg(&csr6,csr6.value^CSR6_ST);
break
default: break;
}
}
}
}
}
4.3 RECEPTION MODULE
bmrx()
4.2 TRANSMISSION MODULE
bmtx()
{
unsigned char editmode, j;
struct TX_RESOURCE *tx_pointer;
initialize();
fill_pattern(6); //fill pattern
NIC_write_reg(&csr6,csr6.value&(~CSR6_ST)); //stop
NIC_read_reg(&csr6);
NIC_write_reg(&csr6,csr6.value|CSR6_SF);
//store and forward
NIC_read_reg(&csr0)
P/N:PM0706 REV. 0.2, NOV. 30, 2000
{
unsigned char editmode,i,j;
unsigned long physicaladdress;
struct RX_RESOURCE *rcv_pointer;
initialize();
rcv_pointer=rx_resource[0];
j=0;
editmode=1;
while (editmode) {
// if data received
4
MX98715BEC
if ((rcv_pointer->frame_length & 0x8000)==0) {
j++;
j%=6;
if (rcv_pointer->rstatus & RDES0_LS)
rx_error_detect(rcv_pointer->rstatus);
rcv_pointer->frame_length |= 0x8000;
rcv_pointer=rx_resource[j];
}
if (kbhit()) {
keycode_get();
if (M_code!=0) {
switch (M_code) {
case 0x1b: // ESC: quit
editmode=0;
break;
default: break;
}
}
}
}
}
4.4 SPECIAL CODING of MX98715BEC
4.4.1 SPEED SELECTION
Speed selection for MX98715BEC is controlled by internal Nway registers.
The Internal NWay registers are remov ed and protocol
selection is controlled by Operation Mode Register
(CSR6) and 10Base-T Control Register (CSR14)
NWay Active 100F 100H 10F 10H
CSR6_PS 0 1 1 0 0
4.5 EEPROM ACCESSING
The following is a reference code for accessing the contents of EEPROM that stores ID information and node
configuration for the MX98715BEC.
/*************************************
* Read all content from EEPROM
**************************************/
eeprom_read()
{
unsigned int i, address, eeval;
char bit;
for (address=0; address<64; address++){
NIC_write_reg(&csr9,(unsigned long)0x04800);
eeprom_serial_in(0);
eeprom_serial_in(1); //command
eeprom_serial_in(1);
eeprom_serial_in(0);
for(i=0; i<6; i++){ //address serial in
bit = ((address>>(5-i)) & 0x01) ? 1:0;
eeprom_serial_in(bit);
}
eeval=0;
for(i=0; i<16; i++){ //dat serial out
NIC_write_reg(&csr9,(unsigned long)0x04803);
NIC_read_reg(&csr9);
eeval += (((unsigned long)0x008 & csr9.value)>>3)<<(15i);
NIC_write_reg(&csr9,(unsigned long)0x04801);
}
NIC_write_reg(&csr9,(unsigned long)0x04800);
c46[address*2] = eeval & 0x0ff;
c46[address*2+1] = (eeval >>8) & 0x0ff;
}
}
CSR6_PCS X 1 1 X X
CSR6_FD 1 1 0 1 0
CSR14_ANE 1 0 0 0 0
4.4.2 REGISTERS SETTING FOR DEVELOPING
Y OUR OWN DRIVER
The contents of CSR16 for MXIC 10/100Base NIC controllers should be set differently as follow:
MX98715BEC = 0x0b2cXXXX
/*************************************
* Write a word to EEPROM
**************************************/
eeprom_write(unsigned int address, unsigned int data)
{
unsigned int i;
char bit;
eeprom_wen();
NIC_write_reg(&csr9,(unsigned long)0x04800);
eeprom_serial_in(0);
eeprom_serial_in(1); //command
eeprom_serial_in(0);
eeprom_serial_in(1);
Meanwhile, you could directly access the Nway autonegotiation status from CSR20. Detailed format information please refer to MX98715BEC data sheet.
P/N:PM0706 REV. 0.2, NOV. 30, 2000
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