MXIC MX98205 Technical data

1. Features

INDEX

ADVANCED INFORMATION

MX98205

4-Port Dual-Speed Ethernet Switch Controller

• Provide single-chip controller of switching function
among 4 10/100Mbps Full/Half-duplex Ethernet ports
at wire speed.

• Support "Store-and-Forward" and "Cut-Through"
switching scheme

• Support 1.0GBps (@66MHz) expansion (inter-switch)
bus interface.

• Support source/destination address lookup, learning,
and aging.

2. Description

The MX98205 is a 4-port 10/100MBps single-chip
shared-memory Ethernet switch controller. A desktop
or segment switched Ethernet solution can be achieved
by combining MX98205, the necessary physical inter­faces and low-cost memory. All 4 ports are full-duplex
capable to provide private 20/200MBps bandwidth con­nection to power users or servers through external ph ysi­cal (PHY) layers . System manufacturers can cascade 2
MX98205 switch controllers to build an 8-port 10/
100MBps switched Ethernet box without extr a logic.

The operation of MX98205 is as following. Data frame
received from MII interface is buffered in Rx FIFO be­fore being transferred to external packet buffers under
control of queue manager (QM). Priority-based arbitra­tion is utilized in QM to maintain memory I/O bandwidth
and fast data transfer without contention. The address
information of incoming frame, namely source address
(SA) and destination address (DA), is extracted for ad­dress self-learning and determining the forwarding port.
MX98205 builds the filtering database (or called address
table) within external memory. Via hashing method, the
new SA is verified and a new address entry of MAC and
physical port I.D. mapping pair is recorded in address
table. Same hash transformation is applied to DA to
search the address table for determining forw arding port.
If DAs of received frames are not recognized through
address table, the frames would be f orwarded to all other
ports. Aging is provided to prevent address table from
being overridden. Aging mechanism checks entries in
the database to discard the least used ones. When the
forwarding port is found, received frames is relayed to
destination host through either Store-and-Forward or
Cut-Through switching scheme. The switching scheme
depends on the output buffer status of destination port.

• Support IEEE802.3x flow control for FDX and back­pressure flow control for HDX.

• Support up to 2MB sync. SRAM interface.

• Integrate 4 10/100MBps MAC controllers.

• Cascade 2 switch controllers to construct 8 10/
100MBps switched Ethernet ports in a box easily
without extra logic.

• 208-pin PQFP.

If the output buffer is empty and D A of received frame is
recognized, Cut-through scheme is applied. But mostly
there are frames queued in output buffer, Store-and­Forward scheme is applied.

Contention occurs if frames from different source hosts
are forwarded to the same destination host simulta­neously. Contention makes multiple frames be queued
in data buffers. The flow control mechanism is built to
prevent buffer overflow which forces controller to lose
packets. Controller sets some water marks on output/
input queue per port to justify the fullness of data buff­ers. As soon as buffer fullness is ov er the warning thresh­old, flow control mechanism is triggered to stop the re­spondent host(s) to transmit frames for sometime. For
half-duplex operation MII(s), the jam pattern is issued
to host. F or full-duplex operation MII(s), specific “pause”
frame of IEEE Std. 802.3x is issued to host. After b uffer
fullness drops below the safe threshold, controller re­leases flow control status to allow hosts to work in norm
condition.

System manufactures’ design flexibility is our concern
too. MX98205 provides 8-bit width Tx bus, 8-bit width
Uni-Rx bus and 8-bit width Broad-Rx bus associated
with command line interface for system scalability. Sys­tem manufacturers can cascade 2 MX98205s to make
8-port 10/100MBps switched Ethernet box without ex­tra logic. Also system vendors can build 10/100Mbps
dual-speed repeater with MX98205. In the application
two of switch ports are connected by 10M segment and
100M segment separately for segment switch, other two
switch ports could be used for uplink and server con­nection.

P/N:PM0584 REV. 0.0, OCT. 20, 1998

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MX98205

INDEX

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