• Compatible with all PC Card Services and Socket
Service.
• Fast ATA host-to-buffer burst transfer rates up to
20MB/sec. which support PIO mode 4(16.6MB/sec)
and DMA mode 2(16.6MB/sec).
• Automatic sensing of PCMCIA or True IDE host inter
face.
• Integrated PCMCIA attribute memory of 256 bytes
(CIS)
- CIS and Buffer RAM use same SRAM area to
simplify internal bus design
• PCMCIA card configuration register support.
• Polarity control for Host reset signal.
• PCMCIA twin card support.
• PCMCIA based ATA address decode support.
• Emulate the IBM task file for PC/AT.
• Separate status for Host reset signal and Host program
reset.
• Separate Host and Disk interrupt pins.
Flash Memory Interface
Buffer RAM Manager
• Dual port circular Buffer RAM control
• 1KB data Buffer RAM.
• Automatically correct error data in Buffer RAM.
- Single word error correct and double word detect.
• Provide logic to speed up Buffer RAM access.
• Support 8 bit as well as 16 bit transfer on host bus.
DSP core
• High performance MX93011 DSP (21Mips) core.
• 4KB Internal RAM(direct access).
• 2KB Internal expansion RAM(indirect access) for store
data or shadow ROM space.
• ICE debugging mode supported to ease system
verification.
• Lower power and automatic power saving operation.
- Automatic Standby Mode. (Operating Current < 10mA,
VCC=5.5V), wake-up by interrupt signal.
- Very Low Operating Current Sleep Mode.
(<1mA,VCC=5.5V), wake-up by Host reset signal or
Host program reset or ATA command asserted by host.
Tec hnology
• Support all the control signals to execute read/ write/
erase operation for flash memory.
• Flexible Disk Capacity Configuration for series type or
linear type flash memory
- Upto 32MB(unformatted) capacity for 16 pcs. 16Mbit
linear type flash memory.
- Upto 1GB(unformatted) capacity for 32 pcs. 256Mbit
series type flash memory.
• Flash Memory Power Down or write protect control
support.
• Flash Memory Ready/Busy status detect.
• Inverted data bus control to reduce flash memory
program/erase operation in DOS FAT and ECC code
field.
• Optional store firmware in flash memory array w/o
external ROM while MXIC's MX29F1610(linear type)
used.
- Allow code fetch in Shadow ROM during flash
memory program or erase.
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• 128 pin LQFP(14X14X1.4 mm3)
• 128 pin TQFP(14X14X1.0 mm3)
• 0.6um Low-power, High-speed CMOS technology.
• 5Volt ± 10% or 3.3Volt ± 5%.
Utility Support
• Provide integrated test environment with 82365SLcompatible adaptor.
• Firmware upload from host and allows easy upgrade for
custom feature.
• Physical devices test cover basic PCB test after
assembly and more detial analysis.
• Logical sector test cover SSD functionality and data
transfer test.
1
2. GENERAL DESCRIPTION
MX9691L
The Macronix's Solid State Disk controller MX9691L is
a wide-range supply voltage(3.3V olt~5V olt) and fully integrated flash memory controller that provides all the
control logic for PCMCIA/True IDE host and flash
memory . The MX9691L combines 1KB dual-port b uffer
and buffer manager , integrated MX93011 DSP core, and
a complete host interface for both the PC Card ATA and
True IDE standard.
The MX9691L provides flexible disk capacity configuration and supports all the control signals to execute
read/write/erase operation for linear type or series type
flash memory chip. It is typically configured with up to
32MB(unformatted) capacity for 16 pcs. 16Mbit linear
flash memory or 1GB(unformatted) capacity for 32 pcs.
256Mbit series type flash memory while capacity
extention mode is enabled f or series type flash memory
used. The MX9691L also provides flexible architecture
to implement defect management and wear-lev eling by
firmware for series type or linear type flash memory.
In linear mode, the linear type 16 Mbit flash memory is
supported, such as MXIC's MX29F1610 etc. In flash
memory interface there are two banks of flash memory to
be provided. Each bank support 8 pcs. flash memory when
linear type flash memory is used. In series mode, the series type 16MBit/32Mbit/64Mbit/256Mbit flash memory is
supported, such as Toshiba's TC5816FT/TR or
TC58V32FT, Samsung's KM29N16000T/R or
KM29N32000TS/RS etc. Each bank support or 16 pcs.
flash memory when series type flash memory is used.
The MX9691L is fully compliant with the PC Card ATA
specification. It includes 256 bytes of integrated attribute
memory(for the required Card Information Structure) and
four Card Configuration registers. The PCMCIA device
driver can access the MX9691L's ATA command block
through four different modes b y writing the different modes
by writing the configuration index of the attribute memory
configuration option register.
(CMOS)Both pins include internal pull-up resistors that is default in
PCMCIA mode.
IOR#,IOW#107,110IHost I/O access.
(CMOS)Both pins include internal pull-up resistor.
HRESET/HRESET#100IThe host reset signal, when active, initializes the control/
(CMOS)status registers and stops any command in process.
In PCMCIA mode, the signal is active high.
In True IDE mode, this signal is active low.
This signal include internal pull-down resistor.
WAIT/ IOCHRDY98O,ODWAIT or INPUT CHANNEL READY : In both PCMCIA and
(CMOS)True IDE modes, this signal holds host transfers until the
controller is ready to respond.
RDY/BSY#/119O, ZREAD Y/B USY or HOST INTERR UPT : In PCMCIA mode,
IREQ#/(CMOS)this signal has two functions. In PCMCIA common memory
HOSTINTmode, this signal is ready/busy. It is asserted busy by the
reset logic, and can be deasserted by the DSP or
represents the ready/busy bit of ATA status register.
In PCMCIA I/O mode, this signal is IREQ#.
In True IDE mode, this active high signal is HOSTINT, which,
when enable, send an interrupt to the host.
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MX9691L
SymbolNo.TypeDescription
WP/IOCS16#83O,ODWRITE PROTECT or 16-bit I/O TRANSFER :
(CMOS)In PCMCIA mode, this bit has two functions. In PCMCIA
common-memory mode,this signal indicates write protect.
In PCMCIA I/O mode, when IOIS16# is asserted low, it
indicates that a 16-bit data transfer is active on PCMCIA
bus.
In True IDE mode, the IOCS16# signal indicates that a
16-bit buffer transf er is activ e on the host b us .
This open drain signal is only driven on assertion(low).
REG#/DA CK#95IAttribute memory and I/O select :
(CMOS)In PCMCIA mode, this signal is used to select attribute
memory and I/O space. In T rue IDE mode, this signal is
used during DMA with the DREQ, IOR# and IOW# signals
to transfer data between the host and the MX9691L. This pin
includes an internal pull-up resistor.
HCE1#/115ICard enable 1 or Chip select 0:In PCMCIA mode,this signal
CS1FX#(CMOS)is card enable 1. This signal can enable either even or odd
numbered-address bytes onto HD7:0. In True IDE mode, this
signal accesses the MX9691 command block registers. This
input is ignored during DMA data transfer, i.e. when the
DA CK# signal is low. This pin includes an internal pull-up
resistor.
HCE2#/114ICard enable 2 or Chip select 1:
CS3FX#(CMOS)In PCMCIA mode,this signal is card enable 2. This signal
can enable odd numbered-address bytes onto HD15:8. In
True IDE mode, this signal accesses the MX9691L control
block registers. This pin includes an internal pull-up
resistor.
INPACK#/ DREQ118OInput Acknowledge or DMA request :In PCMCIA mode, this
(CMOS)signal is asserted when the MX9691 is configured to respond
to I/O card read cycles at all addresses. In T rue IDE mode,
this signal is DREQ and is issued during DMA transfers to
indicate that the MX9691L is ready for DMA transfer.
SPKR/DASP#93I/OSpeaker or slave present : In PCMCIA mode, the
(CMOS)output-enable f or this signal is controlled b y the card
configuration registers. In T rue IDE mode, this signal is used
as the slave-present detector .
STSCHG/90I/OStatus change or pass diagnostics :In PCMCIA mode, this
PDIAG#(CMOS)signal is used to indicate changes in the RDY/BSY#,WP
signals in card configuration registers. In True IDE mode,
this active low signal is used between two embedded ATA
drive to indicate that the drive in slave mode has passed
diagnostics.
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MX9691L
External Memory Bus Interface
SymbolNo.TypeDescription
D[15:0]33-37,39-41, I/ODSP IO/RAM/ROM/FLASH memory array external data bus.
55-58,60-63 (CMOS)These pins include internal pull- up resistors.
A[15:0]3-5,8-11,I/OIn F ree-run mode, these signals are output that used as DSP
22-24,26-31 (CMOS)IO/RAM/ROM e xternal address. A14-A0 are used f or flash
memory array address also. In upgrade mode, these
address are used for ROM address that controlled b y
CYH,CYL registers. In ICE-deb ugging mode,these address
are input, asserted by DSP ICE(external MX93011 DSP).
And the internal DSP is disabled at this time.
These pins include internal pull-up resistors.
PCE#67I/OIn Free-run mode, this signal is output that is used as
(TTL)external program chip enable. In upgrade mode , this signal
is drived to high. In ICE-deb ugging mode, this signal is
input, asserted by DSP ICE(external MX93011 DSP). And
the internal DSP is disabled at this time. This pin includes a
bus holder circuit.
DCE#6 8I/OIn Free-run mode, this signal is output that is used as
(TTL)external data chip enable. In upg rade mode, this signal is
drived to high. In ICE-debugging mode , this signal is input,
asserted by DSP ICE(external MX93011 DSP). And the
internal DSP is disabled at this time. This pin includes a bus
holder circuit.
RD#65I/OIn Free-run mode, this signal is output that is used as DSP
(TTL)IO/RAM/ROM external read. In upgr ade mode, this signal is
output and asserted when the data register is read in host
interface. In ICE-deb ugging mode , this signal is input, as
serted by DSP ICE(external MX93011 DSP). And the
internal DSP is disabled at this time.
This pin includes a bus holder circuit.
WR#66I/OIn Free-run mode, this signal is output that is used as DSP
(TTL)IO/RAM/ROM external write. In upgrade mode , this signal is
drived to high. In ICE-debugging mode , this signal is input,
asserted by DSP ICE(external MX93011 DSP). And the
internal DSP is disabled at this time. This pin includes a bus
INT1#14I/OIn Free-run mode, this signal is input that is used as
(CMOS)interrupt pin. Interrupt will be internally asserted also when
data transfer done, or command end. In ICE-deb ugging
mode, this signal is output and asserted when data transfer
done, or command end. This pin includes an pull-up resistor .
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MX9691L
SymbolNo.TypeDescription
HOLD#16I/OIn Free-run mode, this signal is input that is used as holding
(CMOS)DSP clock down and release b us. Bus hold will be internally
asserted also when upgrade mode enable. In ICE-debu g
ging mode, this signal is output and asserted when upgrade
mode enable. This pin includes an pull-up resistor.
HLDA#73I/OIn Free-run mode, this signal is output that is used as ack to
(CMOS)HOLD# signal. This signal will be internally sent to PCMCIA/
AT A interf ace also when upg rade mode enab le . In ICE-de
bugging mode, this signal is input and ack to HOLD# when
upgrade mode enable.
XF#/SCTRL#74OSleep control, this pin can be directly asserted to low while
(CMOS)power do wn bit is set b y DSP. This pin is connected to
external RC circuit. Def ault inactiv e (Logic High).
In ICE-debugging mode, this signal is used to reset DSP.
Flash Memory Interface
SymbolNo.TypeDescription
F A19/CLE12OIn linear mode, this signal is used as flash memory chip high
(CMOS)address line 19. In series mode, this signal is used as flash
memory chip command latch enable.
F A18/ALE/20I/OIn linear mode, this signal is used as flash memory chip high
ICEMODE(CMOS)address line 18. In series mode, this signal is used as flash
memory chip address latch enable. This signal is also used
to select whether the MX9691 initializes in Free-run mode
or in ICE-debugging mode at power-on reset. If this pin go
high, then the MX9691L will switch to F ree-run mode at
power-on reset,and if this pin remains low , then the MX9691L
will initializes in ICE-debugging mode. This pin includes an
internal pull-up resistor.
ICE-debugging mode select :
ICEMODE=1 —> Free-run mode.
ICEMODE=0 —> ICE-debugging mode.
F A17/ER OM21I/O(CMOS) This signal is used as flash memory chip high address line
17. This signal is also used to select whether the firmware
store in linear type flash memory array or in separate
external ROM at power-on reset. If this pin go high, then the
firmware will be executed in linear type flash memory arra y,
and if this pin remains low , then the firmware will be executed
in separate external ROM.
Store firmware in external ROM or linear type Flash memory
array select:
EROM = 0 —> Store in External ROM.
EROM = 1 —> Store in flash memory array.
This pin includes an internal pull-up resistor.
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MX9691L
SymbolNo.TypeDescription
F A[16:15]/1-2I/OThis signal is used as flash memory chip high address line
A TADET[1:0](CMOS)16-15. These signals are also used to select configuration in
T rue IDE mode at power-on reset. ATADET1 is connected to
DSP's IPT1. ATADET0 is connected to DSP's IPT0. VDD is
connected to IPT2.
Master/Slave selection in True IDE mode :
AT ADET1AT ADET0mode selected
11one driv e
00master of tw o drives
10sla v e of tw o drives
This power-on configuration can be accessed from PCMCIA/
AT A port 601Ch bit3-2. These pins include internal pull-up
resistors.
RDFLASH1#54OFlash memory ouptut enable 1 for bank1:
(CMOS)This signal will be asserted by flash memory read operation
when flash memory read address latch, port 601Dh
bit 8= 1(i.e. FA23=1).
Note: Flash memory access window is mapped to 32KW
data and code space 8000h~ffffh.
RDFLASH0#42OFlash memory ouptut enable 0 for bank0:
(CMOS)This signal will be asserted by flash memory read operation
when flash memory read address latch, port 601Dh
bit 8 = 0(i.e. FA23=0).
WRFLASH1#19OFlash memory write enable 1 for bank1:
(CMOS)This signal will be asserted by flash memory write operation
when flash memory write address latch, port 601Fh
bit 8 = 1(i.e. FA23=1).
WRFLASH0#18OFlash memory write enable 0 for bank0:
(CMOS)This signal will be asserted by flash memory write operation
46-47(CMOS)In linear mode, These signals are decoded from port 601Dh
49-52bit 7-5 when flash memory read or port 601Fh bit 7-5 when
flash memory write.
Decoding combination :
bit7 bit6 bit5 FCE[7:0]#
0 0 0 11111110
0 0 1 11111011
0 1 0 11101111
0 1 1 10111111
1 0 0 11111101
1 0 1 11110111
1 1 0 11011111
1 1 1 01111111
In series mode, These are decoded from port 601Dh bit 7-5
only when port 601Eh bit 2 is set.
PWD0#/WP#32OIn linear mode, this signal is used as deep power-down
(CMOS)control of flash memory chips of bank0. PWD0# is activ e
low and also locks out erase or progr am operation providing
data protection during power transitions. P o wer do wn pin
PWD0# will be active if FA23=1.
In series mode, this signal is used to protect the device from
inadvertent programming or erasing. WP# is activ e lo w.
PWD1#/SE#64OIn linear mode, this signal is used as deep power-down
(CMOS)control of flash memory chips of bank1. PWD1# is activ e
low and also locks out erase or progr am operation providing
data protection during power transitions. P o wer do wn pin
PWD0# will be active if FA23=0. In series mode,this signal
is used to spare area control. SE# is active low.
FRY/FBY#13IFlash memory Ready/busy input:
(CMOS)This signal indicate the state of erase or program operation
in flash memory chips.This pin includes an internal pull-up
resistor.
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MX9691L
Control ROM interface
SymbolNo.TypeDescription
ROMCS#/75OROM chip select/Flash memory data buffer enable :
FWIN#(CMOS)In Free-run mode, this signal is used as R OM chip enable if
firmware that stored in external ROM. In ICE-deb ugging
mode, this signal is used as flash memory data buffer (74640)
enable if firmware that stored in flash memory array.
ROMWR#/FDIR76OROM write enable/Flash memory data buffer direction
(CMOS)control:
In Free-run mode, this signal is used as ROM write enable if
firmware that stored in external ROM. In ICE-deb ugging
mode, this signal is used as flash memory data buffer (74640)
direction control if firmware that stored in flash memory
array.
Miscellaneous
SymbolNo.TypeDescription
X179ICrystal input.
X278OCrystal ouput.
SWAIT#71I(CMOSSleep wait, this pin is connected to external RC circuit.
Schmitt)
N.C.70ONo connect.
TEST81IThis signal is used to select the main system clock, either
(CMOS)from external clock source if this signal is high or from
internal PLL circuit if this signal is low. This pin includes an
internal pull-up resistor.
PWR_RST#82I(CMOSPower on reset, CMOS Schmite-triggered:
Schmitt)The MX9691L include debouncing circuit to stabilize
internal DSP reset signal.
LED#6OLED output:
(CMOS)This signal is connected to external LED in debugging
system to indicate system status. The LED will be turn-on
during reset. The contorl firmware will turn off the LED after
H/W initialization and pass diagnostics. If system f ail, the
control firmware will flash the LED to indicate some error
occur. This signal will be high if port 601Ch bit0 set to 1 or
OPTR bit2 set to 1.
VCC17,45,53,5 or 3.3 volt Power pin
72,80,105,
112
GND7,25,38,Ground pin
48,59,69,
77,91,108,
120
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5. Functional and Operation Description
5-1. Block Dia gram
MX9691L
Host Interface
PCMCIA/ATA
Clock
Clock & Reset
Register Bank
PCMCIA/ATA
interface
256 Byte
CIS RAM
External Memory Bus
MX93011
DSP CORE
1KB Buffer
RAM
Buffer RAM
Control
4KB Internal
RAM
2KB Internal
RAM
Flash Memory
Control
ECC Control
Logic
MX9691L Signal Chip Solid State Disk Controller
Flash
Interface
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5-2. System Memory Map
Data Space :
AddressFunction & Usage
0000h~007fhInternal RAM (128W) to store control variables
0080h~07ffhInternal RAM(1920W) for flash memory algorithm usage
0800h~5fffhUser define (22kW)
6000h~63ffhI/O range(1kW): ATA CTL. use I/O range (6000h~601fh)
6400h~6fffhUser define (3kW)
7000h~73ffhUser define (1kW)
7400h~77ffhInternal RAM (1kW) for expansion RAM or shadow R OM space
7800h~7fffhROM Data space(2kW)
8000h~ffffhFlash memory access windows(32kW)
Program Space :
AddressFunction & Usage
0000h~77ffhROM program space (32kW)
7800h~7fffhUnused
8000h~ffffhFlash memory access windows(32kW)
MX9691L
5-3. P o wer-on detection
* Store firmware in external ROM or Flash memory array
:
FA17/EROM = 0 —> Store in External ROM
FA17/EROM = 1 —> Store in flash memory array
* Master/Slave selection in True IDE mode :
FA16/ATADET1 FA15/ATADET0 mode selected
1 1 one drive
0 0 master of two drives
1 0 slave of two drives
Note : For some customers design the master/slave
selection is selected by only one jumper that may be
FA16 or FA15. It need to change firmware only.
* ICE debugging mode select :
FA18/ICEMDOE = 0 ---> ICE-debugging mode
FA18/ICEMODE = 1---> Free-run mode, DSP fetch
code from external memory bus and execute it.
* Flash memory data buffer control
ROMCS# is replaced by FWIN# if ICE-debugging
mode & firmware in linear type flash memory array.
ROMWR# is replaced by FDIR if ICE-debugging mode
& firmware in linear type flash memory array.
* PCMCIA mode or True IDE mode select
HOE# Mode
0 True IDE mode
1 PCMCIA mode
To enable True IDE mode this input should be grounded
by the host.
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MX9691L
5-4. Decoding Configuration of all registers in Host interface
* Common Momory Mode Decode
Register AddressRegister Read EnableRegister Write Enable
CE1# CE2#REG# HA10 HA9:4 HA3:0HOE# =0HWE# = 0
0010xh000xbRead Data Register HD[15:0] Write Data Register HD[15:0]
0110xh0000bRead Data HD[7:0]Write Data HD[7:0]
Even & Odd byteEven & Odd byte
1010xh0000bError Status HD[15:8]Features HD[15:8]
0110xh0001bError Status HD[7:0]Features HD[7:0]
1010xh0001bError Status HD[15:8]Features HD[15:8]
0010xh001xbSector Count HD[7:0]Sector Count HD[7:0]
Sector Number HD[15:8]Sector Number HD[15:8]
0110xh0010bSector Count HD[7:0]Sector Count HD[7:0]
0110xh0011bSector Number HD[7:0]Sector Number HD[7:0]
1010xh0011bSector Number HD[15:8]Sector Number HD[15:8]
0010xh010xbCyl. Low HD[7:0]Cyl. Lo w HD[7:0]
Cly. High HD[15:8]Cly. High HD[15:8]
0110xh0100bCyl. Low HD[7:0]Cyl. Lo w HD[7:0]
0110xh0101bCly. High HD[7:0]Cly . High HD[7:0]
1010xh0101bCly. High HD[15:8]Cly. High HD[15:8]
0010xh011xbDrive/Head HD[7:0]Drive/Head HD[7:0]
Ctl. Status HD[15:8]Command HD[15:8]
0110xh0110bDrive/Head HD[7:0]Drive/Head HD[7:0]
0110xh0111bCtl. Status HD[7:0]Command HD[7:0]
1010xh0111bCtl. Status HD[15:8]Command HD[15:8]
0010xh100xbRead Data Register HD[15:0] Write Data Register HD[15:0]
(Duplicate)(Duplicate)
0110xh1000bRead Data HD[7:0]Write Data HD[7:0]
Even & Odd byte (Duplicate) Even & Odd byte (Duplicate)
1010xh1001bRead Data HD[15:8]Write Data HD[15:8]
Odd byte (Duplicate)Odd byte (Duplicate)
0110xh1001bRead Data HD[7:0]Write Data HD[7:0]