MXIC MX9691 Technical data

FEATURES

INDEX

PRELIMINARY

MX9691

SINGLE CHIP SOLID STATE DISK CONTROLLER

Host Interface

• Fully compatible with PCMCIA Release 2.1, and PC Card ATA Release 1.02 specification.

• Compatible with all PC Card Services and Socket Service.

• Fast ATA host-to-buffer burst transfer rates up to 20MB/ sec. which support PIO mode 4(16.6MB/sec) and DMA mode 3(16.6MB/sec).

• Automatic sensing of PCMCIA or ATA host interface.

• Integrated PCMCIA attribute memory of 256 bytes (CIS).

- CIS and Buffer RAM use same SRAM area to simplify internal bus design

• PCMCIA card configuration register support.

• Polarity control for host reset signal.

• PCMCIA twin card support.

• PCMCIA based ATA address decode support.

• Emulate the IBM task file for PC/AT.

• Separate status for Bus reset and Host program reset.

• Separate Host and Disk interrupt pins.

Flash Memory Interface

• Support all the control signals to execute read/write/ erase operation for flash memory.

• Upto 32MB(unformatted) capacity for 16 pcs. 16Mbit flash memory or 64MB(unformatted) capacity for 16 pcs. 32Mbit flash memory.

• Flash Memory Power Down or write protect control support.

- Don't power down the flash memory chip which used to store firmware

• Flash Memory Ready/Busy status detect.

• Inverted data bus control to reduce program operation in DOS FAT and ECC code field.

• Optional store firmware in flash memory array w/o externalROM.

- Shadow ROM control to allow code fetch during data program or erase

• Media speed is upto 8MB/sec, sustain read data rate and 125KB/sec write data rate.

Buffer RAM control

• Dual port circular Buffer RAM control

• 1KB data Buffer RAM.

• Automatically correct error data in Buffer RAM.

- Single word error correct and double word detect.

• Provide logic to speed up Buffer RAM access.

• Support 8 bit as well as 16 bit transfer on host bus.

DSP core

• High performance MX93011 DSP (21Mips) core.

• 4KB Internal RAM(direct access).

• 2KB Internal expansion RAM(indirect access) for store data or shadow ROM space.

• ICE debugging mode supported to ease system verifi cation.

• Lower power and automatic power saving operation Operating current for 25MHz system speed

- Active mode < 40mA

- Idle mode < 35mA

- Standby mode < 10mA

- Sleep mode < 1mA

Tec hnology

• 128 pin TQFP

• 0.6um Low-power, High-speed CMOS technology.

• Five-volt-only power supply.

Utility Support

• Upload firmware from Host.

• Physical Devices test.

• Preformat.

• CIS Manufacturer code and Model code edit.

P/N:PM0502 REV. 1.2, NOV. 27, 1997

GENERAL DESCRIPTION

INDEX

MX9691

The Macronix's Solid State Disk controller is fully integrated flash memory controller that provides all the control logic for a PC Card ATA flash memory . The MX9691 combines 1KB dual-port buffer and buffer manager , integrated MX93011 DSP core , and a complete host interface for both the PC Card ATA and ATA standard.

The MX9691 is typically configured with up to 32MB(unformatted) capacity for 16 pcs. 16Mbit flash memory or 64MB(unformatted) capacity for 16 pcs. 32Mbit flash memory . The MX9691 supports all the con-

trol signals to execute read/write/erase operation f or flash memory chip.

The MX9691 is fully compliant with the PC Card ATA specification. It includes 256 b ytes of integrated attribute memory(for the required Card Information Structure) and four Card Configuration registers. The PCMCIA device driver can access the MX9691 ATA command block through four different modes b y writing the different modes by writing the configuration index of the attribute memory configuration option register.

PIN DESCRIPTION

Host Interface

Symbol No. Type Description HA[10:0] 92,94, 96-97, I Host address line 10-0.

99,101-103, These pins include internal pull-up resistors. 106,109,113

HD[15:0] 84-89,116-117, I/O Host data line 15-0.

121-128 These pins include internal bus holder circuit that keep previous state

when tri-state.

HOE#,HWE# 104,111 I Host memory read/write/mode select : Both pins include internal pull-

up resistors that is default in PCMCIA mode.

IOR#,IOW# 107,110 I Host I/O access.

Both pins include internal pull-up resistors. HRESET/ 100 I The host reset signal, when active, initializes the control/status HRESET# registers and stops any command in process.In PCMCIA mode, the

signal is active high. In ATA extension mode, this signal is active low.

This signal include internal pull-down resistor. WAIT/ 98 O,OD WAIT or INPUT CHANNEL READY : In both PCMCIA and AT A IOCHRD Y extension modes, this signal holds host transfers until the controller is

ready to respond. RDY/BSY#/ 119 O,Z READY/BUSY or HOST INTERRUPT : In PCMCIA mode , this signal IREQ#/ has two functions. In PCMCIA common memory mode, this signal is HOSTINT ready/busy . It is asserted busy by the reset logic, and can be deasserted

by the local uC. In PCMCIA I/O mode, this signal is IREQ#. In ATA

extension mode, this activ e high signal is HOSTINT, which, when

enable, send an interrupt to the host.

MX9691

INDEX

Symbol No. Type Description WP/IOCS16# 83 O,OD WRITE PROTECT or 16-bit I/O TRANSFER : In PCMCIA mode, this

bit has two functions. In PCMCIA common-memory mode,this signal

indicates write protect. In PCMCIA I/O mode, when IOIS16# is as

serted low, it indicates that a 16-bit data transf er is activ e on PCMCIA

bus. In AT A extension mode , the IOCS16# signal indicates that a 16-bit

buffer transf er is activ e on the host b us. This open drain signal is only

driven on assertion(low). REG#/DA CK# 95 I Attribute memory and I/O select : In PCMCIA mode, this signal is used

to select attribute memory and I/O space. In AT A e xtension mode, this

signal is used during DMA with the DREQ, IOR# and IOW# signals to

transfer data between the host and the MX9691. This pin includes an

internal pull-up resistor. HCE1#/ 115 I Card enable 1 or Chip select 0: In PCMCIA mode ,this signal is card CS1FX# enable 1. This signal can enable either ev en or odd numbered-address

bytes onto HD7:0. In ATA extension mode, this signal accesses the

MX9691 command block registers. This input is ignored during DMA

data transfer , i.e . when the DACK# signal is low. This pin includes an

internal pull-up resistor. HCE2#/ 114 I Card enable 2 or Chip select 1: In PCMCIA mode ,this signal is card CS3FX# enable 2. This signal can enable odd numbered-address bytes onto

HD15:8. In ATA extension mode, this signal accesses the MX9691

control block registers. This pin includes an internal pull-up resistor. INPACK#/ 11 8 O Input Acknowledge or DMA request : In PCMCIA mode , this signal is DREQ asserted when the MX9691 is configured to respond to I/O card read

cycles at all addresses. In ATA extension mode, this signal is DREQ

and is issued during DMA transfers to indicate that the MX9691 is ready

for DMA transfer. SPKR/DASP# 93 I/O Speaker or slave present : In PCMCIA mode, the output-enable f or this

signal is controlled by the card configuration registers. In AT A

extension mode, this signal is used as the sla v e-present detector. STSCHG/ 90 I/O Status change or pass diagnostics : In PCMCIA mode, this signal is PDIAG# used to indicate changes in the RDY/BSY#,WP signals in card con

figuration registers. In ATA extension mode, this active low signal is

used between two embedded ATA drive to indicate that the drive in

slave mode has passed diagnostics.

MX9691

INDEX

Microcontroller interface :

Symbol No. Type Description D[15:0] 33-37, I/O DSP IO/RAM/ROM/FLASH memory array external data bus . These

39-41, pins in clude internal pull-up resistors. 55-58, 60-63

A[15:0] 3-5, I/O In normal mode, these signals are output that used as DSP IO/RAM/

8-11, ROM external address. A14-A0 are for flash memory array address 22-24, also. In upgrade mode, these address is used for R OM address that 26-31 controlled by CYH,CYL registers. In ICE debugging mode, these ad

dress are input,asserted by external MX93011 DSP. The internal DSP

is disabled. These pins include internal pull-up resistors. PCE# 67 I/O In normal mode, this signal is output that is used as e xternal program

chip enable. In upgrade mode, this signal is drived to high. In ICE de

bugging mode, this signal is input, asserted by external MX93011 DSP.

The internal DSP is disabled. This pin includes a bus holder circuit. DCE# 68 I/O In normal mode, this signal is output that is used as external data chip

enable. In upgrade mode, this signal is drived to high. In ICE debug

ging mode, this signal is input, asserted by external MX93011 DSP.

The internal DSP is disabled. This pin includes a bus holder circuit. RD# 65 I/O In normal mode, this signal is output that is used as DSP IO/RAM/

ROM external read. In upgr ade mode , this signal is output and as

serted when the data register is read in host interface. In ICE deb u g

ging mode, this signal is input, asserted by external MX93011 DSP.

The internal DSP is disabled. This pin includes a bus holder circuit. WR# 66 I/O In normal mode, this signal is output that is used as DSP IO/RAM/

ROM external write. In upgr ade mode , this signal is driv ed to high. In

ICE debugging mode, this signal is input, asserted by external MX93011

DSP. The internal DSP is disabled. This pin includes a bus holder cir

cuit. NMI# 15 I Non maskable interrupt pin. This pin includes an pull-up resistor. INT1# 14 I/O In normal mode, this signal is input that is used as interrupt pin.

Interrupt will be internally asserted also when data transfer done , or

command end. In ICE deb ugging mode , this signal is output and as

serted when data transfer done, or command end. This pin includes

an pull-up resistor.

MX9691

INDEX

Symbol No. Type Description HOLD# 16 I/O In normal mode, this signal is input that is used as holding DSP clock

down and release bus. Bus hold will be internally asserted also when

upgrade mode enable . In ICE deb ugging mode , this signal is output

and asserted when upgrade mode enable. In ICE debugging mode ,

this signal is output and asserted when upgrade mode enable. This

pin includes an pull-up resistor. HLDA# 73 I/O In normal mode, this signal is output that is used as ac k to HOLD#

signal. This signal will be internally sent to PCMCIA/AT A interf ace also

when upgrade mode enable . In ICE debugging mode, this signal is

input and ack to HOLD# when upgrade mode enable. This pin in

cludes an pull-up resistor. XF#/CPURST# 74 O External flag, this pin can be directly written by one DSP instruction.

Default inactive (5 Volt output). In ICE deb ugging mode, this signal is

used to reset CPU.

Flash Memory Interface :

Symbol No. Type Description F A19/CLE 12 O In random mode, this signal is used as flash memory chip high

address line 19. In sequential mode, this signal is used as flash memory

chip command latch enable. F A18/ALE/ 20 I/O In r andom mode , this signal is used as flash memory chip high

address line 18. In sequential mode, this signal is used as flash memory

chip address latch enable. This signal is used to select whether the

MX9691 initializes in normal mode or in ICE debugging mode at power-

on reset. If this pin go high, then the MX9691 will s witch to normal

mode at power-on reset,and if this pin remains low, then the MX9691

will initializes in ICE debugging mode. This pin includes an internal

pull-up resistor.

ICEMODE

ICE debugging mode select :

ICEMODE=1 —> Normal mode

ICEMODE=0 —> ICE debugging mode

MX9691

INDEX

Symbol No. Type Description F A17/ER OM 21 I/O This signal is used as flash memory chip high address line 17. This

signal is used to select whether the firmware store in flash memory

array or in separate e xternal ROM at power-on reset. If this pin go high,

then the firmware will be executed in flash memory array, and if this pin

remains low , then the firmware will be e xecuted in separate external

ROM.

Store firmware in external ROM or Flash memory array:

EROM = 0 —> Store in External ROM

EROM = 1 —> Store in flash memory array

This pin includes an internal pull-up resistor. F A[16:15]/ 1-2 I/O This signal is used as flash memory chip high address line 16-15. These A T ADET[1:0] signals are used to select configuration in A TA extension mode at power-

on reset. A TADET1 is connected to DSP's IPT1. AT ADET0 is connected

to DSP's IPT0. VDD is connected to IPT2.

Master/Slave selection in ATA mode :

AT ADET1 ATADET0 mode selected

1 1 one drive

0 0 master of two drives

1 0 slave of two drives

This power-on configuration can be accessed from PCMCIA/ATA port

601Ch bit3-2. These pins include internal pull-up resistors. RDFLASH1# 54 O Flash memory ouptut enable 1 for bank1: This signal will be asserted

by flash memory read operation when flash memory read address latch,

port 601Dh bit 8 = 1(i.e. FA23=1).

Note: Flash memory access window is mapped to 32KW data and

code space 8000h~ffffh. RDFLASH0# 42 O Flash memory ouptut enable 0 for bank0: This signal will be asserted

by flash memory read operation when flash memory read address latch,

port 601Dh bit 8 = 0(i.e. FA23=0). WRFLASH1# 19 O Flash memory write enable 1 for bank1: This signal will be asserted by

flash memory write operation when flash memory write address latch,

port 601Fh bit 8 = 1(i.e. FA23=1). WRFLASH0# 18 O Flash memory write enable 0 for bank0: This signal will be asserted by

flash memory write operation when flash memory write address latch,

port 601Fh bit 8 = 0(i.e. FA23=0).

MX9691

INDEX

Symbol No. Type Description FCE[7:0]# 43-44,46-47, O Flash memory chip enable 7-0 :

49-52 In random mode, These signals are decoded from port 601Dh bit 7-5

when flash memory read or port 601Fh bit 7-5 when flash memory

write.

Decoding combination :

bit7 bit6 bit5 FCE[7:0]#

0 0 0 11111110

0 0 1 11111011

0 1 0 11101111

0 1 1 10111111

1 0 0 11111101

1 0 1 11110111

1 1 0 11011111

1 1 1 01111111 In sequential mode, These are decoded from port 601Dh bit 7-5 only when port 601Eh bit 2 is set.

PWD0# 32 O Deep power down output 0 f or bank0: This signal will put the flash

memory chips of bank0 in deep power-down mode. PWD0# is active low;PWD0# high enables normal operation. PWD0# also locks out erase or program operation when active lo w providing data protection during power transitions. Power down pin PWD0# will be activ e if FA23=1.

PWD1# 64 O Deep power down output 1 f or bank1: This signal will put the flash

memory chips of bank1 in deep power-down mode. PWD1# is active low;PWD1# high enables normal operation. PWD1# also locks out erase or program operation when active lo w providing data protection during power transitions. Power down pin PWD1# will be activ e if FA23=0.

FRY/FBY# 13 I Flash memory Ready/busy input:

This signal indicate the state of erase or program operation in flash memory chips.This pin includes an internal pull-up resistor.

MX9691

INDEX

Control ROM interface :

Symbol No. Type Description ROMCS#/ 75 O ROM chip select/Flash memory data buffer enable : In normal mode, FWIN# this signal is used as ROM chip enable if firmware that stored in

external ROM. In ICE debugging mode, this signal is used as flash memory data buffer (74640) enable if firmware that stored in flash memory array.

ROMWR#/ 76 O ROM write enable/Flash memory data buffer direction control: In FDIR normal mode, this signal is used as ROM write enable if firmware that

stored in external ROM. In ICE debugging mode , this signal is used as flash memory data buffer (74640) direction control if firmware that stored in flash memory array.

Miscellaneous :

Symbol No. T ype Description X1 79 I Crystal input. X2 78 O Crystal ouput. X32I 71 I 32K Crystal input. X32O 70 I 32K Crystal output. TEST 81 I This signal is used to select the main system clock, either from

external clock source if this signal is high or from internal PLL circuit if this signal is low . This pin includes an internal pull-up resistor.

PWR_RST# 82 I Power on reset, CMOS Schmite-triggered: The MX9691 include

debouncing circuit to stabilize internal DSP reset signal.

LED# 6 O LED output: This signal is connected to e xternal LED in debugging

system to indicate system status. The LED will be turn-on during reset. The contorl firmware will turn off the LED after H/W initialization and pass diagnostics. If system fail, the control firmware will flash the LED to indicate some error occur. This signal will be high if port 601Ch bit0 set to 1 or OPTR bit2 set to 1.

VCC 17,45,53,72, 5 volt P o wer pin

80,105,112

GND 7,25,38,48, Ground pin

59,69,77,91, 108,120

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