MXIC MX93000KC, MX93000SC Datasheet

P/N: PM0306

FEATURES

• Single +5V power supply

• Sigma-Delta A/D D/A with digital filters

• Support u/A Law and 16-bit linear format

• On-chip automatic level control

• On-chip differential line driver

• On-chip digital volume control

• Programmable transmit/receive gain control

• Support switch paths for DAM (Digital Answering Machine) applications

• Easy interface to general purpose DSPs

• Easy read/write of control register by microprocessors

• Programmable power-down

• Support power-low/battery-low detection

• 28-pin DIP/SOP package

REV. 3.0, JUL 15, 1996

MX93000

PRODUCT OVERVIEW

The MX93000 Special Codec integrates key functions of the analog-front-end of Digital Answering Machine (DAM) into a single integrated circuit. The MX93000 is intended to provide a complete, low cost, and single chip solution for telephone applications requiring a single +5V power supply.

The MX93000 Special Codec is especially powerful when applied to some DAM models which are intended to meet different countries' specifications in the same system hardware. User can achieve this goal by simply setting control firmware. This benifit will help DAM system makers to save developing time and R/D resources.

The A/D D/A converters are implemented with 2ndorder sigma-Delta modulators. The on-chip digital filters, which are carried out with 16-bit and 2's complement format, are used to get the required frequency response of a PCM Codec. The Codec can support 8-bit u/A law and linear format. For the latter, it is 16-bit format with 14-bit resolution .

Before the A/D digitizing the voice-band analog signal into digital format, the analog signal can be processed by a built-in Automatic Level Control (ALC) and programmable Gain Amplifier (PGA). The ALC circuit controls the input level of A/D converter to about 1.5 Volt, so as to get a better signal to noise ratio during a low-level input. The PGA circuit is used to control the gain of different sources : microphone, aux or line input. After the digital data is converted into analog signal by the D/A converter, a fully differential line driver is supported to drive the telephone line directly without the need of external amplifier. On the other hand, the analog signal can be monitored by passing the analog signal to the on-chip volume control circuit, which can drive an external driver like LM386.

In addition, the MX93000 supports switches and control registers so that users can program the Special Codec to be under line operations and all other specific operations of DAM. To enhance an easy read/write of control registers by microprocessors, the control data is clocked by the 8 kHz sampling clock and synchronized by SDEN\, where SDEN\ is coming from the output port of microprocessor by detecting one of the rising edge of 8 kHz clock.

PIN CONFIGURATION

28PIN SOP/DIP

28 27 26 25 24 23 22 21 20 19 18 17 16 15

2 3 4 5 6 7 8 9 10 11 12 13 14

SDATA

SDEN\

DX DR

MCLK

VDD

GND

PRST

BAT\

VBAT

PDN\

VPOW

LIN

SPK VR VREF FILT ALCC ALCRC PGAC AUX MIC AG AGND AVDD LOUT2 LOUT1

MX93000

SPECIAL CODEC BLOCK DIAGRAM

MX93000

PCM CODEC :

This block includes A/D & D/A converters and all of the digital filters. A/D & D/A converters:

which are implemented with 2nd-order sigma-delta modulation. Output formats are A-Law/u-Law/16-bit linear, where u/A laws are of CCITT specifications and the 16-bit linear data can get 14-bit resolution and higher linearity than that of u/A law.

Digital filters : For the purpose of A/D out-of-band noise filtering and D/A image attenuation, digital filters are implemented on the same chip. The digital input applied to D/A converter can not be a dc signal other than idle (bits all zero), as limit cycles in the digital modulator at a level of -70 dBm will present at the analog output.

POWER MANAGEMENT :

The MX93000 supports the automatic power-down control and power supply detection. This function will work well even under 3V power supply.

Regarding the power_down procedure please refer to register 4 description for details. POWER_LOW/BATTERY_LOW detectors : active low

2 comparators and references are used to check whether POWER_LOW/BATTERY_LOW or not. The relationship between POWER_ON_RESET and POWER_LOW/BATTERY_LOW is as the following table:

(I) POWER_LOW (PDN\) 0 0 1 1 (I) BATTERY_LOW (BAT\) 0 1 0 1

(0)POWER_ON_RESET (PRST) 0 1 1 1

LINE DRIVER :

Not only support the programmable gain from 0 to 22.5 dB with 16 steps and 1.5 dB/step, but also fully differentially drive -5 dBm power over 300 ohms. If switches SWE , SWJ , and SWK are opened, then the line driver will be muted to -70dB automatically. In addition, when SWJ or SWK are turned on, there are loss at the line driver output due to single-ended to fully-differential transform.

LINE_IN BUFFER :

Buffer stage with selection of echo cancellation path or not. For the echo cancellation path, 3-6 dB cancellation can get it.

PROGRAMABLE GAIN CONTROL (PGA) :

It supports 0 to 22.5 dB gain with 16 steps and 1.5dB/step. The gain value is controlled separately by 3 registers, where different input signal paths will have a different gain value, and when the input path is changed, the respective register value will keep no change.

FUNCTIONAL DESCRIPTION

MX93000

AUTOMATIC LEVEL CONTROL (ALC) :

The ALC can support 36 dB gain with the attack time and release time controlled by C6 and R3 * C6, respectively.

SPK ATTENUATOR :

Speaker output signal can be attenuated either by internal register or external resister. For the former, the attenuation is from 0 to -45 dB with 16 steps and -3.0dB/step. For the later, 10K ohms variable resistor is suggested. If switches SWF and SWH are open, then attenuator will be muted to -70dB automatically.

SERIAL_CONTROL_INTERFACE :

To read/write the internal registers. SDEN\ (serial data enable) is used to start receiving control signal. 8kHz frame sync.is used to transmit/receive the serial data (SDATA).

CODEC_SERIAL_PORT :

4-pin signal will complete the data trasmitting/receiving. MCLK is not only the data rate but also the chip master clock. Currently, it is fixed at 1.536 MHz and the frame synchronization clock, Fs, is 8 kHz. For simplicity, the A/D and D/A are synchronous so that MCLK and Fs are enough. Data transfer of DX/DR are MSB first in both 8-bit and 16-bit formats.

VOLTAGE REFERENCE :

Two 2.25V voltage references are on-chip generated . VREF is for external and AG is for internal uses. Both two pins need the decoupling capacitors AGND at all times. VREF can be used to bias the microphone, the level shift circuits, or others.

SWITCHES :

There are 2 registers which are used to control all of the switches so that user can direct many different signal paths, of which 3 of them are : a) Path of normal operation MIC input --> SWA --> PGA/ALC --> SWC --> SWD --> PCM Codec Ain LOUT1/LOUT2 <-- LINE DRIVER <-- SWE <-- PCM Codec Aout

b) Path of room monitor MIC input --> SWA --> PGA/ALC --> SWC --> SWJ --> Line Driver LINE IN --> Line Buffer --> SWI --> PCM Codec Ain

c) Path of line play LINE IN --> SWA --> PGA/ALC --> SWC --> SWD --> PCM Codec Ain LOUT1/LOUT2 <-- Line Driver <-- SWE <-- PCM Codec Aout SPK <-- Attenuator <-- SWF <-- PCM Codec Aout

MX93000

PARAMETER MIN TYP MAX UNITS

Input Voltage with max S/(N+THD)

MIC/AUX/LINE/FILT 3.4 Vpp Input Resistance* 15 Kohm Input Capacitance* 15 pF

ANALOG INPUT

PARAMETER REG.5 D1=0 REG.5 D1=1 UNITS

MIN TYP MAX MIN TYP MAX

Dynamic Range* 36 30 dB THD*

< 75 mVpp 40 dB

< 1 Vpp 30 dB

< 100 mVpp 40 dB

<1 Vpp 25 dB

PARAMETER MIN TYP MAX UNITS

Gain Range 0 22.5 dB Step Size 1.3 1.5 1.7 dB

PROGRAMMABLE GAIN AMPLIFIER

SPECIFICATIONS

PARAMETER MIN TYP MAX UNITS

Line Driver:

Gain Range 0.0 22.5 dB

Step Size 1.2 1.5 1.8 dB

Full Swing Output (@600 ohm load)

-- Fully differential(LOUT1-LOUT2) 6.0 Vpp

-- Single Ended (LOUT1) 3.0 Vpp

External Load

-- Resistance* 300 ohm

-- Capacitance* 200 pF

ANALOG OUTPUT

AUTOMATIC LEVEL CONTROL

MX93000

SPK Attenuator :

Gain Range -45 0.0 dB

Step Size -3.5 -3.0 -2.4 dB

Full Swing Output 3.0 Vpp

External Load

-- Resistance* 10 Kohm

-- Capacitance* 100 pF

Mute Attenuation* -70 dB FILT (I/O)

Input Resistance* 10 Kohm

Output Resistance* 10 Kohm

External Load

-- Capacitance * 1000 pF

AUX (I/O)

Input Capacitance* 15 pF

Input Resistance* 20 Kohm

Output Resistance* 1 Kohm

External Load

-- Capacitance* 100 pF

PARAMETER MIN TYP MAX UNITS

VREF Output 2.0 2.25 2.5 V VREF Output Current* 800 uA

VOLTAGE REFERENCE

PARAMETER MIN TYP MAX UNITS

Comparator Transfer point 1.10 1.25 1.40 V Hysteresis* 0.15 V

COMPARATOR DETECTOR

MX93000

PARAMETER MIN TYP MAX UNITS

Dynamic Range (-40 dB FS) 72 dB THD+N (-6 dB FS) -50 dB THD+N (u Law) -36 dB Interchannel Isolation*

Line/AUX/MIC 70 dB Gain Variation (Note 3) 5 % Frequency Response

50-60 -25 dB 300-3k -1.0 +1.0 dB

3.2k-3.4k -0.9 +0.25 dB 4K -15 dB > 4.6 K -32 dB

A/D PATH CHARACTERISTICS (Note 1)

PARAMETER MIN TYP MAX UNITS

Dynamic Range (-40 dB FS) 72 dB THD+N (-6 dB FS) -50 dB Gain Variation (Note 3) 5 % Total Out-of-Band Energy

.6 Fs to 20 KHz -50 dB

Frequency Response

< 300 -0.25 +0.25 dB 300-3k -0.25 +0.25 dB

3.2k-3.4k -0.9 +0.25 dB 4K -15 dB > 4.6k -32 dB

D/A PATH CHARACTERISTICS (Note 2)

MX93000

PARAMETER MIN TYP MAX UNITS

Idle-channel Noise (Note 4)

-- A/D Path -70 dB

-- D/A Path -70 dB

VDD Power Supply Rejection (Note 5)

-- A/D Channel 40 dB

-- D/A Channel 40 dB

AVDD Power Supply Rejection (Note 5)

-- A/D Channel -50 dB

-- D/A Channel -50 dB

Crosstalk*

-- A/D to D/A (Note 6) -65 dB

-- D/A to A/D (Note 7) -65 dB

NOISE

PARAMETER MIN TYP MAX UNITS

High Level Input Voltage (VIH) 2.0 VDD Volt Low Level Input Voltage (VIL) 0 0.8 Volt High Level Output Voltage (VOH) 2.4 VDD Volt Low Level Output Voltage (VOL) 0.4 Volt Output Capacitance* 15 pF Input Capacitance* 15 pF

DIGITAL STATIC SPECIFICATIONS

PARAMETER MIN TYP MAX UNITS

Power Supply - Digital & Analog 4.5 5.5 Volt Power Supply Current -- Operating

-- Analog (Note 8) 24 mA

-- Digital 6 mA

Power Supply Current -- Power Down 0.6 mA

POWER SUPPLY

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