MXIC MX29LV008BTC-70, MX29LV008BTC-90, MX29LV008BTI-70, MX29LV008BTI-90, MX29LV008TTC-70 Datasheet

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FEA TURES

PRELIMINARY

MX29LV008T/B

8M-BIT [1M x 8] CMOS SINGLE VOLTAGE

3V ONLY FLASH MEMORY

• Extended single - supply voltage range 2.7V to 3.6V

• 1,048,576 x 8

• Single power supply operation

- 3.0V only operation for read, erase and program operation

• Fast access time: 70/90ns

• Low power consumption

- 20mA maximum active current

- 0.2uA typical standby current

• Command register architecture

- Byte Programming (7us typical)

- Sector Erase (Sector structure 16K-Bytex1, 8K-Bytex2, 32K-Bytex1, and 64K-Byte x15)

• Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with Erase Suspend capability.

- Automatically program and verify data at specified address

• Erase suspend/Erase Resume

- Suspends sector erase operation to read data from, or program data to, any sector that is not being erased, then resumes the erase.

• Status Reply

- Data polling & Toggle bit for detection of program and erase operation completion.

• Ready/Busy pin (RY/BY)

- Provides a hardware method of detecting program or erase operation completion.

• Sector protection

- Hardware method to disable any combination of sectors from program or erase operations

- Tempoary sector unprotect allows code changes in previously locked sectors.

• 100,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Low VCC write inhibit is equal to or less than 2.3V

• Package type:

- 40-pin TSOP

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power supply Flash

GENERAL DESCRIPTION

The MX29LV008T/B is a 8-mega bit Flash memory organized as 1M bytes of 8 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write nonvolatile random access memory. The MX29LV008T/B is packaged in 40-pin TSOP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.

The standard MX29L V008T/B off ers access time as fast as 70ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29L V008T/B has separate chip enab le (CE) and output enable (OE) controls.

MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV008T/B uses a command register to manage this functionality . The command register allo ws for 100% TTL level control inputs and fixed power supply levels

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during erase and programming, while maintaining maximum EPROM compatibility.

MXIC Flash technology reliably stores memory contents even after 100,000 erase and prog ram cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling. The MX29LV008T/B uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.

The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.

PIN CONFIGURATIONS

40 TSOP (Standard Type) (10mm x 20mm)

1 2 3 4 5 6 7

9 10 11 12 13 14

A16 A15 A14 A13 A12 A11

RESET

RY/BY

A18

MX29LV008T/B

A17

GND

A19

A10

VCC

GND

PIN DESCRIPTION

SYMBOL PIN NAME

A0~A19 Address Input Q0~Q7 Data Input/Output CE Chip Enable Input WE Write Enable Input RESET Hardware Reset Pin OE Output Enable Input RY/BY Ready/Busy Output VCC Power Supply Pin (2.7V~3.6V) GND Ground Pin

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BLOCK STRUCTURE

Table 1: MX29LV008T SECTOR ARCHITECTURE

Sector Sector Size Address range Sector Address

A19 A18 A17 A16 A15 A14 A13

SA0 64Kbytes 00000h-0FFFFh 0000XXX SA1 64Kbytes 10000h-1FFFFh 0001XXX SA2 64Kbytes 20000h-2FFFFh 0010XXX SA3 64Kbytes 30000h-3FFFFh 0011XXX SA4 64Kbytes 40000h-4FFFFh 0100XXX SA5 64Kbytes 50000h-5FFFFh 0101XXX SA6 64Kbytes 60000h-6FFFFh 0110XXX SA7 64Kbytes 70000h-7FFFFh 0111XXX SA8 64Kbytes 80000h-8FFFFh 1000XXX SA9 64Kbytes 90000h-9FFFFh 1 0 0 1 X X X SA10 64Kbytes A0000h-AFFFFh 1 0 1 0 X X X SA11 64Kbytes B0000h-BFFFFh 1 0 1 1 X X X SA12 64Kbytes C0000h-CFFFFh 1 1 0 0 X X X SA13 64Kbytes D0000h-DFFFFh 1 1 0 1 X X X SA14 64Kbytes E0000h-EFFFFh 1 1 1 0 X X X SA15 32Kbytes F0000h-F7FFFh 1 1110XX SA16 8Kbytes F8000h-F9FFFh 111110 0 SA17 8Kbytes FA000h-FBFFFh 111110 1 SA18 16kbytes FC000h-FFFFFh 111111 X

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Table 2: MX29LV008B SECTOR ARCHITECTURE

Sector Sector Size Address range Sector Address

A19 A18 A17 A16 A15 A14 A13

SA0 16Kbytes 00000h-03FFFh 000000 X SA1 8Kbytes 04000h-05FFFh 000001 0 SA2 8Kbytes 06000h-07FFFh 000001 1 SA3 32Kbytes 08000h-0FFFFh 00001XX SA4 64Kbytes 10000h-1FFFFh 0001XXX SA5 64Kbytes 20000h-2FFFFh 0010XXX SA6 64Kbytes 30000h-3FFFFh 0011XXX SA7 64Kbytes 40000h-4FFFFh 0100XXX SA8 64Kbytes 50000h-5FFFFh 0101XXX SA9 64Kbytes 60000h-6FFFFh 0110XXX SA10 64Kbytes 70000h-7FFFFh 0111XXX SA11 64Kbytes 80000h-8FFFFh 1 0 0 0 X X X SA12 64Kbytes 90000h-9FFFFh 1 0 0 1 X X X SA13 64Kbytes A0000h-AFFFFh 1010XXX SA14 64Kbytes B0000h-BFFFFh 1011XXX SA15 64Kbytes C0000h-CFFFFh 1 1 0 0 X X X SA16 64Kbytes D0000h-DFFFFh 1101XXX SA17 64Kbytes E0000h-EFFFFh 1110XXX SA18 64kbytes F0000h-FFFFFh 1111XXX

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BLOCK DIAGRAM

MX29LV008T/B

CE OE

RESET

A0-A19

CONTROL

INPUT LOGIC

ADDRESS

LATCH

AND

BUFFER

PROGRAM/ERASE

HIGH VOLTAGE

X-DECODER

MX29L V008T/B

FLASH ARRA Y

Y-DECODER

Y-PASS GATE

SENSE

AMPLIFIER

PGM

DATA

ARRAY

SOURCE

WRITE

STATE

MACHINE

(WSM)

STATE

COMMAND

DATA DECODER

COMMAND

DATA LATCH

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Q0-Q7

PROGRAM

DATA LATCH

I/O BUFFER

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MX29LV008T/B

AUTOMATIC PROGRAMMING

The MX29L V008T/B is byte programmab le using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29LV008T/B is less than 10 seconds.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the program verification, and counts the number of sequences. The device provides an unlock bypass mode with faster programming. Only two write cycles are needed to program a word or byte, instead of f our . A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation. Refer to write operation status, table 7, for more information on these status bits.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the status of the erasing operation.

Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry . During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE or CE, whichev er happens first.

MXIC's Flash technology combines years of EPROM experience to produce the highest lev els of quality, reliability , and cost effectiv eness. The MX29LV008T/B electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are prog rammed by using the EPROM programming mechanism of hot electron injection.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. T ypical erasure at room temper ature is accomplished in less than 25 second. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and v erification of electrical erase are controlled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29L V008T/B is sector(s) erasab le using MXIC's Auto Sector Erase algorithm. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device. An erase operation can erase one sector, multiple sectors, or the entire device.

During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command register to respond to its full command set.

AUTOMATIC SELECT

The auto select mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on Q7~Q0. This mode is mainly adapted for programming equipment on the device to be programmed with its programming algorithm. When programming by high voltage method, automatic select mode requires VID (11.5V to 12.5V) on address pin A9 and other address pin A6, A1 and A0 as referring to Table 3. In addition, to access the automatic select codes in-system, the host can issue the automatic se-

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MX29LV008T/B

lect command through the command register without requiring VID , as shown in tab le4.

T o v erify whether or not sector being protected, the sector address must appear on the appropriate highest order address bit (see Table 1 and Table 2). The rest of address bits, as shown in table3, are don't care. Once all necessary bits have been set as required, the programming equipment may read the corresponding identifier code on Q7~Q0.

T ABLE 3. MX29LV008T/B AUTO SELECT MODE OPERA TION

A19 A12 A9 A8 A6 A5 A1 A0

Description CE OE WE | | | | Q7~Q0

A13 A10 A7 A2

Read Silicon ID L L H X X VID X L X L L C2H Manfacturer Code Read Silicon ID L L H X X VID X L X L H 3EH (Top Boot Block) Device ID L L H X X VID X L X L H 37H (Bottom Boot Block)

01H

Sector Protection L L H SA X VID X L X H L (protected) Verification 00H

(unprotected)

NOTE:SA=Sector Address, X=Don't Care, L=Logic Lo w , H=Logic High

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T ABLE 4. MX29LV008T/B COMMAND DEFINITIONS

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Reset 1 XXXH F0H Read 1 RA R D Read Silicon Top Boot 4 555H AAH 2AAH 55H 555H 90H ADI DDI ID Bottom Boot 4 555H AAH 2AAH 55H 555H 90H ADI DDI Sector Protect 4 555H AAH 2AAH 55H 555H 90H (SA) 00H Verify x02H 0 1H Porgram 4 555H AAH 2AAH 55H 555H A0H PA PD Chip Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 5 5H 555H 10H Sector Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 5 5H SA 30 H Sector Erase Suspend 1 XXXH B 0H Sector Erase Resume 1 XXXH 30 H

Note:

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A18=do not care. (Refer to table 3) DDI = Data of Device identifier : C2H for manufacture code, 3E/37 (Top/Bottom Boot) for device code. X = X can be VIL or VIH RA=Address of memory location to be read. RD=Data to be read at location RA.

2.PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address of the sector to be erased.

3.Address A19-A11 are don't cares for unlock and command cycles.

4. For Sector Protect Verify operation:If read out data is 01H, it means the sector has been protected. If read out data is 00H, it means the sector is still not being protected.

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COMMAND DEFINITIONS

MX29LV008T/B

Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them

sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the

Sector Erase operation is in progress. in the improper sequence will reset the device to the read mode. Table 4 defines the valid register command

T ABLE 5. MX29LV008T/B BUS OPERATION

ADDRESS

DESCRIPTION CE OE WE RESET A19 A12 A9 A8 A6 A5 A1 A0 Q0~Q7

A13 A10 A7 A2

Read L L H H AIN Dout Write L H L H AIN DIN(3) Reset X X X L X High Z Temproary Sector Unprotect X X X VID AIN DI N Output Disable L H H H X High Z Standby Vc c±0.3V X X Vcc±0.3V X High Z Sector Protect L H L VID SA X X X L X H L DIN Sector Unprotect L H L VID X X X X H X H L DIN Sector Protection Verify L L H H SA X VID X L X H L CODE(5)

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 4 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H means unprotected.

Code=01H means protected.

6. A19~A13=Sector address for sector protect.

7.The sector protect and chip unprotect functions may also be implemented via programming equipment.

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REQUIREMENTS FOR READING ARRAY DATA

To read array data from the outputs, the system must drive the CE and OE pins to VIL. CE is the pow er control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at VIH.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory contect occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. The device remains enab led for read access until the command register contents are altered.

WRITE COMMANDS/COMMAND SEQUENCES

T o program data to the de vice or erase sectors of memory , the sysytem must drive WE and CE to VIL, and OE to VIH.

The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a byte, instead of four. The "byte Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector , multiple sectors , or the entire device. Table indicates the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The "Writing specific address and data commands or sequences into the command register initiates device operations. Table 1 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data."section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal reqister (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode.

Refer to the Autoselect Mode and Autoselect Command

Sequence section for more information.

ICC2 in the DC Characteristics table represents the

active current specification for the write mode. The "A C

Characteristics" section contains timing specification

table and timing diagrams for write operations.

STANDBY MODE

When using both pins of CE and RESET, the device

enter CMOS Standby with both pins held at Vcc ± 0.3V.

IF CE and RESET are held at VIH, but not within the

range of VCC ± 0.3V , the device will still be in the standb y

mode, but the standby current will be larger . During Auto

Algorithm operation, Vcc activ e current (Icc2) is required

even CE = "H" until the oper ation is complated. The de-

vice can be read with standard access time (tCE) from

either of these standby modes, before it is ready to read

data.

OUTPUT DISABLE

With the OE input at a logic high level (VIH), output from

the devices are disabled. This will cause the output pins

to be in a high impedance state.

RESET OPERATION

The RESET pin provides a hardware method of resetting

the device to reading arra y data. When the RESET pin is

driven low for at least a period of tRP, the device

immediately terminates any operation in progress,

tristates all output pins, and ignores all read/write

commands for the duration of the RESET pluse. The

device also resets the internal state machine to reading

array data. The operation that was interrupted should be

reinitated once the device is ready to accept another

command sequence, to ensure data integrity

Current is reduced for the duration of the RESET pulse.

When RESET is held at VSS±0.3V, the device draws

CMOS standby current (ICC4). If RESET is held at VIL

but not within VSS±0.3V, the standby current will be

greater.

The RESET pin may be tied to system reset circuitry . A

system reset would that also reset the Flash memory,

enabling the system to read the boot-up firm-ware from

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MX29LV008T/B

the Flash memory . If RESET is asserted during a program or erase

operation, the R Y/BY pin remains a "0" (b usy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The sysytem can thus monitor RY/BY to determine whether the reset operation is complete. If RESET is asserted when a program or erase operation is commpleted within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET pin returns to VIH.

Refer to the AC Characteristics tables for RESET parameters and to Figure 20 for the timing diagram.

READ/RESET COMMAND

The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered.

If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid command must then be written to place the device in the desired state.

SET-UP AUTOMATIC CHIP/SECTOR ERASE

COMMANDS

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed b y writing the

"set-up" command 80H. Two more "unlock" write cy-

cles are then followed by the chip erase command 10H

or sector erase command 30H.

The Automatic Chip Erase does not require the device

to be entirely pre-programmed prior to executing the Au-

tomatic Chip Erase. Upon executing the Automatic Chip

Erase, the device will automatically program and verify

the entire memory for an all-zero data pattern. When the

device is automatically verified to contain an all-zero

pattern, a self-timed chip erase and verify begin. The

erase and verify operations are completed when the data

on Q7 is "1" at which time the device returns to the

Read mode. The system is not required to pro vide any

control or timing during these operations.

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array(no

erase verification command is required).

If the Erase operation was unsuccessful, the data on

Q5 is "1"(see Table 7), indicating the erase operation

exceed internal timing limit.

SILICON-ID READ COMMAND

Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage(VID). Howev er, m ultiplexing high voltage onto address lines is not generally desired system design practice.

The MX29L V008T/B contains a Silicon-ID-Read operation to supple traditional PROM programming methodology . The oper ation is initiated by writing the read silicon ID command sequence into the command register. F ollowing the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of 3EH for MX29LV008T, 37H f or MX29L V008B .

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The automatic erase begins on the rising edge of the

last WE or CE pulse, whichever happens first in the

command sequence and terminates when the data on

Q7 is "1" and the data on Q6 stops toggling for two con-

secutive read cycles, at which time the device returns

to the Read mode.

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MX29LV008T/B

T ABLE 6. SILICON ID CODE

Pins A0 A1 Q7 Q6 Q 5 Q 4 Q3 Q2 Q1 Q 0 Code(Hex)

Manufacture code VIL VIL 1 1 0 0 0010C2H Device code VIH VIL 001111103EH for MX29L V008T Device code VIH VIL 0 0 1 1 011137H for MX29L V008B Sector Protection X VIH 0 0 0 0 000101H (Protected) Verification X VIH 0 0 0 0 000000H (Unprotected)

READING ARRAY DATA

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read arra y data after completing an Automatic Program or Automatic Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See rase Suspend/Erase Resume Commands” for more infor-mation on this mode. The system able the device for reading array data if Q5 goes high, or while in the autoselect mode. See the "Reset Command" section, next.

must issue the reset command to re-en-

RESET COMMAND

Writing the reset command to the device resets the

device to reading array data. Address bits are don't care

for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ignores

reset commands until the operation is complete.

The reset command may be written between the se-

quence cycles in a program command sequence be-fore

programming begins. This resets the device to reading

array data (also applies to programming in Erase

Suspend mode). Once prog ramming begins ,how ever, the

device ignores reset commands until the operation is

complete.

The reset command may be written between the se-

quence cycles in an SILICON ID READ command

sequence. Once in the SILICON ID READ mode, the

reset command

data (also applies to SILICON ID READ during Erase

Suspend).

must be written to return to reading array

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If Q5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing

array data (also applies during Erase Suspend).

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MX29LV008T/B

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Sector Erase Set-up command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system is not required to provide any control or timing during these operations.

When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations.

When using the Automatic sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE or CE, whichever happens later , while the command(data) is latched on the rising edge of WE or CE, whichever happens first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE or CE, whichever happens later. Each successiv e sector load cycle started by the falling edge of WE or CE, whichever happens later must begin within 50us from the rising edge of the preceding WE or CE, whichev er happens first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer .) Any command other than Sector Erase(30H) or Erase Suspend(B0H) during the time-out period resets the device to read mode.

ERASE SUSPEND

This command only has meaning while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend Com-

mand is issued during the sector erase operation, the

device requires a maximum 20us to suspend the sector

erase operation. However , when the Erase Suspend com-

mand is written during the sector erase time-out, the

device immediately terminates the time-out period and

suspends the erase operation. After this command has

been executed, the command register will initiate erase

suspend mode. The state machine will return to read

mode automatically after suspend is ready . At this time,

state machine only allows the command register to re-

spond to Erase Resume, program data to , or read data

from any sector not selected for erasure.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend pro-

gram operation is complete, the system can once again

read array data within non-suspended sectors.

ERASE RESUME

This command will cause the command register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

other conditions. Another Erase Suspend command can

be written after the chip has resumed erasing.

WORD/BYTE PROGRAM COMMAND SEQUENCE

The device programs one byte of data for each program

operation. The command sequence requires four bus

cycles, and is initiated by writing two unlock write cycles,

followed by the program set-up command. The program

address and data are written next, which in turn initiate

the Embedded Program algorithm. The system is

required to provide further controls or timings. The device

automatically generates the program pulses and verifies

the programmed cell margin. Table 1 shows the address

and data requirements for the byte program command

sequence.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and

addresses are no longer latched. The system can

determine the status of the program operation by using

Q7, Q6, or RY/BY. See "Write Operation Status" for

information on these status bits.

Any commands written to the device during the Em-

not

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MX29LV008T/B

bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operat ion. The Byte Prog ram command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity.

Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set Q5 to "1" ,” or cause the Data Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1".

WRITE OPERSTION STATUS

The device provides several bits to determine the status of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/ BY. Table 10 and the following subsections describe the functions of these bits. Q7, R Y/BY, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first.

Q7: Data Polling

The Data Polling bit, Q7, indicates to the host sys-tem whether an Automatic Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data Polling is v alid after the rising edge of the final WE pulse in the program or erase command sequence.

During the Automatic Program algorithm, the device outputs on Q7 the complement of the datum programmed to Q7. This Q7 status also applies to progr amming during Er ase Suspend. When the Automatic Program algorithm is complete, the device outputs the datum programmed to Q7. The system must provide the progr am address to read valid status information on Q7. If a program address falls within a protected sector, Data Polling on Q7 is active for approximately 1 us, then the device returns to reading array data.

During the Automatic Erase algorithm, Data Polling produces a "0" on Q7. When the Automatic Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data P olling produces a "1" on Q7. This is analogous to the complement/true datum out-put de-

scribed for the Automatic Program algorithm: the erase

function changes all the bits in a sector to "1" prior to

this, the device outputs the "complement,” or "0".” The

system must provide an address within any of the sec-

tors selected for erasure to read valid status information

on Q7.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Data P olling on

Q7 is active for approximately 100 us, then the device

returns to reading array data. If not all selected sectors

are protected, the Automatic Erase algorithm erases the

unprotected sectors, and ignores the selected sectors

that are protected.

When the system detects Q7 has changed from the

complement to true data, it can read valid data at Q7-Q0

on the following read cycles. This is because Q7 may

change asynchr onously with Q0-Q6 while Output En-

able (OE) is asserted low.

RY/BY:Ready/Busy

The RY/BY is a dedicated, open-drain output pin that

indicates whether an Automatic Erase/Program algorithm

is in progress or complete. The RY/BY status is valid

after the rising edge of the final WE or CE, whichever

happens first, in the command sequence. Since R Y/BY

is an open-drain output, sever al RY/BY pins can be tied

together in parallel with a pull-up resistor to Vcc.

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the Erase

Suspend mode.)If the output is high (Ready), the device

is ready to read array data (including during the Erase

Suspend mode), or is in the standby mode.

T able 7 sho ws the outputs for R Y/BY during write opera-

tion.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-

gram or Erase algorithm is in progress or complete, or

whether the device has entered the Erase Suspend mode.

Toggle Bit I may be read at any address, and is valid

after the rising edge of the final WE or CE, whichever

happens first, in the command sequence(prior to the pro-

gram or erase operation), and during the sector time-

out.

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During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete , Q6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.

The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase suspended. When the de vice is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. Ho wever, the system m ust also use Q2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7.

If a program address falls within a protected sector, Q6 toggles for approximately 2 us after the program command sequence is written, then returns to reading array data.

Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete.

Table 7 shows the outputs f or Toggle Bit I on Q6.

Q2:Toggle Bit II

The "T oggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively eraseing (that is, the Automatic Erase alorithm is in process), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE or CE, whichever happens first, in the command sequence.

Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus , both status bits

are required for sectors and mode information. Refer to

Table 7 to compare outputs f or Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to

determine whether a toggle bit is toggling. T ypically, the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has

completed the program or erase operation. The system

can read array data on Q7-Q0 on the following read cycle.

Howe v e r, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of Q5 is high

(see the section on Q5). If it is, the system should then

determine again whether the toggle bit is toggling, since

the toggle bit may have stopped toggling just as Q5 went

high. If the toggle bit is no longer toggling, the device

has successfuly completed the program or erase opera-

tion. If it is still toggling, the device did not complete the

operation successfully, and the system must write the

reset command to return to reading array data.

The remaining scenario is that system initially determines

that the toggle bit is toggling and Q5 has not gone high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the sta-

tus as described in the previous paragraph. Alterna-

tively, it may choose to perform other system tasks. In

this case, the system must start at the beginning of the

algorithm when it returns to determine the status of the

operation.

Exceeded Timing Limits

Q5 will indicate if the program or erase time has ex-

ceeded the specified limits(internal pulse count). Under

these conditions Q5 will produce a "1". This time-out

condition indicates that the program or erase cycle was

not successfully completed. Data Polling and Toggle Bit

are the only operating functions of the device under this

condition.

If this time-out condition occurs during sector erase op-

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eration, it specifies that a particular sector is bad and it may not be reused. Howe ver , other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute prog ram or erase command sequence. This allows the system to continue to use the other active sectors in the device.

If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad.

T able 7. WRITE OPERATION ST ATUS

Status Q7 Q6 Q5 Q3 Q2 RY/BY

Byte Program in Auto Program Algorithm Q7 Toggle 0 N/A No 0

Auto Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase Suspend Read 1 No 0 N/A Toggle 1 (Erase Suspended Sector) Toggle

In Progress

Erase Suspended Mode Erase Suspend Read Data Data Data Data Data 1

(Non-Erase Suspended Sector)

If this time-out condition occurs during the byte program-

ming operation, it specifies that the entire sector con-

taining that byte is bad and this sector maynot be re-

used, (other sectors are still functional and can be re-

used).

The time-out condition will not appear if a user tries to

program a non blank location without erasing. Please

note that this is not a device failure condition since the

device was incorrectly used.

(Note1) (Note2)

Toggle

Erase Suspend Program Q7 Toggle 0 N/A N/A 0

Byte Program in Auto Program Algorithm Q7 Toggle 1 N/A No 0

Exceeded Time Limits Auto Erase Algorithm 0 Toggle 1 1 Toggle 0

Erase Suspend Program Q7 Toggle 1 N/A N/A 0

Toggle

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5:Exceeded Timing Limits " for more information.

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