- 2.7 to 3.6 volt for read, erase, and program operations
• Configuration
- 16,777,216 x 8 / 8,388,608 x 16 switchable
• Sector structure
- 8KB(4KW) x 8 and 64KB(32KW) x 255
• Latch-up protected to 250mA fro m -1V to VCC + 1V
• Low VCC write inhibit is equal to or less than 1.5V
• Compatible with JEDEC standard
- Pin-out and software compatible to single power supply Flash
PERFORMANCE
• High Perf ormance
- Fast access time: 90R/100ns
- Page read time: 25ns
- Sector erase time: 0.5s (typ.)
- 4 word/8 b yte page read buffer
- 16 word/ 32 b yte write buffer: reduces pro gramming
time fo r multiple-wo rd/byte updates
• Low Po wer Consumptio n
- Active read current: 18mA(typ.)
- Active write current: 20mA(typ.)
- Standby current: 20uA(typ.)
• Minimum 100,000 erase/prog ram cycle
• 20-years data retention
SOFTW ARE FEA TURES
• Support Commo n Flash Interf ace (CFI)
- Flash device parameters stored on the device and
provide the host system to access.
• Program Suspend/Pro gram Resume
- Suspend prog ram operatio n to read o ther secto rs
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data/program o ther sectors
• Status Reply
- Data# polling & Toggle bits pro vide detectio n o f program and erase operation completion
HARDW ARE FEA TURES
• Ready/Busy (RY/BY#) Output
- Provides a hardware method of detecting program
and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal
state machine to read mode
• WP#/ACC input
- Write pro tect (WP#) functio n allows pro tection o f all
sectors, regardless o f secto r pro tectio n settings
- ACC (high voltage) accelerates programming time
fo r higher throughput during system
SECURITY
• Sector Pro tection/Chip Unpro tect
- Pro vides sector gro up pro tect function to pre vent program o r erase o peration in the pro tected secto r gro up
- Provides chip unprotect function to allow code
changes
- Provides tempo rary secto r gro up unprotect functio n
fo r code changes in pre viously pro tected secto r groups
• Sector P ermanent Loc k
- A unique lock bit feature allows the content to be
permanently lock ed
(Please contact Macronix sales for specific information regarding this permanent lock feature)
• Secured Silicon Secto r
- Provides a 128-word OTP area for permanent, secure identification
- Can be programmed and lo ck ed at facto ry or by customer
P A CKAGE
• 56-pin TSOP
GENERAL DESCRIPTION
The MX29LA128M T/B is a 128-mega bit Flash memo ry
organiz ed as 16M bytes o f 8 bits or 8M wo rds of 16 bits.
MXIC's Flash memories o ffer the mo st co st-effective and
reliable read/write non-v o latile random access memo ry .
The MX29LA128M T/B is pac kaged in 56-pin TSOP. It is
designed to be reprog rammed and erased in system o r in
standard EPROM pro grammers.
P/N:PM1170REV. 0.04, JUL. 11, 2005
The standard MX29LA128M T/B offers access time as
fast as 90ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29LA128M T/B has separate chip enable
(CE#) and output enab le (OE#) co ntrols.
with in-circuit electrical erasure and prog ramming. The
MX29LA128M T/B uses a co mmand register to manage
this functionality.
MXIC Flash technology reliably stores memory contents
even after 100,000 er ase and program cycles. The MXIC
cell is designed to optimize the erase and program
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and programming operations produces reliable
cycling. The MX29LA128M T/B uses a 2.7V to 3.6V
VCC supply to perform the High Reliability Erase and
auto Progr am/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.
AUTOMATIC PROGRAMMING
The MX29LA128M T/B is b yte/word/page pro grammab le
using the Auto matic Pro gramming algo rithm. The Automatic Programming algorithm makes the external system do not need to ha ve time o ut sequence no r to verify
the data prog rammed.
AUTOMATIC PROGRAMMING ALGORITHM
AUTOMATIC SECTOR ERASE
The MX29LA128M T/B is secto r(s) erasable using MXIC's
Auto Secto r Erase algo rithm. Secto r erase mo des allo w
sectors o f the arra y to be erased in o ne erase cycle. The
Auto matic Sector Er ase algorithm auto matically progr ams
the specified sector(s) prio r to electrical erase. The timing and verificatio n of electrical erase are co ntrolled internally within the device.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using standard micropro cesso r write timings. The de vice will automatically pre-prog r am and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the
status of the programming operation.
Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry . During write cycles, the co mmand register internally latches address and data needed for the programming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge o f WE# .
MXIC's Automatic Programming algorithm require the user
to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The de vice automatically times
the programming pulse width, provides the program verification, and counts the number of sequences. A status
bit similar to DATA# polling and a status bit to ggling between consecutive read cycles, provide feedback to the
user as to the status of the programming operation.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 50 ms erase pulses
according to MXIC's A utomatic Chip Er ase algorithm. The
Automatic Erase algorithm automatically programs the
entire array prio r to electrical erase. The timing and verification o f electrical erase are co ntro lled internally within
the device.
P/N:PM1170
MXIC's Flash technology combines years of EPROM
experience to pro duce the highest le vels of quality, reliability, and cost effectiveness. The MX29LA128M T/B
electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are pro grammed b y using the EPROM programming mechanism of hot electron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command register to respond to its full command set.
OperationCE# OE# W E #RE-WP#ACCAddressQ0~Q7WordByte
SET#ModeMode
ReadLLHHXXA
IN
D
OUT
D
OUT
Q8-Q14=
High Z
Q15=A-1
Write (Program/Erase)LHLH(Note 3)XA
IN
(No te 4) (Note 4 Q8-Q14=
High Z
Q15=A-1
Accelerated ProgramLHLH(Note 3)V
HH
A
IN
(No t e 4 ) (No t e 4 ) Q8-Q14=
High Z
Q15=A-1
StandbyVC C ±XXVCC±XHXHigh-ZHigh-ZHigh-Z
0.3V0.3V
Output DisableLHHHXXXHigh-ZHigh-ZHigh-Z
ResetXXXLXXXHigh-ZHigh-ZHigh-Z
Sector Group ProtectLHLV
ID
HXSector Addresses, (Note 4)XX
(Note 2)A6=L,A3=L, A2=L,
A1=H,A0=L
Chip unprotectLHLV
ID
HXSector Addresses, (Note 4)XX
(Note 2)A6=H, A3=L, A2=L,
A1=H, A0=L
Temporary SectorXXXV
ID
HXAIN(Note 4) (Note 4)High-Z
Group Unprotect
Legend:
L=Logic LOW=VIL, H=Logic High=VIH, VID=12.0±0.5V, VHH=12.0±0.5V, X=Don't Care, AIN=Address IN, DIN=Data IN,
D
=Data OUT
OUT
No tes:
1. Address are A21:A0 in word mo de; A21:A-1 in byte mo de . Secto r addresses are A21:A15 in bo th mo des.
2 . The sector gro up pro tect and chip unpro tect functio ns may also be implemented via pro gramming equipment. See
the "Sector Gro up Pro tectio n and Chip Unpro tect" section.
3. If WP#=VIL, all the secto rs remain protected. If WP#=VIH, all sectors pro tectio n depends o n whether they were last
protected o r unpro tect using the method described in "Secto r/ Secto r Bloc k Protectio n and Unpro tect".
4. DIN or D
P/N:PM1170
as required by co mmand sequence, Data# po lling or secto r pro tect algo rithm (see Figure 15).
OUT
REV. 0.04, JUL. 11, 2005
19
MX29LA128M T/B
Table 2. AUTOSELECT CODES (High Voltage Method)
A22 A14A8A5A3 Q8 to Q15
DescriptionCE# OE# WE# totoA9toA6totoA1 A0WordByteQ7 t o Q 0
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care.
P/N:PM1170
REV. 0.04, JUL. 11, 2005
20
MX29LA128M T/B
REQUIREMENTS FOR READING ARRAY
DATA
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the o utput pins . WE# should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
micropro cesso r read cycles that assert valid address on
the device address inputs produce valid data on the device data outputs . The de vice remains enabled fo r read
access until the command register contents are altered.
PAGE MODE READ
The MX29LA128M T/B o ffers "f ast page mode read" function. This mode provides faster read access speed for
random locations within a page. The page size of the
device is 4 words/8 bytes. The appropriate page is selected by the higher address bits A0~A1(Wo rd Mo de)/A1~A1(Byte Mode) This is an asynchro nous o peratio n; the
microprocessor supplies the specific word location.
The system perfo rmance could be enhanced by initiating
1 normal read and 3 fast page read (for word mode A0A1) or 7 fast page read (for byte mode A-1~A1). When
CE# is deasserted and reasserted fo r a subsequent access, the access time is tACC or tCE. Fast page mode
accesses are obtained by keeping the "read-page addresses" constant and changing the "intra-read page"
addresses.
WRITING COMMANDS/COMMAND SEQUENCES
T o pro gram data to the device o r erase secto rs of memo ry ,
the system must drive WE# and CE# to VIL, and OE# to
VIH.
An erase operation can erase one sector, multiple sectors, or the entire device. Table indicates the address
space that each sector occupies. A "sector address"
consists o f the address bits required to uniquely select a
sector . The Writing specific address and data commands
or sequences into the co mmand register initiates de vice
operations. Table 1 defines the valid register command
sequences. Writing inco rrect address and data values o r
writing them in the improper sequence resets the device
to reading array data. Section has details on erasing a
sector or the entire chip, or suspending/resuming the erase
operation.
After the system writes the Automatic Select command
sequence, the device enters the Automatic Select mode.
The system can then read Automatic Select codes from
the internal register (which is separate from the memory
array) on Q7-Q0. Standard read cycle timings apply in
this mode. Refer to the Automatic Select Mode and Automatic Select Command Sequence section for more
information.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC
Characteristics" section contains timing specification
table and timing diagrams for write operations.
WRITE BUFFER
Write Buffer Programming allows the system to write a
maximum of 16 words/32 bytes in one programming operatio n. This results in faster eff ective pro gramming time
than the standard programming algorithms. See "Write
Buffer" for more information.
ACCELERATED PROGRAM OPERATION
The device offers accelerated program operations through
the ACC function. This is one of two functions provided
by the ACC pin. This function is primarily intended to
allow faster manuf acturing throughput at the f actory .
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors, and
uses the higher voltage on the pin to reduce the time
required fo r pro gram oper ations . Remo ving VHH from the
ACC
pin must not be at VHH for operations o ther than accelerated programming, or device damage may result.
P/N:PM1170
REV. 0.04, JUL. 11, 2005
21
MX29LA128M T/B
STANDBY MODE
When using both pins o f CE# and RESET#, the de vice
enter CMOS Standby with bo th pins held at VCC ± 0.3V .
If CE# and RESET# are held at VIH, but not within the
range o f VCC ± 0.3V , the device will still be in the standby
mode, b ut the standby current will be larger. During Auto
Algorithm o peration, VCC active current (ICC2) is required
even CE# = "H" until the operation is completed. The
device can be read with standard access time (tCE) from
either of these standby modes, before it is ready to read
data.
AUTOMATIC SLEEP MODE
The automatic sleep mode minimizes Flash device energy consumptio n. The de vice auto matically enables this
mode when address remain stab le for tA CC+30ns . The
automatic sleep mo de is independent of the CE#, WE#,
and OE# control signals. Standard address access timings pro vide new data when addresses are changed. While
in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table
represents the automatic sleep mode current specification.
OUTPUT DISABLE
With the OE# input at a logic high level (VIH), output
from the de vices are disabled. This will cause the output
pins to be in a high impedance state.
RESET# OPERATION
but not within VSS±0.3V, the standby current will be
greater.
The RESET# pin may be tied to system reset circuitry.
A system reset would that also reset the Flash memo ry ,
enabling the system to read the boot-up firmware from
the Flash memory.
If RESET# is asserted during a program or erase
operatio n, the R Y/BY# pin remains a "0" (busy) until the
internal reset operation is complete, which requires a time
of tREADY (during Embedded Algo rithms). The system
can thus monito r RY/BY# to determine whether the reset
operation is complete. If RESET# is asserted when a
program or erase operation is completed within a time of
tREAD Y (not during Embedded Algo rithms). The system
can read data tRH after the RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 3 for the timing diagram.
SECTOR GROUP PROTECT OPERATION
The MX29LA128M T/B f eatures hardw are secto r g roup
protection. This feature will disable both program and
erase operations for these sector group protected. In
this device, a sector group consists of four adjacent sectors which are protected or unprotected at the same time.
T o activ ate this mode, the pro gramming equipment must
fo rce VID o n address pin A9 and contro l pin OE#, (suggest VID = 12V) A6 = VIL and CE# = VIL. (see Tab le 2)
Programming of the protection circuitry begins on the
falling edge of the WE# pulse and is terminated on the
rising edge. Please refer to sector group protect algorithm and waveform.
The RESET# pin provides a hardware method of resetting
the device to reading arra y data. When the RESET# pin
is driven low for at least a period of tRP, the device
immediately terminates any operation in progress,
tristates all output pins, and ignores all read/write
commands for the duration of the RESET# pulse. The
device also resets the internal state machine to reading
array data. The o peratio n that was interrupted should be
reinitiated once the device is ready to accept another
command sequence, to ensure data integrity
Current is reduced for the duration of the RESET# pulse.
When RESET# is held at VSS±0.3V, the device draws
CMOS standby current (ICC4). If RESET# is held at VIL
P/N:PM1170
MX29LA128M T/B also pro vides ano ther metho d. Which
requires VID on the RESET# only. This method can be
implemented either in-system or via programming equipment. This method uses standard microprocessor bus
cycle timing.
T o v erify programming o f the pro tection circuitry , the programming equipment must fo rce VID o n address pin A9
( with CE# and OE# at VIL and WE# at VIH). When
A1=1, it will produce a logical "1" code at device output
Q0 fo r a pro tected sector . Otherwise the device will produce 00H for the unprotected sector. In this mode, the
addresses, except for A1, are don't care. Address locations with A1 = VIL are reserved to read manufacturer
and device codes. (Read Silicon ID)
REV. 0.04, JUL. 11, 2005
22
MX29LA128M T/B
It is also possib le to determine if the gro up is protected
in the system by writing a Read Silicon ID command.
Perf o rming a read operatio n with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.
CHIP UNPROTECT OPERATION
The MX29LA128M T/B also f eatures the chip unpro tect
mode, so that all sectors are unprotected after chip
unprotect is completed to incorporate any changes in
the code. It is recommended to protect all sectors before
activating chip unprotect mode.
T o activ ate this mode , the programming equipment m ust
force VID on control pin OE# and address pin A9. The
CE# pins must be set at VIL. Pins A6 must be set to
VIH. (see Table 2) Refer to chip unprotect algo rithm and
wavef o rm for the chip unpro tect algo rithm. The unprotect
mechanism begins on the f alling edge o f the WE# pulse
and is terminated on the rising edge.
MX29LA128M T/B also pro vides ano ther metho d. Which
requires VID on the RESET# only. This method can be
implemented either in-system or via programming equipment. This method uses standard microprocessor bus
cycle timing.
It is also possible to determine if the chip is unprotect in
the system by writing the Read Silicon ID command.
Perf orming a read o peratio n with A1=VIH, it will pro duce
00H at data outputs (Q0-Q7) f o r an unpro tect sector . It is
noted that all sectors are unprotected after the chip
unprotect algorithm is completed.
WRITE PROTECT (WP#)
last protected o r unpro tect using the method described in
"Sector/Secto r Gro up Pro tection and Chip Unpro tect".
Note that the WP# pin must no t be left flo ating o r unco nnected; inconsistent behavior of the device may result.
TEMPORARY SECTOR GROUP UNPROTECT
OPERATION
This feature allows temporary unprotect of previously
protected secto r to change data in-system. The Temporary Sector Unprotect mode is activated by setting the
RESET# pin to VID(11.5V -12.5V). During this mo de, fo rmerly protected sectors can be programmed or erased
as unprotect sector. Once VID is remove from the RESET# pin, all the previously protected sectors are protected again.
SILICON ID READ OPERATION
Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the
device resides in the target system. PROM programmers typically access signature codes by raising A9 to
a high vo ltage. Howe ver , m ultiplexing high v o ltage onto
address lines is not generally desired system design practice.
MX29LA128M T/B pro vides hardware metho d to access
the silicon ID read o peratio n. Which metho d requires VID
on A9 pin, VIL on CE#, OE#, A6, and A1 pins. Which
apply VIL o n A0 pin, the de vice will output MXIC's manufacture co de of which apply VIH o n A0 pin, the device will
output MX29LA128M T/B de vice cod e.
The write protect function provides a hardware method
to protect all sectors witho ut using VID.
If the system asserts VIL on the WP# pin, the device
disables pro gram and erase functio ns in all sectors independently of whether those sectors were protected or
unprotect using the method described in Sector/Sector
Group Pro tectio n and Chip Unpro tect".
If the system asserts VIH on the WP# pin, the device
reverts to whether the sectors were last set to be protected or unprotect. That is, sector protection or
unprotectio n fo r the secto rs depends on whether they w ere
P/N:PM1170
VERIFY SECTOR GROUP PROTECT STATUS
OPERATION
MX29LA128M T/B pro vides hardware metho d f or secto r
group protect status verify. Which method requires VID
on A9 pin, VIH on WE# and A1 pins, VIL on CE#, OE#,
A6, and A0 pins, and secto r address on A16 to A21 pins.
Which the identified sector is protected, the device will
output 01H. Which the identified sector is no t pro tect, the
device will o utput 00H.
REV. 0.04, JUL. 11, 2005
23
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