Datasheet MX29LA128MT-B Datasheet (MXIC)

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FEATURES

PRELIMINARY

MX29LA128M T/B

128M-BIT SINGLE VOLTAGE 3V ONLY

BOOT SECTOR FLASH MEMORY

GENERAL FEA TURES

• Single Po wer Supply Operatio n

- 2.7 to 3.6 volt for read, erase, and program operations

• Configuration

- 16,777,216 x 8 / 8,388,608 x 16 switchable

• Sector structure

- 8KB(4KW) x 8 and 64KB(32KW) x 255

• Latch-up protected to 250mA fro m -1V to VCC + 1V

• Low VCC write inhibit is equal to or less than 1.5V

• Compatible with JEDEC standard

- Pin-out and software compatible to single power supply Flash

PERFORMANCE

• High Perf ormance

- Fast access time: 90R/100ns

- Page read time: 25ns

- Sector erase time: 0.5s (typ.)

- 4 word/8 b yte page read buffer

- 16 word/ 32 b yte write buffer: reduces pro gramming time fo r multiple-wo rd/byte updates

• Low Po wer Consumptio n

- Active read current: 18mA(typ.)

- Active write current: 20mA(typ.)

- Standby current: 20uA(typ.)

• Minimum 100,000 erase/prog ram cycle

• 20-years data retention

SOFTW ARE FEA TURES

• Support Commo n Flash Interf ace (CFI)

- Flash device parameters stored on the device and provide the host system to access.

• Program Suspend/Pro gram Resume

- Suspend prog ram operatio n to read o ther secto rs

• Erase Suspend/ Erase Resume

- Suspends sector erase operation to read data/program o ther sectors

• Status Reply

- Data# polling & Toggle bits pro vide detectio n o f program and erase operation completion

HARDW ARE FEA TURES

• Ready/Busy (RY/BY#) Output

- Provides a hardware method of detecting program and erase operation completion

• Hardware Reset (RESET#) Input

- Provides a hardware method to reset the internal state machine to read mode

• WP#/ACC input

- Write pro tect (WP#) functio n allows pro tection o f all sectors, regardless o f secto r pro tectio n settings

- ACC (high voltage) accelerates programming time fo r higher throughput during system

SECURITY

• Sector Pro tection/Chip Unpro tect

- Pro vides sector gro up pro tect function to pre vent program o r erase o peration in the pro tected secto r gro up

- Provides chip unprotect function to allow code changes

- Provides tempo rary secto r gro up unprotect functio n fo r code changes in pre viously pro tected secto r groups

• Sector P ermanent Loc k

- A unique lock bit feature allows the content to be permanently lock ed

(Please contact Macronix sales for specific information regarding this permanent lock feature)

• Secured Silicon Secto r

- Provides a 128-word OTP area for permanent, secure identification

- Can be programmed and lo ck ed at facto ry or by customer

P A CKAGE

• 56-pin TSOP

GENERAL DESCRIPTION

The MX29LA128M T/B is a 128-mega bit Flash memo ry organiz ed as 16M bytes o f 8 bits or 8M wo rds of 16 bits. MXIC's Flash memories o ffer the mo st co st-effective and reliable read/write non-v o latile random access memo ry . The MX29LA128M T/B is pac kaged in 56-pin TSOP. It is designed to be reprog rammed and erased in system o r in standard EPROM pro grammers.

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The standard MX29LA128M T/B offers access time as fast as 90ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29LA128M T/B has separate chip enable (CE#) and output enab le (OE#) co ntrols.

MXIC's Flash memories augment EPROM functio nality

MX29LA128M T/B

with in-circuit electrical erasure and prog ramming. The MX29LA128M T/B uses a co mmand register to manage this functionality.

MXIC Flash technology reliably stores memory contents even after 100,000 er ase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29LA128M T/B uses a 2.7V to 3.6V VCC supply to perform the High Reliability Erase and auto Progr am/Erase algorithms.

The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamperes on address and data pin from -1V to VCC + 1V.

AUTOMATIC PROGRAMMING

The MX29LA128M T/B is b yte/word/page pro grammab le using the Auto matic Pro gramming algo rithm. The Automatic Programming algorithm makes the external system do not need to ha ve time o ut sequence no r to verify the data prog rammed.

AUTOMATIC PROGRAMMING ALGORITHM

AUTOMATIC SECTOR ERASE

The MX29LA128M T/B is secto r(s) erasable using MXIC's Auto Secto r Erase algo rithm. Secto r erase mo des allo w sectors o f the arra y to be erased in o ne erase cycle. The Auto matic Sector Er ase algorithm auto matically progr ams the specified sector(s) prio r to electrical erase. The timing and verificatio n of electrical erase are co ntrolled internally within the device.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard micropro cesso r write timings. The de vice will automatically pre-prog r am and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the status of the programming operation.

Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry . During write cycles, the co mmand register internally latches address and data needed for the programming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge o f WE# .

MXIC's Automatic Programming algorithm require the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The de vice automatically times the programming pulse width, provides the program verification, and counts the number of sequences. A status bit similar to DATA# polling and a status bit to ggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 50 ms erase pulses according to MXIC's A utomatic Chip Er ase algorithm. The Automatic Erase algorithm automatically programs the entire array prio r to electrical erase. The timing and verification o f electrical erase are co ntro lled internally within the device.

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MXIC's Flash technology combines years of EPROM experience to pro duce the highest le vels of quality, reliability, and cost effectiveness. The MX29LA128M T/B electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are pro grammed b y using the EPROM programming mechanism of hot electron injection.

During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command register to respond to its full command set.

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PIN CONFIGURATION

MX29LA128M T/B

56 TSOP

NC A22 A15 A14 A13 A12 A11 A10

A19 A20

WE#

RESET#

A21

WP#/ACC

RY/BY#

A18 A17

1 2 3 4 5 6 7 8 9

11 12 13 14 15 16 17 18 19 20

27 28

A16

BYTE#

VSS

Q15/A-1

Q14

Q13

Q12

43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE# VSS CE# A0 NC VIO

PIN DESCRIPTION

SYMBOL PIN NAME

A0~A22 Address Input Q0~Q14 Data Inputs/Outputs Q15/A-1 Q15(Word Mode)/LSB addr(Byte Mode) CE# Chip Enable Input WE# Write Enable Input OE# Output Enable Input RESET# Hardware Reset Pin, Active Low WP#/ACC Hardware Write Protect/Prog ramming

Acceleration input RY/BY# Read/Busy Output BYTE# Selects 8 bit or 16 bit mode VC C +3.0V single power supply VI/O Output Buffer P ower (2.7V~3.6V this

input should be tied directly to VCC ) GN D Device Ground N C Pin Not Connected Internally

LOGIC SYMBOL

A0-A22

CE# OE# WE# RESET# WP#/ACC BYTE# VI/O

Q0-Q15

16 or 8

(A-1)

RY/BY#

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BLOCK DIAGRAM

MX29LA128M T/B

CE#

OE# WE# WP#

BYTE#

RESET#

A0-A22

CONTROL INPUT

LOGIC

ADDRESS

LATCH

AND

BUFFER

PROGRAM/ERASE

HIGH VOLTA GE

X-DECODER

FLASH ARRAY

Y-DECODER

Y-PASS GATE

WRITE

STATE

MACHINE

(WSM)

STATE

ARRAY

SOURCE

COMMAND

DATA DECODER

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Q0-Q15/A-1

SENSE

AMPLIFIER

I/O BUFFER

PGM

DATA

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

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MX29LA128M T/B

MX29LA128MT SECTOR ADDRESS TABLE

Sector Sector Sector Address Sector Size (x8) (x16) Group A22-A12 (Kbytes/Kwords) Address Range Address Range

1 SA0 00000000xxx 64/32 000000-0FFFFF 000000-007FFF 1 SA1 00000001xxx 64/32 010000-1FFFFF 008000-00FFFF 1 SA2 00000010xxx 64/32 020000-2FFFFF 010000-017FFF 1 SA3 00000011xxx 64/32 030000-3FFFFF 018000-01FFFF 2 SA4 00000100xxx 64/32 040000-4FFFFF 020000-027FFF 2 SA5 00000101xxx 64/32 050000-5FFFFF 028000-02FFFF 2 SA6 00000110xxx 64/32 060000-6FFFFF 030000-037FFF 2 SA7 00000111xxx 64/32 070000-7FFFFF 038000-03FFFF 3 SA8 00001000xxx 64/32 080000-8FFFFF 040000-047FFF 3 SA9 00001001xxx 64/32 090000-9FFFFF 048000-04FFFF 3 SA10 00001010xxx 64/32 0A0000-AFFFFF 050000-057FFF 3 SA11 00001011xxx 64/32 0B0000-BFFFFF 058000-05FFFF 4 SA12 00001100xxx 64/32 0C0000-CFFFFF 060000-067FFF 4 SA13 00001101xxx 64/32 0D0000-DFFFFF 068000-06FFFF 4 SA14 00001110xxx 64/32 0E0000-EFFFFF 070000-077FFF 4 SA15 00001111xxx 64/32 0F0000-FFFFFF 078000-07FFFF 5 SA16 00010000xxx 64/32 100000-0FFFFF 080000-087FFF 5 SA17 00010001xxx 64/32 110000-1FFFFF 088000-08FFFF 5 SA18 00010010xxx 64/32 120000-2FFFFF 090000-097FFF 5 SA19 00010011xxx 64/32 130000-3FFFFF 098000-09FFFF 6 SA20 00010100xxx 64/32 140000-4FFFFF 0A0000-0A7FFF 6 SA21 00010101xxx 64/32 150000-5FFFFF 0A8000-0AFFFF 6 SA22 00010110xxx 64/32 160000-6FFFFF 0B0000-0B7FFF 6 SA23 00010111xxx 64/32 170000-7FFFFF 0B8000-0BFFFF 7 SA24 00011000xxx 64/32 180000-8FFFFF 0C0000-0C7FFF 7 SA25 00011001xxx 64/32 190000-9FFFFF 0C8000-0CFFFF 7 SA26 00011010xxx 64/32 1A0000-AFFFFF 0D0000-0D7FFF 7 SA27 00011011xxx 64/32 1B0000-BFFFFF 0D8000- 0DFFFF 8 SA28 00011100xxx 64/32 1C0000-CFFFFF 0E0000-0E7FFF 8 SA29 00011101xxx 64/32 1D0000-DFFFFF 0E8000-0EFFFF 8 SA30 00011110xxx 64/32 1E0000-EFFFFF 0F0000-0F7FFF 8 SA31 00011111xxx 64/32 1F0000-FFFFFF 0F8000-0FFFFF 9 SA32 00100000xxx 64/32 200000-0FFFFF 100000-107FFF 9 SA33 00100001xxx 64/32 210000-1FFFFF 108000-10FFFF 9 SA34 00100010xxx 64/32 220000-2FFFFF 110000-117FFF 9 SA35 00100011xxx 64/32 230000-3FFFFF 118000-11FFFF 10 SA36 00100100xxx 64/32 240000-4FFFFF 120000-127FFF 10 SA37 00100101xxx 64/32 250000-5FFFFF 128000-12FFFF 10 SA38 00100110xxx 64/32 260000-6FFFFF 130000-137FFF

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MX29LA128M T/B

Sector Sector Sector Address Sector Size (x8) (x16) Group A22-A12 (Kbytes/Kwords) Address Range Address Range

10 SA39 00100111xxx 64/32 270000-7FFFFF 138000-13FFFF 11 SA40 00101000xxx 64/32 280000-8FFFFF 140000-147FFF 11 SA41 00101001xxx 64/32 290000-9FFFFF 148000-14FFFF 11 SA42 00101010xxx 64/32 2A0000-AFFFFF 150000-157FFF 11 SA43 00101011xxx 64/32 2B0000-BFFFFF 158000-15FFFF 12 SA44 00101100xxx 64/32 2C0000-CFFFFF 160000-167FFF 12 SA45 00101101xxx 64/32 2D0000-DFFFFF 168000-16FFFF 12 SA46 00101110xxx 64/32 2E0000-EFFFFF 170000-177FFF 12 SA47 00101111xxx 64/32 2F0000-FFFFFF 178000-17FFFF 13 SA48 00110000xxx 64/32 300000-0FFFFF 180000-187FFF 13 SA49 00110001xxx 64/32 310000-1FFFFF 188000-18FFFF 13 SA50 00110010xxx 64/32 320000-2FFFFF 190000-197FFF 13 SA51 00110011xxx 64/32 330000-3FFFFF 198000-19FFFF 14 SA52 00110100xxx 64/32 340000-4FFFFF 1A0000-1A7FFF 14 SA53 00110101xxx 64/32 350000-5FFFFF 1A8000-1AFFFF 14 SA54 00110110xxx 64/32 360000-6FFFFF 1B0000-1B7FFF 14 SA55 00110111xxx 64/32 370000-7FFFFF 1B8000-1BFFFF 15 SA56 00111000xxx 64/32 380000-8FFFFF 1C0000-1C7FFF 15 SA57 00111001xxx 64/32 390000-9FFFFF 1C8000-1CFFFF 15 SA58 00111010xxx 64/32 3A0000-AFFFFF 1D0000-1D7FFF 15 SA59 00111011xxx 64/32 3B0000-BFFFFF 1D8000-1DFFFF 16 SA60 00111100xxx 64/32 3C0000-CFFFFF 1E0000-1E7FFF 16 SA61 00111101xxx 64/32 3D0000-DFFFFF 1E8000-1EFFFF 16 SA62 00111110xxx 64/32 3E0000-EFFFFF 1F0000-1F7FFF 16 SA63 00111111xxx 64/32 3F0000-FFFFFF 1F8000-1FFFFF 17 SA64 01000000xxx 64/32 400000-0FFFFF 200000-207FFF 17 SA65 01000001xxx 64/32 410000-1FFFFF 208000-20FFFF 17 SA66 01000010xxx 64/32 420000-2FFFFF 210000-217FFF 17 SA67 01000011xxx 64/32 430000-3FFFFF 218000-21FFFF 18 SA68 01000100xxx 64/32 440000-4FFFFF 220000-227FFF 18 SA69 01000101xxx 64/32 450000-5FFFFF 228000-22FFFF 18 SA70 01000110xxx 64/32 460000-6FFFFF 230000-237FFF 18 SA71 01000111xxx 64/32 470000-7FFFFF 238000-23FFFF 19 SA72 01001000xxx 64/32 480000-8FFFFF 240000-247FFF 19 SA73 01001001xxx 64/32 490000-9FFFFF 248000-24FFFF 19 SA74 01001010xxx 64/32 4A0000-AFFFFF 250000-257FFF 19 SA75 01001011xxx 64/32 4B0000-BFFFFF 258000-25FFFF 20 SA76 01001100xxx 64/32 4C0000-CFFFFF 260000-267FFF 20 SA77 01001101xxx 64/32 4D0000-DFFFFF 268000-26FFFF 20 SA78 01001110xxx 64/32 4E0000-EFFFFF 270000-277FFF 20 SA79 01001111xxx 64/32 4F0000-FFFFFF 278000-27FFFF

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MX29LA128M T/B

Sector Sector Sector Address Sector Size (x8) (x16) Group A22-A12 (Kbytes/Kwords) Address Range Address Range

21 SA80 01010000xxx 64/32 500000-0FFFFF 280000-287FFF 21 SA81 01010001xxx 64/32 510000-1FFFFF 288000-28FFFF 21 SA82 01010010xxx 64/32 520000-2FFFFF 290000-297FFF 21 SA83 01010011xxx 64/32 530000-3FFFFF 298000-29FFFF 22 SA84 01010100xxx 64/32 540000-4FFFFF 2A0000-2A7FFF 22 SA85 01010101xxx 64/32 550000-5FFFFF 2A8000-2AFFFF 22 SA86 01010110xxx 64/32 560000-6FFFFF 2B0000-2B7FFF 22 SA87 01010111xxx 64/32 570000-7FFFFF 2B8000-2BFFFF 23 SA88 01011000xxx 64/32 580000-8FFFFF 2C0000-2C7FFF 23 SA89 01011001xxx 64/32 590000-9FFFFF 2C8000-2CFFFF 23 SA90 01011010xxx 64/32 5A0000-AFFFFF 2D0000-2D7FFF 23 SA91 01011011xxx 64/32 5B0000-BFFFFF 2D8000-2DFFFF 24 SA92 01011100xxx 64/32 5C0000-CFFFFF 2E0000-2E7FFF 24 SA93 01011101xxx 64/32 5D0000-DFFFFF 2E8000-2EFFFF 24 SA94 01011110xxx 64/32 5E0000-EFFFFF 2F0000-2F7FFF 24 SA95 01011111xxx 64/32 5F0000-FFFFFF 2F8000-2FFFFF 25 SA96 01100000xxx 64/32 600000-0FFFFF 300000-307FFF 25 SA97 01100001xxx 64/32 610000-1FFFFF 308000-30FFFF 25 SA98 01100010xxx 64/32 620000-2FFFFF 310000-317FFF 25 SA99 01100011xxx 64/32 630000-3FFFFF 318000-31FFFF 26 SA100 01100100xxx 64/32 640000-4FFFFF 320000-327FFF 26 SA101 01100101xxx 64/32 650000-5FFFFF 328000-32FFFF 26 SA102 01100110xxx 64/32 660000-6FFFFF 330000-337FFF 26 SA103 01100111xxx 64/32 670000-7FFFFF 338000-33FFFF 27 SA104 01101000xxx 64/32 680000-8FFFFF 340000-347FFF 27 SA105 01101001xxx 64/32 690000-9FFFFF 348000-34FFFF 27 SA106 01101010xxx 64/32 6A0000-AFFFFF 350000-357FFF 27 SA107 01101011xxx 64/32 6B0000-BFFFFF 358000-35FFFF 28 SA108 01101100xxx 64/32 6C0000-CFFFFF 360000-367FFF 28 SA109 01101101xxx 64/32 6D0000-DFFFFF 368000-36FFFF 28 SA110 01101110xxx 64/32 6E0000-EFFFFF 370000-377FFF 28 SA111 01101111xxx 64/32 6F0000-FFFFFF 378000-37FFFF 29 SA112 01110000xxx 64/32 700000-0FFFFF 380000-387FFF 29 SA113 01110001xxx 64/32 710000-1FFFFF 388000-38FFFF 29 SA114 01110010xxx 64/32 720000-2FFFFF 390000-397FFF 29 SA115 01110011xxx 64/32 730000-3FFFFF 398000-39FFFF 30 SA116 01110100xxx 64/32 740000-4FFFFF 3A0000-3A7FFF 30 SA117 01110101xxx 64/32 750000-5FFFFF 3A8000-3AFFFF 30 SA118 01110110xxx 64/32 760000-6FFFFF 3B0000-3B7FFF 30 SA119 01110111xxx 64/32 770000-7FFFFF 3B8000-3BFFFF 31 SA120 01111000xxx 64/32 780000-8FFFFF 3C0000-3C7FFF

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MX29LA128M T/B

Sector Sector Sector Address Sector Size (x8) (x16) Group A22-A12 (Kbytes/Kwords) Address Range Address Range

31 SA121 01111001xxx 64/32 790000-9FFFFF 3C8000-3CFFFF 31 SA122 01111010xxx 64/32 7A0000-AFFFFF 3D0000-3D7FFF 31 SA123 01111011xxx 64/32 7B0000-BFFFFF 3D8000 -3DFFFF 32 SA124 01111100xxx 64/32 7C0000-CFFFFF 3E0000-3E7FFF 32 SA125 01111101xxx 64/32 7D0000-DFFFFF 3E8000-3EFFFF 32 SA126 01111110xxx 64/32 7E0000-EFFFFF 3F0000-3F7FFF 32 SA127 01111111xxx 64/32 7F0000-FFFFFF 3F8000-3FFFFF 33 SA128 10000000xxx 64/32 800000-0FFFFF 400000-407FFF 33 SA129 10000001xxx 64/32 810000-1FFFFF 408000-40FFFF 33 SA130 10000010xxx 64/32 820000-2FFFFF 410000-417FFF 33 SA131 10000011xxx 64/32 830000-3FFFFF 418000-41FFFF 34 SA132 10000100xxx 64/32 840000-4FFFFF 420000-427FFF 34 SA133 10000101xxx 64/32 850000-5FFFFF 428000-42FFFF 34 SA134 10000110xxx 64/32 860000-6FFFFF 430000-437FFF 34 SA135 10000111xxx 64/32 870000-7FFFFF 438000-43FFFF 35 SA136 10001000xxx 64/32 880000-8FFFFF 440000-447FFF 35 SA137 10001001xxx 64/32 890000-9FFFFF 448000-44FFFF 35 SA138 10001010xxx 64/32 8A0000-AFFFFF 450000-457FFF 35 SA139 10001011xxx 64/32 8B0000-BFFFFF 458000-45FFFF 36 SA140 10001100xxx 64/32 8C0000-CFFFFF 460000-467FFF 36 SA141 10001101xxx 64/32 8D0000-DFFFFF 468000-46FFFF 36 SA142 10001110xxx 64/32 8E0000-EFFFFF 470000-477FFF 36 SA143 10001111xxx 64/32 8F0000-FFFFFF 478000-47FFFF 37 SA144 10010000xxx 64/32 900000-0FFFFF 480000-487FFF 37 SA145 10010001xxx 64/32 910000-1FFFFF 488000-48FFFF 37 SA146 10010010xxx 64/32 920000-2FFFFF 490000-497FFF 37 SA147 10010011xxx 64/32 930000-3FFFFF 498000-49FFFF 38 SA148 10010100xxx 64/32 940000-4FFFFF 4A0000-4A7FFF 38 SA149 10010101xxx 64/32 950000-5FFFFF 4A8000-4AFFFF 38 SA150 10010110xxx 64/32 960000-6FFFFF 4B0000-4B7FFF 38 SA151 10010111xxx 64/32 970000-7FFFFF 4B8000-4BFFFF 39 SA152 10011000xxx 64/32 980000-8FFFFF 4C0000-4C7FFF 39 SA153 10011001xxx 64/32 990000-9FFFFF 4C8000-4CFFFF 39 SA154 10011010xxx 64/32 9A0000-AFFFFF 4D0000-4D7FFF 39 SA155 10011011xxx 64/32 9B0000-BFFFFF 4D8000 -4DFFFF 40 SA156 10011100xxx 64/32 9C0000-CFFFFF 4E0000-4E7FFF 40 SA157 10011101xxx 64/32 9D0000-DFFFFF 4E8000-4EFFFF 40 SA158 10011110xxx 64/32 9E0000-EFFFFF 4F0000-4F7FFF 40 SA159 10011111xxx 64/32 9F0000-FFFFFF 4F8000-4FFFFF 41 SA160 10100000xxx 64/32 A00000-0FFFFF 500000-507FFF 41 SA161 10100001xxx 64/32 A10000-1FFFFF 508000-50FFFF

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MX29LA128M T/B

Sector Sector Sector Address Sector Size (x8) (x16) Group A22-A12 (Kbytes/Kwords) Address Range Address Range

41 SA162 10100010xxx 64/32 A20000-2FFFFF 510000-517FFF 41 SA163 10100011xxx 64/32 A30000-3FFFFF 518000-51FFFF 42 SA164 10100100xxx 64/32 A40000-4FFFFF 520000-527FFF 42 SA165 10100101xxx 64/32 A50000-5FFFFF 528000-52FFFF 42 SA166 10100110xxx 64/32 A60000-6FFFFF 530000-537FFF 42 SA167 10100111xxx 64/32 A70000-7FFFFF 538000-53FFFF 43 SA168 10101000xxx 64/32 A80000-8FFFFF 540000-547FFF 43 SA169 10101001xxx 64/32 A90000-9FFFFF 548000-54FFFF 43 SA170 10101010xxx 64/32 AA0000-AFFFFF 550000-557FFF 43 SA171 10101011xxx 64/32 AB0000-BFFFFF 558000-55FFFF 44 SA172 10101100xxx 64/32 AC0000-CFFFFF 560000-567FFF 44 SA173 10101101xxx 64/32 AD0000-DFFFFF 568000-56FFFF 44 SA174 10101110xxx 64/32 AE0000-EFFFFF 570000-577FFF 44 SA175 10101111xxx 64/32 AF0000-FFFFFF 578000-57FFFF 45 SA176 10110000xxx 64/32 B00000-0FFFFF 580000-587FFF 45 SA177 10110001xxx 64/32 B10000-1FFFFF 588000-58FFFF 45 SA178 10110010xxx 64/32 B20000-2FFFFF 590000-597FFF 45 SA179 10110011xxx 64/32 B30000-3FFFFF 598000-59FFFF 46 SA180 10110100xxx 64/32 B40000-4FFFFF 5A0000-5A7FFF 46 SA181 10110101xxx 64/32 B50000-5FFFFF 5A8000-5AFFFF 46 SA182 10110110xxx 64/32 B60000-6FFFFF 5B0000-5B7FFF 46 SA183 10110111xxx 64/32 B70000-7FFFFF 5B8000-5BFFFF 47 SA184 10111000xxx 64/32 B80000-8FFFFF 5C0000-5C7FFF 47 SA185 10111001xxx 64/32 B90000-9FFFFF 5C8000-5 CFFFF 47 SA186 10111010xxx 64/32 BA0000-AFFFFF 5D0000-5D7FFF 47 SA187 10111011xxx 64/32 BB0000-BFFFFF 5D800 0 - 5 DFFFF 48 SA188 10111100xxx 64/32 BC0000-CFFFFF 5E0000-5E7FFF 48 SA189 10111101xxx 64/32 BD0000-DFFFFF 5E8000-5EFFFF 48 SA190 10111110xxx 64/32 BE0000-EFFFFF 5F0000-5F7FFF 48 SA191 10111111xxx 64/32 BF0000-FFFFFF 5F8000-5FFFFF 49 SA192 11000000xxx 64/32 C00000-0FFFFF 600000-607FFF 49 SA193 11000001xxx 64/32 C10000-1FFFFF 608000-60FFFF 49 SA194 11000010xxx 64/32 C20000-2FFFFF 610000-617FFF 49 SA195 11000011xxx 64/32 C30000-3FFFFF 618000-61FFFF 50 SA196 11000100xxx 64/32 C40000-4FFFFF 620000-627FFF 50 SA197 11000101xxx 64/32 C50000-5FFFFF 628000-62FFFF 50 SA198 11000110xxx 64/32 C60000-6FFFFF 630000-637FFF 50 SA199 11000111xxx 64/32 C70000-7FFFFF 638000-63FFFF 51 SA200 11001000xxx 64/32 C80000-8FFFFF 640000-647FFF 51 SA201 11001001xxx 64/32 C90000-9FFFFF 648000-64FFFF 51 SA202 11001010xxx 64/32 CA0000-AFFFFF 650000-657FFF

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MX29LA128M T/B

Sector Sector Sector Address Sector Size (x8) (x16) Group A22-A12 (Kbytes/Kwords) Address Range Address Range

51 SA203 11001011xxx 64/32 CB0000-BFFFFF 658000-65FFFF 52 SA204 11001100xxx 64/32 CC0000-CFFFFF 660000-667FFF 52 SA205 11001101xxx 64/32 CD0000-DFFFFF 668000-66FFFF 52 SA206 11001110xxx 64/32 CE0000-EFFFFF 670000-677FFF 52 SA207 11001111xxx 64/32 CF0000-FFFFFF 678000-67FFFF 53 SA208 11010000xxx 64/32 D00000-0FFFFF 680000-687FFF 53 SA209 11010001xxx 64/32 D10000-1FFFFF 688000-68FFFF 53 SA210 11010010xxx 64/32 D20000-2FFFFF 690000-697FFF 53 SA211 11010011xxx 64/32 D30000-3FFFFF 698000-69FFFF 54 SA212 11010100xxx 64/32 D40000-4FFFFF 6A0000-6A7FFF 54 SA213 11010101xxx 64/32 D50000-5FFFFF 6A8000-6AFFFF 54 SA214 11010110xxx 64/32 D60000-6FFFFF 6B0000-6B7FFF 54 SA215 11010111xxx 64/32 D70000-7FFFFF 6B8000-6BFFFF 55 SA216 11011000xxx 64/32 D80000-8FFFFF 6C0000-6C7FFF 55 SA217 11011001xxx 64/32 D90000-9FFFFF 6C8000-6CFFFF 55 SA218 11011010xxx 64/32 DA0000-AFFFFF 6D0000-6D7FFF 55 SA219 11011011xxx 64/32 DB0000-BFFFFF 6D8000- 6DFFFF 56 SA220 11011100xxx 64/32 DC0000-CFFFFF 6E0000-6E7FFF 56 SA221 11011101xxx 64/32 DD0000-DFFFFF 6E8000-6EFFFF 56 SA222 11011110xxx 64/32 DE0000-EFFFFF 6F0000-6F7FFF 56 SA223 11011111xxx 64/32 DF0000-FFFFFF 6F8000-6FFFFF 57 SA224 11100000xxx 64/32 E00000-0FFFFF 700000-707FFF 57 SA225 11100001xxx 64/32 E10000-1FFFFF 708000-70FFFF 57 SA226 11100010xxx 64/32 E20000-2FFFFF 710000-717FFF 57 SA227 11100011xxx 64/32 E30000-3FFFFF 718000-71FFFF 58 SA228 11100100xxx 64/32 E40000-4FFFFF 720000-727FFF 58 SA229 11100101xxx 64/32 E50000-5FFFFF 728000-72FFFF 58 SA230 11100110xxx 64/32 E60000-6FFFFF 730000-737FFF 58 SA231 11100111xxx 64/32 E70000-7FFFFF 738000-73FFFF 59 SA232 11101000xxx 64/32 E80000-8FFFFF 740000-747FFF 59 SA233 11101001xxx 64/32 E90000-9FFFFF 748000-74FFFF 59 SA234 11101010xxx 64/32 EA0000-AFFFFF 750000-757FFF 59 SA235 11101011xxx 64/32 EB0000-BFFFFF 758000-75FFFF 60 SA236 11101100xxx 64/32 EC0000-CFFFFF 760000-767FFF 60 SA237 11101101xxx 64/32 ED0000-DFFFFF 768000-76FFFF 60 SA238 11101110xxx 64/32 EE0000-EFFFFF 770000-777FFF 60 SA239 11101111xxx 64/32 EF0000-FFFFFF 778000-77FFFF 61 SA240 11110000xxx 64/32 F00000-0FFFFFF 780000-787FFF

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Sector Sector Sector Address Sector Size (x8) (x16) Group A22-A12 (Kbytes/Kwords) Address Range Address Range

61 SA241 11110001xxx 64/32 F10000-1FFFFF 788000-78FFFF 61 SA242 11110010xxx 64/32 F20000-2FFFFF 790000-797FFF 61 SA243 11110011xxx 64/32 F30000-3FFFFF 798000-79FFFF 62 SA244 11110100xxx 64/32 F40000-4FFFFF 7A0000-7A7FFF 62 SA245 11110101xxx 64/32 F50000-5FFFFF 7A8000-7AFFFF 62 SA246 11110110xxx 64/32 F60000-6FFFFF 7B0000-7B7FFF 62 SA247 11110111xxx 64/32 F70000-7FFFFF 7B8000-7BFFFF 63 SA248 11111000xxx 64/32 F80000-8FFFFF 7C0000-7C7FFF 63 SA249 11111001xxx 64/32 F90000-9FFFFF 7C 800 0- 7CFFFF 63 SA250 11111010xxx 64/32 FA0000-AFFFFF 7D0000-7D7FFF 63 SA251 11111011xxx 64/32 FB0000-BFFFFF 7D8000- 7DFFFF 64 SA252 11111100xxx 64/32 FC0000-CFFFFF 7E0000-7E7FFF 64 SA253 11111101xxx 64/32 FD0000-DFFFFF 7E8000-7EFFFF 64 SA254 11111110xxx 64/32 FE0000-EFFFFF 7F0000-7F7FFF 65 SA255 11111111000 8/4 FF0000-FF1FFF 7F8000-7F8FFF 66 SA256 11111111001 8/4 FF2000-FF3FFF 7F9000-7F9FFF 67 SA257 11111111010 8/4 FF4000-FF5FFF 7F A000-7FAFFF 68 SA258 11111111011 8/4 FF6000-FF7FFF 7FB000-7FBFFF 69 SA259 11111111100 8/4 FF8000-FF9FFF 7FC000-7FCFFF 70 SA260 11111111101 8/4 FFA000-FFBFFF 7FD000-7FDFFF 71 SA261 11111111110 8/4 FFC000-FFDFFF 7FE000-7FEFFF 72 SA262 11111111111 8/4 FFE000-FFFFFF 7FF000-7FFFFF

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

MX29LA128MB SECTOR ADDRESS TABLE

Sector Sector Sector Address Sector Size (x8) (x16) Group A22-A12 (Kbytes/Kwords) Address Range Address Range

1 SA0 00000000000 8/4 000000-001FFF 000000-000FFF 2 SA1 00000000001 8/4 002000-003FFF 001000-001FFF 3 SA2 00000000010 8/4 004000-005FFF 002000-002FFF 4 SA3 00000000011 8/4 006000-007FFF 003000-003FFF 5 SA4 00000000100 8/4 008000-009FFF 004000-004FFF 6 SA5 00000000101 8/4 00A000-00BFFF 005000-005FFF 7 SA6 00000000110 8/4 00C000-00DFFF 006000-006FFF 8 SA7 00000000111 8/4 00E000-00FFFF 007000-007FFF 9 SA8 00000001xxx 64/32 010000-1FFFFF 008000-00FFFF 9 SA9 00000010xxx 64/32 020000-2FFFFF 010000-017FFF 9 SA10 00000011xxx 64/32 030000-3FFFFF 018000-01FFFF 10 SA11 00000100xxx 64/32 040000-4FFFFF 020000-027FFF 10 SA12 00000101xxx 64/32 050000-5FFFFF 028000-02FFFF 10 SA13 00000110xxx 64/32 060000-6FFFFF 030000-037FFF 10 SA14 00000111xxx 64/32 070000-7FFFFF 038000-03FFFF 11 SA15 00001000xxx 64/32 080000-8FFFFF 040000-047FFF 11 SA16 00001001xxx 64/32 090000-9FFFFF 048000-04FFFF 11 SA17 00001010xxx 64/32 0A0000-AFFFFF 050000-057FFF 11 SA18 00001011xxx 64/32 0B0000-BFFFFF 058000-05FFFF 12 SA19 00001100xxx 64/32 0C0000-CFFFFF 060000-067FFF 12 SA20 00001101xxx 64/32 0D0000-DFFFFF 068000-06FFFF 12 SA21 00001110xxx 64/32 0E0000-EFFFFF 070000-077FFF 12 SA22 00001111xxx 64/32 0F0000-FFFFFF 078000-07FFFF 13 SA23 00010000xxx 64/32 100000-0FFFFF 080000-087FFF 13 SA24 00010001xxx 64/32 110000-1FFFFF 088000-08FFFF 13 SA25 00010010xxx 64/32 120000-2FFFFF 090000-097FFF 13 SA26 00010011xxx 64/32 130000-3FFFFF 098000-09FFFF 14 SA27 00010100xxx 64/32 140000-4FFFFF 0A0000-0A7FFF 14 SA28 00010101xxx 64/32 150000-5FFFFF 0A8000-0AFFFF 14 SA29 00010110xxx 64/32 160000-6FFFFF 0B0000-0B7FFF 14 SA30 00010111xxx 64/32 170000-7FFFFF 0B8000-0BFFFF 15 SA31 00011000xxx 64/32 180000-8FFFFF 0C0000-0C7FFF 15 SA32 00011001xxx 64/32 190000-9FFFFF 0C8000-0CFFFF 15 SA33 00011010xxx 64/32 1A0000-AFFFFF 0D0000-0D7FFF 15 SA34 00011011xxx 64/32 1B0000-BFFFFF 0D8000-0DFFFF 16 SA35 00011100xxx 64/32 1C0000-CFFFFF 0E0000-0E7FFF 16 SA36 00011101xxx 64/32 1D0000-DFFFFF 0E8000-0EFFFF 16 SA37 00011110xxx 64/32 1E0000-EFFFFF 0F0000-0F7FFF 16 SA38 00011111xxx 64/32 1F0000-FFFFFF 0F8000-0FFFFF

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Sector Sector Sector Address Sector Size (x8) (x16) Group A22-A12 (Kbytes/Kwords) Address Range Address Range

17 SA39 00100000xxx 64/32 200000-0FFFFF 100000-107FFF 17 SA40 00100001xxx 64/32 210000-1FFFFF 108000-10FFFF 17 SA41 00100010xxx 64/32 220000-2FFFFF 110000-117FFF 17 SA42 00100011xxx 64/32 230000-3FFFFF 118000-11FFFF 18 SA43 00100100xxx 64/32 240000-4FFFFF 120000-127FFF 18 SA44 00100101xxx 64/32 250000-5FFFFF 128000-12FFFF 18 SA45 00100110xxx 64/32 260000-6FFFFF 130000-137FFF 18 SA46 00100111xxx 64/32 270000-7FFFFF 138000-13FFFF 19 SA47 00101000xxx 64/32 280000-8FFFFF 140000-147FFF 19 SA48 00101001xxx 64/32 290000-9FFFFF 148000-14FFFF 19 SA49 00101010xxx 64/32 2A0000-AFFFFF 150000-157FFF 19 SA50 00101011xxx 64/32 2B0000-BFFFFF 158000-15FFFF 20 SA51 00101100xxx 64/32 2C0000-CFFFFF 160000-167FFF 20 SA52 00101101xxx 64/32 2D0000-DFFFFF 168000-16FFFF 20 SA53 00101110xxx 64/32 2E0000-EFFFFF 170000-177FFF 20 SA54 00101111xxx 64/32 2F0000-FFFFFF 178000-17FFFF 21 SA55 00110000xxx 64/32 300000-0FFFFF 180000-187FFF 21 SA56 00110001xxx 64/32 310000-1FFFFF 188000-18FFFF 21 SA57 00110010xxx 64/32 320000-2FFFFF 190000-197FFF 21 SA58 00110011xxx 64/32 330000-3FFFFF 198000-19FFFF 22 SA59 00110100xxx 64/32 340000-4FFFFF 1A0000-1A7FFF 22 SA60 00110101xxx 64/32 350000-5FFFFF 1A8000-1AFFFF 22 SA61 00110110xxx 64/32 360000-6FFFFF 1B0000-1B7FFF 22 SA62 00110111xxx 64/32 370000-7FFFFF 1B8000-1BFFFF 23 SA63 00111000xxx 64/32 380000-8FFFFF 1C0000-1C7FFF 23 SA64 00111001xxx 64/32 390000-9FFFFF 1C8000-1CFFFF 23 SA65 00111010xxx 64/32 3A0000-AFFFFF 1D0000-1D7FFF 23 SA66 00111011xxx 64/32 3B0000-BFFFFF 1D8000-1DFFFF 24 SA67 00111100xxx 64/32 3C0000-CFFFFF 1E0000-1E7FFF 24 SA68 00111101xxx 64/32 3D0000-DFFFFF 1E8000-1EFFFF 24 SA69 00111110xxx 64/32 3E0000-EFFFFF 1F0000-1F7FFF 24 SA70 00111111xxx 64/32 3F0000-FFFFFF 1F8000-1FFFFF 25 SA71 01000000xxx 64/32 400000-0FFFFF 200000-207FFF 25 SA72 01000001xxx 64/32 410000-1FFFFF 208000-20FFFF 25 SA73 01000010xxx 64/32 420000-2FFFFF 210000-217FFF 25 SA74 01000011xxx 64/32 430000-3FFFFF 218000-21FFFF 26 SA75 01000100xxx 64/32 440000-4FFFFF 220000-227FFF 26 SA76 01000101xxx 64/32 450000-5FFFFF 228000-22FFFF 26 SA77 01000110xxx 64/32 460000-6FFFFF 230000-237FFF 26 SA78 01000111xxx 64/32 470000-7FFFFF 238000-23FFFF 27 SA79 01001000xxx 64/32 480000-8FFFFF 240000-247FFF

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Sector Sector Sector Address Sector Size (x8) (x16) Group A22-A12 (Kbytes/Kwords) Address Range Address Range

27 SA80 01001001xxx 64/32 490000-9FFFFF 248000-24FFFF 27 SA81 01001010xxx 64/32 4A0000-AFFFFF 250000-257FFF 27 SA82 01001011xxx 64/32 4B0000-BFFFFF 258000-25FFFF 28 SA83 01001100xxx 64/32 4C0000-CFFFFF 260000-267FFF 28 SA84 01001101xxx 64/32 4D0000-DFFFFF 268000-26FFFF 28 SA85 01001110xxx 64/32 4E0000-EFFFFF 270000-277FFF 28 SA86 01001111xxx 64/32 4F0000-FFFFFF 278000-27FFFF 29 SA87 01010000xxx 64/32 500000-0FFFFF 280000-287FFF 29 SA88 01010001xxx 64/32 510000-1FFFFF 288000-28FFFF 29 SA89 01010010xxx 64/32 520000-2FFFFF 290000-297FFF 29 SA90 01010011xxx 64/32 530000-3FFFFF 298000-29FFFF 30 SA91 01010100xxx 64/32 540000-4FFFFF 2A0000-2A7FFF 30 SA92 01010101xxx 64/32 550000-5FFFFF 2A8000-2AFFFF 30 SA93 01010110xxx 64/32 560000-6FFFFF 2B0000-2B7FFF 30 SA94 01010111xxx 64/32 570000-7FFFFF 2B8000-2BFFFF 31 SA95 01011000xxx 64/32 580000-8FFFFF 2C0000-2C7FFF 31 SA96 01011001xxx 64/32 590000-9FFFFF 2C8000-2CFFFF 31 SA97 01011010xxx 64/32 5A0000-AFFFFF 2D0000-2D7FFF 31 SA98 01011011xxx 64/32 5B0000-BFFFFF 2D8000-2DFFFF 32 SA99 01011100xxx 64/32 5C0000-CFFFFF 2E0000-2E7FFF 32 SA100 01011101xxx 64/32 5D0000-DFFFFF 2E8000-2EFFFF 32 SA101 01011110xxx 64/32 5E0000-EFFFFF 2F0000-2F7FFF 32 SA102 01011111xxx 64/32 5F0000-FFFFFF 2F8000-2FFFFF 33 SA103 01100000xxx 64/32 600000-0FFFFF 300000-307FFF 33 SA104 01100001xxx 64/32 610000-1FFFFF 308000-30FFFF 33 SA105 01100010xxx 64/32 620000-2FFFFF 310000-317FFF 33 SA106 01100011xxx 64/32 630000-3FFFFF 318000-31FFFF 34 SA107 01100100xxx 64/32 640000-4FFFFF 320000-327FFF 34 SA108 01100101xxx 64/32 650000-5FFFFF 328000-32FFFF 34 SA109 01100110xxx 64/32 660000-6FFFFF 330000-337FFF 34 SA110 01100111xxx 64/32 670000-7FFFFF 338000-33FFFF 35 SA111 01101000xxx 64/32 680000-8FFFFF 340000-347FFF 35 SA112 01101001xxx 64/32 690000-9FFFFF 348000-34FFFF 35 SA113 01101010xxx 64/32 6A0000-AFFFFF 350000-357FFF 35 SA114 01101011xxx 64/32 6B0000-BFFFFF 358000-35FFFF 36 SA115 01101100xxx 64/32 6C0000-CFFFFF 360000-367FFF 36 SA116 01101101xxx 64/32 6D0000-DFFFFF 368000-36FFFF 36 SA117 01101110xxx 64/32 6E0000-EFFFFF 370000-377FFF 36 SA118 01101111xxx 64/32 6F0000-FFFFFF 378000-37FFFF 37 SA119 01110000xxx 64/32 700000-0FFFFF 380000-387FFF 37 SA120 01110001xxx 64/32 710000-1FFFFF 388000-38FFFF

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Sector Sector Sector Address Sector Size (x8) (x16) Group A22-A12 (Kbytes/Kwords) Address Range Address Range

37 SA121 01110010xxx 64/32 720000-2FFFFF 390000-397FFF 37 SA122 01110011xxx 64/32 730000-3FFFFF 398000-39FFFF 38 SA123 01110100xxx 64/32 740000-4FFFFF 3A0000-3A7FFF 38 SA124 01110101xxx 64/32 750000-5FFFFF 3A8000-3AFFFF 38 SA125 01110110xxx 64/32 760000-6FFFFF 3B0000-3B7FFF 38 SA126 01110111xxx 64/32 770000-7FFFFF 3B8000-3BFFFF 39 SA127 01111000xxx 64/32 780000-8FFFFF 3C0000-3C7FFF 39 SA128 01111001xxx 64/32 790000-9FFFFF 3C8000-3CFFFF 39 SA129 01111010xxx 64/32 7A0000-AFFFFF 3D0000-3D7FFF 39 SA130 01111011xxx 64/32 7B0000-BFFFFF 3D8000 -3DFFFF 40 SA131 01111100xxx 64/32 7C0000-CFFFFF 3E0000-3E7FFF 40 SA132 01111101xxx 64/32 7D0000-DFFFFF 3E8000-3EFFFF 40 SA133 01111110xxx 64/32 7E0000-EFFFFF 3F0000-3F7FFF 40 SA134 01111111xxx 64/32 7F0000-FFFFFF 3F8000-3FFFFF 41 SA135 10000000xxx 64/32 800000-0FFFFF 400000-407FFF 41 SA136 10000001xxx 64/32 810000-1FFFFF 408000-40FFFF 41 SA137 10000010xxx 64/32 820000-2FFFFF 410000-417FFF 41 SA138 10000011xxx 64/32 830000-3FFFFF 418000-41FFFF 42 SA139 10000100xxx 64/32 840000-4FFFFF 420000-427FFF 42 SA140 10000101xxx 64/32 850000-5FFFFF 428000-42FFFF 42 SA141 10000110xxx 64/32 860000-6FFFFF 430000-437FFF 42 SA142 10000111xxx 64/32 870000-7FFFFF 438000-43FFFF 43 SA143 10001000xxx 64/32 880000-8FFFFF 440000-447FFF 43 SA144 10001001xxx 64/32 890000-9FFFFF 448000-44FFFF 43 SA145 10001010xxx 64/32 8A0000-AFFFFF 450000-457FFF 43 SA146 10001011xxx 64/32 8B0000-BFFFFF 458000-45FFFF 44 SA147 10001100xxx 64/32 8C0000-CFFFFF 460000-467FFF 44 SA148 10001101xxx 64/32 8D0000-DFFFFF 468000-46FFFF 44 SA149 10001110xxx 64/32 8E0000-EFFFFF 470000-477FFF 44 SA150 10001111xxx 64/32 8F0000-FFFFFF 478000-47FFFF 45 SA151 10010000xxx 64/32 900000-0FFFFF 480000-487FFF 45 SA152 10010001xxx 64/32 910000-1FFFFF 488000-48FFFF 45 SA153 10010010xxx 64/32 920000-2FFFFF 490000-497FFF 45 SA154 10010011xxx 64/32 930000-3FFFFF 498000-49FFFF 46 SA155 10010100xxx 64/32 940000-4FFFFF 4A0000-4A7FFF 46 SA156 10010101xxx 64/32 950000-5FFFFF 4A8000-4AFFFF 46 SA157 10010110xxx 64/32 960000-6FFFFF 4B0000-4B7FFF 46 SA158 10010111xxx 64/32 970000-7FFFFF 4B8000-4BFFFF 47 SA159 10011000xxx 64/32 980000-8FFFFF 4C0000-4C7FFF 47 SA160 10011001xxx 64/32 990000-9FFFFF 4C8000-4CFFFF 47 SA161 10011010xxx 64/32 9A0000-AFFFFF 4D0000-4D7FFF 47 SA162 10011011xxx 64/32 9B0000-BFFFFF 4D8000 -4DFFFF

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Sector Sector Sector Address Sector Size (x8) (x16) Group A22-A12 (Kbytes/Kwords) Address Range Address Range

48 SA163 10011100xxx 64/32 9C0000-CFFFFF 4E0000-4E7FFF 48 SA164 10011101xxx 64/32 9D0000-DFFFFF 4E8000-4EFFFF 48 SA165 10011110xxx 64/32 9E0000-EFFFFF 4F0000-4F7FFF 48 SA166 10011111xxx 64/32 9F0000-FFFFFF 4F8000-4FFFFF 49 SA167 10100000xxx 64/32 A00000-0FFFFF 500000-507FFF 49 SA168 10100001xxx 64/32 A10000-1FFFFF 508000-50FFFF 49 SA169 10100010xxx 64/32 A20000-2FFFFF 510000-517FFF 49 SA170 10100011xxx 64/32 A30000-3FFFFF 518000-51FFFF 50 SA171 10100100xxx 64/32 A40000-4FFFFF 520000-527FFF 50 SA172 10100101xxx 64/32 A50000-5FFFFF 528000-52FFFF 50 SA173 10100110xxx 64/32 A60000-6FFFFF 530000-537FFF 50 SA174 10100111xxx 64/32 A70000-7FFFFF 538000-53FFFF 51 SA175 10101000xxx 64/32 A80000-8FFFFF 540000-547FFF 51 SA176 10101001xxx 64/32 A90000-9FFFFF 548000-54FFFF 51 SA177 10101010xxx 64/32 AA0000-AFFFFF 550000-557FFF 51 SA178 10101011xxx 64/32 AB0000-BFFFFF 558000-55FFFF 52 SA179 10101100xxx 64/32 AC0000-CFFFFF 560000-567FFF 52 SA180 10101101xxx 64/32 AD0000-DFFFFF 568000-56FFFF 52 SA181 10101110xxx 64/32 AE0000-EFFFFF 570000-577FFF 52 SA182 10101111xxx 64/32 AF0000-FFFFFF 578000-57FFFF 53 SA183 10110000xxx 64/32 B00000-0FFFFF 580000-587FFF 53 SA184 10110001xxx 64/32 B10000-1FFFFF 588000-58FFFF 53 SA185 10110010xxx 64/32 B20000-2FFFFF 590000-597FFF 53 SA186 10110011xxx 64/32 B30000-3FFFFF 598000-59FFFF 54 SA187 10110100xxx 64/32 B40000-4FFFFF 5A0000-5A7FFF 54 SA188 10110101xxx 64/32 B50000-5FFFFF 5A8000-5AFFFF 54 SA189 10110110xxx 64/32 B60000-6FFFFF 5B0000-5B7FFF 54 SA190 10110111xxx 64/32 B70000-7FFFFF 5B8000-5BFFFF 55 SA191 10111000xxx 64/32 B80000-8FFFFF 5C0000-5C7FFF 55 SA192 10111001xxx 64/32 B90000-9FFFFF 5C8000-5 CFFFF 55 SA193 10111010xxx 64/32 BA0000-AFFFFF 5D0000-5D7FFF 55 SA194 10111011xxx 64/32 BB0000-BFFFFF 5D800 0 - 5 DFFFF 56 SA195 10111100xxx 64/32 BC0000-CFFFFF 5E0000-5E7FFF 56 SA196 10111101xxx 64/32 BD0000-DFFFFF 5E8000-5EFFFF 56 SA197 10111110xxx 64/32 BE0000-EFFFFF 5F0000-5F7FFF 56 SA198 10111111xxx 64/32 BF0000-FFFFFF 5F8000-5FFFFF 57 SA199 11000000xxx 64/32 C00000-0FFFFF 600000-607FFF 57 SA200 11000001xxx 64/32 C10000-1FFFFF 608000-60FFFF 57 SA201 11000010xxx 64/32 C20000-2FFFFF 610000-617FFF 57 SA202 11000011xxx 64/32 C30000-3FFFFF 618000-61FFFF

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Sector Sector Sector Address Sector Size (x8) (x16) Group A22-A12 (Kbytes/Kwords) Address Range Address Range

58 SA203 11000100xxx 64/32 C40000-4FFFFF 620000-627FFF 58 SA204 11000101xxx 64/32 C50000-5FFFFF 628000-62FFFF 58 SA205 11000110xxx 64/32 C60000-6FFFFF 630000-637FFF 58 SA206 11000111xxx 64/32 C70000-7FFFFF 638000-63FFFF 59 SA207 11001000xxx 64/32 C80000-8FFFFF 640000-647FFF 59 SA208 11001001xxx 64/32 C90000-9FFFFF 648000-64FFFF 59 SA209 11001010xxx 64/32 CA0000-AFFFFF 650000-657FFF 59 SA210 11001011xxx 64/32 CB0000-BFFFFF 658000-65FFFF 60 SA211 11001100xxx 64/32 CC0000-CFFFFF 660000-667FFF 60 SA212 11001101xxx 64/32 CD0000-DFFFFF 668000-66FFFF 60 SA213 11001110xxx 64/32 CE0000-EFFFFF 670000-677FFF 60 SA214 11001111xxx 64/32 CF0000-FFFFFF 678000-67FFFF 61 SA215 11010000xxx 64/32 D00000-0FFFFF 680000-687FFF 61 SA216 11010001xxx 64/32 D10000-1FFFFF 688000-68FFFF 61 SA217 11010010xxx 64/32 D20000-2FFFFF 690000-697FFF 61 SA218 11010011xxx 64/32 D30000-3FFFFF 698000-69FFFF 62 SA219 11010100xxx 64/32 D40000-4FFFFF 6A0000-6A7FFF 62 SA220 11010101xxx 64/32 D50000-5FFFFF 6A8000-6AFFFF 62 SA221 11010110xxx 64/32 D60000-6FFFFF 6B0000-6B7FFF 62 SA222 11010111xxx 64/32 D70000-7FFFFF 6B8000-6BFFFF 63 SA223 11011000xxx 64/32 D80000-8FFFFF 6C0000-6C7FFF 63 SA224 11011001xxx 64/32 D90000-9FFFFF 6C8000-6CFFFF 63 SA225 11011010xxx 64/32 DA0000-AFFFFF 6D0000-6D7FFF 63 SA226 11011011xxx 64/32 DB0000-BFFFFF 6D8000- 6DFFFF 64 SA227 11011100xxx 64/32 DC0000-CFFFFF 6E0000-6E7FFF 64 SA228 11011101xxx 64/32 DD0000-DFFFFF 6E8000-6EFFFF 64 SA229 11011110xxx 64/32 DE0000-EFFFFF 6F0000-6F7FFF 64 SA230 11011111xxx 64/32 DF0000-FFFFFF 6F8000-6FFFFF 65 SA231 11100000xxx 64/32 E00000-0FFFFF 700000-707FFF 65 SA232 11100001xxx 64/32 E10000-1FFFFF 708000-70FFFF 65 SA233 11100010xxx 64/32 E20000-2FFFFF 710000-717FFF 65 SA234 11100011xxx 64/32 E30000-3FFFFF 718000-71FFFF 66 SA235 11100100xxx 64/32 E40000-4FFFFF 720000-727FFF 66 SA236 11100101xxx 64/32 E50000-5FFFFF 728000-72FFFF 66 SA237 11100110xxx 64/32 E60000-6FFFFF 730000-737FFF 66 SA238 11100111xxx 64/32 E70000-7FFFFF 738000-73FFFF 67 SA239 11101000xxx 64/32 E80000-8FFFFF 740000-747FFF 67 SA240 11101001xxx 64/32 E90000-9FFFFF 748000-74FFFF 67 SA241 11101010xxx 64/32 EA0000-AFFFFF 750000-757FFF 67 SA242 11101011xxx 64/32 EB0000-BFFFFF 758000-75FFFF

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Sector Sector Sector Address Sector Size (x8) (x16) Group A22-A12 (Kbytes/Kwords) Address Range Address Range

68 SA243 11101100xxx 64/32 EC0000-CFFFFF 760000-767FFF 68 SA244 11101101xxx 64/32 ED0000-DFFFFF 768000-76FFFF 68 SA245 11101110xxx 64/32 EE0000-EFFFFF 770000-777FFF 68 SA246 11101111xxx 64/32 EF0000-FFFFFF 778000-77FFFF 69 SA247 11110000xxx 64/32 F00000-0FFFFFF 780000-787FFF 69 SA248 11110001xxx 64/32 F10000-1FFFFF 788000-78FFFF 69 SA249 11110010xxx 64/32 F20000-2FFFFF 790000-797FFF 69 SA250 11110011xxx 64/32 F30000-3FFFFF 798000-79FFFF 70 SA251 11110100xxx 64/32 F40000-4FFFFF 7A0000-7A7FFF 70 SA252 11110101xxx 64/32 F50000-5FFFFF 7A8000-7AFFFF 70 SA253 11110110xxx 64/32 F60000-6FFFFF 7B0000-7B7FFF 70 SA254 11110111xxx 64/32 F70000-7FFFFF 7B8000-7BFFFF 71 SA255 11111000xxx 64/32 F80000-8FFFFF 7C0000-7C7FFF 71 SA256 11111001xxx 64/32 F90000-9FFFFF 7C 800 0- 7CFFFF 71 SA257 11111010xxx 64/32 FA0000-AFFFFF 7D0000-7D7FFF 71 SA258 11111011xxx 64/32 FB0000-BFFFFF 7D8000- 7DFFFF 72 SA259 11111100xxx 64/32 FC0000-CFFFFF 7E0000-7E7FFF 72 SA260 11111101xxx 64/32 FD0000-DFFFFF 7E8000-7EFFFF 72 SA261 11111110xxx 64/32 FE0000-EFFFFF 7F0000-7F7FFF 72 SA262 11111111xxx 64/32 FF0000-FF1FFF 7F8000-7F8FFF

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Table 1. BUS OPERATION (1)

Q8~Q15

Operation CE# OE# W E # RE- WP# ACC Address Q0~Q7 Word Byte

SET# Mode Mode

Read L L H H X X A

OUT

Q8-Q14=

High Z

Q15=A-1

Write (Program/Erase) L H L H (Note 3) X A

(No te 4) (Note 4 Q8-Q14=

High Z

Q15=A-1

Accelerated Program L H L H (Note 3) V

(No t e 4 ) (No t e 4 ) Q8-Q14=

High Z

Q15=A-1

Standby VC C ± X X VCC± X H X High-Z High-Z High-Z

0.3V 0.3V Output Disable L H H H X X X High-Z High-Z High-Z Reset X X X L X X X High-Z High-Z High-Z Sector Group Protect L H L V

H X Sector Addresses, (Note 4) X X

(Note 2) A6=L,A3=L, A2=L,

A1=H,A0=L

Chip unprotect L H L V

H X Sector Addresses, (Note 4) X X

(Note 2) A6=H, A3=L, A2=L,

A1=H, A0=L

Temporary Sector X X X V

HX AIN(Note 4) (Note 4) High-Z

Group Unprotect

Legend: L=Logic LOW=VIL, H=Logic High=VIH, VID=12.0±0.5V, VHH=12.0±0.5V, X=Don't Care, AIN=Address IN, DIN=Data IN,

=Data OUT

OUT

No tes:

1. Address are A21:A0 in word mo de; A21:A-1 in byte mo de . Secto r addresses are A21:A15 in bo th mo des. 2 . The sector gro up pro tect and chip unpro tect functio ns may also be implemented via pro gramming equipment. See

the "Sector Gro up Pro tectio n and Chip Unpro tect" section.

3. If WP#=VIL, all the secto rs remain protected. If WP#=VIH, all sectors pro tectio n depends o n whether they were last protected o r unpro tect using the method described in "Secto r/ Secto r Bloc k Protectio n and Unpro tect".

4. DIN or D

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as required by co mmand sequence, Data# po lling or secto r pro tect algo rithm (see Figure 15).

OUT

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Table 2. AUTOSELECT CODES (High Voltage Method)

A22 A14 A8 A5 A3 Q8 to Q15

Description CE# OE# WE# to to A9 to A6 to to A1 A0 Word Byte Q7 t o Q 0

A15 A10 A7 A4 A2 Mode Mode

Manufacturer ID L L H X X VID X L X L L L 00 X C2h

Cycle 1 L L H 2 2 X 7Eh Cycle 2 L L H X X VID X L X H H L 22 X 1 1h Cycle 3 H H H 22 X 00h (bottom boot)

29LA128MT/B

Sector Group 01h (protected), Protection L L H SA X VID X L X L H L X X Verification 00h (unprotected) Secured Silicon 98h Sector Indicator (factory locked), Bit (Q7), WP# L L H X X VID X L X L H H X X protects top two 18h

01h (top boot)

address sector (not factory locked) Secured Silicon 88h Sector Indicator (factory locked), Bit (Q7), WP# pro- L L H X X VID X L X L H H X X tects botto m tw o 08h address sector (not factory locked)

Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care.

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REQUIREMENTS FOR READING ARRAY DATA

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the o utput pins . WE# should remain at VIH.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard micropro cesso r read cycles that assert valid address on the device address inputs produce valid data on the device data outputs . The de vice remains enabled fo r read access until the command register contents are altered.

PAGE MODE READ

The MX29LA128M T/B o ffers "f ast page mode read" function. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 words/8 bytes. The appropriate page is selected by the higher address bits A0~A1(Wo rd Mo de)/A1~A1(Byte Mode) This is an asynchro nous o peratio n; the microprocessor supplies the specific word location.

The system perfo rmance could be enhanced by initiating 1 normal read and 3 fast page read (for word mode A0A1) or 7 fast page read (for byte mode A-1~A1). When CE# is deasserted and reasserted fo r a subsequent access, the access time is tACC or tCE. Fast page mode accesses are obtained by keeping the "read-page addresses" constant and changing the "intra-read page" addresses.

WRITING COMMANDS/COMMAND SEQUENCES

T o pro gram data to the device o r erase secto rs of memo ry , the system must drive WE# and CE# to VIL, and OE# to VIH.

An erase operation can erase one sector, multiple sectors, or the entire device. Table indicates the address space that each sector occupies. A "sector address"

consists o f the address bits required to uniquely select a sector . The Writing specific address and data commands or sequences into the co mmand register initiates de vice operations. Table 1 defines the valid register command sequences. Writing inco rrect address and data values o r writing them in the improper sequence resets the device to reading array data. Section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

After the system writes the Automatic Select command sequence, the device enters the Automatic Select mode. The system can then read Automatic Select codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the Automatic Select Mode and Automatic Select Command Sequence section for more information.

ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations.

WRITE BUFFER

Write Buffer Programming allows the system to write a maximum of 16 words/32 bytes in one programming operatio n. This results in faster eff ective pro gramming time than the standard programming algorithms. See "Write Buffer" for more information.

ACCELERATED PROGRAM OPERATION

The device offers accelerated program operations through the ACC function. This is one of two functions provided by the ACC pin. This function is primarily intended to allow faster manuf acturing throughput at the f actory .

If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required fo r pro gram oper ations . Remo ving VHH from the ACC pin must not be at VHH for operations o ther than accelerated programming, or device damage may result.

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STANDBY MODE

When using both pins o f CE# and RESET#, the de vice enter CMOS Standby with bo th pins held at VCC ± 0.3V . If CE# and RESET# are held at VIH, but not within the range o f VCC ± 0.3V , the device will still be in the standby mode, b ut the standby current will be larger. During Auto Algorithm o peration, VCC active current (ICC2) is required even CE# = "H" until the operation is completed. The device can be read with standard access time (tCE) from either of these standby modes, before it is ready to read data.

AUTOMATIC SLEEP MODE

The automatic sleep mode minimizes Flash device energy consumptio n. The de vice auto matically enables this mode when address remain stab le for tA CC+30ns . The automatic sleep mo de is independent of the CE#, WE#, and OE# control signals. Standard address access timings pro vide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification.

OUTPUT DISABLE

With the OE# input at a logic high level (VIH), output from the de vices are disabled. This will cause the output pins to be in a high impedance state.

RESET# OPERATION

but not within VSS±0.3V, the standby current will be greater.

The RESET# pin may be tied to system reset circuitry. A system reset would that also reset the Flash memo ry , enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operatio n, the R Y/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algo rithms). The system can thus monito r RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is completed within a time of tREAD Y (not during Embedded Algo rithms). The system can read data tRH after the RESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# parameters and to Figure 3 for the timing diagram.

SECTOR GROUP PROTECT OPERATION

The MX29LA128M T/B f eatures hardw are secto r g roup protection. This feature will disable both program and erase operations for these sector group protected. In this device, a sector group consists of four adjacent sectors which are protected or unprotected at the same time. T o activ ate this mode, the pro gramming equipment must fo rce VID o n address pin A9 and contro l pin OE#, (suggest VID = 12V) A6 = VIL and CE# = VIL. (see Tab le 2) Programming of the protection circuitry begins on the falling edge of the WE# pulse and is terminated on the rising edge. Please refer to sector group protect algorithm and waveform.

The RESET# pin provides a hardware method of resetting the device to reading arra y data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The o peratio n that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity

Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL

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MX29LA128M T/B also pro vides ano ther metho d. Which requires VID on the RESET# only. This method can be implemented either in-system or via programming equipment. This method uses standard microprocessor bus cycle timing.

T o v erify programming o f the pro tection circuitry , the programming equipment must fo rce VID o n address pin A9 ( with CE# and OE# at VIL and WE# at VIH). When A1=1, it will produce a logical "1" code at device output Q0 fo r a pro tected sector . Otherwise the device will produce 00H for the unprotected sector. In this mode, the addresses, except for A1, are don't care. Address locations with A1 = VIL are reserved to read manufacturer and device codes. (Read Silicon ID)

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MX29LA128M T/B

It is also possib le to determine if the gro up is protected in the system by writing a Read Silicon ID command. Perf o rming a read operatio n with A1=VIH, it will produce a logical "1" at Q0 for the protected sector.

CHIP UNPROTECT OPERATION

The MX29LA128M T/B also f eatures the chip unpro tect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotect mode.

T o activ ate this mode , the programming equipment m ust force VID on control pin OE# and address pin A9. The CE# pins must be set at VIL. Pins A6 must be set to VIH. (see Table 2) Refer to chip unprotect algo rithm and wavef o rm for the chip unpro tect algo rithm. The unprotect mechanism begins on the f alling edge o f the WE# pulse and is terminated on the rising edge.

It is also possible to determine if the chip is unprotect in the system by writing the Read Silicon ID command. Perf orming a read o peratio n with A1=VIH, it will pro duce 00H at data outputs (Q0-Q7) f o r an unpro tect sector . It is noted that all sectors are unprotected after the chip unprotect algorithm is completed.

WRITE PROTECT (WP#)

last protected o r unpro tect using the method described in "Sector/Secto r Gro up Pro tection and Chip Unpro tect".

Note that the WP# pin must no t be left flo ating o r unco nnected; inconsistent behavior of the device may result.

TEMPORARY SECTOR GROUP UNPROTECT OPERATION

This feature allows temporary unprotect of previously protected secto r to change data in-system. The Temporary Sector Unprotect mode is activated by setting the RESET# pin to VID(11.5V -12.5V). During this mo de, fo rmerly protected sectors can be programmed or erased as unprotect sector. Once VID is remove from the RESET# pin, all the previously protected sectors are protected again.

SILICON ID READ OPERATION

Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high vo ltage. Howe ver , m ultiplexing high v o ltage onto address lines is not generally desired system design practice.

MX29LA128M T/B pro vides hardware metho d to access the silicon ID read o peratio n. Which metho d requires VID on A9 pin, VIL on CE#, OE#, A6, and A1 pins. Which apply VIL o n A0 pin, the de vice will output MXIC's manufacture co de of which apply VIH o n A0 pin, the device will output MX29LA128M T/B de vice cod e.

The write protect function provides a hardware method to protect all sectors witho ut using VID.

If the system asserts VIL on the WP# pin, the device disables pro gram and erase functio ns in all sectors independently of whether those sectors were protected or unprotect using the method described in Sector/Sector Group Pro tectio n and Chip Unpro tect".

If the system asserts VIH on the WP# pin, the device reverts to whether the sectors were last set to be protected or unprotect. That is, sector protection or unprotectio n fo r the secto rs depends on whether they w ere

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VERIFY SECTOR GROUP PROTECT STATUS OPERATION

MX29LA128M T/B pro vides hardware metho d f or secto r group protect status verify. Which method requires VID on A9 pin, VIH on WE# and A1 pins, VIL on CE#, OE#, A6, and A0 pins, and secto r address on A16 to A21 pins. Which the identified sector is protected, the device will output 01H. Which the identified sector is no t pro tect, the device will o utput 00H.

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DATA PROTECTION

The MX29LA128M T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorpo rates sev eral features to prev ent inadvertent write cycles resulting from VCC power-up and pow er-down transition or system noise.

SECURED SILICON SECTOR

The MX29LA128M T/B features a OTP memory region where the system may access through a command sequence to create a permanent par t identification as so called Electronic Serial Number (ESN) in the device. Once this region is programmed, any further modificatio n on the regio n is impo ssible. The secured silicon sector is a 128 words in length, and uses a Secured Silicon Sector Indicator Bit (Q7) to indicate whether or not the Secured Silicon Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevent duplication of a factory locked part. This ensures the security of the ESN once the product is shipped to the field.

The MX29LA128M T/B offers the device with Secured Silicon Sector either factory locked or customer lockable. The f actory-lo cked versio n is alwa ys protected when shipped from the factory , and has the Secured Silicon Sector Indicator Bit permanently set to a "1". The customer-lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to utilize that sector in any form they prefer. The customer-lockable version has the secured sector Indicator Bit permanently set to a "0". Theref ore, the Secured Silico n Sector Indicator Bit pre v ents custo mer, lo ckab le device from being used to replace devices that are factory locked.

The system access the Secured Silicon Sector through a command sequence (refer to "Enter Secured Silicon/ Exit Secured Silicon Secto r co mmand Sequence). After the system has written the Enter Secured Silicon Secto r command sequence, it may read the Secured Silicon Sector by using the address normally occupied by the first sector SA0. Once entry the Secured Silicon Secto r the operatio n o f boo t secto rs is disabled but the o peratio n

of main sectors is as normally. This mode of operation continues until the system issues the Exit Secured Silicon Secto r co mmand sequence, o r until power is remo ved from the device. On power-up, or following a hardware reset, the device rev erts to sending co mmand to secto r SA0.

Secured Silicon ESN factory Customer Sector address locked lockable range

000000h-000007h ESN Determined by 000008h-00007Fh Unavailable Customer

FACTORY LOCKED:Secured Silicon Sector Programmed and Protected At the Factory

In device with an ESN, the Secured Silicon Sector is protected when the device is shipped from the factory. The Secured Silicon Sector cannot be modified in any way. A f actory lo cked de vice has an 8-wo rd rando m ESN at address 000000h-000007h.

CUSTOMER LOCKABLE:Secured Silicon Sector NOT Programmed or Protected At the Factory

As an alternative to the factory-locked version, the device may be ordered such that the customer may program and protect the 128-word Secured Silicon Sector. Programming and protecting the Secured Silicon Sector must be used with caution since, once protected, there is no procedure available for unprotected the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way.

The Secured Silicon Sector area can be protected using one of the following procedures:

Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 15, except that RESET# may be at either VIH or VID . This allo ws insystem protection of the Secured Silicon Sector without raising any device pin to a high voltage. Note that method is only applicab le to the Secured Silico n Secto r.

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MX29LA128M T/B

Write the three-cycle Enter Secured Silicon Secto r Regio n co mmand sequence, and then alternate method of secto r protectio n described in the :Secto r Group Pro tectio n and Unprotect" section.

Once the Secured Silicon Sector is programmed, locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing the remainder of the arra y .

LOW VCC WRITE INHIBIT

When VCC is less than VLKO the device does not accept any write cycles. This protects data during VCC power-up and power-do wn. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are igno red until VCC is greater than VLKO . The system must pro vide the proper signals to the control pins to prevent unintentional write when VCC is greater than VLK O.

WRITE PULSE "GLITCH" PROTECTION

POWER SUPPLY DE COUPLING

In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND .

Noise pulses of less than 5ns (typical) on CE# or WE# will not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE# = VIL, CE# = VIH o r WE# = VIH. T o initiate a write cycle CE# and WE# must be a logical zero while OE# is a logical one.

POWER-UP SEQUENCE

The MX29LA128M T/B pow ers up in the Read only mo de. In addition, the memory contents may only be altered after successful completion of the predefined command sequences.

POWER-UP WRITE INHIBIT

If WE#=CE#=VIL and OE#=VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.

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SOFTWARE COMMAND DEFINITIONS

Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Either of the two

Device operations are selected by writing specific address and data sequences into the command register.

reset command sequences will reset the device (when applicable).

Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mod e. Table 3 defines the valid register command sequences. Note that the Erase Suspend (B0H) and

All addresses are latched on the f alling edge of WE# or CE#, whichever happens later. All data are latched on rising edge of WE# o r CE#, whichev er happens first.

TABLE 3. MX29LA128M T/B COMMAND DEFINITIONS

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycles Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read (Note 5) 1 RA R D Reset (Note 6) 1 XXX F0 Automatic Select (Note 7) Manufacturer ID Word 4 555 AA 2AA 55 555 90 X00 C2H

Byte 4 AAA AA 555 55 AAA 90 X00 C2H Device ID Word 4 555 AA 2AA 55 555 90 X01 ID1 X0E ID2 X0F ID3 (Note 8) Byte 4 AAA AA 555 55 AAA 90 X02 ID1 X1C ID2 X1E ID3 Secured Sector Fact- Word 4 555 AA 2AA 55 555 90 X03 see ory Protect (Note 9) Byte 4 AAA AA 555 55 AAA 90 X06 note 9 Sector Group Protect Word 4 555 AA 2AA 55 555 90 (SA)X02 XX00/ Verify (Note 10) Byte 4 AAA AA 555 55 AAA 90 (SA)X04 XX01 Enter Secured Silicon Word 3 55 5 AA 2AA 55 5 55 8 8 Sector Byte 3 AAA AA 555 55 AAA 88 Exit Secured Silicon Word 4 5 55 AA 2AA 5 5 55 5 90 XXX 0 0 Sector Byte 4 AAA AA 55 5 55 AAA 90 XXX 00 Program Word 4 555 AA 2AA 55 555 A0 PA PD

Byte 4 AAA AA 555 55 AAA A0 PA PD Write to Buffer (Note 11) Word 6 555 AA 2AA 55 SA 25 SA WC PA PD WBL PD

Byte 6 AAA AA 555 55 SA 25 SA BC PA PD WBL PD Program Buffer to Flash Word 1 SA 2 9

Byte 1 SA 29 Write to Buffer Abort Word 3 555 AA 2AA 55 555 F0 Reset (Note 12) Byte 3 AAA AA 55 5 55 AAA F0 Chip Erase Word 6 555 AA 2AA 55 55 5 80 55 5 AA 2 AA 5 5 555 1 0

Byte 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Sector Erase Word 6 55 5 AA 2 AA 55 55 5 8 0 55 5 AA 2AA 55 SA 30

Byte 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30

Program/Erase Suspend (Note 13) 1 XXX B0 Program/Erase Resume (Note 14) 1 XXX 30

CFI Query (Note 15) Word 1 55 9 8

Byte 1 A A 98

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Legend: X=Don't care RA=Address of the memory location to be read. RD=Data read from location RA during read operation. PA=Address o f the memo ry lo catio n to be pro grammed. Addresses are latched on the f alling edge o f the WE# or CE# pulse, whichever happen later . DDI=Data of device identifier C2H for manufacture code

Notes:

1. See Table 1 f o r descriptions o f b us oper ations .

2. All values are in hexadecimal.

3. Except when reading array or auto matic select data, all bus cycles are write o peratio n.

4. Address bits are do n't care f or unloc k and co mmand cycles , e xcept when PA or SA is required.

5. No unlo ck o r co mmand cycles required when de vice is in read mo de.

6. The Reset co mmand is required to return to the read mo de when the device is in the auto matic select mo de o r if Q5 goes high.

7. The fourth cycle of the auto matic select command sequence is a read cycle.

8. The device ID m ust be read in three cycles. The data is 01h fo r top bo o t and 00h f or bottom bo o t.

9. If WP# protects the top two address sectors, the data is 98h for factory locked and 18h for not factory locked. If WP# protects the botto m two address sectors, the data is 88h for facto ry lo c k ed and 08h f or not f actor lo c ked.

10. The data is 00h for an unprotected secto r/secto r blo c k and 01h fo r a pro tected secto r/sector blo c k.

11. The total number o f cycles in the co mmand sequence is determined by the n umber o f words written to the write buffer . The maximum number o f cycles in the co mmand sequence is 21(W ord Mo de) / 37(Byte Mo de).

12 . Command sequence resets device f or ne xt command after abo rted write-to-buffer o peration.

13. The system may read and prog ram functions in no n-erasing secto rs, o r enter the auto matic select mo de, when in the erase Suspend mo de. The Erase Suspend co mmand is v alid only during a secto r erase o peratio n.

14. The Erase Resume command is valid only during the Erase Suspend mod e.

15. Command is valid when de vice is ready to read arr ay data or when device is in automatic select mo de.

PD=Data to be programmed at location PA. Data is latched on the rising edge o f WE# o r CE# pulse . SA=Address of the sector to be erase or verified (in autoselect mode). Address bits A21-A12 uniquely select any secto r . WBL=Write Buffer Location. Address must be within the same write buffer page as PA. WC=Word Count. Number of write buffer locations to load minus 1. BC=Byte Count. Number of write buffer locations to load minus 1.

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READING ARRAY DATA

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Automatic Program or Automatic Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See Erase Suspend/Erase Resume Commands for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if Q5 goes high, or while in the automatic select mode. See the "Reset Command" section, next.

RESET COMMAND

array data (also applies during Erase Suspend).

SILICON ID READ COMMAND SEQUENCE

The SILICON ID READ command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. T ab le 2 shows the address and data requirements. This method is an alternative to that shown in Table 1, which is intended for PROM programmers and requires VID on address bit A9.

The SILICON ID READ command sequence is initiated by writing two unlock cycles, followed by the SILICON ID READ command. The device then enters the SILICON ID READ mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h returns 01h if that sector is protected, or 00h if it is unprotected. Refer to T a ble fo r valid sector addresses.

Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command.

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once er asure begins, howe ver , the device igno res reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an SILICON ID READ command sequence. Once in the SILICON ID READ mode, the reset command must be written to return to reading array data (also applies to SILICON ID READ during Erase Suspend).

The system must write the reset command to exit the automatic select mode and return to reading array data.

BYTE/WORD PROGRAM COMMAND SEQUENCE

The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the pro gram set-up co mmand. The pro gram address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the progr ammed cell margin. Tab le 3 shows the address and data requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the pro g ram o peratio n b y using Q7, Q6, or R Y/ BY#. See "Write Operation Status" for information on these status bits.

If Q5 goes high during a program or erase operation, writing the reset command returns the device to reading

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Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hard-

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ware reset immediately terminates the programming o peration. The Byte/Word Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity.

Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set Q5 to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1".

Write Buffer Programming

Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster eff ective pro gramming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unloc k cycles. This is f ollowed b y a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will program 6 unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Pro gram Buff er to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort.

The fifth cycle writes the first address location and data to be progr ammed. The write-buff er-page is selected by address bits A must fall within the selected-write-buffer-page . The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any o rder.

The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming canno t be performed across m ultiple write-buffer pages. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abo rt.

Note that if a Write Buffer address location is loaded

-4. All subsequent address/data pairs

MAX

multiple times, the address/data pair counter will be decremented fo r ev ery data load oper ation. The host system must therefore account for loading a write-buffer location mo re than o nce. The co unter decrements f or each data load operation, not for each unique write-buffer-address location. Note also that if an address location is loaded mo re than o nce into the buffer , the final data loaded for that address will be programmed.

Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address locatio n lo aded into the write buff er. Q7, Q6, Q5, and Q1 should be monitored to determine the device status during Write Buff er Pro gramming.

The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Upon successful co mpletio n of the Write Buffer Pro gramming operation, the device is ready to execute the next command.

The Write Buffer Pro gramming Sequence can be abo rted in the following ways:

• Load a value that is greater than the page buffer size during the Number of Locations to Program step.

• Write to an address in a sector different than the one specified during the Write-Buffer-Lo ad co mmand.

• Write an Address/Data pair to a different write-bufferpage than the one selected b y the Starting Address during the write buffer data loading stage of the operation.

• Write data other than the Confirm Command after the specified number of data load cycles.

The abort condition is indicated by Q1 = 1, Q7 = D ATA# (for the last address location loaded), Q6 = toggle, and Q5=0. A Write-to-Buffer-Abo rt Reset command sequence must be written to reset the device for the next operation. No te that the full 3-cycle Write-to-Buffer-Abo rt Reset command sequence is required when using WriteBuffer-Programming features in Unlock Bypass mode.

Program Suspend/Program Resume Command Sequence

The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer

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prog ramming operatio n so that data can be read fro m any non-suspended secto r . When the Prog ram Suspend command is written during a programming process, the device halts the program operation within 15us maximum (5 us typical) and updates the status bits. Addresses are not required when writing the Program Suspend command.

After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area (One-time Prog ram area), then user must use the proper command sequences to enter and e xit this regio n.

The system may also write the autoselect command sequence when the device is in the Program Suspend mode. The system can read as many autoselect codes as required. When the device e xits the auto select mod e, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information.

After the Program Resume command is written, the device reverts to pro gramming. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. See Write Operatio n Status f or more inf ormation.

AUTOMATIC CHIP/SECTOR ERASE COMMAND

The device does not require the system to preprogram prior to erase. The A uto matic Er ase algo rithm automatically pre-program and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 3 shows the address and data requirements for the chip erase command sequence.

Any commands written to the chip during the Automatic Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operatio n. The Chip Erase co mmand sequence sho uld be reinitiated once the device has returned to reading array data, to ensure data integrity.

The system can determine the status of the erase operatio n by using Q7, Q6, Q2, o r RY/BY#. See "Write Operation Status" f or inf ormatio n o n these status bits. When the Automatic Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched.

Figure 10 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to Figure 9 for timing diagrams.

SETUP AUTOMATIC CHIP/SECTOR ERASE

Chip erase is a six-bus cycle operation. There are two "unloc k" write cycles. These are f ollowed by writing the "set-up" command 80H. T w o more "unlo ck" write cycles are then followed by the chip erase command 10H, or the sector erase command 30H.

The MX29LA128M T/B contains a Silicon-ID-Read operation to supplement traditional PROM programming methodo lo gy . The o peratio n is initiated by writing the read silicon ID command sequence into the command register. Following the command write, a read cycle with A1=VIL,A0=VIL retrieves the manuf acturer co de. A read cycle with A1=VIL, A0=VIH returns the device cod e.

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SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system is no t required to provide an y control or timing during these operations.

When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mod e. The system is no t required to provide any control or timing during these operations.

When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle o peratio n. There are two "unlo ck" write cycles. These are followed by writing the set-up command 80H. Tw o mo re "unlo ck" write cycles are then f o llowed by the sector erase command 30H. The sector address is latched on the falling edge of WE# or CE#, whichever happens later , while the command (data) is latched on the rising edge of WE# or CE#, whichever happens first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE# or CE#, whichever happens later . Each successiv e secto r load cycle started by the falling edge of WE# or CE#, whichever happens later must begin within 50us from the rising edge of the preceding WE# or CE#, whiche ver happens first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Secto r Erase Timer.) Any co mmand o ther than Sector Erase(30H) or Erase Suspend(B0H) during the time-out period resets the device to read mode.

device requires a maximum 20us to suspend the sector erase operatio n. Howev er, When the Erase Suspend co mmand is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode auto matically after suspend is ready. At this time, state machine only allows the command register to respond to the Erase Resume, program data to, or read data from any sector not selected for erasure.

The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend program operation is complete, the system can once again read array data within non-suspended blocks.

ERASE RESUME

This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the chip has resumed erasing.

ERASE SUSPEND

This command only has meaning while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Er ase operatio n. When the Er ase Suspend command is issued during the sector erase operation, the

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QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE

The single cycle Query command is valid only when the device is in the Read mode, including Erase Suspend, Standby mo de, and Read ID mo de; how ever , it is igno red

MX29LA128M T/B is capab le of o perating in the CFI mode.

otherwise.

This mode all the host system to determine the manufacturer of the device such as operating parameters and configuratio n. T wo co mmands are required in CFI mo de. Query command of CFI mode is placed first, then the Reset command e xits CFI mo de. These are described in

The Reset command exits from the CFI mode to the Read mode, or Erase Suspend mode, or read ID mode. The command is valid only when the device is in the CFI mode.

T able 4.

Table 4-1. CFI mode: Identification Data Values

(All values in these tables are in hexadecimal)

Description Address h Address h Data h

(x16) (x8)

Query-unique ASCII string "QRY" 1 0 20 0051

11 22 0052 12 24 0059

Primary vendor command set and control interface ID code 1 3 2 6 0002

14 28 0000

Address for primary algorithm extended query table 1 5 2 A 0040

16 2C 0000

Alternate vendor command set and control interface ID code (none) 17 2E 0000

18 30 0000

Address for secondary algorithm extended query table (none) 1 9 32 0000

1A 34 0000

Table 4-2. CFI Mode: System Interface Data Values

Description Address h Address h Data h

(x16) (x8)

VCC supply, minimum (2.7V) 1B 36 0027 VCC supply, maximum (3.6V) 1 C 38 0036 VPP supply, minimum (none) 1 D 3 A 0000 VPP supply, maximum (none) 1E 3C 0000 Typical timeout for single word/byte write (2N us) 1F 3E 0007 Typical timeout for maximum size buffer write (2N us) 20 40 0007 Typical timeout for individual block erase (2N ms) 21 42 000A Typical timeout for full chip erase (2N ms) 22 44 0000 Maximum timeout for single word/byte write times (2 Maximum timeout for maximum size buffer write times (2 Maximum timeout for individual block erase times (2 Maximum timeout for full chip erase times (not supported) 2 6 4C 0000

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X Typ) 23 4 6 0001

X Typ) 2 4 48 0005

X Typ) 25 4A 0004

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Table 4-3. CFI Mode: Device Geometry Data Values

Description Address h Address h Data h

(x16) (x8)

Device size (2n bytes) 2 7 4E 0018 Flash device interface code 2 8 5 0 0002

29 52 0000

Maximum number of bytes in multi-byte write =2

2A 54 0005

2B 56 0000 Number of erase block regions (X=# of Erase Block Regions) 2C 5 8 0002 Erase block region 1 information 2 D 5A 0007 [2E,2D] = # of blocks in region -1 2E 5C 0000 [30, 2F] = size in multiples of 256-bytes 2F 5E 0020

30 60 0000 31 6 2 00FE

Erase Block Region 2 Information (refer to CFI publication 100) 32 6 4 0000

33 66 0000 34 68 0001 35 6A 0000

Erase Block Region 3 Information (refer to CFI publication 100) 36 6C 0000

37 6E 0000 38 70 0000 39 72 0000

Erase Block Region 4 Information (refer to CFI publication 100) 3A 7 4 0000

3B 76 0000

3C 78 0000

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Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values

Description Address h Address h Data h

(x16) (x8)

Query-unique ASCII string "PRI" 4 0 8 0 0050

41 82 0052

42 84 0049 Major version number, ASCII 4 3 8 6 0031 Minor version number, ASCII 4 4 8 8 0033 Address sensitive unlock (0=required, 1= not required) 4 5 8A 0000 Erase suspend (2= to read and write) 4 6 8C 0002 Sector protect (N= # of sectors/group) 4 7 8E 0001 Temporary sector unprotect (1=supported) 48 90 0001 Sector protect/unprotect scheme 4 9 92 0004 Simultaneous R/W operation (0=not supported) 4A 94 0000 Burst mode type (0=not supported) 4B 9 6 0000 Page mode type (1=4 word page) 4 C 98 0001 ACC (Acceleration) Supply Minimum 4 D 9A 00B5 00h=Not Supported, D7-D4: Volt, D3-D0:100mV ACC (Acceleration) Supply Maximum 4E 9 C 00C5 00h=Not Supported, D7-D4: Volt, D3-D0:100mV Top/Bottom Boot Sector Flag 4F 9E 0002/ 02h=Bottom Boot Device, 03h=Top Boot Device 0003 04h=uniform sectors bottom WP# protect, 05h=uniform sectors top WP# protect Program Suspend 50 A0 0001 00h=Not Supported, 01h=Supported

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WRITE OPERATION STATUS

The device provides several bits to determine the status of a write operation: Q2, Q3, Q5, Q6, Q7, and R Y/BY#. T ab le 5 and the fo llowing subsectio ns describe the functions of these bits. Q7, RY/BY#, and Q6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first.

Table 5. Write Operation Status

Status Q7 Q6 Q5 Q3 Q2 Q1 RY/BY#

Byte/Word Program in Auto Program Algorithm Q7 # To ggle 0 N/A No 0 0

To ggle

Auto Erase Algorithm 0 T o ggle 0 1 T oggle N/A 0

Erase Suspend Read 1 No 0 N/A T o ggle N/A 1 Erase (Erase Suspended Sector) T o ggle Suspended Erase Suspend Read Data Data Data Data Data Data 1 Mode (Non-Erase Suspended Sector)

Erase Suspend Program Q7 # T o ggle 0 N/A N/A N/A 0

Program-Suspended Read Invalid (not allowed) 1 Program (Program-Suspended Sector) Suspend Program-Suspended Read Data 1

(Non-Program-Suspended Sector) Write-to-Buffer Busy Q7# Toggle 0 N/A N/A 0 0

Abort Q7# Toggle 0 N/A N/A 1 0

Notes:

1. Q5 s witches to "1" when an W ord/Byte Pro gram, Erase , o r Write-to-Buffer operation has e xceeded the maximum timing limits. Refer to the section on Q5 for more information.

2. Q7 and Q2 require a v alid address when reading status info rmation. Ref er to the appro priate subsection fo r further details.

3. The Data# Polling algo rithm sho uld be used to mo nitor the last lo aded write-buff er address lo cation.

4. Q1 switches to "1" when the device has abo rted the write-to-buffer operation.

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Q7: Data# Polling

The Data# Polling bit, Q7, indicates to the host system whether an Automatic Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Po lling is valid after the rising edge o f the final WE# pulse in the program or erase command sequence.

During the Automatic Program algorithm, the device outputs on Q7 the complement of the datum programmed to Q7. This Q7 status also applies to prog ramming during Erase Suspend. When the A uto matic Pro gram algorithm is complete, the device outputs the datum programmed to Q7. The system must provide the prog r am address to read valid status information on Q7. If a program address falls within a pro tected secto r , Data# Po lling on Q7 is active for approximately 1 us, then the device returns to reading array data.

During the Auto matic Erase algorithm, Data# P olling produces a "0" o n Q7. When the Auto matic Erase algo rithm is complete, or if the device enters the Erase Suspend mode, Data# P o lling pro duces a "1" on Q7. This is analogous to the complement/true datum output described for the Automatic Program algorithm: the erase function changes all the bits in a sector to "1" prior to this, the device o utputs the "complement," o r "0". The system must pro vide an address within any o f the sectors selected f or erasure to read valid status info rmatio n o n Q7.

After an erase command sequence is written, if all sectors selected f o r erasing are pro tected, Data# P o lling o n Q7 is active for approximately 100 us, then the device returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.

happens first pulse in the command sequence (prior to the program or erase operation), and during the sector time-out.

During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE# or CE# to contro l the read cycles. When the o peratio n is co mplete, Q6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles for 100us and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.

The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase suspended. When the device is actively erasing (that is, the Automatic Erase algorithm is in pro gress), Q6 to ggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system m ust also use Q2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7.

If a program address falls within a protected sector , Q6 toggles for approximately 2us after the program command sequence is written, then returns to reading array data.

Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete.

Table 5 shows the outputs for Toggle Bit I on Q6.

When the system detects Q7 has changed from the complement to true data, it can read valid data at Q7-Q0 on the following read cycles. This is because Q7 may change asynchronously with Q0-Q6 while Output Enable (OE#) is asserted low.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# o r CE#, whiche ver

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Q2:Toggle Bit II

The "To ggle Bit II" o n Q2, when used with Q6, indicates whether a particular sector is actively erasing (that is, the Automatic Erase algorithm is in process), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# o r CE#, whiche ver happens first pulse in the command sequence.

Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by com-

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parison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure . Thus , both status bits are required for sectors and mode information. Refer to Table 5 to compare o utputs f or Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is to ggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program o r erase o peration. The system can read array data on Q7-Q0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previo us paragraph. Alternatively , it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation.

Q5:Program/Erase Timing

Q5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditio ns Q5 will pro duce a "1". This time-o ut co nditio n indicates that the program or erase cycle was not successfully completed. Data# Polling and Toggle Bit are the only operating functions of the device under this condition.

If this time-out conditio n occurs during sector erase operation, it specifies that a particular secto r is bad and it may no t be reused. Ho wev er, o ther secto rs are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute pro gram o r erase co mmand sequence. This allows the system to continue to use the other active sectors in the device.

If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad.

If this time-out condition occurs during the byte/word programming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused).

The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Automatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used.

The Q5 failure condition may appear if the system tries to program a to a "1" location that is previously programmed to "0". Only an erase operation can change a "0" back to a "1". Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, Q5 produces a "1".

Q3:Sector Erase Timer

After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-o ut is co mplete. Data# P o lling and Toggle Bit are valid after the initial secto r erase co mmand sequence.

If Data# Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is co mpleted as indicated b y Data# Po lling or

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T o ggle Bit. If Q3 is low ("0"), the de vice will accept additional sector erase co mmands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted.

If the time between additional erase commands from the system can be less than 50us, the system need not to monitor Q3.

Q1: Write-to-Buffer Abort

Q1 indicates whether a Write-to-Buffer operation was aborted. Under these conditio ns Q1 pro duces a "1". The system must issue the Write-to-Buffer-Abo rt-Reset command sequence to return the device to reading array data. See Write Buffer section for more details.

MX29LA128M T/B

RY/BY#:READY/BUSY OUTPUT

The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the co mmand sequence. Since RY/BY# is an open-drain o utput, se v eral RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC .

If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode.

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ABSOLUTE MAXIMUM RATINGS

Storage T emperature

Plastic Packages . . . . . . . . . . . . . .....-65oC to +150oC

Ambient T emperature

with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC

V o ltage with Respect to Gro und

VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V

A9, OE#, and

RESET# (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V

All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V

Output Short Circuit Current (No te 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input o r I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20ns .

2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During vo ltage transitio ns, A9, OE#, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin A9 is +12.5 V which ma y oversho o t to 14.0 V f o r periods up to 20 ns.

3. No mo re than o ne o utput may be sho rted to ground at a time. Duration of the short circuit should not be greater than one second.

OPERATING RATINGS

Commercial (C) Devices

Ambient Temperature (T

Industrial (I) Devices

Ambient Temperature (T

VCC

Supply Voltages

VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V

Operating ranges define those limits between which the functionality of the device is guaranteed.

A ) . . . . . . . . . . . . 0°C to +70°C

A ) . . . . . . . . . . -40°C to +85°C

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

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DC CHARACTERISTICS TA=-40

Parameter Description Test Conditions Min. Typ. Max. Unit

I LI Input Load Current (Note 1) VIN = VSS to VCC , ±1.0 uA

I LIT A9 Input Leakage Current VCC=VCC max; A9 = 12.5V 35 uA I LO Output Leakage Current V OUT = VSS to VCC , ±1.0 uA

ICC1 VCC Initial Read Current CE# = VIL, 10 MHz 35 5 0 mA

(No tes 2,3) OE# = VIH 5 MHz 18 2 5 mA

ICC2 VCC Intra-Page Read CE# = VIL , 10 MHz 5 20 mA

Current (Notes 2,3) OE# = VIH 40 MHz 10 40 mA

ICC3 VCC Active Write Current CE# = VIL , OE# = VIH 50 60 mA

(Notes 2,4,6)

ICC4 VCC Standby Current CE#, RESET# = VCC ± 0.3V 20 50 uA

(No te 2) WP# = VIH

ICC5 VCC Reset Current RESET# = VSS ± 0.3V 20 50 uA

(No te 2) WP# = VIH

ICC6 Automatic Sleep Mode VIL = VSS ± 0.3 V, 20 50 uA

(No tes 2,5) VIH = VCC ± 0.3 V,

VIL Input Low V o ltage -0.5 0.8 V VIH Input High V o ltage 0.7xVCC VCC+0.5 V VHH Vo ltage for ACC Progr a m VCC = 2.7V ~ 3.6V 11.5 12.0 12.5 V

Acceleration

VID Vo ltage f o r A utoselect and VCC = 3.0 V ± 10% 11.5 12.0 12.5 V

T empo rary Sector Unpro tect V OL Output Low Vo ltage IOL= 4.0mA,VCC=VCC min 0.45 V V OH1 Output High V oltage IOH=-2.0mA,VCC=VCC min 0.85VCC V VO H2 IOH=-100uA,VCC=VCC min VCC-0.4 V VLK O Low VCC Lock-Out V oltage 2.3 2.5 V

(Note 4)

°°

°C to 85

°°

VCC = VCC max

WP# = VIH

°°

°C, VCC=2.7V~3.6V (VCC=3.0V~3.6V for 90R)

°°

1 MHz 5 20 mA

Notes:

1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0uA.

2. Maxim um ICC specifications are tested with VCC = VCC max.

3. The ICC current listed is typically is less than 2 mA/MHz, with OE# at VIH. Typical specifications are for VCC =

3.0V. 4 . ICC active while Embedded Erase or Embedded Program is in progress. 5 . Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 30 ns. 6 . No t 100% tested. 7 . A9=12.5V when T A=0°C to 85°C, A9=12V when when T A=-40°C to 0°C.

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

SWITCHING TEST CIRCUITS

TEST SPECIFICATIONS

T est Co ndition All Speeds Unit Output Load 1 TTL gate

DEVICE UNDER

TEST

2.7K ohm

3.3V

Output Load Capacitance, CL 30 pF (including jig capacitance) Input Rise and Fall Times 5 ns

6.2K ohm

DIODES=IN3064 OR EQUIVALENT

Input Pulse Levels 0.0-3.0 V Input timing measurement 1. 5 V reference levels Output timing measurement 1.5 V reference levels

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Don't Care, An y Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State(High Z)

SWITCHING TEST WAVEFORMS

3.0V

0.0V INPUT

Steady

Changing from H to L

Changing from L to H

1.5V 1.5V

Measurement Level

OUTPUT

P/N:PM1170

REV. 0.04, JUL. 11, 2005

AC CHARACTERISTICS

MX29LA128M T/B

Read-Only Operations TA=-40

Parameter Speed Options Std. Description Test Setup 90R 10 0 Unit

tR C Read Cycle Time (No te 1) Min 90 100 ns tACC Address to Output Delay CE#, OE#=VIL Max 90 100 ns tCE Chip Enable to Output Delay OE#=VIL Max 9 0 100 ns tPA C C Page Access Time Max 25 2 5 ns tOE Output Enable to Output Delay Max 35 3 5 ns tDF Chip Enable to Output High Z (Note 1) Ma x 1 6 ns tDF Output Enable to Output High Z (Note 1) Max 16 ns tOH Output Ho ld Time Fro m Address, CE# Min 0 n s

or OE#, whiche v er Occurs First

tOEH Output Enable Ho ld Time T o ggle and Min 10 ns

(No te 1) Data# Po lling

Notes:

1. Not 100% tested.

2. See SWITCHING TEST CIRCUITS and TEST SPECIFICATIONS TABLE for test specifications .

°°

°C to 85

°°

Read Min 35 ns

°°

°C, VCC=2.7V~3.6V (VCC=3.0V~3.6V for 90R)

°°

P/N:PM1170

REV. 0.04, JUL. 11, 2005

Figure 1. READ TIMING WAVEFORMS

VIH

Addresses

CE#

WE#

VIL

VIH

VIL

VIH

VIL

tRH

tOEH

MX29LA128M T/B

tRC

ADD Valid

tCE

tOE

tDF

OE#

Outputs

VIH

VIL

HIGH Z HIGH Z

VOH

VOL

VIH

RESET#

VIL

RY/BY#

Figure 2. PAGE READ TIMING WAVEFORMS

A2-A21

tACC

Same Page

tOH

DATA V alid

P/N:PM1170

(A-1), A0~A2

CE#

OE#

Output

tACC

tPACC

Qa Qb Qc Qd

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

AC CHARACTERISTICS

Parameter Description T est Setup All Speed OptionsUnit

tREAD Y1 RESET# PIN Low (During Automatic Algorithms) MAX 2 0 us

to Read or Write (See Note)

tREADY2 RESET# PIN Low (NO T During Auto matic Algo rithms) MAX 50 0 ns

to Read or Write (See Note) tRP RESET# Pulse Width (NOT During Auto matic Algo rithms) MIN 500 ns tR H RESET# High Time Befo re Read (See Note) MIN 50 ns tRB RY/BY# Reco very Time(to CE#, OE# go lo w) MIN 0 ns tRPD RESET# Low to Standby Mode MIN 20 us

Note:Not 100% tested

Figure 3. RESET# TIMING WAVEFORM

RY/BY#

CE#, OE#

RESET#

RY/BY#

CE#, OE#

tRH

tRP

tReady2

Reset Timing NOT during Automatic Algorithms

tReady1

tRB

RESET#

P/N:PM1170

tRP

Reset Timing during Automatic Algorithms

REV. 0.04, JUL. 11, 2005

AC CHARACTERISTICS

MX29LA128M T/B

Erase and Program Operations TA=-40

Parameter Speed Options Std. Description 90 R 100 Unit

tW C Write Cycle Time (No te 1) Min 90 10 0 ns tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during to ggle bit po lling Min 15 ns tAH Address Hold Time Min 45 ns tAHT Address Hold Time Fro m CE# o r OE# high during toggle Min 0 ns

bit polling tDS Data Setup Time Min 35 ns tDH Data Hold Time Min 0 ns tCEPH CE# High During T o ggle Bit P o lling Min 20 ns tOEPH Output Enable High during toggle bit po lling Min 20 ns tGHWL Read Recovery Time Bef ore Write Min 0 ns

(OE# High to WE# Low) tGHEL Read Recovery Time Befo re Write Min 0 ns tCS CE# Setup Time Min 0 ns tCH CE# Hold Time Min 0 ns tWP Write Pulse Width Min 35 ns tWPH Write Pulse Width High Min 30 ns

Write Buffer Pro gram Operatio n (No tes 2,3) T y p 240 us

Single Wo rd/Byte Pro gram Byte Typ 60 us tWHWH1 Operation (Notes 2,5) W o r d T yp 60 us

Accelerated Single Wo rd/Byte Byte Typ 54 us

Prog ramming Operation (No tes 2,5) Wo r d T yp 54 us tWHWH2 Sector Erase Operation (No te 2) T y p 0 .5 sec tVCS VCC Setup Time (No te 1) Min 50 us tRB Write Reco very Time from R Y/BY# Min 0 ns tBUSY Program/Er ase V alid to R Y/BY# Delay Min 90 10 0 ns tVHH VHH Rise and Fall Time (No te 1) Min 250 ns tPOLL Program V alid Befo re Status Po lling (No te 6) Max 4 us

°°

°C to 85

°°

°C, VCC=2.7V~3.6V (VCC=3.0V~3.6V for 90R)

°°

Notes:

1. Not 100% tested.

2. See the "Erase And Programming P erf ormance" section f or more inf ormation.

3. For 1-16 words/1-32 bytes programmed.

4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.

5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer .

6. When using the pro gram suspend/resume feature, if the suspend co mmand is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming.

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

ERASE/PROGRAM OPERATION

Figure 4. AUTOMATIC PROGRAM TIMING WAVEFORMS

tWC

tAS

Read Status Data (last two cycle)Program Command Sequence(last two cycle)

Address

CE#

OE#

WE#

Data

RY/BY#

tVCS

XXXh

tCH

tWP

tCS tWPH

tDS tDH

A0h

tAH

tBUSY

PA PA

tWHWH1

Status

DOUT

tRB

VCC

Note :

1.PA=Program Address, PD=Program Data, DOUT is the true data the program address

Figure 5. ACCELERATED PROGRAM TIMING DIAGRAM

VHH

ACC

VIL or VIH

tVHH

P/N:PM1170

VIL or VIH

tVHH

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Figure 6. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

Increment Address

Verify Word Ok ?

Last Address ?

Auto Program Completed

Data Poll from system

YES

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Figure 7. WRITE BUFFER PROGRAMMING ALGORITHM FLOWCHART

Write "Write to Buffer"

command and

Sector Address

Q1 = 1 ?

Yes

(Note 1)

Write number of addresses

to program minus 1(WC)

and Sector Address

Write first address/data

WC = 0 ?

Abort Write to

Buffer Operation ?

Write next address/data pair

WC = WC - 1

Write program buffer

to flash sector address

Read Q7~Q0 at Last

Loaded Address

Q7 = Data ?

Q5 = 1 ?

Yes

Read Q7~Q0 with address

= Last Loaded Address

Part of "Write to Buffer"

Command Sequence

Yes

Write to a different

sector address

Write to buffer ABORTED.

Must write "Write-to-buffer

Abort Reset" command sequence

to return to read mode.

Notes:

1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page.

2. Q7 may change simultaneously with Q5. Therefore, Q7 should be verified.

3. If this flowchart location was reached because Q5= "1" then the device FAILED. If this flowchart location was reached because Q1="1", then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin another operation. If Q1=1, write the Write-Buffer-Programming-Abort-Reset command. If Q5=1, write the Reset command.

4. See Table 3 for command sequences required for write buffer programming.

P/N:PM1170

(Note 2)

(Note 3)

Q7 and Q15 = Data ?

FAIL or ABORT PASS

Yes

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Program Operation

or Write-to-Buffer

Sequence in Progress

Write address/data

XXXh/B0h

Write Program Suspend Command Sequence Command is also valid for Erase-suspended-program operations

Autoselect and Secured Sector read operations are also allowed Data cannot be read from erase-or program-suspended sectors

Write Program Resume Command Sequence

Read data as

required

Write address/data

XXXh/30h

Device reverts to operation prior to Program Suspend

Wait 15us

Done reading ?

Yes

Figure 8. PROGRAM SUSPEND/RESUME FLOWCHART

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Figure 9. AUTOMATIC CHIP/SECTOR ERASE TIMING WAVEFORM

Read Status Data Erase Command Sequence(last two cycle)

tWC

tAS

Address

CE#

OE#

WE#

Data

RY/BY#

tVCS

2AAh

555h for chip erase

tCH

tWP

tCS tWPH

tDS tDH

55h

tAH

30h

10 for Chip Erase

tBUSY

VA VA

tWHWH2

Progress

Complete

tRB

P/N:PM1170

VCC

Note :

1.SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Figure 10. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 10H Address 555H

Data Poll from system

DATA = FFh ?

Auto Erase Completed

YES

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Figure 11. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

Last Sector

to Erase ?

YES

Data Poll from System

Data=FFh?

YES

Auto Sector Erase Completed

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Figure 12. ERASE SUSPEND/RESUME FLOWCHART

START

Write Data B0H

Toggle Bit checking Q6

not toggled

YES

Read Array or

Program

Reading or

Programming End

YES

Write Data 30H

Continue Erase

Another

Erase Suspend ?

YES

ERASE SUSPEND

ERASE RESUME

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations TA=-40

°°

°C to 85

°°

Parameter Speed Options Std. Description 90 R 100 Unit

tW C Write Cycle Time (No te 1) Min 90 100 ns tAS Address Setup Time Min 0 n s tAH Address Hold Time Min 45 ns tDS Data Setup Time Min 35 ns tD H Data Hold Time M in 0 ns tGHE L Read Recov ery Time Befo re Write Min 0 ns

tWS WE# Setup Time Min 0 ns tW H WE# Hold Time Min 0 ns tCP CE# Pulse Width Min 35 ns tCPH CE# Pulse Width High Min 25 ns

tWHWH1 Operation (No tes 2,5) W o rd T y p 60 us

tWHWH2 Sector Erase Operation (No te 2) T y p 0 .5 sec tR H RESET HIGH Time Before Write (Note 1) Min 50 ns tPOLL Pro gram Valid Before Status Polling (Note 6) Max 4 us

°°

°C, VCC=2.7V~3.6V (VCC=3.0V~3.6V for 90R)

°°

(OE# High to WE# Low)

Write Buffer Pro gram Operatio n (No tes 2,3) T y p 240 us Single Wo rd/Byte Pro gram Byte Typ 60 us

Accelerated Single W ord/Byte Byte Typ 54 us Prog ramming Operation (No tes 2,5) W o rd T yp 54 us

Notes:

1. Not 100% tested.

2. See the "Erase And Programming P erf ormance" section f or mo re inf ormation.

3. For 1-16 words/1-32 bytes programmed.

4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.

5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer .

6 . When using the program suspend/resume f eature, if the suspend co mmand is issued within tPOLL, tPOLL must be

fully re-applied upon resuming the pro gramming o peratio n. If the suspend command is issued after tPOLL, tPOLL is not required again prio r to reading the status bits upo n resuming.

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Figure 13. CE# CONTROLLED PROGRAM TIMING WAVEFORM

Address

WE#

OE#

CE#

Data

555 for program 2AA for erase

tWC

tWH

tGHEL

tWS

tRH

PA for program SA for sector erase 555 for chip erase

tCP

tDS

tDH

tAS

tAH

tCPH

A0 for program 55 for erase

Data# Polling

tBUSY

PD for program 30 for sector erase 10 for chip erase

tWHWH1 or 2

DOUT

RESET#

RY/BY#

NOTES:

1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device.

2.Figure indicates the last two bus cycles of the command sequence.

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

SECTOR GROUP PROTECT/CHIP UNPROTECT

Figure 14. Sector Group Protect / Chip Unprotect Waveform (RESET# Control)

VID

RESET#

VIH

SA, A6

A1, A0

Data

CE#

WE#

OE#

Valid*

Sector Group Protect or Chip Unprotect

1us

Sector Group Protect:150us

Chip Unprotect:15ms

Valid* Valid*

Verify

40h60h60h

Note: For sector group protect A6=0, A1=1, A0=0. For chip unprotect A6=1, A1=1, A0=0

Status

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Figure 15. IN-SYSTEM SECTOR GROUP PROTECT/CHIP UNPROTECT ALGORITHMS WITH

RESET#=VID

Temporary Sector

Unprotect Mode

Increment PLSCNT

PLSCNT=25?

Device failed

Sector Protect

Algorithm

START

PLSCNT=1

RESET#=VID

Wait 1us

First Write

Cycle=60h?

Yes

Set up sector address

Sector Protect:

Write 60h to sector

address with

A6=0, A1=1, A0=0

Wait 150us

Verify Sector Protect:

Write 40h to sector

address with

A6=0, A1=1, A0=0

Read from

sector address

with

A6=0, A1=1, A0=0

Data=01h?

YesYes

Protect another

sector?

Remove VID from RESET#

Write reset command

Yes

Reset

PLSCNT=1

Protect all sectors:

The indicated portion of

the sector protect algorithm

must be performed

for all unprotected sectors

prior to issuing the first

sector unprotect address

Increment PLSCNT

PLSCNT=1000?

Yes

Device failed

START

PLSCNT=1

RESET#=VID

Wait 1us

First Write

Cycle=60h?

Yes

All sectors protected?

Yes

Set up first sector address

Sector Unprotect:

Write 60h to sector

address with

A6=1, A1=1, A0=0

Wait 15 ms

Verify Sector Unprotect:

Write 40h to sector

address with

A6=1, A1=1, A0=0

Read from

sector address

with

A6=1, A1=1, A0=0

Data=00h?

Yes

Last sector

verified?

Temporary Sector

PLSCNT=1

Unprotect Mode

Reset

P/N:PM1170

Sector Protect complete

Chip Unprotect

Algorithm

Yes

Remove VID from RESET#

Write reset command

Sector Unprotect complete

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

AC CHARACTERISTICS

Parameter Description Test Setup All Speed Options Unit

tVLHT V oltage transition time Min. 4 us tWPP1 Write pulse width for sector group protect Min. 100 ns tOESP OE# setup time to WE# active Min. 4 us

Figure 16. SECTOR GROUP PROTECT TIMING WAVEFORM (A9, OE# Control)

12V

OE#

WE#

CE#

Data

A21-A16

tVLHT

Verify

tVLHT

tWPP 1

tOESP

01H F0H

tOE

Sector Address

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Figure 17. SECTOR GROUP PROTECTION ALGORITHM (A9, OE# Control)

START

Set Up Sector Addr

PLSCNT=1

OE#=VID, A9=VID, CE#=VIL

A6=VIL

Activate WE# Pulse

Time Out 150us

PLSCNT=32?

Yes

Device Failed

Set WE#=VIH, CE#=OE#=VIL

A9 should remain VID

Read from Sector

Addr=SA, A1=1

Protect Another

Remove VID from A9

Write Reset Command

Sector Protection

Data=01H?

Yes

Sector?

Complete

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Figure 18. CHIP UNPROTECT TIMING WAVEFORM (A9, OE# Control)

12V

tVLHT

12V

OE#

tVLHT

tWPP 2

tVLHT

Verify

WE#

CE#

Data

tOESP

tOE

00H

F0H

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Figure 19. CHIP UNPROTECT FLOWCHART (A9, OE# Control)

START

Protect All Sectors

PLSCNT=1

Set OE#=A9=VID

CE#=VIL, A6=1

Activate WE# Pulse

Increment

Sector Addr

Set OE#=CE#=VIL

Set Up First Sector Addr

Read Data from Device

Remove VID from A9

Write Reset Command

Time Out 15ms

A9=VID, A1=1

Data=00H?

Yes

All sectors have

been verified?

Yes

Increment

PLSCNT

PLSCNT=1000?

Yes

Device Failed

P/N:PM1170

Chip Unprotect

Complete

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

AC CHARACTERISTICS

Parameter Description T e s t All Speed Options Unit

Setup

tVIDR VID Rise and Fall Time (see No te) M in 500 ns tRSP RESET# Setup Time fo r T emporary Sector Unprotect Min 4 us tRRB RESET# Hold Time from R Y/BY# High fo r Temporary Mi n 4 us

Sector Group Unprotect

Figure 20. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORMS

12V

RESET#

0 or 3V

VIL or VIH

CE#

WE#

RY/BY#

tVIDR

Program or Erase Command Sequence

tRSP

tRRB

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Figure 21. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART

Start

RESET# = VID (Note 1)

Perform Erase or Program Operation

Operation Completed

RESET# = VIH

Temporary Sector Unprotect Completed(Note 2)

Notes :

1. All protected sectors are temporary unprotected. VID=11.5V~12.5V

2. All previously protected sectors are protected again.

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Figure 22. SECURED SILICON SECTOR PROTECTED ALGORITHMS FLOWCHART

START

Enter Secured Silicon Sector

Wait 1us

First Wait Cycle Data=60h

Second Wait Cycle Data=60h

A6=0, A1=1, A0=0

Wait 300us

Secured Sector Protect Complete

Data = 01h ?

Write Reset CommandDevice Failed

Yes

P/N:PM1170

REV. 0.04, JUL. 11, 2005

Figure 23. SILICON ID READ TIMING WAVEFORM

MX29LA128M T/B

VCC

ADD

CE#

WE#

OE#

DATA

Q0-Q15

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VID

VIH

VIL

tACC

tCE

tOE

DATA OUT DATA OUT DATA OUT

Manufacturer ID Device ID

tACC

tOH

tACC tACC

tOH tOH

Cycle 1

Device ID

Cycle 2

tDF

tOH

DATA OUT

Device ID

Cycle 3

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

WRITE OPERATION STATUS

Figure 24. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)

tRC

Address

tACC

tCE

VAVAVA

CE#

tCH

tOE

OE#

tOEH

tDF

WE#

tOH

Q0-Q6

Status Data

tBUSY

Complement

Status Data

True Valid Data

Valid DataTrue

RY/BY#

Note :

VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data raed cycle.

High Z

P/N:PM1170

REV. 0.04, JUL. 11, 2005

Figure 25. DATA# POLLING ALGORITHM

MX29LA128M T/B

Start

Read Q7~Q0

Add.=VA(1)

Yes

(2)

Pass

Q7 = Data ?

Q5 = 1 ?

Yes

Read Q7~Q0

Add.=VA

Q7 = Data ?

FAIL

Notes:

1.V A=valid address f o r pro gramming.

2.Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

Figure 26. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)

tRC

Address

CE#

OE#

WE#

Q6/Q2

RY/BY#

tCH

tOEH

tDH

Valid Status

tACC

tCE

tOE

tDF

tOH

Valid Status (first read)

Valid Status

(second read) (stops toggling)

Valid Data

P/N:PM1170

Note :

VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle.

REV. 0.04, JUL. 11, 2005

Figure 27. TOGGLE BIT ALGORITHM

MX29LA128M T/B

START

Read Q7~Q0

Toggle Bit Q6

=Toggle?

Program/Erase Operation Not

Complete, Write Reset Command

Q5=1?

Read Q7~Q0 Twice

Toggle Bit Q6=

Toggle?

(Note 1)

YES

(Note 1,2)

YES

Program/Erase Operation Complete

Notes :

1. Read toggle bit twice to determine whether or not it is toggling.

2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".

P/N:PM1170

REV. 0.04, JUL. 11, 2005

Figure 28. Q6 versus Q2

MX29LA128M T/B

WE#

Enter Embedded

Erasing

Erase

Suspend

Erase Suspend

Read

Enter Erase

Suspend Program

Erase Suspend Program

Erase Suspend

Read

Erase

Resume

Erase

Note :

The system can use OE# or CE# to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended

Erase

Complete

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

ERASE AND PROGRAMMING PERFORMANCE (1)

PARAMETER Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.5 2 sec Excludes 00h

programming

Chip Erase Time 12 8 256 sec prior to erasure

Note 6 Total Write Buffer Program Time (Note 4) 24 0 us Excludes Total Accelerated Effective Write Buffer 200 us system level Program Time (Note 4) overhead Chip Program Time 12 6 sec Note 7

Notes:

1. T ypical pro gram and er ase times assume the following co nditions: 25°C, 3.0V VCC. Pro gramming specificatio ns assume checkboard data pattern.

2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles.

3 . Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the

write buffer .

4 . For 1-16 words or 1-32 bytes programmed in a single write buffer programming operation.

5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation.

6 . In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 7 . System-level overhead is the time required to execute the command sequence(s) for the program command. See

T ables 3 f o r further informatio n on co mmand definitio ns.

8 . The device has a minimum erase and program cycle endurance of 100,000 cycles.

LATCH-UP CHARACTERISTICS

MIN. MAX.

Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V Input Voltage with respect to GND on all I/O pins -1.0V VCC + 1.0V Current -100mA +100mA Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

DATA RETENTION

Parameter Min Unit

Minimum Pattern Data Retention Time 20 Years

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MX29LA128M T/B

TSOP PIN AND BGA PACKAGE CAPACITANCE

Parameter Symbol Parameter Description Test Set TYP MAX UNIT

CIN Input Capacitance VIN=0 TSOP 6 7.5 pF

CSP 4.2 5.0 pF

COUT Output Capacitance VOUT=0 TSOP 8.5 12 pF

CSP 5.4 6.5 pF

CIN2 Control Pin Capacitance VIN=0 TSOP 7.5 9 pF

CSP 3.9 4.7 pF

Notes:

1. Sampled, not 100% tested.

2. Test co nditions T A=25°C, f=1.0MHz

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MX29LA128M T/B

ORDERING INFORMATION

PLASTIC P ACKA GE

PART NO. ACCESS TIME PACKAGE Remark

(ns)

MX29LA128MTTC-90R 90 56 Pin TSOP

(Normal Type)

MX29LA128MTTC-10 100 56 Pin TSOP

(Normal Type)

MX29LA128MBTC-90R 90 56 Pin TSOP

(Normal Type)

MX29LA128MBTC-10 100 56 Pin TSOP

(Normal Type)

MX29LA128MTTI-90R 90 56 Pin TSOP

(Normal Type)

MX29LA128MTTI-10 100 56 Pin TSOP

(Normal Type)

MX29LA128MBTI-90R 90 56 Pin TSOP

(Normal Type)

MX29LA128MBTI-10 100 56 Pin TSOP

(Normal Type)

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PACKAGE INFORMATION

MX29LA128M T/B

P/N:PM1170

REV. 0.04, JUL. 11, 2005

MX29LA128M T/B

REVISION HISTORY

Revision No. Description Page Date

0.01 1. Revised 90 ns as 90R ns, and added 100 ns option P1,40,42, DEC/29/2004 P45,54

2. Removed PB free order information P73

0.02 1. Changed standby current from 1uA to 20uA P1 APR/21/2005

0.03 1. To modify WP# protect function P1,19,23 JUN/10/2005

0.04 1. Changed title from "Advanced Information" to "Preliminary" P1 JUL/11/2005

2. To add note 7 for ILIT parameter in DC Characteristics table P40

3. To add comments into performance table P71

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MX29LA128M T/B

MACRONIX INTERNATIONAL CO., LTD .

Headquarters:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

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MACRONIX AMERICA, INC.

TEL:+1-408-262-8887

FAX:+1-408-262-8810

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

Datasheet MX29LA128MT-B Datasheet (MXIC)

Specifications and Main Features

Frequently Asked Questions

User Manual