MXIC MX29L1611MC-10, MX29L1611MC-12, MX29L1611MC-75, MX29L1611MC-90, MX29L1611TC-10 Datasheet

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FEATURES

PRELIMINARY

MX29L1611

16M-BIT [2M x 8/1M x 16] CMOS

SINGLE VOLTAGE PAGEMODE FLASH EEPROM

• Regulated voltage range 3.0 to 3.6V write, erase and read(MX29L1611-75/10/12)

• Fast random access/page mode access time: 75/ 30ns, 100/30ns, 120/30ns.

• Full voltage range 2.7 to 3.6V write, erase and read (MX29L1611-90)

• Fast random access/page mode access time: 90/ 35ns

• Endurance: 10,000 cycles

• Page access depth: 16 bytes/8 words, page address A0, A1, A2

• Sector erase architecture

- 32 equal sectors of 64k bytes each

- Sector erase time: 200ms typical

• Auto Erase and Auto Program Algorithms

- Automatically erases any one of the sectors or the whole chip with Erase Suspend capability

GENERAL DESCRIPTION

The MX29L1611 is a 16-mega bit pagemode Flash memory organized as either 1M wordx16 or 2M bytex8. The MX29L1611 includes 32 sectors of 64KB(65,536 Bytes or 32,768 words). MXIC's Flash memories offer the most cost-effective and reliable read/write nonvolatile random access memory and fast page mode access. The MX29L1611 is packaged 44-pin SOP and 48-TSOP(I). It is designed to be reprogrammed and erased in-system or in-standard EPROM programmers.

The standard MX29L1611 offers access times as fast as 100ns,allowing operation of high-speed microprocessors without wait. To eliminate bus contention, the MX29L1611 has separate chip enable CE, output enable (OE), and write enable (WE) controls.

MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29L1611 uses a command register to manage this functionality.

- Automatically programs and verifies data at specified addresses

• Status Register feature for detection of program or erase cycle completion

• Low VCC write inhibit < 1.8V

• Software and hardware data protection

• Page program operation

- Internal address and data latches for 128 bytes/64 words per page

- Page programming time: 5ms typical

• Low power dissipation

- 50mA active current

- 20uA standby current

• Two independently Protected sectors

• Industry standard surface mount packaging

- 44 lead SOP, 48 TSOP(I)

To allow for simple in-system reprogrammability, the MX29L1611 does not require high input voltages for programming. Three-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM.

MXIC Flash technology reliably stores memory contents even after 10,000 cycles. The MXIC's cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29L1611 uses a 2.7V~3.6V VCC supply to perform the Auto Erase and Auto Program algorithms.

The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC +1V.

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PIN CONFIGURATIONS

44 SOP(500mil)

A18

A17

GND

OE Q0 Q8 Q1 Q9 Q2

Q10

Q11

48 TSOP (NORMAL TYPE)

14 15 16 17 18 19 20 21 22

MX29L1611

PIN DESCRIPTION

SYMBOL PIN NAME

A19

A10

A11

A12

A13

A14

A15

A16

BYTE

GND

Q15/A-1

Q14

Q13

Q12

VCC

A0 - A19 Address Input Q0 - Q14 Data Input/Output Q15/A-1 Q15(Word mode)/LSB addr.(Byte

mode) CE Chip Enable Input OE Output Enable Input WE Write Enable Input WP* Sector Write Protect Input BYTE Word/Byte Selection Input VCC Power Supply GND Ground Pin

*Only for 44-SOP

BYTE

A16 A15 A14 A13 A12 A11 A10

A9 A8

A19

GND

WE A18 A17

A7 A6 A5 A4 A3 A2 A1 A0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

MX29L1611

(Normal T ype)

GND

Q15/A-1

Q14

Q13

Q12

VCC

Q11

Q10

GND

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BLOCK DIAGRAM

BYTE

CONTROL

INPUT LOGIC

PROGRAM/ERASE

HIGH VOLT A GE

MX29L1611

WRITE

STATE

MACHINE

(WSM)

Q15/A-1 A0-A19

ADDRESS

LA TCH

AND

BUFFER

X-DECODER

MX29L1611

FLASH ARRA Y

Y-DECODER

Y-PASS GATE

SENSE

AMPLIFIER

Y-select

COMMAND INTERF ACE REGISTER (CIR)

ARRAY

SOURCE

COMMAND

DATA DECODER

PGM

DATA

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

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Q0-Q15/A-1

I/O BUFFER

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Table1.PIN DESCRIPTIONS

SYMBOL TYPE NAME AND FUNCTION

A0 - A19 INPUT ADDRESS INPUTS: for memory addresses. Addresses are internally

latched during a write cycle.

Q0 - Q7 INPUT/OUTPUT LOW-BYTE DATA BUS: Input data and commands during Command Interface

Register(CIR) write cycles. Outputs array,status and identifier data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled.

Q8 - Q14 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations.

Outputs array, identifier data in the appropriate read mode; not used for status register reads. Floated when the chip is de-selected or the outputs are disabled

Q15/A -1 INPUT/OUTPUT Selects between high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB

ADDRESS(BYTE = LOW)

CE INPUT CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers,

decoders and sense amplifiers. With CE high, the device is deselected and power consumption reduces to Standby level upon completion of any current program or erase operations. CE must be low to select the device.

OE INPUT OUTPUT ENABLES: Gates the device's data through the output buffers

during a read cycle OE is active low.

WE INPUT WRITE ENABLE: Controls writes to the Command Interface Register(CIR).

WE is active low.

WP INPUT WRITE PROTECT: Top or Bottom sector can be protected by writing a non-

volatile protect-bit for each sector. When WP is high, all sectors can be programmed or erased regardless of the state of the protect-bits.

BYTE INPUT BYTE ENABLE: BYTE Low places device in x8 mode. All data is then input

or output on Q0-7 and Q8-14 float. AddressQ15/A-1 selects between the high and low byte. BYTE high places the device in x16 mode, and turns off the Q15/ A-1 input buffer. Address A0, then becomes the lowest order address.

VCC DEVICE POWER SUPPLY(3.0V~3.6V for MX29L1611-75/10/12 ; 2.7V~3.6V

for MX29L1611-90)

GND GROUND

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BUS OPERATION

Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.

Table 2.1 Bus Operations for Word-Wide Mode (BYTE = VIH)

Mode Notes CE OE WE A0 A1 A9 Q0-Q7 Q8-Q14 Q15/A-1

Read 1 VIL VIL VIH X X X DOUT DOUT DOUT Output Disable 1 VIL VIH VIH X X X High Z High Z HighZ Standby 1 VIH X X X X X High Z HIgh Z HighZ Manufacturer ID 2,4 VIL VIL VIH VIL VIL VID C2H 00H 0B Device ID 2,4 VIL VIL VIH VIH VIL VID F8H 00H 0B Write 1,3 VIL VIH VIL X X X DIN DIN DIN

Table2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL)

Mode Notes CE OE WE A0 A1 A9 Q0-Q7 Q8-Q14 Q15/A-1

Read 1 VIL VIL VIH X X X DOUT HighZ VIL/VIH Output Disable 1 VIL VIH VIH X X X High Z High Z X Standby 1 VIH X X X X X High Z HIgh Z X Manufacturer ID 2,4 VIL VIL VIH VIL VIL VID C2H High Z VIL Device ID 2,4 VIL VIL VIH VIH VIL VID F8H High Z VIL Write 1,3 VIL VIH VIL X X X DIN High Z VIL/VIH

NOTES :

1. X can be VIH or VIL for address or control pins.

2. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes. A0 at VIL, A1 at VIH and with appropriate sector addresses provide Sector Protect Code.(Refer to Table 4)

3. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully completed through proper command sequence.

4. VID = 11.5V- 12.5V.

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WRITE OPERATIONS

MX29L1611

Commands are written to the COMMAND INTERFACE REGISTER (CIR) using standard microprocessor write timings. The CIR serves as the interface between the microprocessor and the internal chip operation. The CIR can decipher Read Array, Read Silicon ID, Erase and Program command. In the event of a read command, the CIR simply points the read path at either the array or

CIR will only respond to status reads. During a sector/ chip erase cycle, the CIR will respond to status reads and erase suspend. After the write state machine has completed its task, it will allow the CIR to respond to its full command set. The CIR stays at read status register mode until the microprocessor issues another valid command sequence.

the silicon ID, depending on the specific read command given. For a program or erase cycle, the CIR informs the write state machine that a program or erase has been requested. During a program cycle, the write state

Device operations are selected by writing commands into the CIR. Table 3 below defines 16 Mbit flash family command.

machine will control the program sequences and the

TABLE 3. COMMAND DEFINITIONS

Command Read/ Silicon Page/Byte Chip Sector Erase Erase Read Clear Sequence Reset ID Read Program Erase Erase Suspend Resume Status Reg. Status Reg. Bus Write 4 4 4 6 6 3 3 4 3 Cycles Req'd First Bus Addr 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H Write Cycle Data AAH AAH AAH AAH AAH AAH AAH AAH AAH Second Bus Addr 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Write Cycle Data 55H 55H 55H 55H 55H 55H 55H 55H 55H Third Bus Addr 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H Write Cycle Data F0H 90H A0H 80H 80H B0H D0H 70H 50H Fourth Bus Addr RA 00H/01H PA 5555H 5555H X Read/Write Cycle Data RD C2H/F8H PD AAH A AH SRD Fifth Bus Addr 2AAAH 2AAAH Write Cycle Data 55H 55H Sixth Bus Addr 5555H SA Write Cycle Data 10H 30H

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TABLE 3. COMMAND DEFINITIONS

Command Sector Sector Verify Sector Abort Sequence Protection Unprotect Protect Bus Write 6 6 4 3 Cycles Req'd First Bus Addr 5555H 5555H 5555H 5555H Write Cycle Data AAH AAH AAH AAH Second Bus Addr 2AAAH 2AAAH 2AAAH 2AAAH Write Cycle Data 55H 55H 55H 55H Third Bus Addr 5555H 5555H 5555H 5555H Write Cycle Data 60H 60H 90H E0H Fourth Bus Addr 5555H 5555H * Read/Write Cycle Data AAH AAH C2H* Fifth Bus Addr 2AAAH 2AAAH Write Cycle Data 55H 55H Sixth Bus Addr SA** SA** Write Cycle Data 20H 40H

MX29L1611

Notes:

1. Address bit A15 -- A19 = X = Don't care for all address commands except for Program Address(PA) and Sector Address(SA).

5555H and 2AAAH address command codes stand for Hex number starting from A0 to A14.

2. Bus operations are defined in Table 2.

3. RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A15 -- A19 will uniquely select any sector.

4. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE. SRD = Data read from status register.

5. Only Q0-Q7 command data is taken, Q8-Q15 = Don't care.

* Refer to Table 4, Figure 12. ** Only the top and the bottom sectors have protect- bit feature. SA = (A19,A18,A17,A16,A15) = 00000B or 11111B is valid.

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DEVICE OPERATION

SILICON ID READ

The Silicon ID Read mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device.

To activate this mode, the programming equipment must force VID (11.5V~12.5V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are don't cares except A0 and A1.

MX29L1611

The manufacturer and device codes may also be read via the command register, for instances when the MX29L1611 is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 3.

Byte 0 (A0=VIL) represents the manfacturer's code (MXIC=C2H) and byte 1 (A0=VIH) the device identifier code (MX29L1611=F8H).

To terminate the operation, it is necessary to write the read/reset command sequence into the CIR.

Table 4. MX29L1611 Silion ID Codes and Verify Sector Protect Code

Type A Manufacturer Code X X X X X V IL VIL C2H* 1 1 0 0 0 0 1 0 MX29L1611 Device Code X X X X X VIL VIH F8H* 1 1 1 1 1 0 0 0 Verify Sector Protect Sector Address*** VIH VIL C2H** 1 1 0 0 0 0 1 0

* MX29L1611 Manufacturer Code = C2H, Device Code = F8H when BYTE = VIL MX29L1611 Manufacturer Code = 00C2H, Device Code = 00F8H when BYTE = VIH ** Outputs C2H at protected sector address, 00H at unprotected scetor address. ***Only the top and the bottom sectors have protect-bit feature. Sector address = (A19, A18,A17,A16,A15) = 00000B or 11111B

A18A17A16A15A1A0Code(HEX) DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ

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READ/RESET COMMAND

The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the CIR contents are altered by a valid command sequence.

The device will automatically power-up in the read/reset state. In this case, a command sequence is not required for "read operation". Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.

The MX29L1611 is accessed like an EPROM. When CE and OE are low and WE is high the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual line control gives designers flexibility in preventing bus contention.

After three-cycle command sequence is given, a byte(word) load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Maximum of 128 bytes of data may be loaded into each page by the same procedure as outlined in the page program section below.

BYTE-WIDE LOAD/WORD-WIDE LOAD

Byte(word) loads are used to enter the 128 bytes(64 words) of a page to be programmed or the software codes for data protection. A byte load(word load) is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE.

Either byte-wide load or word-wide load is determined(Byte = VIL or VIH is latched) on the falling edge of the WE (or CE) during the 3rd command write cycle.

Note that the read/reset command is not valid when program or erase is in progress.

PAGE READ

The MX29L1611 offers "fast page mode read" function. The users can take the access time advantage if keeping CE, OE at low and the same page address (A3~A19 unchanged). Please refer to Figure 5-2 for detailed timing waveform. The system performance could be enhanced by initiating 1 normal read and 7 fast page reads(for word mode A0~A2) or 15 fast page reads(for byte mode altering A-1~A2).

PAGE PROGRAM

To initiate Page program mode, a three-cycle command sequence is required. There are two "unlock" write cycles. These are followed by writing the page program command-A0H.

Any attempt to write to the device without the three-cycle command sequence will not start the internal Write State Machine(WSM), no data will be written to the device.

PROGRAM

Any page to be programmed should have the page in the erased state first, i.e. performing sector erase is suggested before page programming can be performed.

The device is programmed on a page basis. If a byte(word) of data within a page is to be changed, data for the entire page can be loaded into the device. Any byte(word) that is not loaded during the programming of its page will be still in the erased state (i.e. FFH). Once the bytes of a page are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte(word) has been loaded into the device, successive bytes(words) are entered in the same manner. Each new byte(word) to be programmed must have its high to low transition on WE (or CE) within 30us of the low to high transition of WE (or CE) of the preceding byte(word). A6 to A19 specify the page address, i.e., the device is page-aligned on 128 bytes(64 words)boundary. The page address must be valid during each high to low transition of WE or CE. A1 to A5 specify the byte address within the page, A0 to A5 specify the word address withih the page. The

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byte(word) may be loaded in any order; sequential loading is not required. If a high to low transition of CE or WE is not detected whithin 100us of the last low to high transition, the load period will end and the internal programming period will start. The Auto page program terminates when status on DQ7 is '1' at which time the device stays at read status register mode until the CIR contents are altered by a valid command sequence.(Refer to table 3,6 and Figure 1,7,8)

CHIP ERASE

Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command-80H. Two more "unlock" write cycles are then followed by the chip erase command-10H.

Chip erase does not require the user to program the device prior to erase.

The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the status on DQ7 is "1" at which time the device stays at read status register mode. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence.(Refer to table 3,6 and Figure 2,7,9)

Table 5. MX29L1611 Sector Address Table

(Byte-Wide Mode)

A19 A18 A17 A16 A15 Address Range[A19, -1]

SA0 0 0 0 0 0 000000H--00FFFFH SA1 0 0 0 0 1 010000H--01FFFFH SA2 0 0 0 1 0 020000H--02FFFFH SA3 0 0 0 1 1 030000H--03FFFFH SA4 0 0 1 0 0 040000H--04FFFFH

... ... ... ... ... ................................

SA31 1 1 1 1 1 1F0000H--1FFFFFH

SECTOR ERASE

Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command-80H. Two more "unlock" write cycles are then followed by the sector erase command-30H. The sector address is latched on the falling edge of WE, while the command (data) is latched on the rising edge of WE.

Sector erase does not require the user to program the device prior to erase. The system is not required to provide any controls or timings during these operations.

The automatic sector erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the status on DQ7 is "1" at which time the device stays at read status register mode. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence.(Refer to table 3,6 and Figure 3,4,7,9)

ERASE SUSPEND

This command only has meaning while the the WSM is executing SECTOR or CHIP erase operation, and therefore will only be responded to during SECTOR or CHIP erase operation. After this command has been executed, the CIR will initiate the WSM to suspend erase operations, and then return to Read Status Register mode. The WSM will set the DQ6 bit to a "1". Once the WSM has reached the Suspend state,the WSM will set the DQ7 bit to a "1", At this time, WSM allows the CIR to respond to the Read Array, Read Status Register, Abort and Erase Resume commands only. In this mode, the CIR will not resopnd to any other comands. The WSM will continue to run, idling in the SUSPEND state, regardless of the state of all input control pins.

ERASE RESUME

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This command will cause the CIR to clear the suspend state and set the DQ6 to a '0', but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions.

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MX29L1611

READ STATUS REGISTER

The MXIC's 16 Mbit flash family contains a status register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. The status register may be read at any time by writing the Read Status command to the CIR. After writing this command, all subsequent read operations output data from the status register until another valid command sequence is written to the CIR. A Read Array command must be written to the CIR to return to the Read Array mode.

The status register bits are output on DQ3 - DQ7(table

6) whether the device is in the byte-wide (x8) or word-

wide (x16) mode for the MX29L1611. In the word-wide mode the upper byte, DQ(8:15) is set to 00H during a Read Status command. In the byte-wide mode, DQ(8:14) are tri-stated and DQ15/A-1 retains the low order address function.

It should be noted that the contents of the status register are latched on the falling edge of OE or CE whichever occurs last in the read cycle. This prevents possible bus errors which might occur if the contents of the status register change while reading the status register. CE or OE must be toggled with each subsequent status read, or the completion of a program or erase operation will not be evident.

CLEAR STATUS REGISTER

The Eraes fail status bit (DQ5) and Program fail status bit (DQ4) are set by the write state machine, and can only be reset by the system software. These bits can indicate various failure conditions(see Table 6). By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several pages or erasing multiple blocks in squence). The status register may then be read to determine if an error occurred during that programming or erasure series. This adds flexibility to the way the device may be programmed or erased. Additionally, once the program(erase) fail bit happens, the program (erase) operation can not be performed further. The program(erase) fail bit must be reset by system software before further page program or sector (chip) erase are attempted. To clear the status register, the Clear Status Register command is written to the CIR. Then, any other command may be issued to the CIR. Note again that before a read cycle can be initiated, a Read command must be written to the CIR to specify whether the read data is to come from the Array, Status Register or Silicon ID.

The Status Register is the interface between the microprocessor and the Write State Machine (WSM). When the WSM is active, this register will indicate the status of the WSM, and will also hold the bits indicating whether or not the WSM was successful in performing the desired operation. The WSM sets status bits four through seven and clears bits six and seven, but cannot clear status bits four and five. If Erase fail or Program fail status bit is detected, the Status Register is not cleared until the Clear Status Register command is written. The MX29L1611 automatically outputs Status Register data when read after Chip Erase, Sector Erase, Page Program or Read Status Command write cycle. The default state of the Status Register after powerup and return from deep power-down mode is (DQ7, DQ6, DQ5, DQ4) = 1000B. DQ3 = 0 or 1 depends on sector-protect status, can not be changed by Clear Status Register Command or Write State Machine.

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TABLE 6. MX29L1611 STATUS REGISTER

STATUS NOTES DQ7 DQ6 DQ5 DQ4 DQ3

IN PROGRESS PROGRAM 1,2, 6 0 0 0 0 0/1

ERASE 1,3, 6 0 0 0 0 0/1 SUSPEND (NOT COMPLETE) 1,4, 6 0 1 0 0 0/1 (COMPLETE) 1 1 0 0 0/1

COMPLETE PROGRAM 1,2, 6 1 0 0 0 0/1

ERASE 1,3, 6 1 0 0 0 0/1

FAIL PROGRAM 1,5, 6 1 0 0 1 0/1

ERASE 1,5, 6 1 0 1 0 0/1

AFTER CLEARING STATUS REGISTER 6 1 0 0 0 0/1

NOTES:

1. DQ7 : WRITE STATE MACHINE STATUS

1 = READY, 0 = BUSY DQ6 : ERASE SUSPEND STATUS 1 = SUSPEND, 0 = NO SUSPEND DQ5 : ERASE FAIL STATUS 1 = FAIL IN ERASE, 0 = SUCCESSFUL ERASE DQ4 : PROGRAM FAIL STATUS 1 = FAIL IN PROGRAM, 0 = SUCCESSFUL PROGRAM DQ3 : SECTOR-PROTECT STATUS 1 = SECTOR 0 OR/AND 15 PROTECTED 0 = NONE OF SECTOR PROTECTED DQ2 - 0 = RESERVED FOR FUTURE ENHANCEMENTS. These bits are reserved for future use ; mask them out when polling the Status Register.

2. PROGRAM STATUS is for the status during Page Programming or Sector Unprotect mode.

3. ERASE STATUS is for the status during Sector/Chip Erase or Sector Protection mode.

4. SUSPEND STATUS is for both Sector and Chip Erase mode .

5. FAIL STATUS bit(DQ4 or DQ5) is provided during Page Program or Sector/Chip Erase modes respectively.

6. DQ3 = 0 or1 depends on Sector-Protect Status.

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