MXIC MX29L1611GPC-10, MX29L1611GPC-12, MX29L1611GPC-90, MX29L1611PC-10, MX29L1611PC-12 Datasheet

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FEATURES

ADVANCED INFORMATION

MX29L1611G / MX29L1611*

16M-BIT [2M x 8/1M x 16] CMOS

SINGLE VOLTAGE FLASH EEPROM

• 3.3V ± 10% for write and read operation

• 11V Vpp erase/programming operation

• Endurance: 100 cycles

• Fast random access time: 90ns/100ns/120ns

• Fast page access time: 30ns (Only for 29L1611PC-90/ 10/12)

• Sector erase architecture

- 32 equal sectors of 64k bytes each

- Sector erase time: 200ms typical

• Auto Erase and Auto Program Algorithms

- Automatically erases any one of the sectors or the whole chip

- Automatically programs and verifies data at specified addresses

GENERAL DESCRIPTION

The MX29L1611G is a 16-mega bit Flash memory organized as either 1M wordx16 or 2M bytex8. The MX29L1611G includes 32 sectors of 64KB(65,536 Bytes or 32,768 words). MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29L1611G is packaged in 42 pin PDIP.

The standard MX29L1611G offers access times as fast as 100ns,allowing operation of high-speed microprocessors without wait. To eliminate bus contention, the MX29L1611G has separate chip enable CE and, output enable (OE).

• Status Register feature for detection of program or erase cycle completion

• Low VCC write inhibit is equal to or less than 1.8V

• Software data protection

• Page program operation

- Internal address and data latches for 64 words per page

- Page programming time: 5ms typical

• Low power dissipation

- 50mA active current

- 20uA standby current

• Two independently Protected sectors

• Package type

- 42 pin plastic DIP

* For page mode read only

MX29L1611G does require high input voltages for programming. Commands require 11V input to determine the operation of the device. Reading data out of the device is similar to reading from an EPROM.

MXIC Flash technology reliably stores memory contents even after 100 cycles. The MXIC's cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29L1611G uses a 11V Vpp supply to perform the Auto Erase and Auto Program algorithms.

MXIC's Flash memories augment EPROM functionality with electrical erasure and programming. The MX29L1611G uses a command register to manage this functionality.

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The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC +1V.

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PIN CONFIGURATIONS

42 PDIP

A18

A17

GND

Q0 Q8 Q1 Q9 Q2

Q10

Q11

15 16 17 18 19 20 21

MX29L1611G

PIN DESCRIPTION

SYMBOL PIN NAME

A19

A10

A11

A12

A13

A14

A15

A16

BYTE/VPP

GND

Q15/A-1

Q14

Q13

Q12

VCC

A0 - A19 Address Input Q0 - Q14 Data Input/Output Q15/A-1 Q15(Word mode)/LSB addr.(Byte

mode, for read mode only) CE Chip Enable Input OE Output Enable Input BYTE/VPP Word/Byte Selection Input, Erase/

Program supply voltage VCC Power Supply GN D Ground Pin

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BLOCK DIAGRAM

BYTE / VPP

MX29L1611G / MX29L1611*

CONTROL INPUT

LOGIC

PROGRAM/ERASE

HIGH VOLTAGE

WRITE

STATE

MACHINE

(WSM)

Q15/A-1 A0-A19

ADDRESS

LATCH

AND

BUFFER

X-DECODER

MX29L1611G

FLASH ARRA Y

Y-DECODER

Y-PASS GATE

SENSE

AMPLIFIER

Y-select

COMMAND INTERF ACE REGISTER (CIR)

ARRAY

SOURCE

COMMAND

DATA DECODER

PGM

DATA

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

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Q0-Q15/A-1

I/O BUFFER

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Table1. PIN DESCRIPTIONS

SYMBOL TYPE NAME AND FUNCTION

A0 - A19 INPUT ADDRESS INPUTS: for memory addresses. Addresses are internally latched

during a write cycle.

Q0 - Q7 INPUT/OUTPUT LOW-BYTE DATA BUS: Input data and commands during Command Interface

Register(CIR) write cycles. Outputs array,status and identifier data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled.

Q8 - Q14 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations.

Outputs array, identifier data in the appropriate read mode; not used for status register reads. Floated when the chip is de-selected or the outputs are disabled

Q15/A -1 INPUT/OUTPUT Selects between high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB

ADDRESS(BYTE = LOW) for raed operation.

CE INPUT CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers,

decoders and sense amplifiers. With CE high, the device is deselected and power consumption reduces to Standby level upon completion of any current program or erase operations. CE must be low to select the device.

OE INPUT OUTPUT ENABLES: Gates the device's data through the output buffers during

a read cycle OE is active low.

BYTE/VPP INPUT BYTE ENABLE: While operating read mode, BYTE Low places device in x8

mode. All data is then input or output on Q0-7 and Q8-14 float. AddressQ15/ A-1 selects between the high and low byte. While operating read mode, BYTE high places the device in x16 mode, and turns off the Q15/A-1 input buffer. Address A0, then becomes the lowest order address. ERASE/PROGRAM ENABLE:When BYTE/VPP=11V would place this device

into ERASE/PROGRAM mode. VC C DEVICE POWER SUPPLY(3.3V ± 10%) GND GROUND

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BUS OPERATION

Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.

Table 2.1 Bus Operations for Word-Wide Mode (BYTE/VPP = VIH)

Mode Notes CE OE BYTE/VPP A0 A1 A9 Q0-Q7 Q8-Q14 Q15/A-1

Read 1 VIL VIL VIH X X X DOUT DOUT DOUT Output Disable 1 VIL VIH VIH X X X High Z High Z HighZ Standby 1 VIH X H/L X X X High Z HIgh Z HighZ Manufacturer ID 2,4 VIL VIL VIH VIL VIL VID C 2H 0 0H 0B Device ID 2,4 VIL VIL VIH VIH VIL VID F 6 H 00 H 0B Write 1,3,5 VIL VIH VPP X X X DIN DIN DIN

Table2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL)

Mode Notes CE OE BYTE/VPP A0 A1 A9 Q0-Q7 Q8-Q14 Q15/A-1

Read 1 VIL VIL VIL X X X DOUT HighZ VIL/VIH Output Disable 1 VIL VIH VIL X X X High Z High Z X Standby 1 VIH X H/L X X X High Z HIgh Z X Manufacturer ID 2,4 VIL VIL VIL VIL VIL VID C 2H High Z VIL Device ID 2,4 VIL VIL VIL VIH VIL VID F 6H High Z VIL Write 1,3,5 VIL VIH VPP X X X D IN DIN DIN

NOTES :

1. X can be VIH or VIL for address or control pins.

2. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes. A0 at VIL, A1 at VIH and with appropriate sector addresses provide Sector Protect Code.(Refer to Table 4),A2~A19=Do not care.

3. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully completed through proper command sequence.

4. VID = 11.5V- 12.5V

5. Word mode only for write operation VPP=10.5V~11.5V

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WRITE OPERATIONS

MX29L1611G / MX29L1611*

Commands are written to the COMMAND INTERFACE REGISTER (CIR) using standard microprocessor write timings. The CIR serves as the interface between the microprocessor and the internal chip operation. The CIR can decipher Read Array, Read Silicon ID, Erase and Program command. In the event of a read command, the

will only respond to status reads. During a sector/chip erase cycle, the CIR will respond to status reads. After the write state machine has completed its task, it will allow the CIR to respond to its full command set. The CIR stays at read status register mode until the microprocessor issues another valid command sequence.

CIR simply points the read path at either the array or the silicon ID, depending on the specific read command given. For a program or erase cycle, the CIR informs the write state machine that a program or erase has been

Device operations are selected by writing commands into the CIR. Table 3 below defines 16 Mbit flash family command.

requested. During a program cycle, the write state machine will control the program sequences and the CIR

TABLE 3. COMMAND DEFINITIONS(BYTE/VPP=VHH)

Command Read/ Silicon Page Chip Sector Read Clear Sequence Reset ID Read Program Erase Erase Status Reg. Status Reg. Bus Write 4 4 4 6 6 4 3 Cycles Req'd First Bus Addr 5555H 5555H 5555H 5555H 5555H 5555H 5555H Write Cycle Data AAH AAH AAH AAH AAH AAH AAH Second Bus Addr 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Write Cycle Data 55H 55H 55H 55H 55H 55H 55H Third Bus Addr 5555H 5555H 5555H 5555H 5555H 5555H 5555H Write Cycle Data F 0H 90H A0H 80H 80H 70H 50H Fourth Bus Addr RA 00H/01H PA 5555H 5555H X Read/Write Cycle Data RD C2H/F6H PD AAH AAH SRD Fifth Bus Addr 2AAAH 2AAAH Write Cycle Data 55H 55H Sixth Bus Addr 5555H SA Write Cycle Data 10H 30H

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TABLE 3. COMMAND DEFINITIONS

Command Sector Sector Verify Sector Abort Sequence Protection Unprotect Protect Bus Write 6 6 4 3 Cycles Req'd First Bus Addr 5555H 5555H 5555H 5555H Write Cycle Data AAH AAH AAH AAH Second Bus Addr 2AAAH 2AAAH 2AAAH 2AAAH Write Cycle Data 55H 55H 55H 55H Third Bus Addr 5555H 5555H 5555H 5555H Write Cycle Data 60H 60H 90H E0H Fourth Bus Addr 5555H 5555H SA** Read/Write Cycle Data AAH AAH C2H* Fifth Bus Addr 2AAAH 2AAAH Write Cycle Data 55H 55H Sixth Bus Addr SA** SA** Write Cycle Data 20H 40H

Notes:

1. Address bit A15 -- A19 = X = Don't care for all address commands except for Program Address(PA) and Sector Address(SA).

5555H and 2AAAH address command codes stand for Hex number starting from A0 to A14.

2. Bus operations are defined in Table 2.

3. RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the CE pulse. SA = Address of the sector to be erased. The combination of A15 -- A19 will uniquely select any sector.

4. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of CE. SRD = Data read from status register.

5. Only Q0-Q7 command data is taken, Q8-Q15 = Don't care.

* Refer to Table 4, Figure 11. ** Only the top and the bottom sectors have protect- bit feature. SA = (A19,A18,A17,A16,A15) = 00000B or 11111B is valid.

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DEVICE OPERATION

SILICON ID READ

MX29L1611G / MX29L1611*

The Silicon ID Read mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its

The manufacturer and device codes may also be read via the command register, for instances when the MX29L1611G is erased or programmed in a system without access to high voltage on the A9 pin. The

command sequence is illustrated in Table 3. corresponding programming algorithm. This mode is functional over the entire temperature range of the device.

Byte 0 (A0=VIL) represents the manfacturer's code

(MXIC=C2H) and byte 1 (A0=VIH) the device identifier

code (MX29L1611G=F6H). To activate this mode, the programming equipment must force VID (11.5V~12.5V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All

To terminate the operation, it is necessary to write the

read/reset command sequence into the CIR. addresses are don't cares except A0 and A1.

Table 4. MX29L1611G Silion ID Codes and Verify Sector Protect Code

Type A19A18A17A16A15A1A0Code(HEX) Q7Q6Q5Q4Q3Q Manufacturer Code X X X X X VIL VIL C2H* 1 1 0 0 0 0 1 0 MX29L1611G Device Code X X X X X VIL VIH F6H* 1 1 1 1 0 1 1 0 Verify Sector Protect Sector Address*** VIH VIL C2H** 1 1 0 0 0 0 1 0

Q1Q

* MX29L1611G Manufacturer Code = C2H, Device Code = F6H when BYTE/VPP = VIL MX29L1611G Manufacturer Code = 00C2H, Device Code = 00F6H when BYTE/VPP = VIH ** Outputs C2H at protected sector address, 00H at unprotected scetor address. ***Only the top and the bottom sectors have protect-bit feature. Sector address = (A19, A18,A17,A16,A15) = 00000B or 11111B

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READ/RESET COMMAND

The read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the CIR contents are altered by a valid command sequence.

The device will automatically power-up in the read/reset state. In this case, a command sequence is not required for "read operation". Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.

The MX29L1611G is accessed like an EPROM. When CE and OE are low the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual line control gives designers flexibility in preventing bus contention.

Note that the read/reset command is not valid when program or erase is in progress.

PAGE READ

The MX29L1611G offers "fast page mode read" function. The users can take the access time advantage if keeping CE, OE at low and the same page address (A3~A19 unchanged). Please refer to Figure 5-2 for detailed timing waveform. The system performance could be enhanced by initiating 1 normal read and 7 fast page reads(for word mode A0~A2) or 15 fast page reads(for byte mode altering A-1~A2).

PAGE PROGRAM

The device is set up in the programming mode when VPP=11V is applied OE=VIH.

command sequence will not start the internal Write State

Machine(WSM), no data will be written to the device.

After three-cycle command sequence is given, a

byte(word) load is performed by applying a low pulse on

the CE input with CE low and OE high. The address is

latched on the falling edge of CE. The data is latched by

the first rising edge of CE. Maximum of 64 words of data

may be loaded into each page by the same procedure as

outlined in the page program section below.

PROGRAM

Any page to be programmed should have the page in the

erased state first, i.e. performing sector erase is suggested

before page programming can be performed.

The device is programmed on a page basis. If a word of

data within a page is to be changed, data for the entire

page can be loaded into the device. Any word that is not

loaded during the programming of its page will be still in

the erased state (i.e. FFH). Once the words of a page

are loaded into the device, they are simultaneously

programmed during the internal programming period.

After the first data word has been loaded into the device,

successive words are entered in the same manner. Each

new word to be programmed must have its high to low

transition on CE within 30us of the low to high transition

of CE of the preceding word. A6 to A19 specify the page

address, i.e., the device is page-aligned on 64 words

boundary. The page address must be valid during each

high to low transition of CE. A0 to A5 specify the word

address withih the page. The word may be loaded in any

order; sequential loading is not required. If a high to low

transition of CE is not detected whithin 100us of the last

low to high transition, the load period will end and the

internal programming period will start. The Auto page

program terminates when status on Q7 is '1' at which time

the device stays at read status register mode until the

CIR contents are altered by a valid command

sequence.(Refer to table 3,6 and Figure 1,7,8)

To initiate Page program mode, a three-cycle command sequence is required. There are two "unlock" write cycles. These are followed by writing the page program command-A0H.

Any attempt to write to the device without the three-cycle

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CHIP ERASE

The device is set up in the erase mode when VPP=11V

is applied OE=VIH.

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

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"set-up" command-80H. Two more "unlock" write cycles are then followed by the chip erase command-10H.

Chip erase does not require the user to program the device prior to erase.

The automatic erase begins on the rising edge of the last CE pulse in the command sequence and terminates when the status on Q7 is "1" at which time the device stays at read status register mode. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence.(Refer to table 3,6 and Figure 2,6,8)

Table 5. MX29L1611G Sector Address Table

(Byte-Wide Mode)

A1 9 A1 8 A 17 A 16 A15 Address Range

[A19, -1]

SA0 0 0 0 0 0 000000H--00FFFFH SA1 0 0 0 0 1 010000H--01FFFFH SA2 0 0 0 1 0 020000H--02FFFFH SA3 0 0 0 1 1 030000H--03FFFFH SA4 0 0 1 0 0 040000H--04FFFFH

.. . .. . ... ... ... ................................

SA31 1 1 1 1 1 1F0000H--1FFFFFH

SECTOR ERASE

Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command-80H. Two more "unlock" write cycles are then followed by the sector erase command-30H. The sector address is latched on the falling edge of CE, while the command (data) is latched on the rising edge of CE.

Sector erase does not require the user to program the device prior to erase. The system is not required to provide any controls or timings during these operations.

The automatic sector erase begins on the rising edge of the last CE pulse in the command sequence and terminates when the status on Q7 is "1" at which time the device stays at read status register mode. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence.(Refer to table 3,6 and Figure 3,4,6,8)

READ STATUS REGISTER

The MXIC's 16 Mbit flash family contains a status

or erase operation is complete, and whether that operation

completed successfully. The status register may be

read at any time by writing the Read Status command to

the CIR. After writing this command, all subsequent read

operations output data from the status register until

another valid command sequence is written to the CIR.

A Read Array command must be written to the CIR to

return to the Read Array mode.

The status register bits are output on Q3 - Q7(table 6)

whether the device is in the byte-wide (x8) or word-wide

(x16) mode for the MX29L1611G. In the word-wide mode

the upper byte, Q(8:15) is set to 00H during a Read Status

command. In the byte-wide mode, Q(8:14) are tri-stated

and Q15/A-1 retains the low order address function.

It should be noted that the contents of the status register

are latched on the falling edge of OE or CE whichever

occurs last in the read cycle. This prevents possible bus

errors which might occur if the contents of the status

OE must be toggled with each subsequent status read,

or the completion of a program or erase operation will not

be evident.

The Status Register is the interface between the

microprocessor and the Write State Machine (WSM).

When the WSM is active, this register will indicate the

status of the WSM, and will also hold the bits indicating

whether or not the WSM was successful in performing the

desired operation. The WSM sets status bits four

through seven and clears bits six and seven, but cannot

clear status bits four and five. If Erase fail or Program fail

status bit is detected, the Status Register is not cleared

until the Clear Status Register command is written. The

MX29L1611G automatically outputs Status Register data

when read after Chip Erase, Sector Erase, Page Program

or Read Status Command write cycle. The default state

of the Status Register after powerup and return from deep

power-down mode is (Q7, Q6, Q5, Q4) = 1000B. Q3 = 0

or 1 depends on sector-protect status, can not be

changed by Clear Status Register Command or Write

State Machine.

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CLEAR STATUS REGISTER

The Eraes fail status bit (Q5) and Program fail status bit (Q4) are set by the write state machine, and can only be reset by the system software. These bits can indicate various failure conditions(see Table 6). By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several pages or erasing multiple blocks in squence). The status register may then be read to determine if an error occurred during that programming or erasure series. This adds flexibility to the way the device may be programmed or erased. Additionally, once the program(erase) fail bit happens, the program (erase) operation can not be performed further. The program(erase) fail bit must be reset by system software before further page program or sector (chip) erase are attempted. To clear the status register, the Clear Status Register command is written to the CIR. Then, any other command may be issued to the CIR. Note again that before a read cycle can be initiated, a Read command must be written to the CIR to specify whether the read data is to come from the Array, Status Register or Silicon ID.

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