MXIC MX29F800TMC-12, MX29F800TMC-70, MX29F800TMI-12, MX29F800TMI-90, MX29F800TTC-12 Datasheet

...

FEATURES

PRELIMINARY

MX29F800T/B

8M-BIT [1Mx8/512Kx16] CMOS FLASH MEMORY

• 1,048,576 x 8/524,288 x 16 switchable

• Single power supply operation

- 5.0V only operation for read, erase and program operation

• Fast access time: 70/90/120ns

• Low power consumption

- 50mA maximum active current

- 0.2uA typical standby current

• Command register architecture

- Byte/word Programming (7us/12us typical)

- Sector Erase (Sector structure 16K-Bytex1, 8K-Bytex2, 32K-Bytex1, and 64K-Byte x15)

• Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with Erase Suspend capability.

- Automatically program and verify data at specified address

• Erase suspend/Erase Resume

- Suspends sector erase operation to read data from, or program data to, another sector that is not being erased, then resumes the erase.

• Status Reply

- Data polling & Toggle bit for detection of program and

erase operation completion.

• Ready/Busy pin (RY/BY)

- Provides a hardware method of detecting program or erase operation completion.

• Sector protection

- Sector protect/chip unprotect for 5V/12V system.

- Hardware method to disable any combination of sectors from program or erase operations

- Tempory sector unprotect allows code changes in previously locked sectors.

• 100,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Boot Code Sector Architecture

- T = Top Boot Sector

- B = Bottom Boot Sector

• Low VCC write inhibit is equal to or less than 3.2V

• Package type:

- 44-pin SOP

- 48-pin TSOP

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power supply Flash

GENERAL DESCRIPTION

The MX29F800T/B is a 8-mega bit Flash memory organized as 1M bytes of 8 bits or 512K words of 16 bits . MXIC's Flash memories offer the most cost-effectiv e and reliable read/write non-volatile random access memory . The MX29F800T/B is packaged in 44-pin SOP, 48-pin TSOP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.

The standard MX29F800T/B offers access time as fast as 70ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29F800T/B has separate chip enable (CE) and output enable (OE) controls.

MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F800T/B uses a command register to manage this functionality. The command register allows for 100%

P/N:PM0578 REV. 1.7, JUL. 24, 2001

TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.

MXIC Flash technology reliably stores memory contents even after 100,000 erase and prog ram cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliab le cycling. The MX29F800T/B uses a 5.0V±10% VCC sup- ply to perform the High Reliability Erase and auto Program/Erase algorithms.

The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.

MX29F800T/B

PIN CONFIGURATIONS

44 SOP(500 mil)

RY/BY

A18 A17

GND

OE Q0 Q8 Q1 Q9 Q2

Q10

Q11

2 3 4

12 13 14

MX29F800T/B

15 16 17 18 19 20 21 22

PIN DESCRIPTION

SYMBOL PIN NAME

RESET

A10

A11

A12

A13

A14

A15

A16

BYTE

GND

Q15/A-1

Q14

Q13

Q12

VCC

A0~A18 Address Input Q0~Q14 Data Input/Output Q15/A-1 Q15(Word mode)/LSB addr(Byte mode) CE Chip Enable Input WE Write Enable Input BYTE Word/Byte Selction input RESET Hardware Reset Pin/Sector Protect

Unlock OE Output Enable Input RY/BY Ready/Busy Output VC C Po wer Supply Pin (+5V) GN D Ground Pin

48 TSOP (Standard Type) (12mm x 20mm)

A15

A14

A13

A12

A11

A10

RESET

NC NC

RY/BY

A18 A17

A7 A6 A5 A4 A3 A2 A1

12 13 14 15 16 17 18 19 20 21 22 23 24

MX29F800T/B

A16

BYTE

GND

Q15/A-1

Q14

Q13

Q12

VCC

Q11

Q10

GND

P/N:PM0578

REV. 1.7, JUL. 24, 2001

MX29F800T/B

BLOCK STRUCTURE

MX29F800T TOP BOOT SECTOR ADDRESS TABLE

Sector Size Address Range (in hexadecimal) (Kbytes/ (x16) (x8)

Sector A18 A17 A16 A15 A14 A13 A12 Kwords) Address Range Address Range

SA0 0 0 0 0 X X X 64/32 00000h-07FFFh 00000h-0FFFFh SA1 0 0 0 1 X X X 64/32 08000h-0FFFFh 10000h-1FFFFh SA2 0 0 1 0 X X X 64/32 10000h-17FFFh 20000h-2FFFFh SA3 0 0 1 1 X X X 64/32 18000h-1FFFFh 30000h-3FFFFh SA4 0 1 0 0 X X X 64/32 20000h-27FFFh 40000h-4FFFFh SA5 0 1 0 1 X X X 64/32 28000h-2FFFFh 50000h-5FFFFh SA6 0 1 1 0 X X X 64/32 30000h-37FFFh 60000h-6FFFFh SA7 0 1 1 1 X X X 64/32 38000h-3FFFFh 70000h-7FFFFh SA8 1 0 0 0 X X X 64/32 40000h-47FFFh 80000h-8FFFFh SA9 1 0 0 1 X X X 64/32 48000h-4FFFFh 90000h-9FFFFh SA10 1 0 1 0 X X X 64/32 50000h-57FFFh A0000h-AFFFFh SA11 1 0 1 1 X X X 64/32 58000h-5FFFFh B0000h-BFFFFh SA12 1 1 0 0 X X X 64/32 60000h-67FFFh C0000h-CFFFFh SA13 1 1 0 1 X X X 64/32 68000h-6FFFFh D0000h-DFFFFh SA14 1 1 1 0 X X X 64/32 70000h-77FFFh E0000h-EFFFFh SA15 1 1 110XX32/16 78000h-7BFFFh F0000h-F7FFFh SA16 1 1 11100 8/4 7C000h-7CFFFh F8000h-F9FFFh SA17 1 1 11101 8/4 7D000h-7DFFFh FA000h-FBFFFh SA18 1 1 1111X 16/8 7E000h-7FFFFh FC000h-FFFFFh

MX29F800B BOTTOM BOOT SECTOR ADDRESS TABLE

Sector Size Address Range (in hexadecimal) (Kbytes/ (x16) (x8)

Sector A18 A17 A16 A15 A14 A13 A12 Kwords) Address Range Address Range

SA0000000X16/8 00000h-01FFFh 00000h-03FFFh SA10000010 8/4 02000h-02FFFh 04000h-05FFFh SA20000011 8/4 03000h-03FFFh 06000h-07FFFh SA300001XX 32/16 04000h-07FFFh 08000h-0FFFFh SA4 0 0 0 1 X X X 64/32 08000h-0FFFFh 10000h-1FFFFh SA5 0 0 1 0 X X X 64/32 10000h-17FFFh 20000h-2FFFFh SA6 0 0 1 1 X X X 64/32 18000h-1FFFFh 30000h-3FFFFh SA7 0 1 0 0 X X X 64/32 20000h-27FFFh 40000h-4FFFFh SA8 0 1 0 1 X X X 64/32 28000h-2FFFFh 50000h-5FFFFh SA9 0 1 1 0 X X X 64/32 30000h-37FFFh 60000h-6FFFFh SA10 0 1 1 1 X X X 64/32 38000h-3FFFFh 70000h-7FFFFh SA11 1 0 0 0 X X X 64/32 40000h-47FFFh 80000h-8FFFFh SA12 1 0 0 1 X X X 64/32 48000h-4FFFFh 90000h-9FFFFh SA13 1 0 1 0 X X X 64/32 50000h-57FFFh A0000h-AFFFFh SA14 1 0 1 1 X X X 64/32 58000h-5FFFFh B0000h-BFFFFh SA15 1 1 0 0 X X X 64/32 60000h-67FFFh C0000h-CFFFFh SA16 1 1 0 1 X X X 64/32 68000h-6FFFFh D0000h-DFFFFh SA17 1 1 1 0 X X X 64/32 70000h-77FFFh E0000h-EFFFFh SA18 1 1 1 1 X X X 64/32 78000h-7FFFFh F0000h-FFFFFh

Note: Address range is A18:A-1 in byte mode and A18:A0 in word mode.

P/N:PM0578

REV. 1.7, JUL. 24, 2001

BLOCK DIAGRAM

MX29F800T/B

CE OE

A0-A18

CONTROL INPUT

LOGIC

ADDRESS

LATCH

AND

BUFFER

PROGRAM/ERASE

HIGH VOLT A GE

X-DECODER

MX29F800T/B

FLASH ARRA Y

Y-DECODER

Y-PASS GATE

SENSE

AMPLIFIER

PGM

DATA

ARRAY

SOURCE

WRITE

STATE

MACHINE

(WSM)

STATE

COMMAND

DATA DECODER

COMMAND

DATA LATCH

P/N:PM0578

Q0-Q15/A-1

PROGRAM

DATA LATCH

I/O BUFFER

REV. 1.7, JUL. 24, 2001

MX29F800T/B

AUTOMATIC PROGRAMMING

The MX29F800T/B is byte programmable using the A utomatic Programming algorithm. The Automatic Programming algorithm makes the e xternal system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29F800T/B is less than 8 seconds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than 8 second. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and v erification of electrical erase are controlled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29F800T/B is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors of the array to be erased in one er ase cycle. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the program verification, and counts the number of sequences. A status bit similar to DAT A polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire arra y . Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedbac k to the user as to the status of the programming operation.

Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry . During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE or CE, whichev er happens first.

MXIC's Flash technology combines years of EPROM experience to produce the highest lev els of quality, reliability , and cost eff ectiveness . The MX29F800T/B electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are prog rammed by using the EPROM programming mechanism of hot electron injection.

During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode . After the state machine has completed its task, it will allow the command register to respond to its full command set.

P/N:PM0578

REV. 1.7, JUL. 24, 2001

MX29F800T/B

TABLE1. SOFTWARE COMMAND DEFINITIONS

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Reset 1 XXXH F0H Read 1 RA RD Read Silicon ID Word 4 555H AAH 2AAH 55H 555H 90H ADI DDI

Byte 4 AAAH AAH 555H 55H AAAH 90H ADI DDI Sector Protect Word 4 555H AAH 2AAH 55H 555H 90H (SA) XX00H Verify x02H XX01H

Byte 4 AAAH AAH 555H 55H AAAH 90H (SA) 00H

x04H 01H

Porgram Word 4 555H AAH 2AAH 55H 555H A0H PA PD

Byte 4 AAAH AAH 555H 55H AAAH A0H PA PD Chip Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H Sector Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H

Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H SA 30H Sector Erase Suspend 1 XXXH B0H Sector Erase Resume 1 XXXH 30H

Note:

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code. A2-A18=do not care. (Refer to table 3) DDI = Data of Device identifier : C2H for manufacture code, D6H/58H (x8) and 22D6H/2258H (x16) for device code. X = X can be VIL or VIH RA=Address of memory location to be read. RD=Data to be read at location RA.

2.PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address to the sector to be erased.

3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or 555H to Address A10~A-1 in byte mode.

Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated with A11~A18 in either state.

4. For Sector Protect Verify operation:If read out data is 01H, it means the sector has been protected. If read out data is 00H, it means the sector is still not being protected.

P/N:PM0578

REV. 1.7, JUL. 24, 2001

COMMAND DEFINITIONS

MX29F800T/B

Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 1 defines the valid register command

sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Either of the two reset command sequences will reset the device(when applicable).

TABLE 2. MX29F800T/B BUS OPERATION

Pins CE OE WE A0 A1 A6 A9 Q0 ~ Q15 Mode Read Silicon ID L L H L L X VID(2) C2H (Byte mode) Manfacturer Code(1) 00C2H (Word mode) Read Silicon ID L L H H L X VID(2) D6H/58H (Byte mode) Device Code(1) 22D6H/2258H (Word mode) Read L L H A0 A1 A6 A9 D Standby H XXXXXX HIGH Z Output Disable L H H XXXX HIGH Z Write L H L A0A1A6A9 DIN(3) Sector Protect(6) L VID(2) L X X L VID(2) X Chip Unprotect L VID(2) L X X H VID(2) X Verify Sector Protect(6) L L H X H X VID(2) Code(5) Reset X XXXXXX HIGH Z

OUT

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H/0000H means unprotected. Code=01H/0001H means protected.

6. A18~A12=Sector address for sector protect.

P/N:PM0578

REV. 1.7, JUL. 24, 2001

MX29F800T/B

READ/RESET COMMAND

The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered.

If program-fail or erase-f ail happen, the write of F0H will reset the device to abort the operation. A valid command must then be written to place the device in the desired state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes m ust be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage(VID). However, multiplexing high voltage onto address lines is not generally desired system design practice.

The MX29F800T/B contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read silicon ID command sequence into the command register. Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manuf acturer code of C2H/ 00C2H. A read cycle with A1=VIL, A0=VIH returns the device code of D6H/22D6H f or MX29F800T , 58H/2258H for MX29F800B.

SET-UP AUTOMATIC CHIP/SECT OR ERASE COMMANDS

Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed b y writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip er ase command 10H.

The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and ve rify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations.

When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array(no erase v erification command is required).

If the Erase operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the erase operation exceed internal timing limit.

The automatic erase begins on the rising edge of the last WE or CE, whichever happens first pulse in the command sequence and terminates when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode.

TABLE 3. EXPANDED SILICON ID CODE

Pins A0 A1 Q15~Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)

Manufacture code Word VIL VIL 00H 1 1 0 0 0 0 1 0 00C2H

Byte VIL VIL X 1 1 0 0 0 0 1 0 C2 H Device code Word VIH VIL 22H 1 1 0 1 0 1 1 0 22D6H for MX29F800T Byte VIH VIL X 1 1 0 1 0 1 1 0 D6 H Device code Word VIH VIL 22H 0 1 0 1 1 0 0 0 2258H for MX29F800B Byte VIH VIL X 0 1 0 1 1 0 0 0 58H Sector Protection X VIH X 0 0 0 0 0 0 0 1 01H (Protected) Verification X VIH X 0 0 0 0 0 0 0 0 00H (Unprotected)

P/N:PM0578

REV. 1.7, JUL. 24, 2001

SECTOR ERASE COMMANDS

MX29F800T/B

The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the de vice will automatically program and verify the sector(s) memory for an all-zero data pattern. The system is not required to provide any control or timing during these operations.

When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutiv e read cycles , at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations.

When using the Automatic sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array

T able 4. Write Operation Status

(no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE or CE, whichever happens later , while the command(data) is latched on the rising edge of WE or CE, whichever happens first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE or CE, whichever happens later. Each successive sector load cycle started by the falling edge of WE or CE, whichever happens later must begin within 30us from the rising edge of the preceding WE or CE, whichever happens first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer .) Any command other than Sector Erase(30H) or Erase Suspend(B0H) during the time-out period resets the device to read mode.

Status Q7 Q6 Q5 Q3 Q2 RY/BY

Note1 Note2

Byte Program in Auto Program Algorithm Q7 Toggle 0 N/A N o 0

Auto Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase Suspend Read 1 No 0 N/A Toggle 1 (Erase Suspended Sector) Toggle

In Progress

Erase Suspended Mode Erase Suspend Read Data Data Data Data Data 1

(Non-Erase Suspended Sector) Erase Suspend Program Q7 Toggle 0 N/A N/A 0

Byte Program in Auto Program Algorithm Q7 Toggle 1 N/A N o 0

Exceeded Time Limits Auto Erase Algorithm 0 Toggle 1 1 Toggle 0

Erase Suspend Program Q7 Toggle 1 N/A N/A 0

Toggle

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5:Exceeded Timing Limits " for more information.

P/N:PM0578

REV. 1.7, JUL. 24, 2001

MX29F800T/B

ERASE SUSPEND

This command only has meaning while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 100us to suspend the erase operations. However , When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready . At this time, state machine only allows the command register to respond to the Read Memory Array, Erase Resume and program commands.

The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend program operation is complete, the system can once again read array data within non-suspended sectors.

ERASE RESUME

This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was pre viously issued. Erase Resume will not have any effect in all other conditions.Another Erase Suspend command can be written after the chip has resumed erasing.

If the program opetation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the program operation exceed internal timing limit. The automatic programming operation is completed when the data read on Q6 stops toggling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the device returns to the Read mode(no program verify command is required).

DATA POLLING-Q7

The MX29F800T/B also features Data Polling as a method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress or completed.

While the Automatic Programming algorithm is in operation, an attempt to read the device will produce the complement data of the data last written to Q7. Upon completion of the Automatic Program Algorithm an attempt to read the device will produce the true data last written to Q7. The Data P olling f eature is valid after the rising edge of the fourth WE or CE, whichev er happens first pulse of the four write pulse sequences for automatic program.

While the Automatic Erase algorithm is in operation, Q7 will read "0" until the erase operation is competed. Upon completion of the erase operation, the data on Q7 will read "1". The Data P olling feature is valid after the rising edge of the sixth WE or CE, whichev er happens first pulse of six write pulse sequences for automatic chip/ sector erase.

SET-UP AUTOMATIC PROGRAM COMMANDS

T o initiate Automatic Progr am mode, A three-cycle command sequence is required. There are two "unlock" write cycles. These are f ollowed by writing the Automatic Program command A0H.

Once the Automatic Program command is initiated, the next WE pulse causes a tr ansition to an active programming operation. Addresses are latched on the falling edge, and data are internally latched on the rising edge of the WE or CE, whichever happens first. The rising edge of WE or CE, whichev er happens first, also begins the programming operation. The system is not required to provide further controls or timings. The device will automatically provide an adequate internally generated program pulse and verify margin.

P/N:PM0578

The Data Polling f eature is active during Automatic Program/Erase algorithm or sector erase time-out.(see section Q3 Sector Erase Timer)

RY/BY:Ready/Busy

The RY/BY is a dedicated, open-drain output pin that indicates whether an Automatic Erase/Program algorithm is in progress or complete. The RY/BY status is valid after the rising edge of the final WE or CE, whichever happens first pulse in the command sequence. Since RY/BY is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to Vcc.

If the output is low (Busy), the device is activ ely erasing or programming. (This includes programming in the Erase Suspend mode.)If the output is high (Ready), the

REV. 1.7, JUL. 24, 2001

MX29F800T/B

device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode.

Table 4 shows the outputs f or RY/BY.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE or CE, whichever happens first, in the command sequence(prior to the program or erase operation), and during the sector time-out.

During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete, Q6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.

The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase suspended. When the de vice is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. Ho wever, the system m ust also use Q2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7.

If a program address falls within a protected sector, Q6 toggles for approximately 2 us after the program command sequence is written, then returns to reading array data.

Q2:Toggle Bit II

The "T oggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively eraseing (that is, the Automatic Erase alorithm is in process), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE or CE, whichever happens first, in the command sequence.

Q2 toggles when the system reads at addresses within those sectors that have been selected f or erasure. (The system may use either OE or CE to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, b y comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus , both status bits are required for sectors and mode inf ormation. Refer to Table 4 to compare outputs for Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whenev er the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. T ypically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the f ollo wing read cycle.

Howe v e r, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may hav e stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfuly completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.

Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete.

Table 4 shows the outputs f or Toggle Bit I on Q6.

P/N:PM0578

The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may contin ue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively , it may choose to perf orm other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation.

REV. 1.7, JUL. 24, 2001

MX29F800T/B

Q5 Exceeded Timing Limits

Q5 will indicate if the program or erase time has exceeded the specified limits(internal pulse count). Under these conditions Q5 will produce a "1". This timeout condition indicates that the program or erase cycle was not successfully completed. Data Polling and T oggle Bit are the only operating functions of the device under this condition.

If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. Howe ver , other sectors are still functional and may be used for the prog ram or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device .

If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad.

If this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector maynot be reused, (other sectors are still functional and can be reused).

The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and ne v er completes the A utomatic Algorithm operation. Hence , the system ne v er reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has e xceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the de vice was incorrectly used.

TEMPORARY SECT OR UNPR OTECT

This feature allows temporary unprotection of previously protected sector to change data in-system. The T emporary Sector Unprotect mode is activated by setting the RESET pin to VID(11.5V-12.5V). During this mode, formerly protected sectors can be programmed or erased as un-protected sector. Once VID is remove from the RESET pin,all the previously protected sectors are protected again.

Sector Erase Timer

After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence.

If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the inter nally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or T oggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. T o insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE or WE will not initiate a write cycle.

DATA PROTECTION

The MX29F800T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the de vice automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several f eatures to prev ent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise .

P/N:PM0578

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. T o initiate a write cycle CE and WE must be a logical zero while OE is a logical one.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device should have a 0.1uF cer amic capacitor connected between its VCC and GND.

REV. 1.7, JUL. 24, 2001

MX29F800T/B

SECTOR PROTECTION

The MX29F800T/B features hardware sector protection. This feature will disable both program and erase oper ations for these sectors protected. T o activ ate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 12V) A6 = VIL and CE = VIL.(see Table 2) Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated on the rising edge. Please ref er to sector protect algorithm and wavef orm.

T o v erify programming of the protection circuitry , the programming equipment must force VID on address pin A9 ( with CE and OE at VIL and WE at VIH). When A1=1, it will produce a logical "1" code at device output Q0 f or a protected sector. Otherwise the device will produce 00H for the unprotected sector. In this mode, the addresses,except f or A1, are don't care. Address locations with A1 = VIL are reserved to read manufacturer and device codes.(Read Silicon ID)

It is also possible to determine if the sector is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected sector.

POWER-UP SEQUENCE

The MX29F800T/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences.

ABSOLUTE MAXIMUM RATINGS

RATING VALUE

Ambient Operating Temperature -40oC to 85oC Storage T emperature -65oC to 125oC Applied Input Voltage -0.5V to 7.0V Applied Output Voltage -0.5V to 7.0V VCC to Ground Potential -0.5V to 7.0V A9 & OE -0.5V to 13.5V

NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.

CHIP UNPROTECT

The MX29F800T/B also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotect mode.

To activate this mode, the programming equipment must force VID on control pin OE and address pin A9. The CE pins must be set at VIL. Pins A6 must be set to VIH.(see Table 2) Refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. The unprotection mechanism begins on the falling edge of the WE pulse and is terminated on the rising edge.

It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command. Performing a read operation with A1=VIH, it will produce 00H at data outputs(Q0-Q7) for an unprotected sector. It is noted that all sectors are unprotected after the chip unprotect algorithm is completed.

NOTICE: Specifications contained within the following tables are subject to change.

P/N:PM0578

REV. 1.7, JUL. 24, 2001

+ 29 hidden pages